お客様各位 受付終了製品のドキュメントについて 本ドキュメントはデータリリースの受付が終了した製品のものであり、掲載内容も当時の情報を掲 載しています。 したがいまして、新規採用には利用できないことをご理解いただけますようお願いいたします。 2013 年 11 月 15 日 富士通セミコンダクター株式会社 http://jp.fujitsu.com/fsl/ FUJITSU SEMICONDUCTOR DS06–20209–6 DATA SHEET CMOS CS86 ■ 0.18 μm CS86 , CS86 , CS81 CMOS ASIC 3 (CS86MN, CS86MZ, CS86ML) I/O PAD , 3 , LSI ■ 0.18 μm Si CMOS 5 1.8 V 0.15 V ( 40 °C 125 °C 6 ) 1.1 V 0.1 V CS86MN , CS86MZ , CS86MN CS86ML , , CS86MZ CS86MN CS86ML *1 70 88 136 ps *2 42.7 40.1 38.3 nW/MHz 3.922 0.023 0.0067 nW *3 *1 : 2 *2 : 2 *3 : 2 NAND ( NAND ( NAND ( ) , F/O ) , F/O ) , F/O 2, , 1, 4 Grid, 0, , Copyright©2003-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2011.7 1.8 V, 1.8 V, 1.8 V, 25 °C 25 °C 25 °C CS86 / IP (RAM/ROM/ PCI, USB CPU (ARM9, FR-V ) , DSP, PCI, USB, IrDA, PLL, DAC, ADC /Delay line) Hardware/Software Co-design Physical Synthesis Low Power Synthesis Memory (RAM, ROM) Scan Memory (RAM) Bist Boundary Scan QFP, LQFP, HQFP, FBGA 2 DS06–20209–6 CS86 ■ 1. Adder AND-OR Inverter Clock Buffer Latch NAND AND NOR OR-AND Scan Flip Flop ENOR Boundary Scan Register Bus Driver 2. IP CPU DSP AND-OR Decoder NON-Scan Flip Flop Inverter Buffer OR-AND Inverter OR Delay Buffer Selector EOR Dummy Clock Buffer FR-V, ARM9, DSP, AV DSP, , , UART, PCI, USB, IrDA, JPEG, MPEG 4.0, ADC, DAC, OPAMP, RAM (1 port, 2 ports) , ROM, Delay Line, PLL I/O DS06–20209–6 , PLL 1.1 V 5 V PCI, USB, , 3 CS86 ■ , CS86 ,( , 1. RAM (1 1 ) ) / 4 16 72 K 16 1K 1 72 bit 16 64 72 K 64 4K 1 18 bit 4 256 144 K 128 2K 2 72 bit 16 24K 1152 K 4K 16 K 6 72 bit 16 16K 1152 K 4K 16 K 4 72 bit 8 256 144 K 64 2K 4 72 bit / 2. RAM (2 1 ,1 ) / 4 16 72 K 16 1K 1 72 bit 16 64 72 K 64 4K 1 18 bit 1 72 bit 1 72 bit 3. (3 1 1 4 4. (4 4 2 1 4 4608 ,2 4 4608 64 ,2 4 ) 64 ) DS06–20209–6 CS86 5. ROM 16 256 1024 K 128 8K 2 128 bit 64 1K 1024 K 512 32 K 2 32 bit 6. Delay line (2 1 ,1 ) 8 256 32 K 32 1K 8 32 bit 16 384 32 K 64 2K 6 16 bit 32 512 32 K 128 4K 4 8 bit DS06–20209–6 5 CS86 ■ *1 VDD *1 VI *1 VO DD, (a) 0.5 2.5 V) *2 VDD 0.5 ( 4.0 V) *3 VDD 0.5 ( 2.5 V) *2 VDD 0.5 ( 4.0 V) *3 YH, XH, YI, XI V 125 °C Tj 40 125 °C 10 (3.3 V CMOS, 2.5 V CMOS) mA *5200 RI ⎯ RO ⎯ 100 Mbps*6 CO ⎯ 3000/RO pF ID ⎯ *7 mA I/O DC *1 125 °C*2 Tj )(mA) VDDE 68 4 VDDE 59 5 VDDE 59 6 VDDI, VDD, VSS 68 4 VDDI, VDD, VSS 93 5 VDDI, VDD, VSS 118 6 125 °C*2 Tj ( YH, XH, YI, XI I/O )(mA) VDDI, VDD, VSS 34 4 VDDI, VDD, VSS 34 5 VDDI, VDD, VSS 59 6 I/O Tj Tj Tj Tj Mbps*6 100 I/O 1 1: 2: V 55 ( 6 0.5 ( 7.5 (1.8 V CMOS) GND 1 (mA) I/O 1 (b) VDD TSTG 1 VSS 0 V 2 3 3.3 V I/F 2.5 V I/F 4 10 ms DC , 5 I/O 6 bps / 7 VDD, GND 1 (mA) V V 4.0 *3 0.5 IO *4 2.5 *2 0.5 111 °C 91 °C 90 °C 125 °C 125 °C 1.0 110 °C1.4 2.8 DS06–20209–6 CS86 ( 6 (2 ) ) 1 • VDD, GND VDDE : (a) I/O 1 VDDE = 59 mA/ VDDI, VSS: (b) I/O 1 • ( / /VSS) Ni/Ne/Ns DC Max Iimax, DC Max Iemax Ni Iimax/59mA, Ne Iemax/59mA, Ns Iimax/59mA Iemax/59mA ( , , ) VDDI = VSS = 59 mA/ , , DS06–20209–6 7 CS86 ■ (V DD 1.8 V 0.15 V) (VSS VDD “H” VIH “L” VIL Tj (V DDE 3.3 V 0.3 V, VDDI 1.8 V 1.65 1.95 V ⎯ VDD 0.3 V 0.3 ⎯ VDD 0.35 V 40 ⎯ VDD 0.15 V/VDDI 1.8 0 V) 0.65 1.5 V °C 125 0.1 V) 0 V) (VSS VDDE VDDI 1.8 V CMOS “H” 1.8 V CMOS “L” 3.3 3.6 1.65 1.8 1.95 1.4 1.5 1.6 3.3 V CMOS Tj (V DDE 2.5 V 0.2 V, VDDI 1.8 V VDDI 0.3 ⎯ VDDE 0.3 0.3 ⎯ VDDI 0.35 0.3 ⎯ 0.8 40 ⎯ 125 0.65 2.0 VIL 0.15 V/VDDI V ⎯ VDDI VIH 3.3 V CMOS 3.0 1.5 V V V °C 0.1 V) (VSS 2.3 2.5 2.7 1.65 1.8 1.95 1.4 1.5 1.6 VDDE VDDI 1.8 V CMOS “H” 2.5 V CMOS 1.8 V CMOS “L” 2.5 V CMOS VDDI 0.3 ⎯ VDDE 0.3 0.3 ⎯ VDDI 0.35 0.3 ⎯ 40 ⎯ 0.65 1.7 VIL Tj V ⎯ VDDI VIH 0.7 V V °C 125 , 0 V) , , , , , , 8 DS06–20209–6 CS86 ■ 1. V 1.8 V DD (VDD 1.8 V 100 μA 0.15 V, VSS 0 V, Tj 40 °C 125 °C) ⎯ VDD V ⎯ 0.2 V “H” VOH “L” VOL IOL “H” V-I ⎯ 1.8 V VDD 1.8 V 0.15 V * ⎯ “L” V-I ⎯ 1.8 V VDD 1.8 V 0.15 V * ⎯ IL VI / IOH VDD 100 μA 0V VI VDD 0, VDD VIL VIH Rp 0.2 0 ⎯ ⎯ 8 18 μA 5 40 kΩ ■V-I (1) 1.8 V V 3.3 V, VDDI DDE “H” “L” 1.8 V/1.5 V/1.1 V 3.3 V 0.3 V/VDDI (VDDE 1.8 V 0.15 V, VDDI 1.5 V 0.1 V, VDDI 1.1 V 0.1 V, VSS 0 V, Tj 40 °C 125 °C) VOH4 3.3 V IOH 100 μA VDDE 0.2 ⎯ VDDE VOH2 1.8 V IOH 100 μA VDDI 0.2 ⎯ VDDI VOL4 3.3 V IOL 100 μA 0 ⎯ 0.2 VOL2 1.8 V IOL 100 μA 0 ⎯ 0.2 3.3 V VDDE 3.3 V 0.3 V *1 1.8 V VDDI 1.8 V 0.15 V *2 3.3 V VDDE 3.3 V 0.3 V *1 1.8 V VDDI 1.8 V 0.15 V *2 “H” V-I ⎯ “L” V-I ⎯ IL VI 0V VI VDDE ⎯ ⎯ 33 V V ⎯ ⎯ 5 μA 3.3 V / Rp VIL VIH 0, VDDE 10 VIL VIH 0, VDDI 8 80 kΩ 1.8 V 1 2 18 40 ■V-I (2) 3.3 V ■V-I (1) 1.8 V DS06–20209–6 9 CS86 V DDE 2.5 V, VDDI 1.8 V/1.5 V/1.1 V (VDDE 2.5 V 0.2 V, VDDI “H” “L” 1.8 V 0.15 V/VDDI 1.5 V 0.1 V/VDDI 1.1 V 0.1 V, VSS 0 V, Tj 40 °C 125 °C) VOH3 2.5 V IOH 100 μA VDDE 0.2 ⎯ VDDE VOH2 1.8 V IOH 100 μA VDDI 0.2 ⎯ VDDI VOL3 2.5 V IOL 100 μA 0 ⎯ 0.2 VOL2 1.8 V IOL 100 μA 0 ⎯ 0.2 “H” V-I ⎯ 2.5 V VDDE 2.5 V 0.2 V ⎯ 1.8 V VDDI 1.8 V 0.15 V * “L” V-I ⎯ 2.5 V VDDE 2.5 V 0.2 V ⎯ 1.8 V VDDI 1.8 V 0.15 V * IL VI 0V VI VDDE 2.5 V / Rp ⎯ ⎯ 25 VIL VIH 0, VDDE ⎯ VIL VIH 0, VDDI 8 V V ⎯ ⎯ μA 5 ⎯ kΩ 1.8 V 18 40 40 °C 125 °C ( ■V-I (1) 1.8 V 2. (VSS tpd*1 1 2 typ 3 typ*2 , tmin*3 typ*2 0 V, Tj ttyp*3 typ*2 )) ns tmax*3 , tmin ttyp tmax VDD 1.8 V 0.15 V, VSS 0 V, Tj 40 °C 125 °C 0.62 1.00 1.88 VDD 1.5 V 0.10 V, VSS 0 V, Tj 40 °C 125 °C 0.76 1.25 2.42 VDD 1.1 V 0.1 V, VSS 1.08 2.14 6.22 , 10 0 V, Tj 40 °C 125 °C , DS06–20209–6 CS86 ■ V-I (1) 1.8 V Min VOH−VDD (V) −1.0 −2.0 Process Typ Process Max Process Slow, Tj Typical, Tj Fast, Tj 125 °C, VDD 1.65 V 25 °C, VDD 1.80 V 40 °C, VDD 1.95 V 40 0.0 0 Max 30 −10 Typ Typ IOL (mA) −20 IOH (mA) Min 20 Min 10 −30 Max 0 0.0 −40 1.0 2.0 VOL (V) 1.8 V CMOS “H” (L, M VOH−VDD (V) −1.0 −2.0 1.8 V CMOS “L” (L, M ) ) 60 0.0 0 50 Max −10 40 −20 Typ IOH (mA) −30 Typ IOL (mA) Min 30 Min 20 −40 10 −50 Max −60 0 0.0 1.0 2.0 VOL (V) 1.8 V CMOS “H” (H, V DS06–20209–6 ) 1.8 V CMOS “L” (H, V ) 11 CS86 (2) 3.3 V Min −3.0 −4.0 VOH−VDDE (V) −2.0 −1.0 Process Typ Process Max Process 0.0 0 Slow, Tj Typical, Tj Fast, Tj 125 °C, VDDE 3.0 V 25 °C, VDDE 3.3 V 40 °C, VDDE 3.6 V 80 Max 60 −20 Typ IOL (mA) −40 Typ IOH (mA) Min 40 Min 20 −60 Max 0 0.0 −80 3.3 V CMOS “H” (L, M 0.0 0 Max −40 80 3.3 V CMOS “H” (H, V 12 ) IOL (mA) 100 ) Typ 60 Min −80 40 −100 20 −120 4.0 Max −20 −60 Typ 3.0 120 IOH (mA) Min 2.0 VOL (V) 3.3 V CMOS “L” (L, M ) VOH−VDDE (V) −2.0 −1.0 −3.0 −4.0 1.0 0 0.0 1.0 2.0 VOL (V) 3.3 V CMOS “L” (H, V 3.0 4.0 ) DS06–20209–6 CS86 ■ 25 °C, VDD (Tj ⎯ VI 0 V, f CIN 16 pF L, M, H, V type COUT 16 pF L, M, H, V type CI/O 16 pF 1 MHz) ■ (Reference Design Flow) , LSI Physical Prototyping , , , ASIC Low Power Gated Clock Gated Clock , , Low Power Synthesis , TAT Physical Synthesis Tool , SoC , , , Support for Signal Integrity , , DS06–20209–6 13 CS86 ■ QFP 208, 240 LQFP 144, 176, 208, 256 HQFP 208, 240, 256, 304 FBGA 112, 144, 176, 192, 224, 240, 272, 288, 304, 368 , 14 , DS06–20209–6 CS86 MEMO DS06–20209–6 15 CS86 0120-198-610 222-0033 2-10-23 : 9 17 ( , ) PHS http://jp.fujitsu.com/fsl/ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,