MB85RDP16LX

FUJITSU SEMICONDUCTOR
DATA SHEET
DS501-00031-1v1-E
Memory
Data-Processing FRAM
16 K (2 K 8) Bit Dual SPI
MB85RDP16LX
 DESCRIPTION
MB85RDP16LX is a Data-Processing FRAM in a configuration of 2,048 words × 8 bits incorporating a 43-bit or
46-bit binary counter, where FRAM (Ferroelectric Random Access Memory) is able to retain data without using
a back-up battery, can be used for 1013 read/write operations and takes no wait time to write data, using the
ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells.
MB85RDP16LX can be accessed via Serial Peripheral interface (SPI) or Dual SPI.
This Data-Processing FRAM features short power up time, fast memory access and ultra-low power
consumption. Together with the 43-bit or 46-bit binary counter function, MB85RDP16LX fits perfectly into
energy harvesting and rotary encoder applications.
 FEATURES
•
•
•
•
•
Non-volatile memory configuration
Binary counter bit (for POS0/1/2/3)
Binary counter bit (for DIBC/DDBC)
Binary counter operation
Interface
•
•
•
•
•
Operating frequency
High endurance
Data retention
Operating power supply voltage
Low power consumption
• Operation ambient temperature
• Package
: 2,048 words × 8 bits
: 43-bit range (42bit mantissa + sign bit)
: 46-bit range (45bit mantissa + sign bit)
: Judged by the input position data or directly Increment and Decrement
: SPI (Serial Peripheral Interface) / Dual SPI
Corresponding to SPI mode 0 (0, 0) and mode 3 (1, 1)
: 15 MHz (Max for SPI) / 7.5 MHz (Max for Dual SPI)
: 1013 times / byte
: 10 years (+105℃)
: 1.65 V to 1.95 V
: Operating power supply current 0.7 mA (Max @15 MHz)
Standby current 11 μA (Max @+105℃), 1 μA (+25℃)
: 40℃ to +105℃
: 8-pin plastic SON (LCC-8P-M04)
RoHS compliant
Copyright 2014-2015 FUJITSU SEMICONDUCTOR LIMITED
June 2015
MB85RDP16LX
 PIN ASSIGNMENT
(TOP VIEW)
__
CS
SO
(IO1)
__
WP
VSS
1
8
2
7
VDD
___
RST
3
6
SCK
4
5
SI
(IO0)
(LCC-8P-M04)
 PIN FUNCTIONAL DESCRIPTIONS
Pin No. Pin Name
Functional description
CS
Chip Select pin
This is an input pin to activate the device. When CS is the “H” level, device is in deselect
(standby) status and SO/SI become High-Z. Inputs from other pins are ignored at this
time. When CS is the “L” level, device is in select (active) status. CS has to be the “L”
level before inputting op-code.
WP
Write Protect pin
This is an input pin to control writing to a status register. The writing of status register
(see “ STATUS REGISTER”) is protected in relation with WP and WPEN bit of the
status register. See “ WRITING PROTECT” for detail.
7
RST
Reset pin
This is an input pin to reset the device internally. When RST is the "L" level, the
interface is inactive and the SPI state machine is reset. RST pin need to be "L" at
power on.
6
SCK
Serial Clock pin
This is a clock input pin to input/output serial data. Inputs are latched synchronously to the
rising edge, Outputs occur synchronously to the falling edge.
5
SI (IO0)
Serial Data Input pin (Serial Data Input Output 0)
This inputs op-code, addresses or writing data and outputs reading data. This is High-Z
during standby.
2
Serial Data Output pin (Serial Data Input Output 1)
SO (IO1) This outputs reading data or status register and inputs addresses or writing data. This is
High-Z during standby.
1
3
8
VDD
Supply Voltage pin
4
VSS
Ground pin
(*)When using Dual SPI instructions, the SI and SO pins become bidirectional IO0 and IO1 pins.
2
DS501-00031-1v1-E
MB85RDP16LX
 BLOCK DIAGRAM
SI(IO0)
DS501-00031-1v1-E
3
MB85RDP16LX
 SPI MODE
MB85RDP16LX corresponds to the SPI mode 0 (CPOL=0, CPHA=0) and SPI mode 3 (CPOL=1, CPHA=1).
CS
SCK
SI
7
6
5
MSB
4
3
2
1
0
LSB
SPI Mode 0
CS
SCK
SI
7
6
5
4
MSB
3
2
1
0
LSB
SPI Mode 3
 SERIAL PERIPHERAL INTERFACE (SPI)
Standard SPI
MB85RDP16LX works as a slave of SPI. Standard SPI uses the SI serial input pin to write op-code,
addresses or data to the device on the rising edge of SCK. The SO serial output pin is used to read data
or status register from the device on the falling edge of SCK.
Dual SPI
MB85RDP16LX supports Dual SPI mode using the “Read Dual I/O (RDIO, B3h)” and “Write Dual I/O
(WDIO, B2h)” op-code. When using Dual SPI op-code, the SI and SO pins become bidirectional IO0 and
IO1 pins.
4
DS501-00031-1v1-E
MB85RDP16LX
 STATUS REGISTER
Bit No.
Bit Name
Function
WPEN
Status Register Write Protect
This is a bit composed of nonvolatile memories (FRAM). WPEN protects
writing to a status register (see “ WRITING PROTECT”) relating with WP
input. Writing with the WRSR command and reading with the RDSR
command are possible.
6 to 4
⎯
Not Used Bits
These are bits composed of nonvolatile memories, writing with the WRSR
command is possible. These bits are not used but they are read with the
RDSR command.
3
BP1
2
BP0
7
1
WEL
0
0
DS501-00031-1v1-E
Block Protect
This is a bit composed of nonvolatile memory. This defines size of write
protect block for the WRITE command and WDIO command (see “ BLOCK
PROTECT”). Writing with the WRSR command and reading with the
RDSR command are possible.
Write Enable Latch
This indicates FRAM Array and status register are writable. The WREN
command is for setting, and the WRDI command is for resetting. With the
RDSR command, reading is possible but writing is not possible with the
WRSR command. WEL is reset after the following operations.
After power ON.
After WRDI command recognition.
At the rising edge of CS after WRSR command recognition.
At the rising edge of CS after WRITE command recognition.
At the rising edge of CS after WDIO command recognition.
This is a bit fixed to “0”.
5
MB85RDP16LX
 OP-CODE
MB85RDP16LX accepts 7 kinds of conventional command (WREN to RDID) and 12 kinds of enhanced
command (RDIO to WRTSd) specified in op-code. Op-code is a code composed of 8 bits shown in the
table below. Do not input invalid codes other than those codes. If CS is risen while inputting op-code, the
command is not performed.
Name
Description
Op-code
WREN
Set Write Enable Latch
0000 0110B
WRDI
Reset Write Enable Latch
0000 0100B
RDSR
Read Status Register
0000 0101B
WRSR
Write Status Register
0000 0001B
READ
Read Memory Code
0000 0011B
WRITE
Write Memory Code
0000 0010B
RDID
Read Device ID
1001 1111B
RDIO
Read Dual I/O
1011 0011B
WDIO
Write Dual I/O
1011 0010B
POS0
Set SPI_DIR&SPI_PP = 00
0011 0000B
POS1
Set SPI_DIR&SPI_PP = 01
0011 0001B
POS2
Set SPI_DIR&SPI_PP = 10
0011 0010B
POS3
Set SPI_DIR&SPI_PP = 11
0011 0011B
DIBC
Directly Increment Binary Counter (+1)
0011 1100B
DDBC
Directly Decrement Binary Counter (-1)
0011 1110B
RDTSs
Read from address 0x000 decoded by a dedicated
function, Single SO
0011 1000B
RDTSd
Read from address 0x000 decoded by a dedicated
function, Dual IO
0111 1000B
WRTSs
Write from address 0x000 encoded by a dedicated
function, Single SI
0011 1111B
WRTSd
Write from address 0x000 encoded by a dedicated
function, Dual IO
0111 1111B
Notes
1-1. Standard SPI Input Address (2bytes)
SI = X, X, X, X, X, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0
(Upper 5bit = any)
1-2. Dual SPI Input Address (2bytes)
IO0 = X, X, A9, A7, A5, A3, A1, X
IO1 = X, X, A10, A8, A6, A4, A2, A0
(Upper 4bit and lower 1bit = any)
2-1. Standard SPI I/O Data
SI (or SO) = (D7, D6, D5, D4, D3, D2, D1, D0)
2-2. Dual SPI I/O Data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
6
DS501-00031-1v1-E
MB85RDP16LX
 COMMAND
• WREN
The WREN command sets WEL (Write Enable Latch). WEL shall be set with the WREN command before
writing operation (WRSR command, WRITE command and WDIO command).
CS
0
1
2
3
4
5
6
7
SCK
SI
Invalid
0
0
0
0
0
1
1
Invalid
0
High-Z
SO
• WRDI
The WRDI command resets WEL (Write Enable Latch). Writing operation (WRITE command, WRSR
command and WDIO command) are not performed when WEL is reset.
CS
0
1
2
3
4
5
6
7
SCK
SI
Invalid
0
0
0
0
0
1
0
0
Invalid
High-Z
SO
DS501-00031-1v1-E
7
MB85RDP16LX
• RDSR
The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input
to SCK. The SI value is invalid during this time. SO is output synchronously to a falling edge of SCK. In the
RDSR command, repeated reading of status register is enabled by sending SCK continuously before rising
of CS.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
Invalid
1
Data Out
High-Z
SO
Invalid
MSB
LSB
• WRSR
The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR
op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR
command. A SI value corresponding to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot
be written. The SI value corresponding to bit 0 is ignored. The WP signal level shall be fixed before performing
the WRSR command, and not be changed until the end of command sequence.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Instruction
SI
0
0
0
0
0
Data In
0
0
1
7
MSB
High-Z
6
5
4
3
2
1
0
LSB
SO
8
DS501-00031-1v1-E
MB85RDP16LX
• READ
The READ command reads FRAM memory cell array data. READ op-code and arbitrary 16 bits address
are input to SI. The 5-bit upper address bits are ignored. Then, 8 clock cycles are input to SCK. SO
outputs 8-bit data synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS
is risen, the READ command is completed, otherwise it keeps on reading with automatic address
increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising.
When it reaches the most significant address, it rolls over to the starting address, and reading cycle
keeps on infinitely.
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13
18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
16-bit address
OP-CODE
SI
0 0
0 0 0 0 1 1 X X X X X 10
5
4
3
2
1
0
Invalid
Data Out
LSB MSB
MSB
LSB
High-Z
SO
7
6
5
4
3
2
1
0
Invalid
• WRITE
The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 16 bits of address
and 8 bits of writing data are input to SI. The 5-bit upper address bit is ignored. When 8 bits of writing data
is input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command.
However, if you continue sending the writing data for 8 bits each before CS rising, it is possible to
continue writing with automatic address increment. When it reaches the most significant address, it rolls
over to the starting address, and writing cycle keeps on infinitely.
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13
18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
OP-CODE
SI
0 0
16-bit address
0 0 0 0 1 0 X X X X X 10
MSB
SO
DS501-00031-1v1-E
5
4
Data In
3
2
1
0
7
6
LSB MSB
5
4
3
2
1
0
LSB
High-Z
9
MB85RDP16LX
• RDID
The RDID command reads fixed Device ID. After performing RDID op-code to SI, 32 clock cycles are input
to SCK. The SI value is invalid during this time. SO is output synchronously to a falling edge of SCK. The
output order is Manufacturer ID (8bit)/Continuation code (8bit)/Product ID (1st Byte)/Product ID (2nd Byte).
In the RDID command, SO holds the output state of the last bit in 32-bit Device ID until CS is risen.
CS
0
1
2
3
4
5
6
7
1
0
0
1
1
1
1
1
8
31 32 33 34 35 36 37 38 39
9 10 11
SCK
SI
Invalid
Data Out
SO
High-Z
Data Out
8
31 30 29 28
7
6
5
4
3
2
1
0
LSB
MSB
bit
Manufacturer ID
Continuation code
Product ID (1st Byte)
Product ID (2nd Byte)
10
7
0
0
6
0
1
5
0
1
Proprietary use
0
0
1
0
1
4
0
1
3
0
1
2
1
1
0
Density
0
0
0
Proprietary use
0
0
0
1
1
0
1
0
0
0
1
Hex
04H Fujitsu
7FH
1
Hex
21H Density: 00001B = 16kbit
1
Hex
45H
DS501-00031-1v1-E
MB85RDP16LX
• RDIO
The RDIO command reads FRAM memory cell array data. RDIO op-code is input to SI(IO0). The 6 even
address bits (A10, A8, A6, A4, A2, A0) of arbitrary 16 bits address are input to SO(IO1) and the 5 odd
address bits (A9, A7, A5, A3, A1) are input to SI(IO0). The other address bits are ignored. Then, 4 clock
cycles are input to SCK. SO(IO1) outputs 4 odd data bits (D7, D5, D3, D1) synchronously to the falling
edge of SCK and SI(IO0) outputs 4 even data bits (D6, D4, D2, D0) as well. When CS is risen, the RDIO
command is completed, otherwise it keeps on reading with automatic address increment which is enabled
by continuously sending clocks to SCK in unit of 4 cycles before CS rising. When it reaches the most
significant address, it rolls over to the starting address, and reading cycle keeps on infinitely.
CS
0
1
2
3 4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
IO switches from Input to Output
16-bit address
OP-CODE
SI
1
0
1 1
0 0
1 1
X X 9
7
5
Data Out
3 1
X 6
4
2
(IO0)
SO
(IO1)
High-Z
X
X 10 8
6 4
2
0 6
4
2
0
5
3
1
LSB
LSB
0 7
5
3
1 7
MSB
MSB
Byte1
Invalid
Byte2
• WDIO
The WDIO command writes data to FRAM memory cell array. WDIO op-code is input to SI(IO0). The 6
even address bits (A10, A8, A6, A4, A2, A0) of arbitrary 16 bits address are input to SO(IO1) and the 5
odd address bits (A9, A7, A5, A3, A1) are input to SI(IO0). The other address bits are ignored. When the
4 odd writing data bits (D7, D5, D3, D1) are input to SO(IO1) and the 4 even writing data bits (D6, D4, D2,
D0) are input to SI(IO0), they are written to FRAM memory cell array. Risen CS will terminate the WDIO
command. However, if you continue sending the writing data for 8 bits each before CS rising, it is
possible to continue writing with automatic address increment. When it reaches the most significant
address, it rolls over to the starting address, and writing cycle keeps on infinitely.
CS
0
1
2
3 4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
16-bit address
OP-CODE
SI
(IO0)
SO
(IO1)
1
0
1 1
0 0
1 0
X X 9
7
5
Data In
3 1
X 6
4
2
High-Z
X
MSB
X 10 8
6 4
2
0 7
4
2
0
Invalid
5
3
1 7
5
3
1
Invalid
MSB
Byte1
DS501-00031-1v1-E
0 6
LSB
LSB
Byte2
11
MB85RDP16LX
• POS0/POS1/POS2/POS3
The POS0, POS1, POS2 and POS3 commands compare the old position data, which is stored in FRAM,
with the new position data, which is input as the lowest 2 bits of the op-code. The comparing result
decides if the 43-bit binary counter is incremented or decremented. The binary counter operation is
accomplished by adding 6 dummy clocks after the 8-bit op-code. The frequency of the dummy clocks
needs less than fDCK (see “2. AC Characteristics”). These commands automatically read 48-bit FRAM cell
array data containing position data, binary counter data and error flags from the address “000H” (see “
MEMORY MAP for POS0/1/2/3” ), calculate them by the 43-bit binary counter and overwrite them to the
address “000H” during the 6 dummy clocks. These 48-bit data are encoded by a dedicated function and
stored in FRAM cell array, therefore the specified commands (RDTSs/RDTSd/WRTSs/WRTSd) are
necessary to read/write the 48-bit data related to the binary counter. SO continues to output low level
during the binary counter operation and turns the output to high level after 6th dummy clock falls. It judges
if last operation is complete or not at 2nd dummy clock using 2-bit Error Flags and 2 copies of the DIR bit.
If last operation is incomplete, SO continues to output low level only until the 2nd dummy clock falls
because the operation stops at the 2nd dummy clock.
In case that last operation is complete (Error Flags == 2’b00 and DIR == DIR’)
CS
Dummy Clocks
0
1
2
3 4
5
6
7
1
2
3
4
5
6
0
0
0
4
5
6
1
1
1
SCK
OP-CODE
SI
0 0
(IO0)
SO
(IO1)
1 1
0 0 DIR PP
Invalid
Signal Processing
0
0
High-Z
0
1
High-Z
In case that last operation is incomplete (Error Flags != 2’b00 or DIR != DIR’)
CS
Dummy Clocks
0
1
2
3 4
5
6
7
1
2
3
SCK
OP-CODE
SI
(IO0)
SO
(IO1)
0 0
1 1
0 0 DIR PP
High-Z
Position data comparison table
old (DIR, PP) new (DIR, PP)
0, 1
0, 0
1, 1
0, 0
1, 0
0, 0
1, 1
0, 1
1, 0
1, 1
0, 0
1, 1
0, 1
1, 1
0, 0
1, 0
others
others
12
Invalid
Signal Processing
0
0
1
1
High-Z
Binary counter operation
+1
+1
+1
+1
-1
-1
-1
-1
0
DS501-00031-1v1-E
MB85RDP16LX
• DIBC/DDBC
The DIBC command increments the 46-bit binary counter by 1 and the DDBC command decrements it by
1. The binary counter operation is accomplished by adding 6 dummy clocks after the 8-bit op-code. The
frequency of the dummy clocks needs less than fDCK (see “2. AC Characteristics”). These commands
automatically read 48-bit FRAM cell array data containing binary counter data and error flags from the
address “000H” (see “ MEMORY MAP for DIBC/DDBC” ), calculate them by the 46-bit binary counter
and overwrite them to the address “000H” during 6 dummy clocks. These 48-bit data are encoded by a
dedicated function and stored in FRAM cell array, therefore the specified commands
(RDTSs/RDTSd/WRTSs/WRTSd) are necessary to read/write the 48-bit data related to the binary counter.
SO continues to output low level during the binary counter operation and turns the output to high level
after the 6th dummy clock falls. It judges if last operation is complete or not at the 2nd dummy clock using
2-bit Error Flags. If last operation is incomplete, SO continues to output low level only until the 2nd dummy
clock falls because the operation stops at the 2nd dummy clock.
In case that last operation is complete (Error Flags == 2’b00)
CS
Dummy Clocks
0
1
2
3 4
5
6
7
1
2
3
4
5
6
0
0
0
4
5
6
1
1
1
SCK
OP-CODE
SI
0 0
(IO0)
SO
(IO1)
1 1
1 1 0/1 0
Invalid
Signal Processing
0
0
High-Z
0
1
High-Z
1
High-Z
In case that last operation is incomplete (Error Flags != 2’b00)
CS
Dummy Clocks
0
1
2
3 4
5
6
7
1
2
3
SCK
OP-CODE
SI
(IO0)
SO
(IO1)
0 0
1 1
High-Z
1 1 0/1 0
Invalid
Signal Processing
0
0
1
OP-CODE table for direct binary counter operation
Name
OP-CODE (8-bit)
Binary counter operation
DIBC
0011 1100B
+1
DDBC
0011 1110B
-1
DS501-00031-1v1-E
13
MB85RDP16LX
• RDTSs (Single SO)
The RDTSs command can read the data related to the binary counter from FRAM memory cell array (see
“ MEMORY MAP”). RDTSs op-code is input to SI. No address bits are input. 8 clock cycles are input to
SCK after 8-bit op-code. SO outputs 8-bit data decoded by a dedicated function from the starting address
“000H” synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen,
the RDTSs command is completed, otherwise it keeps on reading with automatic address increment
which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it
reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on
infinitely. Because of the dedicated function, RDTSs is not compatible to READ.
CS
0
1
2
3 4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
OP-CODE
SI
0
0
1 1
1 0
0 0
Invalid
Data Out
High-Z
SO
7
6
5 4
3
2 1
0 15 14 13 12 11 10 9
LSB MSB
MSB
8
LSB
Invalid
Byte1
Byte0
• RDTSd (Dual IO)
The RDTSd command can read the data related to the binary counter from FRAM memory cell array
(see “ MEMORY MAP”). RDTSd op-code is input to SI(IO0). No address bits are input. 4 clock cycles
are input to SCK after 8-bit op-code. SO(IO1) outputs the 4 odd data bits (D7, D5, D3, D1) and SI(IO0)
outputs the 4 even data bits (D6, D4, D2, D0) decoded by a dedicated function from the starting address
“000H” synchronously to the falling edge of SCK. When CS is risen, the RDTSd command is completed,
otherwise it keeps on reading with automatic address increment which is enabled by continuously
sending clocks to SCK in unit of 4 cycles before CS rising. When it reaches the most significant address,
it rolls over to the starting address, and reading cycle keeps on infinitely. Because of the dedicated
function, RDTSd is not compatible to RDIO.
CS
0
1
2
3 4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
OP-CODE
SI
(IO0)
SO
(IO1)
0 1 1
1
1 0
Data Out
0 0 6
4
2 0 14 12 10 8 22 20 18 16 30 28 26 24
LSB
High-Z
7
5
LSB
3 1 15 13 11 9 23 21 19 17 31 29 27 25
MSB
Byte0
14
LSB
LSB
MSB
Byte1
MSB
Byte2
MSB
Byte3
Invalid
DS501-00031-1v1-E
MB85RDP16LX
• WRTSs (Single SO)
The WRTSs command can write the data related to the binary counter to FRAM memory cell array (see
“ MEMORY MAP”). WRTSs op-code is input to SI. No address bits are input. When 8 writing data bits
are input after the 8-bit op-code, data is encoded by a dedicated function and written to FRAM memory
cell array from the starting address “000H”. Risen CS will terminate the WRTSs command. However, if
you continue sending the writing data for 8 bits each before CS rising, it is possible to continue writing
with automatic address increment. When it reaches the most significant address, it rolls over to the
starting address, and writing cycle keeps on infinitely. Because of the dedicated function, WRTSs is not
compatible to WRITE.
CS
0
1
2
3 4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
OP-CODE
SI
0 0
1 1
1 1
Data In
1 1 7
6
5
4 3
2
1
0 15 14 13 12 11 10 9
MSB
Byte0
High-Z
SO
8
Invalid
LSB
LSB MSB
Byte1
• WRTSd (Dual IO)
The WRTSd command can write the data related to the binary counter to FRAM memory cell array (see
“ MEMORY MAP”). WRTSd op-code is input to SI(IO0). No address bits are input. When the 4 odd
writing data bits (D7, D5, D3, D1) are input to SO(IO1) and 4 even writing data bits (D6, D4, D2, D0) are
input to SI(IO0) after the 8-bit op-code, they are encoded by a dedicated function and written to FRAM
memory cell array from the starting address “000H”. Risen CS will terminate the WRTSd command.
However, if you continue sending the writing data for 8 bits each before CS rising, it is possible to
continue writing with automatic address increment. When it reaches the most significant address, it rolls
over to the starting address, and writing cycle keeps on infinitely. Because of the dedicated function,
WRTSd is not compatible to WDIO.
CS
0
1
2
3 4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
OP-CODE
SI
(IO0)
SO
(IO1)
0 1 1
1
1 1
Data In
1 1 6
4
2 0 14 12 10 8 22 20 18 16 30 28 26 24
LSB
High-Z
7
5
MSB
MSB
Byte1
MSB
Byte2
Invalid
LSB
3 1 15 13 11 9 23 21 19 17 31 29 27 25
Byte0
DS501-00031-1v1-E
LSB
LSB
Invalid
MSB
Byte3
15
MB85RDP16LX
 BLOCK PROTECT
Writing protect block for WRITE and WDIO commands are configured by the value of BP0 and BP1 in the
status register.
BP1
BP0
Protected Block
0
0
None
0
1
600H to 7FFH (upper 1/4)
1
0
400H to 7FFH (upper 1/2)
1
1
000H to 7FFH (all)
 WRITING PROTECT
Writing operation of WRITE, WDIO and WRSR commands are protected with the value of WEL, WPEN,
WP as shown in the table.
WEL
WPEN
WP
Protected Blocks
Unprotected Blocks
Status Register
0
X
X
Protected
Protected
Protected
1
0
X
Protected
Unprotected
Unprotected
1
1
0
Protected
Unprotected
Protected
1
1
1
Protected
Unprotected
Unprotected
Note: writing operation of POS0/1/2/3, DIBC/DDBC and WRTSs/WRTSd commands are not
protected.
16
DS501-00031-1v1-E
MB85RDP16LX
 MEMORY MAP for POS0/1/2/3
In case of using POS0/1/2/3 commands, 43-bit binary counter data (Counter(0) to Counter(42)), 3-bit
position data (PP, DIR and DIR’) and 2-bit error flag (Eflag(0) and Eflag(1)) are written to FRAM memory
cell array from the address “000H” to the address “005H”.
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
000H
Counter(5)
Counter(4)
Counter(3)
Counter(2)
Counter(1)
Counter(0)
DIR
PP
001H
Counter(13) Counter(12) Counter(11) Counter(10) Counter(9)
Counter(8)
Counter(7)
Counter(6)
002H
Counter(21) Counter(20) Counter(19) Counter(18) Counter(17) Counter(16) Counter(15) Counter(14)
003H
Counter(29) Counter(28) Counter(27) Counter(26) Counter(25) Counter(24) Counter(23) Counter(22)
004H
Counter(37) Counter(36) Counter(35) Counter(34) Counter(33) Counter(32) Counter(31) Counter(30)
005H
Eflag(1)
Eflag(0)
DIR’
Counter(42) Counter(41) Counter(40) Counter(39) Counter(38)
Note: the data of this memory map stored in FRAM memory cell array are encoded by a dedicated function
and also can be overwritten by WRTSs/WRTSd command and so on.
 ERROR FLAG for POS0/1/2/3
Unless 2-bit error flag (Eflag(1,0)) is “00”, the binary counter operation stops.
Eflag(1,0)
Status
“00”
Last operation normally completed.
“01”
Counter underflow/overflow and binary counter function stopped.
if counter(42:0) underflowed from 400_0000_0000H to 3FF_FFFF_FFFFH
if counter(42:0) overflowed from 3FF_FFFF_FFFFH to 400_0000_0000H
“10”
ECC error is detected but could not be corrected.
“11”
Last operation did not complete and counter function stopped.
Note: The above values of Eflag(1,0) are logical data. The specified commands (RDTSs/RDTSd) are
necessary to read the values because they encoded by a dedicated function.
 COUNTER VALUE UP/DOWN for POS0/1/2/3
The Eflag(1,0) are set to "01" when the max value 3FF_FFFF_FFFFH is increased by one and then the
new value becomes 400_0000_0000H or when the min value 400_0000_0000H is decreased by one and
then the new value becomes 3FF_FFFF_FFFFH. Therefore, next binary counter operation stops after the
counter overflowed.
Counter Value (hex)
3FF FFFF FFFF
3FF FFFF FFFE
3FF FFFF FFFD
…
000 0000 0002
000 0000 0001
000 0000 0000
7FF FFFF FFFF
7FF FFFF FFFE
…
400 0000 0002
400 0000 0001
400 0000 0000
DS501-00031-1v1-E
Counter Value (decimal)
sign
mantissa
+
242-1
+
242-2
+
242-3
+
…
+
2
+
1
+
0
1
2
…
242-2
242-1
242
17
MB85RDP16LX
 MEMORY MAP for DIBC/DDBC
In case of using DIBC/DDBC commands, 46-bit binary counter data (Counter(0) to Counter(45)) and 2-bit
error flag (Eflag(0) and Eflag(1)) are written to FRAM memory cell array from the address “000H” to the
address “005H”.
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
000H
Counter(7)
Counter(6)
Counter(5)
Counter(4)
Counter(3)
Counter(2)
Counter(1)
Counter(0)
001H
Counter(15) Counter(14) Counter(13) Counter(12) Counter(11) Counter(10) Counter(9)
Counter(8)
002H
Counter(23) Counter(22) Counter(21) Counter(20) Counter(19) Counter(18) Counter(17) Counter(16)
003H
Counter(31) Counter(30) Counter(29) Counter(28) Counter(27) Counter(26) Counter(25) Counter(24)
004H
Counter(39) Counter(38) Counter(37) Counter(36) Counter(35) Counter(34) Counter(33) Counter(32)
005H
Eflag(1)
Eflag(0)
Counter(45) Counter(44) Counter(43) Counter(42) Counter(41) Counter(40)
Note: the data of this memory map stored in FRAM memory cell array are encoded by a dedicated
function and also can be overwritten by WRTSs/WRTSd command and so on.
 ERROR FLAG for DIBC/DDBC
Unless 2-bit error flag (Eflag(1,0)) is “00”, the binary counter operation stops.
Eflag(1,0)
Status
“00”
Last operation normally completed.
“01”
Counter underflow/overflow and binary counter function stopped.
if counter(45:0) underflowed from 2000_0000_0000H to 1FFF_FFFF_FFFFH
if counter(45:0) overflowed from 1FFF_FFFF_FFFFH to 2000_0000_0000H
“10”
ECC error is detected but could not be corrected.
“11”
Last operation did not complete and counter function stopped.
Note: The above values of Eflag(1,0) are logical data. The specified commands (RDTSs/RDTSd) are
necessary to read the values because they need to be encoded by a dedicated function.
 COUNTER VALUE UP/DOWN for DIBC/DDBC
The Eflag(1,0) are set to "01" when the max value 1FFF_FFFF_FFFFH is increased by one and then the
new value becomes 2000_0000_0000H or when the min value 2000_0000_0000H is decreased by one
and then the new value becomes 1FFF_FFFF_FFFFH. Therefore, next binary counter operation stops
after the counter overflowed.
Counter Value (hex)
1FFF FFFF FFFF
1FFF FFFF FFFE
1FFF FFFF FFFD
…
0000 0000 0002
0000 0000 0001
0000 0000 0000
3FFF FFFF FFFF
3FFF FFFF FFFE
…
2000 0000 0002
2000 0000 0001
2000 0000 0000
18
Counter Value (decimal)
sign
mantissa
+
245-1
+
245-2
+
245-3
+
…
+
2
+
1
+
0
1
2
…
245-2
245-1
245
DS501-00031-1v1-E
MB85RDP16LX
 ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Min
Max
Unit
Power supply voltage*
VDD
− 0.5
+ 2.5
V
Input voltage*
VIN
− 0.5
VDD + 0.5
V
VOUT
− 0.5
VDD + 0.5
V
TA
− 40
+ 105
°C
Tstg
− 55
+ 125
°C
Output voltage*
Operation ambient temperature
Storage temperature
*: These parameters are based on the condition that VSS is 0 V.
WARNING: Semiconductor devices may be permanently damaged by application of stress (including,
without limitation, voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
 RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Power supply voltage*1
Operation ambient temperature
VDD
*2
TA
Value
Unit
Min
Typ
Max
1.65
1.8
1.95
V
⎯
+ 105
°C
− 40
*1: These parameters are based on the condition that VSS is 0 V.
*2: Ambient temperature when only this device is working. Please consider it to be the almost same as the
package surface temperature.
WARNING: The recommended operating conditions are required in order to ensure the normal operation
of the semiconductor device. All of the device's electrical characteristics are warranted when
the device is operated under these conditions.
Operation under any conditions other than these conditions may adversely affect reliability of
device and could result in device failure.
No warranty is made with respect to any use, operating conditions or combinations not
represented on this data sheet. If you are considering application under any conditions other
than listed herein, please contact sales representatives beforehand.
DS501-00031-1v1-E
19
MB85RDP16LX
 ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(within recommended operating conditions)
Parameter
Input leakage current
Symbol
|ILI|
Value
Condition
Unit
Min
Typ
Max
CS = VDD
⎯
⎯
1
WP, SCK,
SI = 0 V to VDD
⎯
⎯
1
μA
Output leakage current
|ILO|
SO = 0 V to VDD
⎯
⎯
1
μA
Operating power supply current
IDD
SCK = 15 MHz
⎯
⎯
0.7
mA
Standby current
ISB
SCK = SI = CS = VDD
⎯
1 (25 )
11 (105 )
6 (85 )
μA
Input high voltage
VIH
VDD = 1.65 to 1.95 V
VDD × 0.8
⎯
VDD + 0.3
V
Input low voltage
VIL
VDD = 1.65 to 1.95 V
− 0.5
⎯
VDD × 0.2
V
Output high voltage
VOH
IOH = −2 mA
VDD − 0.5
⎯
VDD
V
Output low voltage
VOL
IOL = 2 mA
VSS
⎯
0.4
V
20
DS501-00031-1v1-E
MB85RDP16LX
2. AC Characteristics
Parameter
Symbol
Value
Min
Max
Unit
SCK clock frequency for SPI
fCK
⎯
15
MHz
Clock high time for SPI
tCH
33
⎯
ns
ns
Clock low time for SPI
tCL
33
⎯
SCK clock frequency for Dual SPI
fCK
⎯
7.5
MHz
Clock high time for Dual SPI
tCH
66
⎯
ns
Clock low time for Dual SPI
tCL
66
⎯
ns
SCK clock frequency for the dummy clocks of
POS0/1/2/3 or DIBC/DDBC commands
(the interval between the commands < 3us)
fDCK
⎯
2
MHz
SCK clock frequency for the dummy clocks of
POS0/1/2/3 or DIBC/DDBC commands
(the interval between the commands
3us)
fDCK
⎯
5
MHz
Clock high time for the dummy clocks of
POS0/1/2/3 or DIBC/DDBC commands
tCH
50
⎯
ns
Clock low time for the dummy clocks of
POS0/1/2/3 or DIBC/DDBC commands
tCL
50
⎯
ns
Chip select set up time
tCSU
10
⎯
ns
Chip select hold time
tCSH
10
⎯
ns
Output disable time
tOD
⎯
20
ns
Output data valid time
tODV
⎯
18
ns
ns
Output hold time
tOH
0
⎯
Deselect time
tD
30
⎯
ns
Data rising time
tR
⎯
50
ns
Data falling time
tF
⎯
50
ns
ns
ns
Data set up time
tSU
5
⎯
Data hold time
tH
5
⎯
AC Test Condition
Power supply voltage
Operation ambient temperature
Input voltage magnitude
Input rising time
Input falling time
Input judge level
Output judge level
DS501-00031-1v1-E
: 1.65 V to 1.95 V
: − 40 °C to + 105 °C
: 0.3 V to 1.65 V
: 5 ns
: 5 ns
: VDD/2
: VDD/2
21
MB85RDP16LX
AC Load Equivalent Circuit
1.8 V
1.2 k
Output
30 pF
0.95 k
3. Pin Capacitance
Parameter
Symbol
Output capacitance
CO
Input capacitance
CI
22
Value
Conditions
VDD = VIN = VOUT = 0 V
f = 1 MHz, TA = + 25 °C
Unit
Min
Max
⎯
4
pF
⎯
4
pF
DS501-00031-1v1-E
MB85RDP16LX
 TIMING DIAGRAM
• Serial Data Timing
DS501-00031-1v1-E
23
MB85RDP16LX
 POWER ON/OFF SEQUENCE
tpd
trs
trh
tr
tf
tpu
VDD
VDD
RST
RST
1.65 V
1.65 V
VIH (Min)
VIH (Min)
1.0 V
1.0 V
VIL (Max)
VIL (Max)
GND
GND
CS
CS >VDD × 0.8 *
CS : don't care
CS >VDD × 0.8 *
CS
* : CS (Max) < VDD + 0.3 V
Parameter
Symbol
Value
Min
Max
Unit
CS and RST level hold time at power OFF
tpd
400
⎯
ns
RST high to first access start
tpu
1
⎯
μs
Power supply falling time
tf
3
⎯
μs
Power supply rising time
tr
3
⎯
μs
RST setup time to VDD(min) at power OFF
trs
0
μs
RST hold time after VDD(min) at power ON
trh
1
μs
If the device does not operate within the specified conditions of read cycle, write cycle or power on/off
sequence, memory data can not be guaranteed.
24
DS501-00031-1v1-E
MB85RDP16LX
 FRAM CHARACTERISTICS
Item
Min
Max
Read/Write Endurance*1
1013
⎯
10
⎯
Data Retention*2
Unit
Parameter
Times/byte Operation Ambient Temperature TA = + 105 °C
Years
Operation Ambient Temperature TA = + 105 °C
*1 : Total number of reading and writing defines the minimum value of endurance, as an FRAM memory operates
with destructive readout mechanism.
*2 : Minimum values define retention time of the first reading/writing data right after shipment, and these values
are calculated by qualification results.
 NOTE ON USE
We recommend programming of the device after reflow. Data written before reflow cannot be guaranteed.
DS501-00031-1v1-E
25
MB85RDP16LX
 ESD AND LATCH-UP
Test
ESD HBM (Human Body Model)
JESD22-A114 compliant
ESD MM (Machine Model)
JESD22-A115 compliant
ESD CDM (Charged Device Model)
JESD22-C101 compliant
Latch-Up (I-test)
JESD78 compliant
Latch-Up (Vsupply overvoltage test)
JESD78 compliant
Latch-Up (Current Method)
Proprietary method
Latch-Up (C-V Method)
Proprietary method
DUT
Value
≥ |2000 V|
≥ |200 V|
―
―
MB85RDP16LXPN-G-AMEWE1
―
―
≥ |200 V|
Current method of Latch-Up Resistance Test
Protection Resistor
A
IIN
VIN
Test terminal
VDD
+
DUT
-
VSS
VDD
(Max. Rating)
V
Reference
terminal
Note: The voltage VIN is increased gradually and the current IIN of 300 mA at maximum shall flow. Confirm
the latch up does not occur under IIN =±300 mA.
In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be
increased to the level that meets the specific requirement.
26
DS501-00031-1v1-E
MB85RDP16LX
C-V method of Latch-Up Resistance Test
Protection Resistor
A
1
Test
2 terminal
SW
+
VIN
V
-
C
200pF
VDD
DUT
VDD
(Max. Rating)
VSS
Reference
terminal
Note: Charge voltage alternately switching 1 and 2 approximately 2 sec intervals. This switching process is
considered as one cycle.
Repeat this process 5 times. However, if the latch-up condition occurs before completing 5times, this
test must be stopped immediately.
 REFLOW CONDITIONS AND FLOOR LIFE
[ JEDEC MSL ] : Moisture Sensitivity Level 3 (ISP/JEDEC J-STD-020D)
 CURRENT STATUS ON CONTAINED RESTRICTED SUBSTANCES
This product complies with the regulations of REACH Regulations, EU RoHS Directive and
China RoHS.
DS501-00031-1v1-E
27
MB85RDP16LX
 ORDERING INFORMATION
Part number
MB85RDP16LXPN-G-AMEWE1
28
Package
8-pin, plastic SON
(LCC-8P-M04)
Shipping form
Minimum shipping
quantity
Embossed Carrier tape
1500
DS501-00031-1v1-E
MB85RDP16LX
 PACKAGE DIMENSION
8-pin plastic SON
Lead pitch
0.5 mm
Package width ×
package length
2.0 mm × 3.0 mm
Sealing method
Plastic mold
Mounting height
0.75 mm MAX
Weight
0.015g
(LCC-8P-M04)
8-pin plastic SON
(LCC-8P-M04)
1.6±0.10
(.063±.004)
2.00±0.07
(.079±.003)
0.40±0.07
(.016±.003)
3.00±0.07
(.118±.003)
1.40±0.10
(.055±.004)
INDEX AREA
1PIN CORNER
(C0.30(C.012))
0.50(.020)
TYP
0.05(.002) MAX
C
0.70±0.05
(.028±.002)
0.15(.006)
2011 FUJITSU SEMICONDUCTOR LIMITED HMbC8-04Sc-1-1
DS501-00031-1v1-E
0.25±0.05
(.010±.002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
29
MB85RDP16LX
 MARKING
[MB85RDP16LXPN-G-AMEWE1]
YYWW
P16X
0XX
[LCC-8P-M04]
30
DS501-00031-1v1-E
MB85RDP16LX
 MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
Change Results
26
27
29
 ESD AND LATCH-UP
 CURRENT STATUS ON CONTAINED
RESTRICTED SUBSTANCES
 PACKAGE DIMENSIONS
DS501-00031-1v1-E
Revised part number.
Deleted the URL info.
Deleted the URL info.
31
MB85RDP16LX
FUJITSU SEMICONDUCTOR LIMITED
Shin-Yokohama Chuo Building, 2-100-45 Shin-Yokohama,
Kohoku-ku, Yokohama, Kanagawa 222-0033, Japan
http://jp.fujitsu.com/fsl/en/
All Rights Reserved.
FUJITSU SEMICONDUCTOR LIMITED, its subsidiaries and affiliates (collectively, "FUJITSU SEMICONDUCTOR")
reserves the right to make changes to the information contained in this document without notice. Please contact your
FUJITSU SEMICONDUCTOR sales representatives before order of FUJITSU SEMICONDUCTOR device.
Information contained in this document, such as descriptions of function and application circuit examples is presented
solely for reference to examples of operations and uses of FUJITSU SEMICONDUCTOR device. FUJITSU
SEMICONDUCTOR disclaims any and all warranties of any kind, whether express or implied, related to such
information, including, without limitation, quality, accuracy, performance, proper operation of the device or
non-infringement. If you develop equipment or product incorporating the FUJITSU SEMICONDUCTOR device based on
such information, you must assume any responsibility or liability arising out of or in connection with such information or
any use thereof. FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any damages whatsoever arising
out of or in connection with such information or any use thereof.
Nothing contained in this document shall be construed as granting or conferring any right under any patents, copyrights, or
any other intellectual property rights of FUJITSU SEMICONDUCTOR or any third party by license or otherwise, express
or implied. FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any infringement of any intellectual
property rights or other rights of third parties resulting from or in connection with the information contained herein or use
thereof.
The products described in this document are designed, developed and manufactured as contemplated for general use
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless
extremely high levels of safety is secured, could lead directly to death, personal injury, severe physical damage or other
loss (including, without limitation, use in nuclear facility, aircraft flight control system, air traffic control system, mass
transport control system, medical life support system and military application), or (2) for use requiring extremely high
level of reliability (including, without limitation, submersible repeater and artificial satellite). FUJITSU
SEMICONDUCTOR shall not be liable for you and/or any third party for any claims or damages arising out of or in
connection with above-mentioned uses of the products.
Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs
and safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures
into your facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and
other abnormal operating conditions.
The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade
Control Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are
responsible for ensuring compliance with such laws and regulations relating to export or re-export of the products and
technical information described herein.
All company names, brand names and trademarks herein are property of their respective owners.
Edited: System Memory Business Division