148KB - Fujitsu

FUJITSU SEMICONDUCTOR
FACT SHEET
NP412-00001-1v0-E
FRAM Authentication IC
MB94R330
MB94R330 is an FRAM (Ferroelectric Random Access Memory) authentication IC using the ferroelectric process
and silicon gate CMOS process technologies for forming the nonvolatile memory cells.
MB94R330 adopts an original communication protocol based on the two-wire serial interface (I2C BUS),
a hardware cryptographic macro and a proprietary control core.
MB94R330 is suitable for detecting cloned peripherals and accessories which is used in an electric
equipment such as a printer, multifunction printer and so on. The Challenge and Response authentication
between the host system and the peripheral enables to identify between authorized and unauthorized parts.
■ FEATURES
 Authentication algorithm
■ ORDERING INFORMATION
・Challenge & Response
(using pseudo random numbers generated by a hardware)
・Message Authentication Code [MAC]
(generated by a hardware cryptographic macro and
a proprietary control core)
Part number
Package
Plastic・SON,8-pins
 Life cycle
MB94R330PN
・4 types of life cycle (shipping, personalization,
operation and destruction)
・Dedicated command group for life cycle
・Change of life cycle to one direction by change command
(LCC-8P-M04)
2.0mm×3.0mm, 0.5mm pitch
 Memory configuration
・Free access area (112 bytes)
・Resouce counter area (4 bytes × 8 slot)
・Protected area (8 bytes × 4 slot)
・ID area (8 bytes × 4 slot)
・One Time Write area (8 bytes × 2 slot)
・Other control information
■ PACKAGE EXAMPLE OF REFERENCE
 Interface
・Two wire serial interface (I2C bus)
・Up to 8 slaves are connected to one host devices
・Two types of slave address definition; by external
address pins, or slave address data stored in FRAM
 Comunication frequency
Maximum serial clock (SCL) frequency 400kHz
 Power supply voltage :3.0V to 3.6V
 Operating ambient temperature :-20℃ to +85℃
 FRAM data retention
10 years (Operating ambient temperature=+75℃,
after Rewriting/reading times=1)
 FRAM read/write endurance
1012 times (Operating ambient temperature=+85℃,
Total rewriting/reading times)
 Active shield
If it detects probing and physical processing
to the authentication IC, it deletes the internal memory
data and change to destruction phase.
In destruction phase, no processing of command or response.
 Low voltage detection circuit
It monitors variation such as increase or decrease of
the power supply voltage, and generates and releases
a reset signal within an IC.
Release level 2.5V
([email protected] ambient temperature=+25℃)
Detection level 2.35V
([email protected] ambient temperature=+25℃)
 Consumption power :Operating current 500μA (Typ)
March 2012
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Copyright©2011-2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
Plastic ・ SON、8-pins
(LCC-8P-M04)
MB94R330
■ PIN ASSIGNMENT
Pin No.
Pin name
Description
Address pins
MB94R330 can be connected up to 8 devices on the same
data bus. Addresses are used in order to identify each
of the devices. Connect these pins to VDD or VSS
externally to specify an address. When the specified
address matches a slave address code inputted from the
SDA pin, the device specified by the address can
operate. In the open pin state, A0, A1, and A2 pins are
internally pulled-down in an IC and recognized as
“L”. In this case, slave address data stored in FRAM
is given priority and is used to identify the device.
(TOP VIEW)
A0
1
8
VDD
A1
2
7
NC
A2
3
6
SCL
VSS
4
5
SDA
1 to 3
A0 to A2
4
VSS
Ground pin
Serial data I/O pin
5
This is an I/O pin for performing bidirectional
communication of data. It is possible to connect up to
8 devices. It is an open drain output, so a pull-up
resistance is required to be connected to the external
circuit.
SDA
Serial clock pin
(LCC-8P-M04)
This is a bidirectional I/O pin for clock of serial data
I/O timing. Data is read on the rising edge of the clock
and output on the falling edge. It is an open drain
output, so a pull-up resistance is required to be
connected to the external circuit.
6
SCL
7
NC
Unused pin
8
VDD
Power supply pin
Leave it open.
■ BLOCKDIAGRAM
FRAM
•Free access area
•Resource counter area
•Protected area
•ID area
•One Time Write area
•Other control information
Core Circuit
•Command processing
•Life cycle control
•Challenge and response
•Message authentication
Device
Control Circuit
code generation
Low Voltage
Detection Circuit
A0
A1
A2
Active Shield Circuit
2
I C-BUS
Interface
Control Circuit
SCL
SDA
NP412-00001-1v0-E
March 2012
2/2
Copyright©2011-2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved