AK4620B Japanese Datasheet

ASAHI KASEI
[AK4620B]
AK4620B
24-Bit 192kHz Audio CODEC with IPGA
AK4620B
192kHz
24bit CODEC
DAC
ADC
(SCF)
AK4620B
PGA
, DVTR
• 24-bit 2-channel ADC
- Selectable Single-ended or Differential Input
- High Performance Linear Phase Digital Anti-Alias Filter
Passband: 0 ~ 20.25kHz (@fs=44.1kHz)
Ripple: ± 0.005dB
Stopband Attenuation: 100dB
- S/(N+D): 90dB (single-ended)
100dB (differential)
- S/N: 110dB (single-ended)
113dB (differential)
- Digital High-pass Filter for Offset Cancellation
- Input PGA: 0dB to +18dB, 0.5dB/step (for single-ended input)
- Input Digital Attenuator: 0dB to – 63dB, 0.5dB/step
- Overflow Flag
2
- Audio Interface Format: MSB justified or I S
• 24-bit 2-channel DAC
- 24-bit 8 times Oversampling Linear Phase Digital Filter
Ripple: ±0.005dB
Stopband Attenuation: 75dB
- Switched-cap Low Pass Filter
- Differential Outputs
- S/(N+D): 97dB
- S/N: 115dB
- De-emphasis for 32kHz, 44.1kHz, 48kHz Sampling
- Output Digital Attenuator: Linear 255 steps
- Soft Mute
- Zero Detection Function
2
- Audio interface format: MSB justified, LSB justified, I S, or DSD
• High Jitter Tolerance
• Sampling Rate: Up to 216kHz
• µP Interface: 3-wire Serial Interface
• Master Clock
- 128fs/192fs/256fs/384fs/512fs/768fs/1024fs
• Power Supply: 5V ± 5%(Analog), 3V~3.6V with 5V tolerant I/O(Digital)
• Small 30-pin VSOP package
• Ta: -10 to 70 °C
MS0401-J-00
2005/07
-1-
ASAHI KASEI
[AK4620B]
„ Block Diagram
ADMODE
VD
VT
DGND
AINL+
AINL-/NC
ADC
DATT
HPF
PDN
AINR+
AINR-/NC
OVF
OVFL/DZFL
Audio I/F
Controller
OVFR/DZFR
LRCK
BICK
SDTO
SDTI
MCLK
DFS0
AOUTL+
AOUTLAOUTR+
AOUTR-
DATT
SMUTE
DAC
Control Register I/F
VCOM
VREF
VA
AGND
DEM0
CSN/
DIF
CCLK/
CKS1
P/S
CDTI/
CKS0
Figure 1. Block Diagram
„ Compatibility with AK4528 / AK4524
Function
Max fs
ADC Inputs
Input analog PGA
Input digital ATT
ADC S/(N+D)
ADC DR, S/N
ADC Digital Filter SA
ADC Overflow detection
DAC S/(N+D)
DAC DR, S/N
Output digital Attenuator
DAC DSD mode
DAC Zero-data detection
X’tal Oscillating Circuit
Master Mode
Parallel Mode
AK4524
96kHz
Single-ended
0dB ~ +18dB
0.5dB/step
Mute, -72dB ~ 0dB
Pseudo-log step
90dB
100dB
75dB
94dB
110dB
Mute, -72dB ~ 0dB
Pseudo-log step
X
X
-
AK4528
108kHz
Differential
Mute, -72dB ~ 0dB
Pseudo-log step
94dB
108dB
75dB
94dB
110dB
Mute, -72dB ~ 0dB
Pseudo-log step
X
MS0401-J-00
AK4620B
216kHz
Single-ended
Differential
0 ~ +18dB
0.5dB/step
Mute,-63.5dB ~ 0dB Mute,-63.5dB ~ 0dB
0.5dB/step
0.5dB/step
90dB
100dB
110dB
113dB
100dB
X
97dB
115dB
Mute, -48dB ~ 0dB Mute, -48dB ~ 0dB
Linear 256 steps
Linear 256 steps
X
X
X
X: Available, -: NOT available
2005/07
-2-
ASAHI KASEI
[AK4620B]
„
AK4620BVF
AKD4620B
−10 ∼ +70°C
AK4620B
30pin VSOP 0.65mm pitch
„
VCOM
1
30
AOUTR+
AINR+
2
29
AOUTR-
AINR-/NC
3
28
AOUTL+
AINL+
4
27
AOUTL-
AINL-/NC
5
26
DGND
VREF
6
25
VD
AGND
7
24
VT
VA
8
23
ADMODE
P/S
9
22
DEM0
MCLK
10
21
PDN
LRCK/DSDR
11
20
DFS0
BICK/DCLK
12
19
CSN/DIF
SDTO
13
18
CCLK/CKS1
SDTI/DSDL
14
17
CDTI/CKS0
OVFR/DZFR
15
16
OVFL/DZFL
Top
View
MS0401-J-00
2005/07
-3-
ASAHI KASEI
No.
Pin Name
[AK4620B]
I/O
Function
1
VCOM
O
2
AINR+
I
I
3
AINR-
4
AINL+
5
AINL-
6
VREF
I
7
8
AGND
VA
-
9
P/S
I
10
MCLK
LRCK
DSDR
BICK
DCLK
SDTO
SDTI
DSDL
OVFR
DZFR
OVFL
DZFL
I
I
I
I
I
O
I
I
O
O
O
O
Common Voltage Output Pin, VA/2
Bias voltage of ADC inputs and DAC outputs.
Rch Positive Input Pin
Rch Negative Input Pin (when ADMODE pin=“H”)
No Connect pin (when ADMODE pin=“L”)
No internal bonding. This pin should be open.
Lch Positive Input Pin
Lch Negative Input Pin (when ADMODE pin=“H”)
No Connect pin (when ADMODE pin=“L”)
No internal bonding. This pin should be open.
Voltage Reference Input Pin, VA
Used as a voltage reference by ADC & DAC. VREF is connected externally to filtered
VA.
Analog Ground Pin
Analog Power Supply Pin, 4.75 ∼ 5.25V
Parallel/Serial Mode Select Pin
“L”: Serial Mode, “H”: Parallel Mode
Do not change this pin during PDN pin = “H”.
Master Clock Input Pin
Input/Output Channel Clock Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)
DSD Rch Data Input Pin (when D/P bit=“1” in Serial Mode)
Audio Serial Data Clock Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)
DSD Clock Pin (when D/P bit=“1” in Serial Mode)
Audio Serial Data Output Pin
Audio Serial Data Input Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)
DSD Lch Data Input Pin (when D/P bit=“1” in Serial Mode)
Rch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)
Rch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)
Lch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)
Lch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)
CDTI
CKS0
CCLK
CKS1
I
I
I
I
Control Data Input Pin (in Serial Mode)
Master Clock Select Pin (in Parallel Mode)
Control Data Clock Pin (in Serial Mode)
Master Clock Select Pin (in Parallel Mode)
CSN
I
Chip Select Pin in Serial Mode (in Serial Mode)
DIF
I
20
DFS0
I
21
PDN
I
22
DEM0
I
23
ADMODE
I
11
12
13
14
15
16
17
18
19
I
I
I
I
Digital Audio Interface Select Pin (in Parallel Mode)
“L”: 24bit MSB justified, “H”: I2S compatible
Double Speed Sampling Mode Pin
Power-Down Mode Pin
“L”: Power down reset and initialize the control register, “H”: Power up
De-emphasis Control Pin
Analog Input Mode Select Pin
“L”: Single-ended Input & IPGA Enable
“H”: Differential Input & IPGA Bypass
MS0401-J-00
2005/07
-4-
ASAHI KASEI
[AK4620B]
(
24
25
26
27
28
29
30
VT
VD
DGND
AOUTLAOUTL+
AOUTRAOUTR+
O
O
O
O
)
Input Buffer Tolerant Pin, 3.0 ∼ 5.25V
Digital Power Supply Pin, 3.0 ∼ 3.6V
Digital Ground Pin
Lch Negative Analog Output Pin
Lch Positive Analog Output Pin
Rch Negative Analog Output Pin
Rch Positive Analog Output Pin
Note: Do not allow digital input pins (P/S, MCLK, LRCK/DSDR, BICK/DCLK, SDTI/DSDL, CDTI/CKS0,
CCLK/CKS1, CSN/DIF, DFS0, PDN, DEM0 and ADMODE pins) to float.
„
Classification
Analog Input
Pin Name
AINL+, AINL-/NC, AINR+, AINR+NC
AINL+, AINL-/NC
AINR+, AINR-/NC
Analog Output
Digital Input
Digital Output
AOUTL+, AOUTL-, AOUTR+,
AOUTRDEM0
OVFL/DZFL, OVFR/DZFR
Setting
ADMODE pin = “L”
ADMODE pin = “H”
pin
ADMODE pin = “H”
pin
AINL+ pin
AINL-/NC
AINR+ pin
AINR-/NC
DVSS
MS0401-J-00
2005/07
-5-
ASAHI KASEI
[AK4620B]
(AGND, DGND=0V; Note 1)
Parameter
Power Supplies:
Analog
Digital
Input Tolerant
|AGND – DGND|
(Note 2)
Input Current, Any Pin Except Supplies
Analog Input Voltage
(Note 3)
Digital Input Voltage
(Note 4)
Ambient Temperature (powered applied)
Storage Temperature
Symbol
VA
VD
VT
∆GND
IIN
VINA
VIND
Ta
Tstg
min
-0.3
-0.3
-0.3
-0.3
-0.3
-10
-65
max
6.0
6.0
6.0
0.3
±10
VA+0.3
VT+0.3
70
150
Units
V
V
V
V
mA
V
V
°C
°C
Note 1.
Note 2. AGND DGND
Note 3. AINL+, AINL-/NC, AINR+ and AINR-/NC pins
Note 4. P/S, MCLK, LRCK/DSDR, BICK/DCLK, SDTI/DSDL, CDTI/CKS0, CCLK/CKS1, CSN/DIF, DFS0, PDN,
DEM0 and ADMODE pins.
:
AGND, DGND=0V; Note 1
Parameter
Power Supplies
Analog
(Note 5) Digital
Input Tolerant
Voltage Reference
Symbol
VA
VD
VT
VREF
min
4.75
3.0
VD
3.0
typ
5.0
3.3
5.0
-
max
5.25
3.6
5.25
VA
Units
V
V
V
V
Note 5: VA, VD, VT
:
MS0401-J-00
2005/07
-6-
ASAHI KASEI
[AK4620B]
ANALOG CHARACTERISTICS (ADC: Single-ended Input)
(Ta=25°C; VA=5V, VD=3.3V, VT=5V; AGND=DGND=0V; VREF=VA; fs=44.1kHz; Signal Frequency =1kHz; 24bit
Data; Measurement frequency=20Hz ∼ 20kHz at fs=44.1kHz, 40Hz ∼ 40kHz at fs=96kHz, 40Hz ∼ 40kHz at fs=192kHz;
unless otherwise specified)
Parameter
min
typ
max
Units
Input PGA Characteristics:
Input Voltage
(Note 6)
2.77
3.07
3.37
Vpp
Input Resistance
(Note 7)
0.7
5.1
kΩ
Step Size
0.2
0.5
0.8
dB
Gain Control Range
0
18
dB
ADC Analog Input Characteristics: IPGA=0dB
Resolution
24
Bits
S/(N+D)
fs=44.1kHz
-1dBFS
80
90
dB
BW=20kHz
-60dBFS
47
dB
fs=96kHz
-1dBFS
90
dB
BW=40kHz
-60dBFS
44
dB
fs=192kHz
-1dBFS
90
dB
BW=40kHz
-60dBFS
44
dB
Dynamic Range
(-60dBFS with A-weighted)
110
dB
S/N
(A-weighted)
101
110
dB
Interchannel Isolation
90
105
dB
Interchannel Gain Mismatch
0.2
0.5
dB
Gain Drift
150
ppm/°C
Power Supply Rejection
(Note 8)
50
dB
ANALOG CHARACTERISTICS (ADC: Differential Input)
(Ta=25°C; VA=5V, VD=3.3V, VT=5V; AGND=DGND=0V; VREF=VA; fs=44.1kHz; Signal Frequency =1kHz; 24bit
Data; Measurement frequency=20Hz ∼ 20kHz at fs=44.1kHz, 40Hz ∼ 40kHz at fs=96kHz, 40Hz ∼ 40kHz at fs=192kHz;
unless otherwise specified)
Parameter
min
typ
max
Units
ADC Analog Input Characteristics:
Resolution
24
Bits
Input Voltage
(Note 9)
±2.62
±2.82
±3.02
Vpp
Input Resistance
fs=44.1kHz
8
14
kΩ
fs=48kHz
13
kΩ
fs=96kHz
13
kΩ
fs=192kHz
13
kΩ
S/(N+D)
fs=44.1kHz
-1dBFS
90
100
dB
BW=20kHz
-60dBFS
50
dB
fs=96kHz
-1dBFS
100
dB
BW=40kHz
-60dBFS
46
dB
fs=192kHz
-1dBFS
100
dB
BW=40kHz
-60dBFS
46
dB
Dynamic Range
(-60dBFS with A-weighted)
113
dB
S/N
(A-weighted)
103
113
dB
Interchannel Isolation
90
120
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Gain Drift
20
ppm/°C
Power Supply Rejection
(Note 8)
50
dB
MS0401-J-00
2005/07
-7-
ASAHI KASEI
[AK4620B]
Note 6. IPGA=0dB
(0dB)
VREF
Vin(typ) = 3.07Vpp x VREF/5.
Note 7.
IPGA
IPGA=0dB; typ. 5.1kΩ, IPGA=+18dB; typ. 1.18kΩ
Note 8. VREF pin
VA, VD, VT 1kHz, 50mVpp
Note 9.
(0dB). Vin (typ) = ±2.82Vpp x VREF/5.
ANALOG CHARACTERISTICS (DAC)
(Ta=25°C; VA=5V, VD=3.3V, VT=5V; AGND=DGND=0V; VREF=VA; fs=44.1kHz; Signal Frequency =1kHz; 24bit
Data; Measurement frequency=20Hz ∼ 20kHz at fs=44.1kHz, 40Hz ∼ 40kHz at fs=96kHz, 40Hz ∼ 40kHz at fs=192kHz;
unless otherwise specified)
DAC Analog Output Characteristics:
Parameter
min
typ
max
Units
Resolution
24
Bits
Dynamic Characteristics
S/(N+D)
0dBFS
87
97
dB
fs=44.1kHz
BW=20kHz
52
dB
−60dBFS
0dBFS
97
dB
fs=96kHz
BW=40kHz
49
dB
−60dBFS
0dBFS
97
dB
fs=192kHz
BW=40kHz
49
dB
−60dBFS
Dynamic Range (−60dBFS with A-weighted) (Note 10, Note 11)
115
dB
S/N
(A-weighted) (Note 11, Note 12)
107
115
dB
Interchannel Isolation (1kHz)
90
110
dB
DC Accuracy
Interchannel Gain Mismatch
0.15
0.3
dB
Gain Drift
(Note 13)
20
ppm/°C
Output Voltage
(Note 14)
±2.6
±2.8
±3.0
Vpp
Load Capacitance
25
pF
Load Resistance
(Note 15)
3
kΩ
Note 10. 100dB at 16bit data and 114dB at 20bit data.
Note 11. Figure 19. External LPF Circuit Example 2 for PCM
Note 12. S/N
bit
Note 13. VREF
+5V
Note 14.
VREF
AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = 5.6Vpp x VREF/5.
Note 15. AC
Parameter
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
VA: ADC Single-ended Mode
ADC Differential Mode
VD+VT (fs=44.1kHz)
(fs=96kHz)
(fs=192kHz)
Power-down mode (PDN pin = “L”)
VA
VD+VT
Note 16.
min
typ
max
Units
60
55
11
21
27
90
83
41
mA
mA
mA
mA
mA
10
10
100
100
µA
µA
(Note 16)
VT or DGND
MS0401-J-00
2005/07
-8-
ASAHI KASEI
[AK4620B]
ADC
(fs=44.1kHz)
(Ta=25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; Normal Speed Mode)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 17) −0.005dB
PB
0
−0.02dB
20.25
−0.06dB
20.4
−6.0dB
22.05
Stopband
(Note 17)
SB
24.3
Passband Ripple
PR
Stopband Attenuation
SA
100
Group Delay
(Note 18)
GD
43.2
Group Delay Distortion
∆GD
0
ADC Digital Filter (HPF):
Frequency Response (Note 17) −3dB
FR
0.9
−0.1dB
6.0
ADC
(fs=96kHz)
(Ta=25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; Double Speed Mode)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 17) −0.005dB
PB
0
−0.02dB
44.08
−0.06dB
44.5
−6.0dB
48.0
Stopband
(Note 17)
SB
53.0
Passband Ripple
PR
Stopband Attenuation
SA
100
Group Delay
(Note 18)
GD
43.1
Group Delay Distortion
∆GD
0
ADC Digital Filter (HPF):
Frequency Response (Note 17) −3dB
FR
2.0
−0.1dB
13.0
max
Units
19.8
-
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
±0.005
Hz
Hz
max
Units
43.0
-
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
±0.005
ADC
(fs=192kHz)
(Ta=25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; Quad Speed Mode)
Parameter
Symbol
min
typ
max
ADC Digital Filter (Decimation LPF):
PB
0
86.0
Passband
(Note 17) −0.005dB
−0.02dB
88.18
89.0
−0.06dB
96.0
−6.0dB
Stopband
(Note 17)
SB
106.0
Passband Ripple
PR
±0.005
Stopband Attenuation
SA
100
Group Delay
(Note 18)
GD
38.2
Group Delay Distortion
∆GD
0
ADC Digital Filter (HPF):
Frequency Response (Note 17) −3dB
FR
4.0
−0.1dB
26.0
Note 17:
fs(
)
1kHz
Note 18:
ADC
.
MS0401-J-00
Hz
Hz
Units
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
Hz
Hz
24bit
2005/07
-9-
ASAHI KASEI
[AK4620B]
DAC
(fs = 44.1kHz)
(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 44.1kHz; Normal Speed Mode; DEM = OFF;
SLOW = “0”)
Parameter
Symbol
min
typ
max
Units
PB
0
24.1
22.05
20.0
-
Digital Filter
Passband
±0.01dB
-6.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 19)
(Note 19)
(Note 20)
SB
PR
SA
GD
75
-
28
-
kHz
kHz
kHz
dB
dB
1/fs
-
± 0.2
-
dB
± 0.005
Digital Filter + SCF
Frequency Response: 0 ∼ 20.0kHz
DAC
(fs = 96kHz)
(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 96kHz; Double Speed Mode; DEM = OFF; SLOW
= “0”)
Parameter
Symbol
min
(Note 19)
PB
(Note 19)
SB
PR
SA
GD
0
52.5
typ
max
Units
48.0
43.5
-
Digital Filter
Passband
±0.01dB
-6.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 20)
75
-
28
-
kHz
kHz
kHz
dB
dB
1/fs
-
± 0.3
-
dB
± 0.005
Digital Filter + SCF
Frequency Response: 0 ∼ 40.0kHz
DAC
(fs = 192kHz)
(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 192kHz; Quad Speed Mode; DEM = OFF; SLOW
= “0”)
Parameter
symbol
min
typ
max
Units
PB
0
105
96.0
87.0
-
kHz
kHz
kHz
dB
dB
1/fs
Digital Filter
Passband
±0.01dB
-6.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 19)
(Note 19)
(Note 20)
SB
PR
SA
GD
± 0.005
75
-
28
-
Digital Filter + SCF
Frequency Response: 0 ∼ 80.0kHz
Note 19.
fs(
Note 20.
)
+0/-1
dB
PB = 0.4535×fs (@±0.01dB), SB = 0.546×fs
16/20/24bit
MS0401-J-00
2005/07
- 10 -
ASAHI KASEI
[AK4620B]
DAC
(fs = 44.1kHz)
(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 44.1kHz; Normal Speed Mode; DEM = OFF;
SLOW = “1”)
Parameter
Symbol
min
typ
max
Units
PB
0
39.2
18.2
8.1
-
Digital Filter
Passband
±0.04dB
-3.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 21)
(Note 21)
(Note 20)
SB
PR
SA
GD
72
-
28
-
kHz
kHz
kHz
dB
dB
1/fs
-
+0/-5
-
dB
± 0.005
Digital Filter + SCF
Frequency Response
0 ∼ 20.0kHz
DAC
(fs = 96kHz)
(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 96kHz; Double Speed Mode; DEM = OFF; SLOW
= “1”)
Parameter
Symbol
min
(Note 21)
PB
(Note 21)
SB
PR
SA
GD
0
85.3
typ
max
Units
39.6
17.7
-
Digital Filter
Passband
±0.04dB
-3.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 20)
72
-
28
-
kHz
kHz
kHz
dB
dB
1/fs
-
+0/-4
-
dB
± 0.005
Digital Filter + SCF
Frequency Response
0 ∼ 40.0kHz
DAC
(fs = 192kHz)
(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 192kHz; Quad Speed Mode; DEM = OFF; SLOW
= “1”)
Parameter
Symbol
min
(Note 21)
PB
(Note 21)
SB
PR
SA
GD
0
171
typ
max
Units
79.1
35.5
-
kHz
kHz
kHz
dB
dB
1/fs
Digital Filter
Passband
±0.04dB
-3.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 20)
± 0.005
72
-
28
-
Digital Filter + SCF
Frequency Response 0 ∼ 80.0kHz
Note 21.
fs(
SB = 0.888 × fs
-
+0/-5
)
MS0401-J-00
dB
PB = 0.185 × fs(@±0.04dB)
2005/07
- 11 -
ASAHI KASEI
[AK4620B]
DIGITAL CHARACTERISTICS
(Ta=25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%VD
Low-Level Input Voltage
VIL
High-Level Output Voltage (Iout=-100µA)
VOH
VD-0.5
Low-Level Output Voltage (Iout=100µA)
VOL
Input Leakage Current
Iin
-
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
Frequency
fCLK
8.192
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
LRCK Frequency
(Note 22)
Normal Speed Mode (DFS0=“0”, DFS1=“0”)
Double Speed Mode (DFS0=“1”, DFS1=“0”)
Quad Speed Mode (DFS0=“0”, DFS1=“1”)
Duty Cycle
PCM Audio Interface Timing
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
(Note 23)
BICK “↑” to LRCK Edge
(Note 23)
LRCK to SDTO (MSB) (Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
fsn
fsd
fsq
32
54
108
45
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
1/128fsn
1/64fsd
1/64fsq
33
33
20
20
LRCK
BICK
typ
max
VT
30%VD
0.5
±10
Units
V
V
V
V
µA
max
Units
55.296
MHz
ns
ns
54
108
216
55
kHz
kHz
kHz
%
20
20
20
20
DSD Audio Interface Timing
tDCK
1/64fs
DCLK Period
tDCKL
160
DCLK Pulse Width Low
tDCKH
160
Pulse Width High
tDDD
-20
DCLK Edge to DSDL/R
(Note 24)
Note 22. Normal Speed Mode, Double Speed Mode, Quad Speed Mode
Note 23.
Note 24.
typ
-
20
PDN pin
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RSTN bit
“↑”
MS0401-J-00
2005/07
- 12 -
ASAHI KASEI
Parameter
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Reset Timing
PDN Pulse Width
(Note 25)
RSTAD “↑” to SDTO valid (Note 26)
Note 25. AK4620B PDN pin =“L”
Note 26. RSTAD bit
LRCK
[AK4620B]
Symbol
min
typ
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
50
50
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
tPD
tPDV
150
ns
1/fs
516
max
Units
“↑”
MS0401-J-00
2005/07
- 13 -
ASAHI KASEI
[AK4620B]
„
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
VIL
LRCK
tBLR
tLRB
VIH
VIL
BICK
tLRS
tBSD
50%VD
SDTO
tSDS
tSDH
VIH
VIL
SDTI
Audio Interface Timing (PCM mode)
MS0401-J-00
2005/07
- 14 -
ASAHI KASEI
[AK4620B]
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”)
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)
MS0401-J-00
2005/07
- 15 -
ASAHI KASEI
[AK4620B]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
C1
CDTI
tCDH
C0
R/W
VIH
A4
VIL
WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
WRITE Data Input Timing
tPD
PDN
VIL
Power Down & Reset Timing
MS0401-J-00
2005/07
- 16 -
ASAHI KASEI
[AK4620B]
„ DA
AK4620B PCM
DSD
D/A
DSD
DCLK, DSDL, DSDR
DSD
PCM
BICK, LRCK, SDTI
pin
RSTAD bit = RSTDA bit = “0”
PCM
D/P bit
ADC
bit PCM/DSD
2~3/fs
PCM
IPGA
D/P
D/P bit
DAC mode
ADC mode
0
PCM
PCM
1
DSD
Power down
Table 1. DSD/PCM Mode Control
„
1. PCM
AK4620B
MCLK, BICK, LRCK
(PDN pin = “H”)
MCLK LRCK
(MCLK, BICK, LRCK)
(PDN pin = “L”
ON
PWAD bit=PWDA bit = “0”)
ADC, DAC
(PDN pin = “L” → “H”)
MCLK, LRCK
AK4620B LRCK
1-1.
(P/S pin= “L”)
MCLK
CMODE, CKS0-1, DFS0-1 bit
OR
DFS1-0 bit
RSTAD bit = RSTDA bit= “0”
DFS1 bit
OR of DFS0 bit /
DFS0 pin
0
0
1
1
0
1
0
1
Mode
DFS0 pin
DFS0 pin DFS0 bit
(Table 2, Table 3, Table 4)
Sampling Rate
Normal speed
32kHz-54kHz
Double speed
54kHz-108kHz
Quad speed
108kHz-216kHz
N/A
Table 2. Sampling speed in serial mode
MS0401-J-00
Default
2005/07
- 17 -
ASAHI KASEI
[AK4620B]
CMODE bit
CKS1 bit
0
0
0
0
1
1
0
0
1
1
0
0
CKS0 bit
MCLK
Normal Speed
(DFS1-0 = “00”)
MCLK
Double Speed
(DFS1-0 = “01”)
MCLK
Quad Speed
(DFS1-0 = “10”)
0
256fs
N/A
N/A
1
512fs
256fs
128fs
0
1024fs
512fs
256fs
1
N/A
Auto Setting Mode (*)
N/A
0
384fs
N/A
N/A
1
768fs
384fs
192fs
Table 3. Master clock frequency in serial mode (“*”; refer to Table 4.)
Auto Setting Mode
MCLK
(Table 4)
LRCK
MCLK/LRCK ratio
Default
Normal/Double/Quad speed mode
Mode
Sampling Rate
512 or 768
Normal speed
32kHz-54kHz
256 or 384
Double speed
54kHz-108kHz
128 or 192
Quad speed
108kHz-216kHz
Table 4. Auto Setting Mode in serial mode (DFS1-0 = “01”, CMODE bit = “0”, CKS1-0 bit = “11”)
1-2.
(P/S pin= “H”)
Table 5 Table 6 Table 7
PDN pin = “L”
MCLK
DFS0 pin
L
H
CKS1 pin
CKS0-1 and DFS0 pin
Mode
Sampling Rate
Normal speed
32kHz-54kHz
Double speed
54kHz-108kHz
Table 5. Sampling speed in parallel mode
CKS0 pin
MCLK
Normal Speed
(DFS0 pin = “L”)
MCLK
Double Speed
(DFS0 pin = “H”)
L
L
256fs
N/A
L
H
512fs
256fs
H
L
384fs
Auto Setting Mode (*)
H
H
1024fs
512fs
Table 6. Master clock frequency in parallel mode (“*”; refer to Table 7.)
Auto Setting Mode
MCLK
(Table 7)
MCLK/LRCK ratio
LRCK
Normal/Double/Quad speed mode
Mode
Sampling Rate
512 or 768
Normal speed
32kHz-54kHz
256 or 384
Double speed
54kHz-108kHz
128 or 192
Quad speed
108kHz-216kHz
Table 7. Auto Setting Mode in parallel Mode (DFS0 pin = “H”, CKS1 pin = “H”, CKS0 pin = “L”)
MS0401-J-00
2005/07
- 18 -
ASAHI KASEI
[AK4620B]
MCLK (Normal speed)
256fs
512fs
1024fs
384fs
768fs
MCLK (Quad speed)
128fs
256fs
192fs
fs=44.1kHz
11.2896MHz
22.5792MHz
45.1584MHz
16.9344MHz
33.8688MHz
fs=48kHz
12.288MHz
24.576MHz
49.152MHz
18.432MHz
36.864MHz
MCLK (Double speed)
N/A
256fs
512fs
N/A
384fs
fs=88.2kHz
N/A
22.5792MHz
45.1584MHz
N/A
33.8688MHz
fs=96kHz
N/A
24.576MHz
49.152MHz
N/A
36.864MHz
fs=176.4kHz
fs=192kHz
22.5792MHz 24.576MHz
45.1584MHz 49.152MHz
33.8688MHz 36.864MHz
Table 8. Master clock frequency example
2) DSD
MCLK, DCLK
DCKS bit
MCLK
MCLK DCLK
(PDN pin = “H”)
(MCLK, DCLK)
(PDN pin = “L”)
(PDN pin = “L” →
ON
“H”) MCLK
„
1. PCM
5
2
Table 9 Table 10
2’s complement
SDTO BICK
Mode 2 16bit 20bit
LSB
DIF2-0 bit
DIF pin
SDTI
MSB
BICK
Mode
DIF2
DIF1
DIF0
0
1
2
3
4
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Mode
DIF pin
2
3
L
H
SDTO
SDTI
24bit, MSB justified
16bit, LSB justified
24bit, MSB justified
20bit, LSB justified
24bit, MSB justified
24bit, MSB justified
24bit, I2S
24bit, I2S
24bit, MSB justified
24bit, LSB justified
Table 9. Audio data format (Serial Mode)
SDTO
SDTI
LRCK
24bit, MSB justified
24bit, MSB justified
H/L
2
2
24bit, I S
24bit, I S
L/H
Table 10. Audio data format (Parallel Mode)
MS0401-J-00
LRCK
BICK
H/L
H/L
H/L
L/H
H/L
≥ 48fs
≥ 48fs
≥ 48fs
≥ 48fs
≥ 48fs
“0”
Default
BICK
≥ 48fs
≥ 48fs
2005/07
- 19 -
ASAHI KASEI
[AK4620B]
LRCK
0
1
2
3
17
18
19
20
30
31
0
1
2
3
17
18
19
20
31
0
1
BICK(64fs)
SDTO(o)
23 22 21
SDTI(i)
7
Don’t Care
6
5
4
3
23 22 21
15 14 13 12 11
2
1
7
Don’t Care
0
6
5
4
3
23
15 14 13 12 11
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
2
1
0
Rch Data
Figure 2. Mode 0 Timing
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
12 11 10
Don’t Care
0
19 18
23 22
8
7
1
12 11 10
Don’t Care
0
0
19 18
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
23
8
7
1
0
Rch Data
Figure 3. Mode 1 Timing
LRCK
0
1
2
18
19
20
21
22
23
24
25
0
1
2
18
19
20
21
22
23
24
25
0
1
BICK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
Lch Data
23
Rch Data
Figure 4. Mode 2 Timing
LRCK
0
1
2
3
19
20
21
22
23
24
25
0
1
2
3
19
20
21
22
23
24
25
0
1
BICK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 5. Mode 3 Timing
MS0401-J-00
2005/07
- 20 -
ASAHI KASEI
[AK4620B]
LRCK
0
1
2
8
9
10
20
21
31
0
1
2
8
9
10
20
21
31
0
1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
16 15 14
Don’t Care
23:MSB, 0:LSB
23 22
0
12 11
23 22
1
0
16 15 14
Don’t Care
Lch Data
23 22
0
12 11
23
1
0
Rch Data
Figure 6. Mode 4 Timing
MS0401-J-00
2005/07
- 21 -
ASAHI KASEI
[AK4620B]
2. DSD
DSD
DIF2-0 bit
DCLK
64fs
DCLK
DCKB bit
DCLK (64fs)
DCKB=1
DCLK (64fs)
DCKB=0
DSDL,DSDR
Normal
D0
DSDL,DSDR
Phase Modulation
D0
D1
D1
D2
D2
D1
D3
D3
D2
Figure 7. DSD Mode Timing
„ D/A
RSTDA bit
≥4/fs
D/A Mode
PCM Mode
DSD Mode
≥0
D/A Data
PCM Data
DSD Data
Figure 8. D/A Mode Switching Timing (PCM to DSD)
RSTDA bit
D/A Mode
DSD Mode
PCM Mode
≥4/fs
D/A Data
DSD Data
PCM Data
Figure 9. D/A Mode Switching Mode Timing (DSD to PCM)
Caution: DSD
DSD
25%
75%
SACD
MS0401-J-00
(Scarlet Book)
2005/07
- 22 -
ASAHI KASEI
[AK4620B]
„
ADC
37
128
IPGA
0dB
0.5dB/
(
“0”
2ch
)
IATT
(IPGA)
(
ATT: IATT)
(IPGL[7:0],IPGR[7:0])
80H
IPGA IATT
IPGA
S/N
MSB
“1”
IPGA, IATT
(Table 11)
ch
(To)
To=256/fs, 512/fs, 1024/fs, 2048/fs
IPGA
IPGA
(L/R
)
fs
ZTM1-0 bit
(ZCEI bit)
IPGA
IPGA
ON/OFF
IATT
29
Input Gain Setting
0dB
+6dB
fs=44.1kHz, A-weight
110dB
108dB
Table 11. IPGA+ADC S/N (typ.)
ZTM1
0
0
1
1
ZTM0
Normal speed Double speed
0
256/fs
512/fs
1
512/fs
1024/fs
0
1024/fs
2048/fs
1
2048/fs
4096/fs
Table 12. LRCK cycles for timeout period
+18dB
101dB
Quad speed
1024/fs
2048/fs
4096/fs
8192/fs
Default
„
AK4620B MUTE
256
DAC
(ATT)
0dB
−48dB
1
256
Table 13
Transition Time
1 Level
255 to 0
Normal Speed Mode
4LRCK
1020LRCK
Double Speed Mode
8LRCK
2040LRCK
Quad Speed Mode
16LRCK
4080LRCK
Table 13. ATT Transition Time
Sampling Speed
MS0401-J-00
2005/07
- 23 -
ASAHI KASEI
[AK4620B]
„
ADC
ch
Lch/Rch
(PDN pin = “H”)
ZOS bit =ZOE bit = “0”
(-0.3dBFS
)
OVF
ADC
516/fs([email protected]=48kHz)
OVFL/R pin
“L”
OVFL/R pin
“H”
„
AK4620B
ZOE bit = “0”
“H”
RSTDA bit “0”
“0”
bit
8192
“0”
“0”
ZOS bit = “1”
DZF pin
DZF pin “L”
DZF pin “H”
RSTDA bit “1”
DZF pin 4 ∼ 5LRCK
“L”
DZF pin
“L”
DZF pin
DZFB bit
DZFE
„
ADC
DC
HPF
fs
HPLN bit, HPRN bit L/R
HPF
HPF fc
ON
fs=44.1kHz
0.9Hz
„
IIR
2
3
(32kHz, 44.1kHz, 48kHz)
DEM1-0 bit
DEM0 pin
DEM1 ”0”
DEM0 pin
OFF
4
PCM
(50/15µs
)
DEM0 bit DEM0 pin
OR
(44.1kHz or OFF)
DSD
DEM1-0 bit
DSD
No
0
1
2
3
DEM1
DEM0
Mode
0
0
44.1kHz
Default
0
1
OFF
1
0
48kHz
1
1
32kHz
Table 14. De-emphasis control (Normal Speed Mode)
MS0401-J-00
2005/07
- 24 -
ASAHI KASEI
[AK4620B]
„ ADC Single-ended/Differential Input Mode
ADC
ADMODE pin, AML bit, AMR bit
IPGA
(Table 15, Table 16
IATT
)
IPGA
ADMODE pin
Lch
Rch
L
Single-ended
Single-ended
H
Differential
Differential
Table 15. ADC Input Mode in parallel mode
ADMODE pin
AML bit
AMR bit
Lch
Rch
0
0
Single-ended
Single-ended
0
1
Single-ended
Differential
1
0
Differential
Single-ended
1
1
Differential
Differential
X
X
Differential
Differential
Table 16. ADC Input Mode in serial mode (X: Don’t care)
L
H
„
ATT
−∞
(Table 12)
ATT
SMUTE bit “1”
−∞ (“0”)
ATT
× ATT
ATT
SMUTE bit “0”
×
ATT
−∞
−∞
ATT
S M U T E bit
(1)
(1)
AT T _Level
(3)
A ttenuation
-∞
GD
(2)
GD
(2)
AOUT
(4)
8192/fs
D ZF pin
(1)ATT
1020LRCK
(2)
(3)
ATT
(4)
× ATT
(Table 12)
Normal Speed Mode
ATT
“255”
(GD)
−∞
8192
“0”
DZF pin “H”
DZF pin “L”
“0”
Figure 10. Soft Mute and Zero Detection
MS0401-J-00
2005/07
- 25 -
ASAHI KASEI
[AK4620B]
„
AK4620B
ADC
DAC
PDN pin
“L”
PDN pin=“L”
1
(RSTAD
ADC, DAC
bit = RSTDA bit =“0”)
ADC
SDTO 516 x LRCK
DAC
(PWAD bit, PWDA bit)
Pow er Supply
PDN pin
RSTAD(register)
RSTDA(register)
PWAD(register)
PWDA(register)
PWVR(register)
ADC Internal State
PD
IATT
Reset INITA
00H → XXH
00H
SDTO
“0”
PD
Reset
OATT
FFH
FFH (1)
AOUT
Hi-z
INITA
Normal
00H 00H → XXH
Output
“0”
XXH
FI
Output
Normal
VCOM
*
PD
XXH
FI
DAC Internal State
External Mute
Example
Normal
PD
FFH → XXH
XXH
FADE
Output
Normal
XXH(2 )
XXH → YYH YYH
Hi-z
*
*
FADE
*
MCLK, LRCK, BICK
External clocks
The clocks can be stopped.
• INITA:
ADC
• PD:
• XXH,YYH:
ATT
• FI:
Fade In
• FADE:
(1) RSTDA bit
“L”
(2) PWDA bit
• AOUT:
“L”
(516/fs)
ATT
OATT
OATT
Fade In
ATT
“XXH”
“YYH”
OATT
OATT
FFH
XXH
XXH
YYH
“*”
Figure 11. Reset & Power down sequence in serial mode
MS0401-J-00
2005/07
- 26 -
ASAHI KASEI
[AK4620B]
PDN pin
“00H(Mute)”
516/fs
IATT
“H”
ADC, DAC
PDN pin = “H” “80H(0dB)”
“0”
DAC
PDN pin
“L”
531/fs
Pow er Supply
PDN pin
ADC Internal State
PD
INITA
IATT
00H
00HÆ80H
SDTO
“0”
DAC Internal State
PD
AOUT
FI
Normal
PD
INITA
80H
00H
00HÆ80H
Output
“0”
Normal
Hi-Z
External Mute
Example
External clocks
FI
PD
Output
*
80H
Output
Normal
Hi-Z
*
Normal
Output
*
MCLK, LRCK, BICK
MCLK, LRCK, BICK
The clocks can be stopped.
• INITA:
• PD:
• FI:
• AOUT:
ADC
(516/fs)
Fade In
“*”
IATT
Fade In
Figure 12. Reset & Power Down Sequence in parallel mode
MS0401-J-00
2005/07
- 27 -
ASAHI KASEI
[AK4620B]
„
3
I/F pin : CSN, CCLK, CDTI
Read/Write(1bit) Register address(MSB first, 5bits)
CCLK
bit
16
CCLK
CSN
I/F
Control data(MSB first, 8bits)
CSN
CCLK
“10”
Chip address(2bits, C0/1)
5MHz(max)
“10”
PDN pin=“L”
Function
Parallel mode
Serial mode
ADC Single-ended/Differential Input mode
X
X
Overflow detection
X
X
Zero detection
X
Soft Mute
X
IPGA
X
IATT
X
OATT
X
HPF OFF
X
DSD mode
X
16/20/24 bit LSB justified format of DAC
X
MCLK = 256fs @ Quad Speed
X
De-emphasis: 32kHz, 48kHz
X
Table 17. Function List (X: available, -: not available)
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “10”)
READ/WRITE (Fixed to “1”:WRITE)
Register Address
Control data
Figure 13. Control I/F Timing
*READ
*CSN pin = “L”
CCLK
15
17
MS0401-J-00
2005/07
- 28 -
ASAHI KASEI
[AK4620B]
„
Addr
00H
01H
02H
03H
04H
05H
06H
07H
Register Name
Power Down Control
Reset Control
Clock and Format Control
D7
SLOW
D/P
DIF2
Deem and Volume Control
SMUTE
Lch IPGA Control
Rch IPGA Control
Lch ATT Control
Rch ATT Control
IPGL7
IPGR7
ATTL7
ATTR7
D6
DZFB
DCKS
DIF1
HPRN
IPGL6
IPGR6
ATTL6
ATTR6
D5
ZOE
DCKB
DIF0
HPLN
IPGL5
IPGR5
ATTL5
ATTR5
D4
ZOS
0
CMODE
ZCEI
IPGL4
IPGR4
ATTL4
ATTR4
D3
0
AML
CKS1
ZTM1
IPGL3
IPGR3
ATTL3
ATTR3
D2
PWVR
AMR
CKS0
ZTM0
IPGL2
IPGR2
ATTL2
ATTR2
D1
PWAD
D0
PWDA
RSTAD
RSTDA
DFS1
DEM1
IPGL1
IPGR1
ATTL1
ATTR1
DFS0
DEM0
IPGL0
IPGR0
ATTL0
ATTR0
Note: 08H
1FH
PDN pin=“L”
„
PDN pin
“L”
“H”
AK4620B
(1)
(2) RSTAD bit, RSTDA bit
(3) ADC
DAC
“1”
Reset Control Register (01H)
RSTAD bit
RSTDA bit
“0”
ADC
DAC
MS0401-J-00
2005/07
- 29 -
ASAHI KASEI
[AK4620B]
„
Addr
00H
Register Name
Power Down Control
DEFAULT
D7
SLOW
0
D6
DZFB
0
D5
ZOE
0
PWDA: DAC power down
0: Power down
1: Power up (Default)
“0” DAC
D4
ZOS
0
D3
0
0
AOUT
D2
PWVR
1
D0
PWDA
1
Hi-Z
ATT
(06H, 07H)
PWAD: ADC power down
0: Power down
1: Power up (Default)
“0” ADC
“00H”
SDTO
“L”
PGA
516LRCK
(04H, 05H)
PWVR: Vref power down
0: Power down
1: Power up (Default)
“0”
ADC
PWAD, PWDA
D1
PWAD
1
“0”
PWVR
PGA
“0”
DAC
“1”
VREF
ZOS: Zero-detection/ Overflow-detection control for #15&16 pins.
0: Overflow detection for ADC input (Default)
1: Zero detection for DAC input.
ZOE: Zero-detection / Overflow-detection Disable
0: Enable (Default)
1: Disable. Outputs “L”.
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection (Default)
1: DZF goes “L” at Zero Detection
SLOW: DAC Slow Roll-off Filter Enable
0: Sharp Roll-off Filter (Default)
1: Slow Roll-off Filter
MS0401-J-00
2005/07
- 30 -
ASAHI KASEI
Addr
01H
[AK4620B]
Register Name
Reset Control
DEFAULT
D7
D/P
0
D6
DCKS
0
D5
DCKB
0
RSTDA: DAC reset
0: Reset (Default)
1: Normal Operation
“0” DAC
D4
0
0
D3
AML
0
AOUT
D2
AMR
0
D1
D0
RSTAD
RSTDA
0
0
VCOM
ATT
(06H, 07H)
RSTAD: ADC reset
0: Reset (Default)
1: Normal Operation
“0” ADC
“00H”
SDTO
“L”
PGA
516LRCK
(04H, 05H)
PGA
“0”
AML, AMR: Default “0” (see Table 16)
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge. (Default)
1: DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (Default)
1: 768fs
D/P: DSD/PCM Mode Select
0: PCM mode (Default)
1: DSD mode
Addr
02H
Register Name
Clock and Format Control
DEFAULT
D7
DIF2
0
D6
DIF1
1
D5
DIF0
0
D4
CMODE
0
D3
CKS1
0
D2
CKS0
0
D1
DFS1
0
D0
DFS0
0
DFS1-0: Sampling Speed Control (see Table 2)
Default: Normal speed
CMODE, CKS1-0: Master Clock Frequency Select (see Table 3)
Default: 256fs
DIF2-0: Audio data interface modes (see Table 9)
000: Mode 0
001: Mode 1
010: Mode 2 (Default)
011: Mode 3
100: Mode 4
Default: 24bit MSB justified for both ADC and DAC
MS0401-J-00
2005/07
- 31 -
ASAHI KASEI
Addr
03H
Register Name
Deem and Volume Control
DEFAULT
[AK4620B]
D7
SMUTE
0
D6
HPRN
0
D5
HPLN
0
D4
ZCEI
1
D3
ZTM1
1
D2
ZTM0
0
D1
DEM1
0
D0
DEM0
1
DEM1-0: De-emphasis response (see Table 3)
00: 44.1kHz
01: OFF (Default)
10: 48kHz
11: 32kHz
ZTM1-0: Zero crossing time out period select (see Table 11)
Default: 1024fs
ZCEI: ADC IPGA Zero crossing enable
0: Input PGA gain changes occur immediately
1: Input PGA gain changes occur only on zero-crossing or after timeout. (Default)
HPLN/RN: Left/Right channel Digital High Pass Filter Disable
0: Enable (Default)
1: Disable
SMUTE: DAC Input Soft Mute control
0: Normal operation (Default)
1: DAC outputs soft-muted
The soft mute is independent of the output ATT and performed digitally.
MS0401-J-00
2005/07
- 32 -
ASAHI KASEI
Addr
04H
05H
[AK4620B]
Register Name
Lch IPGA Control
Rch IPGA Control
DEFAULT
D7
IPGL7
IPGR7
1
D6
IPGL6
IPGR6
0
D5
IPGL5
IPGR5
0
D4
IPGL4
IPGR4
0
D3
IPGL3
IPGR3
0
D2
IPGL2
IPGR2
0
D1
IPGL1
IPGR1
0
D0
IPGL0
IPGR0
0
IPGL/R7-0: ADC Input Gain Level
Refer to Table 10
Default: 80H (0dB)
AK4620B
2ch
ADC
for Rch).
/
MSB “1”
IPGA
80H
IPGA IATT
PDN pin= “L” “00H”
PWAD bit=“0”
“00H”
516(1/fs)
“0”
Differential Mode
Data
FFH ~ A5H
A4H
A3H
:
82H
81H
80H
7FH
7EH
:
02H
01H
00H
Addr
06H
07H
(IPGA. 32 levels by 0.5dB/steps)
(IATT. 128 levels including MUTE) ADC
(04H for Lch, 05H
MSB “0”
IATT
IPGA,IATT
0dB
PDN pin= “H”
“80H”
531(1/fs)
PWAD bit =“1”
RSTAD bit=“0” “00H”
RSTAD bit =“1”
516(1/fs)
“0”
IATT
Analog
Volume (dB)
+18
+18
+17.5
:
+1.0
+0.5
0
0
0
:
0
0
0
Register Name
Lch OATT Control
Rch OATT Control
DEFAULT
Digital
ATT (dB)
0
0
0
:
0
0
0
-0.5
-1.0
:
-63.0
-63.5
MUTE
D7
ATTL7
ATTR7
1
Total Gain (dB)
Step width
(dB)
0.5
:
0.5
0.5
0.5
0.5
0.5
:
0.5
0.5
+18
+18
+17.5
:
+1.0
+0.5
0
-0.5
-1.0
:
-63.0
-63.5
MUTE
Table 10. IPGA code table
D6
ATTL6
ATTR6
1
D5
ATTL5
ATTR5
1
D4
ATTL4
ATTR4
1
IPGA
Analog volume with 0.5dB/step
IATT
Digital volume with 0.5dB/step.
Soft-changes between each level.
D3
ATTL3
ATTR3
1
D2
ATTL2
ATTR2
1
D1
ATTL1
ATTR1
1
D0
ATTL0
ATTR0
1
ATT7-0: Attenuation Level
ATT = 20 log10 (ATT_DATA / 255) [dB]
FFH : 0dB (Default)
00H : Mute
MS0401-J-00
2005/07
- 33 -
ASAHI KASEI
[AK4620B]
SYSTEM DESIGN
Figure 14
Figure 15
(AKD4620B)
0.1u
10u
+
1
VCOM
AOUTR+
30
Rch
Input
Buffer
2
AINR+
AOUTR-
29
3
AINR-
AOUTL+
28
Lch
Input
Buffer
4
AINL+
AOUTL-
27
5
AINL-
DGND
26
6
VREF
VD
25
7
AGND
VT
24
8
VA
ADMODE
23
9
P/S
DEM0
22
10 MCLK
PDN
21
11 LRCK
DFS0
20
CSN/DIF
19
13 SDTO
CCLK/CKS1
18
14 SDTI
CDTI/CKS0
17
15 OVFR/DZFR
OVFL/DZFL
16
4.75 ∼ 5.25V
Analog Supply +
10u
AK4620B
0.1u
Rch
LPF
Rch Out
Lch
LPF
Lch Out
0.1u
3.0 ∼ 3.6V
Digital Supply
3.0 ∼ 5.25V
Digital Supply
0.1u
Audio
DSP
12 BICK
Mode
Setting/
uP
330
330
33p
33p
Notes:
- AK4620B AGND, DGND
- AOUT+/−
- OVFR/DZFR pin
OVFL/DZFL pin
OVFL/DZFL pin
330Ω
33pF
SDTO pin
OVFL/DZFL pin
OVFR/DZFR pin
OVFR/DZFR pin
Figure 14. Typical Connection Diagram (Differential mode)
MS0401-J-00
2005/07
- 34 -
ASAHI KASEI
[AK4620B]
0.1u
4.75 ∼ 5.25V
Analog Supply
+
10u
10u
+
1
VCOM
AOUTR+
30
2
AINR+
AOUTR-
29
3
NC
AOUTL+
28
4
AINL+
AOUTL-
27
5
NC
DGND
26
6
VREF
VD
25
7
AGND
VT
24
8
VA
ADMODE
23
9
P/S
DEM0
22
10 MCLK
PDN
21
11 LRCK
DFS0
20
CSN/DIF
19
13 SDTO
CCLK/CKS1
18
14 SDTI
CDTI/CKS0
17
15 OVFR/DZFR
OVFL/DZFL
16
AK4620B
0.1u
Rch
LPF
Rch Out
Lch
LPF
Lch Out
0.1u
3.0 ∼ 3.6V
Digital Supply
3.0 ∼ 5.25V
Digital Supply
0.1u
Audio
DSP
12 BICK
Mode
Setting/
uP
330
330
33p
33p
Notes:
- AK4620B AGND, DGND
- AOUT+/−
- OVFR/DZFR pin
OVFL/DZFL pin
OVFL/DZFL pin
330Ω
33pF
SDTO pin
OVFL/DZFL pin
OVFR/DZFR pin
OVFR/DZFR pin
Figure 15. Typical Connection Diagram (Single-ended mode)
MS0401-J-00
2005/07
- 35 -
ASAHI KASEI
[AK4620B]
Digital Ground
Analog Ground
System
Controller
1
VCOM
AOUTR+
30
2
AINR+
AOUTR-
29
3
AINR-/NC
AOUTL+
28
4
AINL+
AOUTL-
27
5
AINL-/NC
DGND
26
6
VREF
VD
25
7
AGND
VT
24
8
VA
ADMODE
23
9
P/S
DEM0
22
10
MCLK
PDN
21
11
LRCK
DFS0
20
12
BICK
CSN/DIF
19
13
SDTO
CCLK/CKS1
18
14
SDTI
CDTI/CKS0
17
15
OVFR/DZFR
OVFL/DZFL
16
AK4620B
Figure 16. Ground Layout
1.
VA,VD,VT
VA
VA, VD, VT
VA, VD, VT
VD,VT
AGND DGND
AK4620B
2.
VREF pin AGND
0.1µF
VREF pin
VA
AGND
VCOM
10µF
0.1µF
AGND
VCOM pin
VREF pin VCOM pin
3. ADC
2’s complement
([email protected]=44.1kHz)
128fs
DC
ADC
(ADC
DC
)
HPF
128fs
MS0401-J-00
2005/07
- 36 -
ASAHI KASEI
[AK4620B]
4.
4-1. Single-ended Input (ADMODE pin = “L”)
IPGA=0dB
1.18kΩ(typ.)
fc=1/(2πRC)
DC
VA/2)
(
AK4620B
(RC
5.1kΩ(typ.)
IPGA=+18dB
3.07Vpp (typ. VREF=5V)
128fs
)
4-2. Full-Differential Input (ADMODE pin = “H”)
AGND
VA
Figure 17
AINL+/−(AINR+/−)
10nF
22Ω
360kHz
LPF
2.82Vpp (typ. VREF=5V)
−10dB
LPF
370kHz
910
4.7k
4.7k
470p
VP+
Analog In
47µ
3k
22
2.82Vpp
AIN+
VP9.3Vpp
Bias
NJM5532
910
VA
10k
47µ
22
AIN-
0.1µ 10µ
Bias
10k
3k
AK4620B
10n
470p
VA = 5V
VP+ = 15V
VP- = -15V
Bias
2.82Vpp
Figure 17. Input Buffer example in differential mode
MS0401-J-00
2005/07
- 37 -
ASAHI KASEI
[AK4620B]
5.
(
VREF =5V)
(AOUT−)
1
800000H(@24bit)
∆Σ
Figure 18
(
VA/2)
2.8Vpp (typ.
Vout = (AOUT+) −
AOUT+ AOUT−
5.6Vpp ([email protected]=5V)
2’s complement
7FFFFFH(@24bit)
000000H(@24bit)
AOUT
)
1
0V
(SCF)
LPF
Figure 19
3
LPF
AK4620B
4.7k
4.7k
AOUT200
330p
+Vop
AOUT+
2.2n
4.7k
4.7k
Analog
Out
200
330p
-Vop
Figure 18. External LPF Circuit Example 1 for PCM (fc = 136kHz, Q=0.694)
Frequency Response
20kHz
40kHz
80kHz
Gain
−0.01dB
−0.06dB
−0.59dB
Table 18. Frequency Response of External LPF Circuit Example 1 for PCM
MS0401-J-00
2005/07
- 38 -
ASAHI KASEI
[AK4620B]
+15
3.3n
+
10k
330
180
0.1u
7
3
2 +
4
3.9n
6
NJM5534D
+
10u
0.1u
620
620
3.3n
+
100u
3
+
2 -
+
330
3.9n
2 - 4
+
3
7
100
6
Lch
1.0n NJM5534D
10u
0.1u
7
6
4
NJM5534D
1.2k
10k
AOUTL+
180
+10u
1.0n
1.2k
680
0.1u
560
560
100u
AOUTL- +
-15
10u
680
+
0.1u
10u
+
10u
0.1u
Figure 19. External LPF Circuit Example 2 for PCM
2nd Stage
Total
1st Stage
Cut-off Frequency
182kHz
284kHz
Q
0.637
Gain
+3.9dB
-0.88dB
+3.02dB
20kHz
-0.025
-0.021
-0.046dB
Frequency
40kHz
-0.106
-0.085
-0.191dB
Response
80kHz
-0.517
-0.331
-0.848dB
Table 19. Frequency Response of External LPF Circuit Example 2 for PCM
MS0401-J-00
2005/07
- 39 -
ASAHI KASEI
SACD
−30dB/oct
20)
[AK4620B]
(Scarlet Book)
SACD
AK4620B
50kHz
(Table 20)
(Figure
Frequency
Gain
20kHz
−0.4dB
50kHz
−2.8dB
100kHz
−15.5dB
Table 20. Internal Filter Response at DSD mode
2.0k
1.8k
4.3k
AOUT1.0k
270p
2.8Vpp
2200p
+Vop
3300p
2.0k
1.8k
1.0k
AOUT+
+
2.8Vpp
4.3k
270p
Analog
Out
6.34Vpp
-Vop
Figure 20. External 3rd order LPF Circuit Example for DSD
Frequency
Gain
20kHz
−0.05dB
50kHz
−0.51dB
100kHz
−16.8dB
DC gain = 1.07dB
Table 16. 3rd order LPF (Figure 20) Response
MS0401-J-00
2005/07
- 40 -
ASAHI KASEI
[AK4620B]
30pin VSOP (Unit: mm )
1.5MAX
*9.7±0.1
0.3
30
16
15
1
0.22±0.1
7.6±0.2
5.6±0.1
A
0.15 +0.10
-0.05
0.65
0.12 M
0.45±0.2
+0.10
0.08
0.10 -0.05
1.2±0.10
Detail A
NOTE: Dimension "*" does not include mold flash.
„
MS0401-J-00
2005/07
- 41 -
ASAHI KASEI
[AK4620B]
AKM
AK4620BVF
XXXBYYYYC
XXXBYYYYC
Date code identifier
XXXB : Lot number (X : Digit number, B : Alpha character)
YYYYC : Assembly date (Y : Digit number, C : Alpha character)
Date (YY/MM/DD)
05/07/08
Revision
00
Reason
Page
Contents
•
•
•
•
•
•
MS0401-J-00
2005/07
- 42 -