[AK4122A]
AK4122A
24-Bit 96kHz SRC with DIR
AK4122A
(SRC)
44.1kHz, 48kHz, 96kHz
(DIR)
8kHz ∼ 96kHz
32kHz,
PLL
1. SRC
• Asynchronous Sample Rate Converter
• Input Sample Rate Range (fsi) : 8kHz ∼ 96kHz
• Output Sample Rate (fso) : 32kHz, 44.1kHz, 48kHz, 96kHz
• Input to Output Sample Rate Ratio : 0.33 to 6
• THD+N : −113dB
• I/F format : MSB justified, LSB justified (16/24bit) and I2S compatible
• Clock for Master mode : 256/384/512/768fs
• SRC Bypass mode
• Soft Mute Function
2. DIR
3.
4.
5.
6.
• 4-Channel Inputs Selector & 1-Channel Through Output
• AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible
• Low Jitter Analog PLL
• PLL Lock Range : 32kHz ∼ 96kHz
• Auto detection
- Non-PCM Bit Stream
- DTS-CD Bit Stream
- Validity Flag
- Sampling Frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz)
- Unlock & Parity Error
- DAT Start ID
• 40-bit Channel Status Buffer
• Burst Preamble bit Pc, Pd Buffer for Non-PCM bit streams
• Q-subcode Buffer for CD bit streams
4-wire Serial μP Interface
Power Supply
• AVDD: 3.0 ∼ 3.6V (typ. 3.3V)
• DVDD: 3.0 ∼ 3.6V (typ. 3.3V)
Ta = −10 ∼ 70°C
Package : 48pin LQFP
MS1076-J-01
2010/05
-1-
[AK4122A]
■
INT0 INT1 INT2
RX1
RX2
RX3
RX4
R
FILT
RX1
RX2
OPS1-0
TX
RX3
TX
RX4
PDN
IPS1-0
DIR
SMUTE
PORT3
PORT1
BICK1
LRCK1
SDTI
BICK1
BICK2
LRCK2
SDTIO
BICK2
LRCK1
SDTI
Serial
Audio
I/F
ISEL1-0
De-em
Filter
PORT2
LRCK2
SDTIO
OSEL
SRC
BYPS
Serial
Audio
I/F
LRCK
BICK
SDTO
LRCK
BICK
SDTO
OMCLK
PLL
Serial
Audio
I/F
M/S2
M/S3
Control Register
MCLK2
AVDD AVSS
DVDD DVSS
CDTO CDTI CCLK CSN
Block diagram
MS1076-J-01
2010/05
-2-
[AK4122A]
■
−10 ∼ +70°C
AK4122A
AK4122AVQ
AKD4122A
48pin LQFP (0.5mm pitch)
R
AVSS
PDN
LRCK1
BICK1
SDTI
DVSS
DVDD
MCLK2
LRCK2
BICK2
SDTIO
■
36 35 34 33 32 31 30 29 28 27 26 25
INT0
37
24
TST11
INT1
38
23
TST10
TX
39
22
RX4
SDTO
40
21
TST9
BICK
41
20
RX3
19
TST8
18
RX2
LRCK
AK4122AVQ
42
Top View
BVSS
46
15
TST6
CSN
47
14
AVDD
CCLK
48
1
13
AVSS
4
5
6
7
8
9
10 11 12
MS1076-J-01
FILT
3
TST5
2
TST4
RX1
SMUTE
16
M/S3
45
M/S2
DVDD
TST3
TST7
TST2
17
INT2
44
TST1
DVSS
CDTO
43
CDTI
OMCLK
2010/05
-3-
[AK4122A]
No.
1
2
3
4
5
Pin Name
CDTI
CDTO
TST1
INT2
TST2
I/O
Function
I
O
O
O
O
Control Data Input Pin
Control Data Output Pin
Test 1 Pin
Interrupt 2 Pin
Test 2 Pin
Test 3 Pin
6 TST3
I
This pin should be connected to DVSS.
Master / Slave Mode Pin for PORT2
7 M/S2
I
“H” : Master mode, “L” : Slave Mode
Master / Slave Mode Pin for PORT3
8 M/S3
I
“H” : Master mode, “L” : Slave Mode
Soft Mute Pin
9 SMUTE
I
“H” : Soft Mute, “L” : Normal Operation
Test 4 Pin
10 TST4
I
This pin should be connected to AVSS.
Test 5 Pin
11 TST5
I
This pin should be connected to AVSS.
PLL Loop Filter Pin
12 FILT
O
470Ω±5% resistor and 2.2μF±50% ceramic capacitor in parallel with a
2.2nF±50% ceramic capacitor should be connected to AVSS externally.
13 AVSS
Analog Ground Pin
14 AVDD
Analog Power Supply Pin, 3.0 ∼ 3.6V
Test 6 Pin
15 TST6
I
This pin should be connected to AVSS.
16 RX1
I
Receiver Input 1 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 7 Pin
17 TST7
I
This pin should be connected to AVSS.
18 RX2
I
Receiver Input 2 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 8 Pin
19 TST8
I
This pin should be connected to AVSS.
20 RX3
I
Receiver Input 3 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 9 Pin
21 TST9
I
This pin should be connected to AVSS.
22 RX4
I
Receiver Input 4 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 10 Pin
23 TST10
I
This pin should be connected to AVSS.
24 TST11
O
Test 11 Pin
Note: All input pins except internal biased pins should not be left floating.
MS1076-J-01
2010/05
-4-
[AK4122A]
External Resistor Pin
12kΩ±5% resistor should be connected to AVSS externally.
26 AVSS
Analog Ground Pin
Power-Down Mode Pin
27 PDN
I
“H”: Power up, “L”: Power down reset and initializes the control register.
28 LRCK1
I
Input Channel Clock Pin
29 BICK1
I
Audio Serial Data Clock Pin
30 SDTI
I
Audio Serial Data Input Pin
31 DVSS
Digital Ground Pin
32 DVDD
Digital Power Supply Pin, 3.0 ∼ 3.6V
33 MCLK2
I
Master Clock Input Pin
34 LRCK2
I/O Input / Output Channel Clock Pin
35 BICK2
I/O Audio Serial Data Clock Pin
36 SDTIO
I/O Audio Serial Data Input / Output Pin
37 INT0
O
Interrupt 0 Pin
38 INT1
O
Interrupt 1 Pin
39 TX
O
Transmitter Output Pin
40 SDTO
O
Audio Serial Data Output Pin
41 BICK
I/O Audio Serial Data Clock Pin
42 LRCK
I/O Output Channel Clock Pin
43 OMCLK
I
Master Clock Input Pin
44 DVSS
Digital Ground Pin
45 DVDD
Digital Power Supply Pin, 3.0 ∼ 3.6V
Substrate Ground Pin
46 BVSS
This pin should be connected to AVSS.
47 CSN
I
Chip Select Pin
48 CCLK
I
Control Data Clock Pin
Note: All input pins except internal biased pins should not be left floating.
25
R
-
MS1076-J-01
2010/05
-5-
[AK4122A]
■
PORT1
PORT2
BICK1, LRCK1, SDTI
MCLK2
BICK2, LRCK2
DIR
Control PORT
Other
TEST
@
@
SDTIO
M/S2
OMCLK
PORT3
DVSS
DVSS
DVSS
DVSS
DVDD
DVSS
DVSS
BICK, LRCK
DVSS
@
@
SDTO
M/S3
RX1, RX2, RX3, RX4
INT0, INT1, INT2, TX
CCLK, CDTI, CSN
CDTO
SMUTE
TST1, TST2, TST11
TST3
TST4, TST5, TST6, TST7,
TST8, TST9, TST10
MS1076-J-01
DVDD
DVSS
DVSS
DVSS
DVSS
AVSS
2010/05
-6-
[AK4122A]
(AVSS=BVSS=DVSS=0V; Note 1)
Parameter
Symbol
min
max
Units
Power Supplies:
AVDD
DVDD
ΔGND
IIN
VIND1
VIND2
Ta
Tstg
−0.3
−0.3
−0.3
−0.3
−10
−65
4.6
4.6
0.3
±10
DVDD+0.3
AVDD+0.3
70
150
V
V
V
mA
V
V
°C
°C
Analog
Digital
|BVSS − DVSS| (Note 2)
Input Current, Any Pin Except Supplies
Digital Input Voltage 1 (Except RX1-4 pins)
Digital Input Voltage 2 (RX1-4 pins)
Ambient Temperature (Power applied)
Storage Temperature
Note 1.
Note 2. AVSS, BVSS, DVSS
:
(AVSS=BVSS=DVSS=0V; Note 1)
Parameter
Power Supplies
Analog
(Note 3)
Digital
Note 1.
Note 3. AVDD DVDD
Symbol
AVDD
DVDD
min
3.0
3.0
typ
3.3
3.3
max
3.6
AVDD
Units
V
V
:
MS1076-J-01
2010/05
-7-
[AK4122A]
SRC
(Ta=25°C; AVDD=DVDD=3.3V; AVSS=BVSS=DVSS=0V; data = 24bit; measurement bandwidth = 20Hz ~ FSO/2;
unless otherwise specified.)
Parameter
Symbol
min
typ
max
Units
SRC Characteristics:
Resolution
(Note 4)
24
Bits
Input Sample Rate
FSI
8
96
kHz
Output Sample Rate
FSO
32
96
kHz
THD+N
(Input = 1kHz, 0dBFS, Note 5)
FSO/FSI = 44.1kHz/48kHz
−113
dB
FSO/FSI = 48kHz/44.1kHz
−113
dB
FSO/FSI = 32kHz/48kHz
−114
dB
FSO/FSI = 96kHz/32kHz
−111
dB
Worst Case (FSO/FSI = 48kHz/8kHz)
−103
dB
Dynamic Range (Input = 1kHz, −60dBFS, Note 5)
FSO/FSI = 44.1kHz/48kHz
114
dB
FSO/FSI = 48kHz/44.1kHz
115
dB
FSO/FSI = 32kHz/48kHz
115
dB
FSO/FSI = 96kHz/32kHz
116
dB
Worst Case (FSO/FSI = 32kHz/44.1kHz)
112
dB
Dynamic Range (Input = 1kHz, −60dBFS, A-weighted, Note 5)
FSO/FSI = 44.1kHz/48kHz
117
dB
Ratio between Input and Output Sample Rate
(Note 6) FSO/FSI
0.33
6
Note 4.
24bit
SRC 20bit
4bit
“0”
SRC
“0”
Note 5. ROHDE & SCHWARZ UPD04
Rejection Filter = wide, 8192point FFT
Note 6. “0.33” FSI 96kHz
FSO 32kHz
FSO/FSI
“6” FSI 8kHz
FSO 48kHz
S/PDIF RECEIVER
(Ta=25°C; AVDD=DVDD=3.0 ∼ 3.6V)
Parameter
Input Resistance
Input Voltage
Input Sample Frequency
Symbol
Zin
VTH
fs
MS1076-J-01
min
200
32
typ
10
max
-
-
96
Units
kΩ
mVpp
kHz
2010/05
-8-
[AK4122A]
(Ta=25°C; AVDD=DVDD=3.0 ∼ 3.6V; DEM=OFF)
Parameter
Symbol
Digital Filter
Passband −0.001dB 0.985 ≤ FSO/FSI ≤ 6.000
PB
0.905 ≤ FSO/FSI < 0.985
PB
0.714 ≤ FSO/FSI < 0.905
PB
0.656 ≤ FSO/FSI < 0.714
PB
0.536 ≤ FSO/FSI < 0.656
PB
0.492 ≤ FSO/FSI < 0.536
PB
0.452 ≤ FSO/FSI < 0.492
PB
0.333 ≤ FSO/FSI < 0.452
PB
Stopband
0.985 ≤ FSO/FSI ≤ 6.000
SB
0.905 ≤ FSO/FSI < 0.985
SB
0.714 ≤ FSO/FSI < 0.905
SB
0.656 ≤ FSO/FSI < 0.714
SB
0.536 ≤ FSO/FSI < 0.656
SB
0.492 ≤ FSO/FSI < 0.536
SB
0.452 ≤ FSO/FSI < 0.492
SB
0.333 ≤ FSO/FSI < 0.452
SB
Passband Ripple
PR
Stopband Attenuation
SA
Group Delay
(Note 7)
GD
Note 7.
L, R
L, R
LRCK
min
typ
0
0
0
0
0
0
0
0
0.5417FSI
0.5021FSI
0.3965FSI
0.3643FSI
0.2974FSI
0.2732FSI
0.2510FSI
0.1822FSI
max
Units
0.4583FSI
0.4167FSI
0.3195FSI
0.2852FSI
0.2245FSI
0.2003FSI
0.1781FSI
0.1092FSI
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
±0.01
96
-
58.5
LRCK
-
DC
(Ta=25°C; AVDD=DVDD=3.0 ∼ 3.6V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
(Iout=−400μA)
Low-Level Output Voltage
(Iout=400μA)
Input Leakage Current
Symbol
VIH
VIL
VOH
VOL
Iin
min
70%DVDD
DVDD−0.4
-
typ
-
Parameter
min
typ
Power Supply Current
Normal operation (PDN pin = “H”)
(Note 8)
15
FSI=FSO=48kHz at Slave Mode: AVDD=DVDD=3.3V
29
FSI=FSO=96kHz at Master Mode: AVDD=DVDD=3.3V
FSI=FSO=96kHz at Master Mode: AVDD=DVDD=3.6V
Power down (PDN pin = “L”)
(Note 9)
10
AVDD+DVDD
Note 8. typ
max
AVDD+DVDD
@Slave Mode, AVDD=DVDD=3.3V, FSI=FSO=48kHz
1. PORT1 → SRC → PORT3: AVDD=5mA(typ), DVDD=10mA(typ)
2. PORT2 → SRC → PORT3: AVDD=5mA(typ), DVDD=10mA(typ)
3. DIR → SRC → PORT3: AVDD=6mA(typ), DVDD=9mA(typ)
Note 9.
DVSS
MS1076-J-01
max
30%DVDD
0.4
±10
Units
V
V
V
V
μA
max
Units
45
mA
mA
mA
100
μA
2010/05
-9-
[AK4122A]
(Ta=25°C; AVDD=DVDD=3.0 ∼ 3.6V; CL=20pF)
Parameter
Master Clock Timing
Frequency
Pulse Width Low
Pulse Width High
LRCK for Input data (LRCK1, LRCK2)
Frequency
Duty Cycle
Symbol
min
fCLK
tCLKL
tCLKH
8.192
0.4/fCLK
0.4/fCLK
fs
Duty
8
48
LRCK for Output data (LRCK, LRCK2)
Frequency
(Note 10)
Duty Cycle
Slave Mode
Master Mode
fs
Duty
Duty
32
48
S/PDIF Clock Recover Frequency
fPLL
32
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
1/64fs
65
65
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
1/64fs
65
65
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
1/64fs
65
65
30
30
ns
ns
ns
ns
ns
ns
ns
Audio Interface Timing
Input for PORT1
BICK1 Period
BICK1 Pulse Width Low
Pulse Width High
LRCK1 Edge to BICK1 “↑”
(Note 11)
BICK1 “↑” to LRCK1 Edge
(Note 11)
SDTI Hold Time from BICK1 “↑”
SDTI Setup Time to BICK1 “↑”
Input for PORT2 (Slave mode)
BICK2 Period
BICK2 Pulse Width Low
Pulse Width High
LRCK2 Edge to BICK2 “↑”
(Note 11)
BICK2 “↑” to LRCK2 Edge
(Note 11)
SDTIO Hold Time from BICK2 “↑”
SDTIO Setup Time to BICK2 “↑”
Output for PORT2 (Slave mode)
BICK2 Period
tBCK
BICK2 Pulse Width Low
tBCKL
Pulse Width High
tBCKH
LRCK2 Edge to BICK2 “↑”
(Note 11)
tLRB
tBLR
BICK2 “↑” to LRCK2 Edge
(Note 11)
2
tLRS
LRCK2 to SDTIO (MSB) (Except I S mode)
tBSD
BICK2 “↓” to SDTIO
Note 10.
min 8kHz
Note 11.
LRCK1
BICK1 “↑”
LRCK2
BICK2 “↑”
MS1076-J-01
typ
50
50
50
max
Units
36.864
MHz
ns
ns
96
52
kHz
%
96
52
kHz
%
%
96
kHz
30
30
2010/05
- 10 -
[AK4122A]
Parameter
Output for PORT3 (Slave mode)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
(Note 11)
BICK “↑” to LRCK Edge
(Note 11)
2
LRCK to SDTO (MSB) (Except I S mode)
BICK “↓” to SDTO
Output for PORT2 (Master mode)
BICK2 Frequency
BICK2 Duty
BICK2 “↓” to LRCK2
BICK2 “↓” to SDTIO
Output for PORT3 (Master mode)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
Reset Timing
PDN Pulse Width
Note 11.
LRCK
Note 12. INT2
INT2
Note 13. AK4122A PDN pin = “L”
(Note 12)
Symbol
min
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/64fs
65
65
30
30
fBCK
dBCK
tMBLR
tBSD
fBCK
dBCK
tMBLR
tBSD
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
(Note 13)
tPD
BICK “↑”
typ
max
Units
30
30
ns
ns
ns
ns
ns
ns
ns
20
30
Hz
%
ns
ns
−20
−20
20
30
Hz
%
ns
ns
200
80
80
40
40
150
50
50
1000
64fs
50
−20
−20
64fs
50
45
70
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
max
MS1076-J-01
2010/05
- 11 -
[AK4122A]
■
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSD
tLRS
SDTO
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Audio Interface Timing (Slave mode)
Note : BICK PORT1 BICK1 PORT2 BICK2 PORT3 BICK
LRCK PORT1
LRCK2 PORT3 LRCK
SDTI PORT1 SDTI
PORT2
SDTIO
SDTO PORT3 SDTO
PORT2
SDTIO
MS1076-J-01
LRCK1 PORT2
2010/05
- 12 -
[AK4122A]
LRCK
50%DVDD
tMBLR
dBCK
BICK
50%DVDD
tBSD
SDTO
50%DVDD
tSDH
tSDS
VIH
SDTI
VIL
Audio Interface Timing (Master mode)
Note : BICK PORT1 BICK1 PORT2 BICK2 PORT3 BICK
LRCK PORT1
LRCK2 PORT3 LRCK
SDTI PORT1 SDTI
PORT2
SDTIO
SDTO PORT3 SDTO
PORT2
SDTIO
LRCK1 PORT2
VIH
CSN
VIL
tCSS
tCCKL
tCCKH
VIH
CCLK
VIL
tCDH
tCDS
VIH
CDTI
C1
C0
R/W
VIL
CDTO
Hi-Z
WRITE/READ Command Input Timing
MS1076-J-01
2010/05
- 13 -
[AK4122A]
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
D2
D1
D0
VIL
Hi-Z
CDTO
WRITE Data Input Timing
VIH
CSN
VIL
VIH
CCLK
VIL
VIH
CDTI
A1
A0
VIL
tDCD
CDTO
Hi-Z
D7
D6
50%DVDD
READ Data Output Timing 1
MS1076-J-01
2010/05
- 14 -
[AK4122A]
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
VIL
tCCZ
CDTO
D2
D1
D0
Hi-Z
50%DVDD
READ Data Output Timing 2
tPD
PDN
VIL
Power Down & Reset Timing
MS1076-J-01
2010/05
- 15 -
[AK4122A]
■
SRC DIR, PORT1, PORT2
PORT2, PORT3 SRC, BYPASS
PORT2
PORT2
(PWN bit = “0”)
Figure 1
Table 1
1
(ISEL1-0, etc.)
DIR
PORT3
PORT1
Serial
Audio
I/F
De-em
Filter
ISEL1-0
OSEL
SRC
BYPS
Serial
Audio
I/F
PLL
PORT2
Serial
Audio
I/F
Figure 1. Connection Input Source & Output Source
Mode
0
1
2
3
4
5
6
7
8
9
Input PORT
ISEL1-0 bit
00: PORT1
01: PORT2
10: DIR
00: PORT1
01: PORT2
10: DIR
00: PORT1
10: DIR
00: PORT1
10: DIR
SRC / Bypass
BYPS bit
Output PORT
OSEL bit
0: SRC
0: PORT3
(Note 14)
1: Bypass
0: SRC
1: Bypass
1: PORT2
(Note 15)
Path
PORT1 → SRC → PORT3
PORT2 → SRC → PORT3
DIR → SRC → PORT3
PORT1 → PORT3
PORT2 → PORT3
DIR → PORT3
PORT1 → SRC → PORT2
DIR → SRC → PORT2
PORT1 → PORT2
DIR → PORT2
Table 1. Path Select
Mode 0 (Path : PORT1 → SRC → PORT3)
PORT2 SDTIO pin
DIR
PORT1 DIF1-0 bit
/
“10”(I2S Compatible)
Table 6, Table 7
MS1076-J-01
2010/05
- 16 -
[AK4122A]
Note 14.
PORT2
M/S2 pin
Mode
L
Slave
H
Master
Note 15.
Unused pin
Pin I/O
MCLK2
I
BICK2
I
LRCK2
I
SDTIO
I
MCLK2
I
BICK2
O
LRCK2
O
SDTIO
I
Table 2. Pin Setting for PORT2
PORT3
Setting
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
PORT3
M/S3 pin
Mode
L
Slave
H
Table 2
PORT2
Master
Table 3
Unused pin
Pin I/O
OMCLK
I
BICK
I
LRCK
I
SDTO
O
OMCLK
I
BICK
O
LRCK
O
SDTO
O
Table 3. Pin Setting for PORT3
Setting
DVSS
DVSS
DVSS
DVSS
■
PORT1
PORT2, PORT3
LRCK1, LRCK2
DIR
MCLK
PORT2, PORT3
/
M/S2, M/S3 pin
MCLK
DIR
MCLK
MCLK(MCLK2
OMCLK)
ICKS1
0
0
1
1
OCKS1
0
0
1
1
PLL
PORT2, PORT3
MCLK2 pin
OMCLK pin DVSS
MCLK2 pin OMCLK pin MCLK
Table 4, Table 5 PORT2, PORT3
MCLK2
32kHz ≤ fs ≤ 48kHz 48kHz < fs ≤ 96kHz
0
256fs
256fs
1
384fs
384fs
0
512fs
N/A
1
768fs
N/A
Table 4. MCLK2 frequency select for Master mode
ICKS0
OMCLK
32kHz ≤ fs ≤ 48kHz 48kHz < fs ≤ 96kHz
0
256fs
256fs
1
384fs
384fs
0
512fs
N/A
1
768fs
N/A
Table 5. OMCLK frequency select for Master mode
(default)
OCKS0
MS1076-J-01
(default)
2010/05
- 17 -
[AK4122A]
■
PORT2, PORT3
M/S2
M/S3 pin
AK4122A MCLK
BICK, LRCK
“H”
“L”
BICK, LRCK AK4122A
AK4122A
MCLK
PORT2
M/S2 pin
L
L
H
H
M/S3 pin
L
L
H
H
M/S2 pin
BYPS bit
0
Data I/O
Mode
BICK, LRCK
I/O
Slave, SRC
Input
Input
Slave, Bypass
1
Output
Not Available
0
I/O
Master, SRC
Output
1
I/O
Master, Bypass
Table 6. Master mode/Slave mode for PORT2
BYPS bit
Data I/O
Mode
BICK, LRCK
0
Output
Slave, SRC
Input
1
Output
Not Available
0
Output
Master, SRC
Output
1
Output
Master, Bypass
Table 7. Master mode/Slave mode for PORT3
■
PWN bit = “0”
BICK
64fs
(1) PORT1
4
(Table 8) DIF1-0 bit
SDTI BICK1
Mode
0
1
2
3
:
DIR
DIF1
0
0
1
1
MSB
PORT1
DIF0
Input Format
LRCK BICK
0
16bit, LSB justified
H/L
≥ 32fs
1
24bit, MSB justified
H/L
≥ 48fs
0
24bit, I2S Compatible
L/H
≥ 48fs
1
24bit, LSB justified
H/L
≥ 48fs
Table 8. Audio Interface Format for PORT1
PORT1
MS1076-J-01
DIF1-0 bit
2’s
(default)
“10”(I2S Compatible)
2010/05
- 18 -
[AK4122A]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK1(32fs)
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
0 1 2 3
17 18 19 20
31 0 1 2 3
7 6 5 4 3 2 1 0 15
17 18 19 20
31 0 1
BICK1(64fs)
SDTI(i)
Don't Care
15 14 13 12
1 0
Don't Care
15 14 13 12
2 1 0
SDTI-15:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 0 Timing
LRCK
0 1 2
20 21 22 23 24
31 0 1 2
20 21 22 23 24
31 0 1
BICK1(64fs)
SDTI(i)
23 22
4 3 2 1 0 Don't Care 23 22
4 3 2 1 0
Don't Care 23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 1 Timing
LRCK
0 1 2 3
21 22 23 24 25
0 1 2
21 22 23 24 25
0 1
BICK1(64fs)
SDTI(i)
23 22
4 3 2 1 0 Don't Care 23 22
4 3 2 1 0
Don't Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 2 Timing
LRCK
0 1 2
8 9
24
31 0 1 2
8 9
24
31 0 1
BICK(64fs)
SDTI(i)
Don't Care
23
8
1 0
Don't Care
23
8
1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 5. Mode 3 Timing
MS1076-J-01
2010/05
- 19 -
[AK4122A]
(2) PORT2
4
(Table 9) IDIF1-0 bit
PORT2
SDTIO BICK2
PORT2
PORT2
BICK2
MSB
BICK2
SDTIO
2’s
LRCK2
BICK2
LRCK2
fs 64fs
Mode
0
1
2
3
IDIF1
0
0
1
1
IDIF0
0
1
0
1
Output Format
Input Format
24bit, MSB justified
16bit, LSB justified
24bit, MSB justified
24bit, MSB justified
24bit, I2S Compatible
24bit, I2S Compatible
24bit, MSB justified
24bit, LSB justified
Table 9. Audio Interface Format for PORT2
LRCK
H/L
H/L
L/H
H/L
BICK
≥ 32fs
≥ 48fs
≥ 48fs
≥ 48fs
(default)
LRCK
9 10 11 12 13 14 15 0 1 2 3
0 1 2 3
9 10 11 12 13 14 15 0 1
BICK2(32fs)
SDTIO(o)
23 22 21
15 14 13 12 11 10 9 8 23 22 21
15 14 13 12 11 10 9 8 23
SDTIO(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 2 3
17 18 19 20
23 22 21
7 6 5 4 3
31 0 1 2 3
17 18 19 20
31 0 1
BICK2(64fs)
SDTIO(o)
SDTIO(i)
Don't Care
15 14 13 12
23 22 21
1 0
Don't Care
7 6 5 4 3
15 14 13 12
23
2 1 0
SDTIO-23:MSB, 0:LSB
SDTIO-15:MSB, 0:LSB
Lch Data
Rch Data
Figure 6. Mode 0 Timing
LRCK
0 1 2
20 21 22 23 24
31 0 1 2
20 21 22 23 24
31 0 1
BICK2(64fs)
SDTIO(o)
23 22
4 3 2 1 0
23 22
4 3 2 1 0
23
SDTIO(i)
23 22
4 3 2 1 0 Don't Care 23 22
4 3 2 1 0
Don't Care 23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 7. Mode 1 Timing
MS1076-J-01
2010/05
- 20 -
[AK4122A]
LRCK
0 1 2 3
21 22 23 24 25
21 22 23 24 25
0 1 2
0 1
BICK2(64fs)
SDTIO(o)
23 22
4 3 2 1 0
23 22
4 3 2 1 0
SDTIO(i)
23 22
4 3 2 1 0
Don't Care 23 22
4 3 2 1 0
Don't Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 8. Mode 2 Timing
LRCK
0 1 2
8 9
24
31 0 1 2
8 9
24
31 0 1
BICK2(64fs)
SDTIO(o)
SDTIO(i)
23 22
16 15
Don't Care
0
23
8
23 22
1 0
16 15
Don't Care
0
23
23
8
1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 9. Mode 3 Timing
(3) PORT3
2
(Table 10) ODIF bit
SDTO BICK
MSB
LRCK
LRCK
Mode
0
1
2’s
BICK
BICK
fs 64fs
ODIF
Output Format
LRCK
BICK
0
24bit, MSB justified
H/L
≥ 48fs
1
24bit, I2S Compatible
L/H
≥ 48fs
Table 10. Audio Interface Format for PORT3
(default)
LRCK
0 1 2 3
17 18 19 20
23 22 21
7 6 5 4 3
31 0 1 2 3
17 18 19 20
31 0 1
BICK(64fs)
SDTO(o)
23 22 21
7 6 5 4 3
23
SDTO-23:MSB, 0:LSB
Lch Data
Rch Data
Figure 10. Mode 0 Timing
MS1076-J-01
2010/05
- 21 -
[AK4122A]
LRCK
0 1 2 3
21 22 23 24 25
0 1 2
21 22 23 24 25
0 1
BICK(64fs)
23 22
SDTO(o)
4 3 2 1 0
23 22
4 3 2 1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 11. Mode 1 Timing
■
SRC
OR
−∞ (“0”)
−∞
1024LRCK
1024LRCK
SRC
SMUTE pin “L”
−∞
1024LRCK
SMUTE bit
SMUTE pin
SMUTE bit“1”
SMUTE pin “H”
SMUTE bit “0”
0dB
0dB
S MU TE
DAT T L eve l
(1 )
(1 )
(2 )
A tten u a tion
-∞
S DT IO / S D T O
Figure 12. Soft Mute Function
(1) 1024LRCK
(2) 1024LRCK
0dB
(1024/fs)
−∞ (“0”)
MS1076-J-01
2010/05
- 22 -
[AK4122A]
■
IIR
3
(32kHz, 44.1kHz, 48kHz)
(50/15μs
)
(1) DIR
DIR
DEAU bit = “1”
FS3-0 bit
DEAU bit = “0”
OFF
DEM1-0 bit
PEM bit = “0”
PEM
1
1
1
1
0
FS3
0
0
0
PORT1
FS1
0
1
1
FS0
0
0
1
(Others)
x
x
x
Table 11. De-emphasis Auto Control (DEAU bit = “1”)
x
PEM
1
1
1
1
(2) PORT1
FS2
0
0
0
Mode
44.1kHz
48kHz
32kHz
OFF
OFF
DEM1
DEM0
Mode
0
0
44.1kHz
0
1
OFF
(default)
1
0
48kHz
1
1
32kHz
Table 12. De-emphasis Manual Control (DEAU bit = “0”)
PORT2
PORT2
DEAU bit
DEM1-0 bit
OFF
DEM1
DEM0
Mode
0
0
44.1kHz
0
1
OFF
(default)
1
0
48kHz
1
1
32kHz
Table 13. De-emphasis Manual Control
■
AK4122A
PDN pin
PDN pin
PWN bit
“L”
PDN pin:
“L”
Read/Write
PWN bit (
“0”
00H D0):
Read/Write
MS1076-J-01
2010/05
- 23 -
[AK4122A]
■
AK4122A
PDN pin “L”
PDN pin = “L”
SDTO
“L”
PDN pin
“L”
100msec
“L”
SDTIO pin
External clocks
(input / output port)
(stable)
don’t care
don’t care
PDN
< 100msec
Power-down
(internal state)
PLL locktime & fs detection
SDTO
normal operation
Power-down
normal data
“0” data
“0” data
Figure 13.
■
AK4122A
Figure 14
AK4122A
“0”
100msec
fso/fsi > 4
PDN pin
External clocks
(Input port
or Output port)
Clocks 1
100msec
PWN bit “0”
“L”
Don’t care
Clocks 2
PDN pin
< 100ms
(Internal state) Normal operation Power-down PLL lock &
fs detection
SDTIO/SDTO
Normal data
SMUTE
(recommended)
Att.Level
Note16
Normal data
1024/fso
1024/fso
0dB
- ∞dB
(44.1kHz → 48kHz)
Figure 14.
Note 16.
PDN pin “L”
“0”
SDTIO “0”
Note 17.
1024/fso+100ms
Note 18. PDN pin
Note17
Normal operation
GD
SDTI
SMUTE
SMUTE pin=“H” PDN pin “H”
SDTI “0”
~ ms
MS1076-J-01
2010/05
- 24 -
[AK4122A]
■ 96kHz
DIR
PLL 32kHz
96kHz
20ms
MCLK2
OMCLK
(32k, 44.1k, 48k, 88.2k, 96k)
■
DIR
4
(RX1-4)
200mVpp
IPS1
0
0
1
1
IPS0
Input Data
0
RX1
1
RX2
0
RX3
1
RX4
Table 14. Recovery Data Select
(default)
■
TX pin
RX
TXE bit
75Ω
TX pin
AK4122A TX
OPS1
0
0
1
1
OPS0
Output Data
0
RX1
1
RX2
0
RX3
1
RX4
Table 15. Output Data Select for TX
MS1076-J-01
OPS1-0 bit
)
(
TX
(default)
2010/05
- 25 -
[AK4122A]
■
0.1uF
RX
75Ω
Coax
75Ω
AK4122A
Figure 15. Consumer Input Circuit (Coaxial Input)
Note 19. Coaxial
RX
50mV
Note 20.
PC
AK4122A AVSS
3.3V
Optical
Fiber
470
O/E
RX
Optical Receiver
AK4122A
Figure 16. Consumer Input Circuit (Optical Input, Using 3.3V Optical Receiver)
Coaxial
RX
RX
MS1076-J-01
2010/05
- 26 -
[AK4122A]
■ DIR
DIR
2
FSO
XTL1-0 bit ICKS1-0, OCKS1-0 bit
OMCLK
MCLK2
OMCLK
MCLK2
FS3-0 bit
XTL1-0 bit = “11”
FS3-0 bit
FS3-0 bit
“0001”
DIR
MCLK(MCLK2
MCLK
OMCLK)
FSO
XTL1
MCLK2 or OMCLK
ICKS1 / OCKS1
ICKS0 / OCKS0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Table 16. Reference MCLK Frequency
XTL0
44.1kHz
0
0
48kHz
0
1
96kHz
1
0
-
1
1
XTL1-0 bit = “11”
Register Output
fs
FS3
FS2
FS1
FS0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
0
Note 21.
Clock comparison
(Note 21)
44.1kHz
Reserved
48kHz
32kHz
88.2kHz
96kHz
±3%
± 3%
± 3%
± 3%
± 3%
± 3%
Table 17. fs Information
MCLK Frequency
11.2896MHz
16.9344MHz
22.5792MHz
33.8688MHz
12.288MHz
18.432MHz
24.576MHz
36.864MHz
24.576MHz
36.864MHz
N/A
N/A
(default)
XTL1-0 bit = “11”
Consumer Mode
Professional Mode
(Note 22)
Byte3
Byte0
Byte4
Bit3,2,1,0
Bit7,6
Bit6,5,4,3
0000
01
0000
0001
(others)
0000
0010
10
0000
0011
11
0000
(1000)
00
1010
(1010)
00
0010
Table 17
32kHz ∼ 96kHz
“1100”, “1110”
“0001”
Note 22.
Byte3 Bit3-0 FS3-0 bit
PEM bit
bit
“1”
(CS12 bit = “0”
2
PEM bit
0
1
)
1
Pre-emphasis
CS12
Consumer mode
Byte0 (Bit3,4,5)
OFF
≠ 0X100
ON
0X100
Table 18. PEM Information
MS1076-J-01
Professional mode
Byte0 (Bit2,3,4)
≠ 100
100
2010/05
- 27 -
[AK4122A]
■ DIR
INT2-0 pin
“H”
9
1. UNLCK: PLL
UNLCK bit = “1”
2. PAR:
PAR bit = “1”
3. AUTO:
Non-Linear PCM
DTS-CD
NPCM bit DTSCD bit OR
4. V:
5. AUDN:
AUDIO
6. STC:
FS3-0 bit, PEM bit
7. CINT:
1
STC bit = “1”
Sync
1
8. QINT:
9. DAT:
U bit Sync
U-bit
1
QINT bit = “1”
Sync
DAT Start ID
DAT
INT1-0 pin
CINT bit = “1”
1
9
INT pin
DAT Start ID
DAT bit = “1”
OR
(
07H, 08H(DAT bit)
1024/fs(EFH1-0 bit
“L”
INT1
1∼5
INT2 pin
07H, 08H Read
)
) INT0
“H”
6 ∼ 9 OR
“H”
07H UNLCK, PAR, AUTO, V, AUDN bit
STC, QINT, CINT
08H DAT bit
07H, 08H(DAT bit)
“0”
“1”
INT0
UNLCK, PAR bit
INT2-0 pin “L”
“H”
INT0
INT1 AUTO, V, AUDN bit
MS1076-J-01
INT2
DIR
2010/05
- 28 -
[AK4122A]
DIR
bit “1”
SDTIO
“0”
AMUTE
Audio
SDTO
SDTIO
Non-PCM/DTS-CD
AMUTE bit
SDTO
“L”
(1) UNLCK, PAR, AUTO, V, AUDN bit
Interrupt
(UNLCK, PAR, AUTO, V, AUDN)
INT0 pin
Hold Time (max:4096/fs)
INT1 pin
Hold Time = 0
INT2 pin
Register 07H
“0”
Hold “1”
“0”
Read 07H
BICK, LRCK (UNLCK)
Free Run
fs : around 20kHz
BICK, LRCK (except UNLCK)
SDTIO / SDTO (AMUTE = “1”)
(UNLCK, AUTO, V, AUDN)
Mute
SDTIO / SDTO (AMUTE = “0”)
(UNLCK)
“L” Output
SDTIO / SDTO (AMUTE = “0”)
(AUTO, V, AUDN)
SDTIO / SDTO (PAR error)
Previous Data
: Normal Operation
Figure 17. INT2-0 Timing (UNLCK, PAR, AUTO, V, AUDN bits)
MS1076-J-01
2010/05
- 29 -
[AK4122A]
(2) STC, CINT, QINT bit
Interrupt
(FS3-0, PEM, C-bit, Q-sub)
Interrupt
(STC, CINT, QINT)
INT0 pin
(1)
(1)
(2)
INT1 pin
(2)
INT2 pin
Register 07H
“0”
Hold “1”
“0”
Hold “1”
“0”
Read 07H
BICK, LRCK
SDTIO / SDTO
: Normal Operation
Figure 18. INT2-0 Timing (STC, CINT, QINT bits)
(1) Hold Time : max. 4096/fs
(2) Hold Time = 0
MS1076-J-01
2010/05
- 30 -
[AK4122A]
(3) DAT bit
Interrupt
(DAT)
INT0 pin
(1)
(1)
(2)
INT1 pin
(2)
INT2 pin
Register 08H
“0”
Hold “1”
“0”
Hold “1”
“0”
Read 08H
BICK, LRCK
SDTIO / SDTO
: Normal Operation
Figure 19. INT2-0 Timing (DAT bit)
(1) Hold Time : max. 4096/fs
(2) Hold Time = 0
MS1076-J-01
2010/05
- 31 -
[AK4122A]
PDN pin ="L" to "H"
Initialize
Read 07H, 08H
INT0/1 pin ="H"
No
Yes
Release
Muting
Mute SDTIO / SDTO
Read 07H, 08H
(Each Error Handling)
Read 07H, 08H
(Resets registers)
No
INT0/1 pin ="H"
Yes
Figure 20. Interrupt Handling Sequence Example 1
MS1076-J-01
2010/05
- 32 -
[AK4122A]
PDN pin ="L" to "H"
Initialize
Read 07H
No
INT1 pin ="H"
Yes
Read 07H
and
Detect QSUB= “1”
(Read Q-buffer)
QCRC = “0”
No
New data
is invalid
Yes
INT1 pin ="L"
No
Yes
New data
is valid
Figure 21. Interrupt Handling Sequence Example 2
MS1076-J-01
2010/05
- 33 -
[AK4122A]
■ U-bit (Q-subcode)
DIR
U bit
CD Q-subcode
(1) Subcode sync word (S0,S1)
16
(2) Start bit “1”
(3) Q-W 7 bit Start bit
(4) Start bit
8-16 bit
Q-subcode
QINT
S0
S1
S2
S3
:
S97
S0
S1
S2
S3
:
Q2
Q3 Q4
CTRL
“0” bit
Q5
Q6
Q7 Q8
ADRS
1
0
0
1
1
:
1
0
0
1
1
:
QINT bit “0”
2
3
4
5
6
7
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Q2
R2
S2
T2
U2
V2
W2
Q3
R3
S3
T3
U3
V3
W3
:
:
:
:
:
:
:
Q97 R97 S97 T97 U97 V97 W97
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Q2
R2
S2
T2
U2
V2
W2
Q3
R3
S3
T3
U3
V3
W3
:
:
:
:
:
:
:
(*)
number
of
“0”
:
min=0;
max=8.
↑
Q
Figure 22. Configuration of U-bit(CD)
Q9
*
0…
0…
0…
0…
:
0…
0…
0…
0…
0…
:
Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25
TRACK NUMBER
INDEX
Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49
MINUTE
SECOND
FRAME
Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73
ZERO
ABSOLUTE MINUTE
ABSOLUTE SECOND
Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97
ABSOLUTE FRAME
CRC
G(x)=x16+x12+x5+1
Figure 23. Q-subcode
Addr
Register Name
13H Q-subcode Address / Control
14H
Q-subcode Track
15H
Q-subcode Index
16H
Q-subcode Minute
17H
Q-subcode Second
18H
Q-subcode Frame
19H
Q-subcode Zero
1AH
Q-subcode ABS Minute
1BH
Q-subcode ABS Second
1CH
Q-subcode ABS Frame
D7
D6
D5
D4
Q9
Q8
···
···
Q17
Q16
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
Q81
Q80
···
···
Figure 24. Q-subcode register map
MS1076-J-01
D3
···
···
···
···
···
···
···
···
···
···
D2
···
···
···
···
···
···
···
···
···
···
D1
Q3
Q11
···
···
···
···
···
···
···
Q75
D0
Q2
Q10
···
···
···
···
···
···
···
Q74
2010/05
- 34 -
[AK4122A]
■ Non-PCM/DTS-CD
DIR
Non-PCM
Dolby “AC-3 Data Stream in IEC60958 Interface”
32-bit Mode Non-PCM
NPCM bit “1”
96-bit sync code 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F
NPCM bit
“1”
4096
4096
sync code
NPCM
bit = “0”
sync code
NPCM bit “0”
(
: Figure 27, Figure
28
)
sync code
2
(Pc: burst information, Pd: length
code; Table 22, Table 23
)
DTS-CD
DTSCD bit “1”
4096
sync code
DTSCD bit = “0”
sync code
DTSCD bit “0”
NPCM bit DTSCD bit OR AUTO bit
AK4122A DTS-CD
14-bit Sync Word 16-bit Sync Word
DTS14, DTS16 bit
ON/OFF
■
4
I/F
: CSN, CCLK, CDTI, CDTO
I/F
Chip
address(2bits, C1/0, “00”
) Read/Write(1bit) Register address(MSB first, 5bits) Control data(MSB first, 8bits)
CCLK “↓”
“↑”
CSN “↑”
CCLK
5MHz(max)
“00”
“00”
PDN pin = “L”
Read/Write MCLK, BICK, LRCK
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
C1
C0
R/W
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
CCLK
CDTI
Write
Hi-Z
CDTO
CDTI
C1
C0
R/W
A4
A3
A2
A1
A0
Read
CDTO
Hi-Z
Hi-Z
C1 - C0 : Chip Address (Fixed to "00")
R/W :
READ / WRITE ("1" : WRITE, "0" : READ)
A4 - A0 : Register Address
D7 - D0 : Control Data
Figure 25. Control I/F Timing
MS1076-J-01
2010/05
- 35 -
[AK4122A]
■
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
Register Name
PDN & Mode Control
Selector & Clock Control
Audio Interface Format
DIR Control
INT0/2 Mask
INT1 Mask
DAT Mask & DTS Detect
Receiver Status 0
Receiver Status 1
Receiver Status 2
RX Channel Status Byte 0
RX Channel Status Byte 1
RX Channel Status Byte 2
RX Channel Status Byte 3
RX Channel Status Byte 4
Burst Preamble Pc Byte 0
Burst Preamble Pc Byte 1
Burst Preamble Pd Byte 0
Burst Preamble Pd Byte 1
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
D7
XTL1
BYPS
0
CS12
MULK0
MULK1
0
UNLCK
DAT
0
CR7
CR15
CR23
CR31
CR39
PC7
PC15
PD7
PD15
Q9
Q17
Q25
Q33
Q41
Q49
Q57
Q65
Q73
Q81
D6
XTL0
OSEL
0
AMUTE
MPAR0
MPAR1
0
PAR
DTSCD
0
CR6
CR14
CR22
CR30
CR38
PC6
PC14
PD6
PD14
Q8
Q16
Q24
Q32
Q40
Q48
Q56
Q64
Q72
Q80
D5
TXE
ISEL1
0
EFH1
MAUT0
MAUT1
0
AUTO
NPCM
0
CR5
CR13
CR21
CR29
CR37
PC5
PC13
PD5
PD13
Q7
Q15
Q23
Q31
Q39
Q47
Q55
Q63
Q71
Q79
D4
SMUTE
ISEL0
ODIF
EFH0
MV0
MV1
0
V
PEM
0
CR4
CR12
CR20
CR28
CR36
PC4
PC12
PD4
PD12
Q6
Q14
Q22
Q30
Q38
Q46
Q54
Q62
Q70
Q78
D3
DEAU
ICKS1
IDIF1
IPS1
MAUD0
MAUD1
DTS16
AUDN
FS3
0
CR3
CR11
CR19
CR27
CR35
PC3
PC11
PD3
PD11
Q5
Q13
Q21
Q29
Q37
Q45
Q53
Q61
Q69
Q77
D2
DEM1
ICKS0
IDIF0
IPS0
MSTC0
MSTC1
DTS14
STC
FS2
0
CR2
CR10
CR18
CR26
CR34
PC2
PC10
PD2
PD10
Q4
Q12
Q20
Q28
Q36
Q44
Q52
Q60
Q68
Q76
D1
DEM0
OCKS1
DIF1
OPS1
MCIT0
MCIT1
MDAT1
CINT
FS1
CCRC
CR1
CR9
CR17
CR25
CR33
PC1
PC9
PD1
PD9
Q3
Q11
Q19
Q27
Q35
Q43
Q51
Q59
Q67
Q75
D0
PWN
OCKS0
DIF0
OPS0
MQIT0
MQIT1
MDAT0
QINT
FS0
QCRC
CR0
CR8
CR16
CR24
CR32
PC0
PC8
PD0
PD8
Q2
Q10
Q18
Q26
Q34
Q42
Q50
Q58
Q66
Q74
PDN pin = “L”
DIR
(07H ∼ 1CH)
Note 23. “0”
Note 24.
(PORT1
PORT2
)
“1”
1DH ∼ 1FH
MS1076-J-01
2010/05
- 36 -
[AK4122A]
■
Addr Register Name
00H PDN & Mode Control
R/W
Default
D7
XTL1
R/W
1
D6
XTL0
R/W
1
D5
TXE
R/W
1
PWN: Power Down Control
0: Power down
1: Normal operation (default)
“0”
(00H ∼ 06H)
D4
SMUTE
R/W
0
D3
DEAU
R/W
0
D2
DEM1
R/W
0
D1
DEM0
R/W
1
D0
PWN
R/W
1
(07H ∼ 1CH)
DEM1-0: De-emphasis Control (Table 12, Table 13)
“01”
DEAU:
De-emphasis Auto Control
0: Disable (default)
1: Enable
“1”
SMUTE: Soft Mute Control
0: Normal operation (default)
1: SDTIO and SDTO soft mute
“1”
SDTIO
SDTO
TXE:
TX Output enable
0: Disable, TX outputs “L”.
1: Enable (default)
XTL1-0: Reference MCLK Frequency Select (Table 16)
“11”
MS1076-J-01
2010/05
- 37 -
[AK4122A]
Addr Register Name
01H Selector & Clock Control
R/W
Default
D7
BYPS
R/W
0
D6
OSEL
R/W
0
D5
ISEL1
R/W
0
D4
ISEL0
R/W
0
D3
ICKS1
R/W
1
D2
ICKS0
R/W
0
D1
OCKS1
R/W
1
D0
OCKS0
R/W
0
OCKS1-0: OMCLK Frequency Select for Master mode (Table 5)
“10”
ICKS1-0: MCLK2 Frequency Select for Master mode (Table 4)
“10”
ISEL1-0: Input Port Select
“00”
ISEL1
0
0
1
1
ISEL0
Input PORT
(default)
0
PORT1
1
PORT2
0
DIR
1
N/A
Table 19. Input PORT Select
OSEL: Output Port Select
“0”
OSEL
Output PORT
(default)
0
PORT3
1
PORT2
Table 20. Output PORT Select
BYPS: Select Bypass mode
0: SRC mode (default)
1: Bypass mode
“1”
SRC
MS1076-J-01
2010/05
- 38 -
[AK4122A]
Addr Register Name
02H Audio Interface Format
R/W
Default
DIF1-0:
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
ODIF
R/W
0
D3
IDIF1
R/W
0
D2
IDIF0
R/W
1
D1
DIF1
R/W
0
D0
DIF0
R/W
1
D5
EFH1
R/W
0
D4
EFH0
R/W
1
D3
IPS1
R/W
0
D2
IPS0
R/W
0
D1
OPS1
R/W
0
D0
OPS0
R/W
0
SDTIO
SDTO
Audio Interface Format for PORT1 (Table 8)
“01”
IDIF1-0: Audio Interface Format for PORT2 (Table 9)
“01”
ODIF: Audio Interface Format for PORT3 (Table 10)
“0”
Addr Register Name
03H DIR Control
R/W
Default
D7
CS12
R/W
0
D6
AMUTE
R/W
1
OPS1-0:
Output Through Data Select for TX (Table 15)
“00”
IPS1-0:
Input Recovery Data Select (Table 14)
“00”
EFH1-0:
Interrupt 0 pin Hold Time Select
“01”
Table 21 LRCK DIR LRCK
EFH1
0
0
1
1
AMUTE: Auto Mute Control
0: Normal operation
1: Auto Mute (default)
“1”
1/fs
EFH0
Hold Count
0
512LRCK
(default)
1
1024LRCK
0
2048LRCK
1
4096LRCK
Table 21. Hold Time Select
Audio
Non-PCM/DTS-CD
CS12: Channel Status select
0: Channel 1 (default)
1: Channel 2
C-bit, AUDN, FS3-0, PEM, Pc, Pd, CRC
MS1076-J-01
2010/05
- 39 -
[AK4122A]
Addr Register Name
04H INT0/2 Mask
R/W
Default
D7
MULK0
R/W
0
MQIT0:
Mask enable for QINT bit
0: Mask disable
1: Mask enable
MCIT0:
Mask enable for CINT bit
0: Mask disable
1: Mask enable
MSTC0:
Mask enable for STC bit
0: Mask disable
1: Mask enable
D6
MPAR0
R/W
0
D5
MAUT0
R/W
1
D4
MV0
R/W
1
D3
MAUD0
R/W
1
D2
MSTC0
R/W
1
D1
MCIT0
R/W
1
D0
MQIT0
R/W
1
MAUD0: Mask enable for AUDN bit
0: Mask disable
1: Mask enable
MV0:
Mask enable for V bit
0: Mask disable
1: Mask enable
MAUT0: Mask enable for AUTO bit
0: Mask disable
1: Mask enable
MPAR0: Mask enable for PAR bit
0: Mask disable
1: Mask enable
MULK0: Mask enable for UNLCK bit
0: Mask disable
1: Mask enable
“0”
INT0 pin
INT2 pin
MS1076-J-01
2010/05
- 40 -
[AK4122A]
Addr Register Name
05H INT1 Mask
R/W
Default
D7
MULK1
R/W
1
MQIT1:
Mask enable for QINT bit
0: Mask disable
1: Mask enable
MCIT1:
Mask enable for CINT bit
0: Mask disable
1: Mask enable
MSTC1:
Mask enable for STC bit
0: Mask disable
1: Mask enable
D6
MPAR1
R/W
1
D5
MAUT1
R/W
0
D4
MV1
R/W
0
D3
MAUD1
R/W
0
D2
MSTC1
R/W
1
D1
MCIT1
R/W
1
D0
MQIT1
R/W
1
MAUD1: Mask enable for AUDN bit
0: Mask disable
1: Mask enable
MV1:
Mask enable for V bit
0: Mask disable
1: Mask enable
MAUT1: Mask enable for AUTO bit
0: Mask disable
1: Mask enable
MPAR1: Mask enable for PAR bit
0: Mask disable
1: Mask enable
MULK1: Mask enable for UNLCK bit
0: Mask disable
1: Mask enable
“0”
INT1 pin
MS1076-J-01
2010/05
- 41 -
[AK4122A]
Addr Register Name
06H DAT Mask & DTS Detect
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
DTS16
R/W
1
D2
DTS14
R/W
1
D1
MDAT1
R/W
1
D0
MDAT0
R/W
1
MDAT0: Mask enable for DAT bit
0: Mask disable
1: Mask enable
“0”
INT0 pin
INT2 pin
MDAT1: Mask enable for DAT bit
0: Mask disable
1: Mask enable
“0”
INT1 pin
DTS14:
DTS-CD 14bit Sync Word Detect
0: Disable
1: Enable (default)
DTS16:
DST-CD 16bit Sync Word Detect
0: Disable
1: Enable (default)
MS1076-J-01
2010/05
- 42 -
[AK4122A]
Addr Register Name
07H Receiver Status 0
R/W
Default
D7
UNLCK
RD
0
D6
PAR
RD
0
D5
AUTO
RD
0
QINT: Q-subcode Buffer Interrupt
0: No change
1: Changed
Addr=13H
1CH
Q
CINT: Channel Status Buffer Interrupt
0: No change
1: Changed
Addr=0AH
0EH
C bit
STC:
D2
STC
RD
0
D1
CINT
RD
0
D0
QINT
RD
0
“1”
“1”
Audio Bit Output
0: Audio
1: Non audio
Validity Bit
0: Valid
1: Invalid
AUTO:
PAR:
D3
AUDN
RD
0
Sampling Frequency or Pre-emphasis Information Change Detection
0: No detect
1: Detect
FS3-0 bit
PEM bit
STC bit “1”
AUDN:
V:
D4
V
RD
0
Non-PCM or DTS-CD Bit Steam Auto Detection
0: No detect
1: Detect
NPCM bit DTSCD bit OR
Parity Error or Bi-phase Error Status
0: No error
1: Error
“1”
UNLCK: PLL Lock Status
0: Lock
1: Unlock
QINT, CINT, STC
Addr=07H
READ
MS1076-J-01
“0”
2010/05
- 43 -
[AK4122A]
Addr Register Name
08H Receiver Status 1
R/W
Default
D7
DAT
RD
0
D6
DTSCD
RD
0
D5
NPCM
RD
0
D4
PEM
RD
0
D3
FS3
RD
0
D2
FS2
RD
0
D1
FS1
RD
0
D0
FS0
RD
1
FS3-0: Sampling Frequency Detect (Table 17)
PEM:
NPCM:
Pre-emphasis Detect (Table 18)
0: OFF
1: ON
Non-PCM Bit Stream Auto Detect
0: No detect
1: Detect
DTSCD: DTS-CD Bit Stream Auto Detect
0: No detect
1: Detect
DAT:
DAT Start ID Detect
0: No detect
1: Detect
DAT
DAT bit Addr=08H
Addr Register Name
09H Receiver Status 2
R/W
Default
READ
Start ID
“1”
“1”
“0”
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
0
RD
0
D1
CCRC
RD
0
D0
QCRC
RD
0
QCRC: Cyclic Redundancy Check for Q-subcode
0: No error
1: Error
CCRC: Cyclic Redundancy Check for Channel Status
0: No error
1: Error
CS12 bit
MS1076-J-01
2010/05
- 44 -
[AK4122A]
Addr
0AH
0BH
0CH
0DH
0EH
Register Name
RX Channel Status Byte 0
RX Channel Status Byte 1
RX Channel Status Byte 2
RX Channel Status Byte 3
RX Channel Status Byte 4
R/W
Default
CR39-0:
Addr
0FH
10H
11H
12H
D7
CR7
CR15
CR23
CR31
CR39
D5
CR5
CR13
CR21
CR29
CR37
D4
CR4
CR12
CR20
CR28
CR36
D3
CR3
CR11
CR19
CR27
CR35
D2
CR2
CR10
CR18
CR26
CR34
D1
CR1
CR9
CR17
CR25
CR33
D0
CR0
CR8
CR16
CR24
CR32
D2
PC2
PC10
PD2
PD10
D1
PC1
PC9
PD1
PD9
D0
PC0
PC8
PD0
PD8
D2
Q4
Q12
Q20
Q28
Q36
Q44
Q52
Q60
Q68
Q76
D1
Q3
Q11
Q19
Q27
Q35
Q43
Q51
Q59
Q67
Q75
D0
Q2
Q10
Q18
Q26
Q34
Q42
Q50
Q58
Q66
Q74
RD
Not initialized
Receiver Channel Status Byte 4-0
1
(192
)
40
Register Name
Burst Preamble Pc Byte 0
Burst Preamble Pc Byte 1
Burst Preamble Pd Byte 0
Burst Preamble Pd Byte 1
R/W
Default
D7
PC7
PC15
PD7
PD15
Burst Preamble Pc Byte 0 and 1
PD15-0:
Burst Preamble Pd Byte 0 and 1
Register Name
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
R/W
Default
Q81-2: Q-subcode
U bit 1
D6
PC6
PC14
PD6
PD14
D5
PC5
PC13
PD5
PD13
D4
PC4
PC12
PD4
PD12
D3
PC3
PC11
PD3
PD11
RD
Not initialized
PC15-0:
Addr
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
D6
CR6
CR14
CR22
CR30
CR38
D7
Q9
Q17
Q25
Q33
Q41
Q49
Q57
Q65
Q73
Q81
D6
Q8
Q16
Q24
Q32
Q40
Q48
Q56
Q64
Q72
Q80
D5
Q7
Q15
Q23
Q31
Q39
Q47
Q55
Q63
Q71
Q79
D4
Q6
Q14
Q22
Q30
Q38
Q46
Q54
Q62
Q70
Q78
D3
Q5
Q13
Q21
Q29
Q37
Q45
Q53
Q61
Q69
Q77
RD
Not initialized
80
MS1076-J-01
2010/05
- 45 -
[AK4122A]
■ Non-PCM
sub-frame of IEC60958
0
3 4
preamble
7 8
Aux.
11 12
27 28 29 30 31
LSB
MSB V U C P
16 bits of bitstream
0
Pa Pb Pc Pd
15
Burst_payload
stuffing
repetition time of the burst
Figure 26. Data Structure of IEC60958
Preamble word
Pa
Pb
Pc
Pd
Length of field
Contents
16 bits
sync word 1
16 bits
sync word 2
16 bits
Burst info
16 bits
Length code
Table 22. Burst Preamble Word
MS1076-J-01
Value
0xF872
0x4E1F
see Table 23
numbers of bits
2010/05
- 46 -
[AK4122A]
Repetition time of burst
in IEC60958 frames
Bits of Pc Value
Contents
0-4
data type
NULL data
Dolby AC-3 data
reserved
PAUSE
MPEG-1 Layer1 data
MPEG-1 Layer2 or 3 data or MPEG-2 without extension
MPEG-2 data with extension
MPEG-2 AAC ADTS
MPEG-2, Layer1 Low sample rate
MPEG-2, Layer2 or 3 Low sample rate
reserved
DTS type I
DTS type II
DTS type III
ATRAC
ATRAC2/3
reserved
reserved, shall be set to “0”
error-flag indicating a valid burst_payload
error-flag indicating that the burst_payload may contain
errors
data type dependent info
bit stream number, must be set to “0”
Table 23. Field of Burst Information Pc
7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-31
0
0
1
8-12
13-15
0
5, 6
MS1076-J-01
≤ 4096
1536
384
1152
1152
1024
384
1152
512
1024
2048
512
1024
2010/05
- 47 -
[AK4122A]
■ Non-PCM
Non-PCM
4096
PDN pin
Bit stream
Pa Pb Pc1 Pd1
Pa Pb Pc2 Pd2
Repetition time
Pa Pb Pc3 Pd3
>4096 frames
AUTO bit
Pc Register
“0”
Pd Register
“0”
Pc1
Pc3
Pc2
Pd1
Pd3
Pd2
Figure 27. Timing example 1
Non-PCM
(MULK0 bit= “0”
)
INT0 hold time
INT0 pin
<20mS (Lock time)
Bit stream
Pa Pb Pc1 Pd1
Stop
Pa Pb Pcn Pdn
2~3 Syncs (B,M or W)
<Repetition time
AUTO bit
Pc Register
Pd Register
Pc0
Pcn
Pc1
Pd0
Pd1
Pdn
Figure 28. Timing example 2
MS1076-J-01
2010/05
- 48 -
[AK4122A]
Figure 29
(AKD4122A)
• PORT2, PORT3 : Slave Mode
Digital Supply
3.0 ~ 3.6V
uP & DSP
DSP3
10μ
fso
0.1μ
48
47
46
45
44
43
42
41
40
39
38
37
CCLK
CSN
BVSS
DVDD
DVSS
OMCLK
LRCK
BICK
SDTO
TX
INT1
INT0
1 CDTI
SDTIO 36
2 CDTO
BICK2 35
3 TST1
LRCK2 34
4 INT2
MCLK2 33
5 TST2
DVDD 32
Top View
6 TST3
7 M/S2
0.1μ
10μ
Digital Supply
3.0 ~ 3.6V
DVSS 31
SDTI 30
8 M/S3
DSP1
BICK1 29
9 SMUTE
LRCK1 28
10 TST4
PDN 27
11 TST5
AVSS 26
fsi
Reset
RX1
TST7
RX2
TST8
RX3
TST9
RX4
TST10
TST11
2.2μ
TST6
470Ω
AVDD
R 25
AVSS
12 FILT
2.2n
DSP2
fsi
13
14
15
16
17
18
19
20
21
22
23
24
12kΩ
0.1μ
10μ
Shield
Analog Supply
3.0 ~ 3.6V
Shield
Shield
Shield
Shield
S/PDIF
sources
:
- AK4122A AVSS, BVSS, DVSS
Figure 29. Typical Connection Diagram
MS1076-J-01
2010/05
- 49 -
[AK4122A]
1.
AVDD, DVDD
AVSS, BVSS, DVSS
PC
2. PLL
FILT pin
470Ω
AVSS
(R1) 2.2μF
(Figure 30
(C1)
) FILT pin
2.2nF
(C2)
AK4122A
FILT
R1
C2
C1
AVSS
Parameter
Recommended value
Accuracy
R1
470Ω
−5% ∼ +5%
C1
2.2μF
−50% ∼ +50%
C2
2.2nF
−50% ∼ +50%
Note: The accuracy includes temperature dependence.
Figure 30. Loop Filter for SRC
R pin
12kΩ
(Figure 31
(R2) AVSS
)
R pin
AK4122A
R
R2
AVSS
Parameter
Recommended value
Accuracy
R2
12kΩ
−5% ∼ +5%
Note: The accuracy includes temperature dependence.
Figure 31. Loop Filter for DIR
MS1076-J-01
2010/05
- 50 -
[AK4122A]
3.
Figure 32
AK4122A ILRCK
Figure 32
0.01UIpp
AK4122A Jitter Tolerance
10.00
1.00
Amplitude [UIpp]
(3)
(2)
0.10
0.01
(1)
0.00
1
10
100
1000
10000
Frequency [Hz]
(1)
(2)
(3)
(−50dB
- 1UI (Unit Interval) ILRCK 1
)
FSI = 48kHz
1UI 1/48kHz = 20.8μs
Figure 32. Jitter Tolerance
MS1076-J-01
2010/05
- 51 -
[AK4122A]
48pin LQFP(Unit: mm)
1.70Max
9.0 ± 0.2
0.13 ± 0.13
7.0
36
25
24
48
13
7.0
37
1
9.0 ± 0.2
1.40 ± 0.05
12
0.16 ± 0.07
0.5
0.22 ± 0.08
0.10 M
0° ∼ 10°
0.10
0.5 ± 0.2
■ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS1076-J-01
2010/05
- 52 -
[AK4122A]
AKM
AK4122AVQ
XXXXXXX
1
XXXXXXXX: Date code identifier
Date (YY/MM/DD)
09/05/19
Revision
00
10/05/17
01
Reason
Page
24
MS1076-J-01
Contents
■
Note
2010/05
- 53 -
[AK4122A]
z
z
z
z
z
z
MS1076-J-01
2010/05
- 54 -