[AK4430] AK4430 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output AK4430 2Vrms 24 ΔΣ DAC (SCF) 192kHz Set-Top-Box, 3.3V TV AV 2Vrms , 16pin TSSOP 128 64 32 24 2Vrms : 8kHz ∼ 192kHz 2 4 8 FIR SCF I/F : 24 : 512fs, 768fs or 1152fs 256fs or 384fs 2 128fs or 192fs 4 , I2S THD+N: –91dB Dynamic Range: 104dB : +3.0 ∼ +3.6V Ta = -20 to 85°C : 16pin TSSOP (6.4mm x 5.0mm) MCLK VDD SMUTE DIF Clock Divider Control Interface VREFH 2.2μ VSS1 LRCK BICK SDTI Audio Data Interface 8X Interpolator ΔΣ Modulator SCF LPF 8X Interpolator ΔΣ Modulator SCF LPF AOUTL AOUTR Charge Pump CP CN 1μ MS1196-J-00 VEE VSS2 CVDD 1μ 2010/05 -1- [AK4430] ■ -20 ∼ +85°C AK4430 AK4430ET AKD4430 16pin TSSOP (0.65mm pitch) ■ ■ AK4430 CN 1 16 VEE CP 2 15 VSS2 SMUTE 3 14 CVDD MCLK 4 13 VREFH BICK 5 12 VSS1 SDTI 6 11 VDD LRCK 7 10 AOUTL DIF 8 9 AOUTR AK4430 Top View AK4420, AK4424, AK4421, AK4421A Power Supply Digital de-emphasis I/F format Pin out Pin#3 Pin#8 Pin#13 THD+N DR Operating Temperature AK4420 +4.5 ∼ +5.5V 24-bit MSB/I²S SMUTE DIF DZF -92dB 105dB ET: -20 ∼ +85°C VT: -40 ∼ +85°C AK4424 +4.5 ∼ +5.5V X I²S DEM SMUTE DZF -92dB 105dB AK4421 +3.0 ∼ +3.6V 24-bit MSB/I²S SMUTE DIF DZF -92dB (-3dBFS) 102dB AK4421A +3.0 ∼ +3.6V 24-bit MSB/I²S SMUTE DIF* DZF -92dB 102dB AK4430 +3.0 ∼ +3.6V 24-bit MSB/I²S SMUTE DIF* VREFH -91dB 104dB ET: -20 ∼ +85°C ET: -20 ∼ +85°C ET: -20 ∼ +85°C ET: -20 ∼ +85°C (-: Not available, X: Available) *: Internal pull up (100kΩ) MS1196-J-00 2010/05 -2- [AK4430] No. Pin Name I/O Function Negative Charge Pump Capacitor Terminal Pin Connect to CP with a 1.0μF low ESR (Equivalent Series Resistance) capacitor 1 CN I over all temperature. When this capacitor is polarized, the positive polarity pin should be connected to the CP pin. Non-polarized capacitors can also be used. Positive Charge Pump Capacitor Terminal Pin Connect to CN with a 1.0μF low ESR (Equivalent Series Resistance) 2 CP I capacitor over temperature. When this capacitor is polarized, the positive polarity pin should be connected to the CP pin. Non-polarized capacitors can also be used. Soft Mute Enable Pin (Internal pull down: 100kΩ) 3 SMUTE I “H”: Enable, “L”: Disable 4 MCLK I Master Clock Input Pin 5 BICK I Audio Serial Data Clock Pin 6 SDTI I Audio Serial Data Input Pin 7 LRCK I L/R Clock Pin Audio Data Interface Format Pin (Internal pull up: 100kΩ) 8 DIF I “L”: 24-bit MSB Justified, “H”: I2S, Right channel Analog Output Pin 9 AOUTR O When MCLK or LRCK or BICK stops, outputs VSS(0V, typ). Left channel Analog Output Pin 10 AOUTL O When MCLK or LRCK or BICK stops, outputs VSS(0V, typ). 11 VDD Power Supply Pin, 3.0V∼3.6V 12 VSS1 Ground Pin 1 Reference Output Pin 13 VREFH O Connect to VSS with a 2.2μF low ESR capacitor over all temperature. 14 CVDD Charge Pump Power Supply Pin 15 VSS2 Ground Pin 2 Negative Voltage Output Pin Connect to VSS2 with a 1.0μF low ESR capacitor over all temperature. 16 VEE O When this capacitor is polarized, the positive polarity pin should be connected to the VSS2 pin. Non-polarized capacitors can also be used. Note: All input pins except for the SMUTE and DIF pins should not be left floating. MS1196-J-00 2010/05 -3- [AK4430] (VSS1=VSS2=0V; Note 1) Parameter Power Supply Symbol VDD CVDD IIN VIND Ta Tstg Input Current (any pins except for supplies) Input Voltage (Note 3) Ambient Operating Temperature Storage Temperature Note 1. Note 2. VSS1 VSS2 Note 3. SMUTE, MCLK, BICK, LRCK, SDTI, DIF pins min -0.3 -0.3 -0.3 -20 -65 max +4.0 +4.0 ±10 VDD+0.3 85 150 Units V V mA V °C °C : (VSS1=VSS2=0V; Note 1) Parameter Power Supply Symbol VDD CVDD min +3.0 typ max +3.6 Units V VDD Note 4. VDD CVDD : MS1196-J-00 2010/05 -4- [AK4430] ( Ta = 25°C; VDD=CVDD = +3.3V; fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ) Parameter min typ max Units Resolution 24 Bits Dynamic Characteristics (Note 5) THD+N fs=44.1kHz, BW=20kHz -91 -82 dB fs=96kHz, BW=40kHz -91 dB fs=192kHz, BW=40kHz -89 dB Dynamic Range (-60dBFS with A-weighted, Note 6) 96 104 dB S/N (A-weighted, Note 7) 96 104 dB Interchannel Isolation (1kHz) 90 100 dB Interchannel Gain Mismatch 0.2 0.5 dB PSRR (Note 9) DC Accuracy DC Offset (at output pin) Gain Drift Output Voltage (Note 8) Load Capacitance (Note 10) Load Resistance Power Supplies Power Supply Current: (Note 11) Normal Operation (fs≤96kHz) Normal Operation (fs=192kHz) Power-Down Mode (Note 12) Note 5. Audio Precision (System Two) Note 6. 98dB at 16bit data Note 7. S/N Note 8. (0dB) VDD AOUT (typ.@ 0dB) = 2.0Vrms × VDD/3.3. Note 9. VDD CVDD 1kHz, 50mVpp Note 10. Note 11. VDD CVDD Note 12. (MCLK, BICK, LRCK) 62 -5 1.85 dB 0 100 2.0 +5 2.15 25 mV ppm/°C Vrms pF kΩ 20 22 10 28 31 100 mA mA μA 5 VDD MS1196-J-00 VSS 2010/05 -5- [AK4430] (Ta = 25°C; VDD=CVDD= +3.0 ∼ +3.6V; fs = 44.1kHz) Parameter Symbol Digital filter PB Passband ±0.05dB (Note 13) -6.0dB Stopband (Note 13) SB Passband Ripple PR Stopband Attenuation SA Group Delay (Note 14) GD Digital Filter + LPF Frequency Response 20.0kHz fs=44.1kHz FR 40.0kHz fs=96kHz FR 80.0kHz fs=192kHz FR Note 13. fs ( PB=0.4535×fs(@±0.05dB) SB=0.546×fs Note 14. 16/24 min typ max Units 0 24.1 22.05 20.0 - 64 - 24 - kHz kHz kHz dB dB 1/fs - ± 0.05 ± 0.05 ± 0.05 - dB dB dB ± 0.01 ) DC (Ta = 25°C; VDD=CVDD =+3.0 ∼ +3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage Input Leakage Current (Note 15) Note 15. SMUTE pin DIF pin SMUTE pin (typ. 100kΩ) Symbol VIH VIL Iin MS1196-J-00 min 70%VDD - typ max Units V 30%VDD V ± 10 μA (typ. 100kΩ) DIF pin 2010/05 -6- [AK4430] (Ta = 25°C; VDD=CVDD = +3.0 ∼ +3.6V) Parameter Master Clock Frequency Duty Cycle LRCK Frequency Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle Audio Interface Timing BICK Period Normal Speed Mode Double Speed Mode Quad Speed Mode BICK Pulse Width Low Pulse Width High BICK “↑” to LRCK Edge (Note 16) LRCK Edge to BICK “↑” (Note 16) SDTI Hold Time SDTI Setup Time Note 16. LRCK BICK Symbol fCLK dCLK min 4.096 40 fsn fsd fsq Duty 8 32 120 45 tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fsn 1/64fsd 1/64fsq 30 30 20 20 20 20 typ - max 36.864 60 Units MHz % 48 96 192 55 kHz kHz kHz % ns ns ns ns ns ns ns ns ns “↑” MS1196-J-00 2010/05 -7- [AK4430] ■ 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Figure 1. Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDH tSDS VIH SDTI VIL Figure 2. Serial Interface Timing MS1196-J-00 2010/05 -8- [AK4430] ■ MCLK, LRCK, BICK (MCLK) (LRCK) ΔΣ (Table 1) MCLK MCLK MCLK,LRCK BICK (typ) MCLK, LRCK BICK MCLK, LRCK BICK LRCK fs 32.0kHz 44.1kHz 48.0kHz 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz AK4430 0V ON MCLK (MHz) 256fs 384fs 512fs 16.3840 22.5792 24.5760 8.192 12.288 11.2896 16.9344 12.288 18.432 22.5792 33.8688 24.5760 36.8640 22.5792 33.8688 24.5760 36.8640 Table 1. MCLK= 256fs/384fs 32kHz~96kHz DR, S/N MCLK= 512fs/768fs 128fs - 192fs - MCLK 256fs/384fs 512fs/768fs Table 2. MCLK 768fs 24.5760 33.8688 36.8640 1152fs 36.8640 - Sampling Speed Normal Double - - (Table 2) Quad 32kHz~48kHz DR,S/N 101dB 104dB DR, S/N (fs = 44.1kHz) ■ BICK pin Mode 0 LRCK MSB SDTI 2’s complement LSB 16/20 Mode 0 1 DIF pin L H SDTI Format 24bit 24bit I2S AK4430 2 (Table 3) DIF BICK “0” BICK ≥48fs ≥48fs Figure Figure 3 Figure 4 Table 3. MS1196-J-00 2010/05 -9- [AK4430] LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1 BICK (64fs) SDTI 23 22 1 0 Don’t care 23 22 0 1 Don’t care 23 22 0 1 23:MSB, 0:LSB Lch Data Rch Data Figure 3. Mode 0 Timing LRCK 0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 BICK (64fs) SDTI 23 22 1 0 Don’t care 23 22 1 0 Don’t care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 1 Timing ■ AK4430 (Figure 5) 2Vrms (Figure 6) Ca Cb ) CP (Figure 5) AK4430 VSS(0V,typ) 1.0μF ESR( VSS2 VSS(0V,typ) AK4430 CVDD Charge Pump CP Negative Power CN VSS2 (+) 1uF Ca VEE Cb 1uF (+) Figure 5. MS1196-J-00 2010/05 - 10 - [AK4430] AK4430 2 Vrms 0V AOUTR (AOUTL) Figure 6. Audio ■ SMUTE pin “H” Normal Speed Mode SMUTE pin “L” -∞ 1024LRCK -∞ (“0”) 0dB LRCK 0dB SMUTE pin 8 1024LRCK -∞ 1024LRCK “H” SMUTE pin 1024/fs 0dB 1024/fs (1) (3) Attenuation -∞ GD (2) GD AOUT : (1) Normal Speed Mode 1024LRCK Double Speed Mode 2048LRCK (4096/fs) -∞(“0”) (2) (3) 1024LRCK 0dB (1024/fs) -∞(“0”) (2048/fs) Quad Speed Mode 4096LRCK (GD) Normal Speed Mode Figure 7. MS1196-J-00 2010/05 - 11 - [AK4430] ■ ON AK4430 MCLK LRCK “↑” LRCK Power Supply (VDD, CVDD) (5) MCLK Low 20 us Analog Power down Circuit Digital Power down Circuit Charge Pump (1) (2) Power-up 2, 3 LRCK Power-up Power down Circuit Power-up (3) Charge Pump Time A Counter circuit D/A In (Digital) “0” data MUTE (D/A Out) D/A Out (Analog) (4) MCLK 2, 3 LRCK (1) (2) MCLK (3) 20us time A D/A Time A = 176/fs: Normal speed mode Time A = 352/fs: Double speed mode Time A = 704/fs: Quad speed mode (4) (5) MCLK pin “L” VDD 80% min.20us MCLK Figure 8. System Reset Diagram MS1196-J-00 2010/05 - 12 - [AK4430] ■ MCLK VSS(0V,typ) LRCK BICK MCLK LRCK BICK AK4430 Clock In (1) MCLK, BICK, LRCK MCLK or BIC K or LRCK Stop Internal State Normal Operation Reset D/A In (Digital) Normal Operation (2) (3) (4) D/A Out (Analog) : (1) (2) (MCLK,LRCK BICK ) VSS (4) (MCLK, BICK, LRCK) “0” MCLK LRCK BICK (3) 180/fs (Normal speed mode ) GD (4) Figure 9. MS1196-J-00 2010/05 - 13 - [AK4430] Figure 10 AK4430 1u (1) (AKD4430) + Master Clock ModeSetting Digital Ground 1 CN VEE 16 2 CP VSS2 15 3 SMUTE 4 MCLK 0.1u CVDD 14 VREFH 13 AK4430 VSS1 12 64fs 5 BICK 24bit Audio Data 6 SDTI fs 7 LRCK AOUTL 10 8 DIF AOUTR + 9 + 10u 2.2u (1) 0.1u VDD 11 Analog 3.3V 1u (1) + + 10u Lch Out Rch Out Analog Ground Figure 10. Typical Connection Diagram (1) ESR CP, VSS2, VREFH (2) VSS1, VSS2 (3) MS1196-J-00 2010/05 - 14 - [AK4430] 1. VDD CVDD VDD CVDD VDD VSS VDD CVDD CVDD VSS2 2. ΔΣ (CTF) VSS(0V,typ) ) ( 1 2’s complement (2 800000H(@24bit) DC ±5 V 2.0Vrms(typ, @VDD=3.3V) (SCF) LPF(Figure 11) ) 7FFFFFH(@24bit) 000000H(@24bit) VAOUT 0V(VSS) AK4430 470 Analog Out AOUT 2.0Vrms (typ) 2.2nF ( = 154kHz, gain = -0.28dB @ 40kHz, gain = -1.04dB @ 80kHz) Figure 11. External 1st order LPF Circuit Example1 MS1196-J-00 2010/05 - 15 - [AK4430] 16pin TSSOP (Unit: mm) 1.1 (max) *5.0±0.1 16 9 8 1 0.13 6.4±0.2 *4.4±0.1 A 0.65 0.22±0.1 M 0.17±0.05 Detail A 0.5±0.2 0.1±0.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° ■ : ( : : ( ) ) MS1196-J-00 2010/05 - 16 - [AK4430] AKM 4430ET XXYYY 1) 2) 3) 4) Date (YY/MM/DD) 10/05/31 Revision 00 Reason Pin #1 indication Date Code: XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code: 4430ET Asahi Kasei Logo Page MS1196-J-00 Contents 2010/05 - 17 - [AK4430] z z z z z z MS1196-J-00 2010/05 - 18 -