AK7722 English Datasheet

[AK7722]
AK7722
24bit 4ch ADC + 24bit 4ch DAC with Audio DSP
GENERAL DESCRIPTION
The AK7722 is a digital signal processor with an integrated 4ch 24bit DAC, a stereo ADC with input selector
and a 2ch input ADC. The integrated 4ch DAC, the 2ch ADC with input selector and the other 2ch ADC
feature high performance achieving 108dB, 96dB and 95dB, respectively. The integrated SRC has three
input selector enabling the DSP to operate in master mode with digital inputs. The audio DSP has
1536step/fs (at 48kHz sampling) parallel arithmetic operation performance and the 5k-word delay RAM
allows surround processing and time alignment adjusting. As the AK7722 is a RAM based DSP, it is
programmable for various user requirements. It is housed in an 80pin LQFP package.
FEATURES
[DSP Block]
- Word length: 24bit (Coefficient RAM & Data RAM: F24 floating point)
- Processing Speed: 13.6 ns (1536step/fs; fs = 48kHz)
- Multiplication: 20 x 24 → 44-bit Double precision arithmetic available
- Divider 20 / 20 → 20bit
- ALU: 48bit arithmetic operation (overflow margin 4bit) 20bit floating point arithmetic
and logic operation
- Program RAM: 3072 x 36bit
- Coefficient RAM: 2048 x 24bit (F24 floating point)
- Data RAM: 2048 x 24-bit (F24 floating point)
- Offset Register: 64 x 13bit
- Delay RAM1: 3072 x 24-bit
- Delay RAM2: 2048 x 24-bit
- Sampling rate: fs= 7.35k ~ 48kHz
- Master Clock: 1536fs
(generated from 32fs, 48fs, 64fs, 128fs, 256fs, 384fs by internal PLL)
- Master/Slave Operation
[ADC1 Block]
- Stereo with 6 Inputs Selector
- DR, S/N: 96dB (fs = 48kHz, when differential input)
- S/(N+D): 90dB (fs = 48kHz)
- Differential & Single-ended Inputs
- Digital HPF (fc=1Hz)
- 6 Analog Inputs Selector (2 differential, 4 single-ended)
- Digital Volume Control (24dB ~ -103dB, 0.5dB Step, Mute)
[ADC2 Block]
- DR, S/N: 95dB (fs = 48kHz)
- Single-ended Inputs
- Digital Volume Control (24dB ~ -103dB, 0.5dB Step, Mute)
[SRC Block]
- 3 Pair of Stereo → 1 Stereo Pair Selector
- 2ch x 1 system
- Supporting frequency: Fin = 7.35kHz ~ 96kHz → Fout = 7.35kHz ~ 48kHz
(FSO/FSI = 0.167~ 6.0)
MS1328-E-00
- 1 -
2011/09
[AK7722]
[Guidance SRC Block] (GSRC)
- 1 Channel (24bit) Up-converter for Voice Guidance
- Supporting frequency: Fin = 7.35kHz ~ 12kHz → Fout = 44.1kHz or 48kHz
[DAC Block]
- 4ch (2 Stereos)
- 24bit 128 x Over-sampling advanced multi-bit (fs=8kHz~48kHz)
- DR, S/N: 108dB (Differential Output)
- S/(N+D): 90dB
- Digital Volume Control (12dB ~ -115dB, 0.5dB Step, Mute)
[Digital Interface Input/Output]
- Digital Signal Input Port (4ch):
24bit MSB justified, 24/20/16bit LSB justified and I2S Format
- Digital Signal Output Port (6ch):
24bit MSB justified, 24/16bit LSB justified and I2S Format
[Micro Computer Interface]
- I2C or 4-wired Interface
[General]
- Integrated PLL
- Integrated Regulator 3.3V → 1.8V
- Power Supply: 3.3V ± 0.3V
- Operating Temperature Range: -40˚C ~ 85˚C
- 80pin LQFP
MS1328-E-00
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[AK7722]
■ Block Diagram
LFLT
2 DVDD
pull down
Hi-z
XTO
2
3 VSS2
Open Drain
3 AVDD
3 VSS3
XTI
REF
BICKI
LRCKI
VCOM
LDO
AVDRV
CLKGEN & CONT
TESTI1
TESTI2
DVOL
IRESETN
ADC2
2 A2INL,A2INR
SDOUTAD2
CLKOE
CLKO
ASEL[2:0]
DVOL
BICKOE
BICKO
LRCKOE
LRCKO
SDOUTAD1
SELDI5
1
0
SDIN5
2 AIN5L,AIN5R
2 AIN4L,AIN4R
2 AIN3L,AIN3R
2
DIN5
GSRC
0
MUX[2:0]
DVOL DAC2
SELDO5[1:0]
SELDI4
0
1
SRIN2
3
2
3
SDINDA2
2
MUX2[2:0]
SRCBICKI
DOUT4
0
DVOL DAC1
MUX2
SDINDA1
2
AOUT1LP
AOUT1LN
AOUT1RP
AOUT1RN
1
SRCI
3
SRCLFLT
UNLOCK
SRCO
SELDO4[1:0]
DOUT3
0
1
DIN3
IRPT
OUT3E
DOUT2
SDOUT3 / IRPT
2
3
DIN1
SDIN1
0
1
SELDI3
SRIN1
SELDO3[1:0]
0
OUT2E
SDOUT2
1
SDIN2 / JX1
2
DIN2
JX1E
JX0
3
SELDO2[1:0]
JX1
JX0
SRIN3
AOUT2LP
AOUT2LN
3
DSP
SRC
1
0
AIN1RP,AIN1RN
AOUT2RP
AOUT2RN
1
DIN4
SRCLRCKI
3
AIN2LP,AIN2LN
4 AIN2RP,AIN2RN
4 AIN1LP,AIN1LN
0
DOUT5
DSEL[1:0]
SRIN1,SRBICK1
SRLRCK1
SRCLFLT
UNLOCK
2 AIN6L,AIN6R
4
3
MUX1
GLRCKI
SRIN2,SRBICK2
SRLRCK2
5
1
GBICKI
SRIN3,SRBICK3
SRLRCK3
ADC1
DOUT1
0
OUT1E
1
JX2E
JX2
SDOUT1 / GP0
2
GP0
3
SELDO1[1:0]
WDTEN
WDT
CRC
STO
MICIF
CRCE
GP1
RDY
SO
RDY
SO
I2CSEL
RQN / CAD1
SI / CAD0
SCLK / SCL
SDA
GP1
Figure 1. Block Diagram
* Figure 1 shows a simplified diagram of the AK7722, which is not the perfect same as the actual circuit diagram.
MS1328-E-00
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[AK7722]
CP0, CP1
DLP0, DLP1
DP0, DP1
DLRAM1:3072W x 24-Bit
DRAM
2048w x 24-Bit
CRAM
2048W x 24-Bit
OFREG
64w x 13-Bit
DLRAM2:2048W x 24-Bit
CBUS(24-Bit)
DBUS(24-Bit)
MPX24
Micon I/F
MPX20
X
Control
DEC
Y
Serial I/F
PRAM
3072w x 36-Bit
Multiply
24 x 20 → 44-Bit
PC
Stack: 5level(max)
TMP 12 x 24-Bit
24-Bit
44-Bit
PTMP(LIFO) 6 x 24-Bit
MUL
DBUS
SHIFT
48-Bit
44-Bit
A
2 x 24(,16)-Bit
DIN5 (ADC2)
2 x 24(,16)-Bit
DIN4 (ADC1)
2 x 24, 20, 16-Bit DIN3 (SRC)
B
2 x 24, 20, 16-Bit DIN2
ALU
2 x 24, 20, 16-Bit DIN1
48-Bit
Overflow Margin: 4-Bit
48-Bit
DR0 ∼ 3
48-Bit
Over Flow Data
Generator
Division 20÷20→20
2 x 24, 20, 16-Bit
DOUT5(DAC2)
2 x 24, 20, 16-Bit
DOUT4(DAC1)
2 x 24, 20, 16-Bit
DOUT3
2 x 24, 20, 16-Bit
DOUT2
2 x 24, 20, 16-Bit
DOUT1
Peak Detector
Figure 2. Main DSP Block Diagram of the AK7722
MS1328-E-00
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2011/09
[AK7722]
■ Ordering Guide
-40 ∼ +85°C
80pin LQFP
Evaluation Board for AK7722
AK7722VQ
AKD7722
SDOUT1 / GP0
SDOUOT2
SDOUT3 / IRPT
STO
SRLRCK2
SRIN2
SRBICK2
SRLRCK3
SRBICK3
SRIN3
UNLOCK
I2CSEL
INITRSTN
TESTI2
AVDRV
VSS4
DVDD
SRCLFLT
VSS5
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AVDD
■ Pin Layout
BICKO
AOUTR2N
AOUTR2P
61
62
40
39
LRCKO
AOUTL2N
63
38
CLKO
AOUTL2P
64
37
VSS3
AOUTR1N
AOUTR1P
65
66
36
35
DVDD
AOUTL1N
67
34
SO
AOUTL1P
68
69
33
32
SI / CAD0
31
RQN / CAD1
AVDD
VCOM
80 pin LQFP
70
VSS6
71
A2INR
A2INL
72
73
AINR6
AINL6
SDA
SCLK / SCL
30
RDY
29
28
SRIN1
74
27
SRLRCK1
75
76
26
25
SDIN2 / JX1
AINR5
(TOP VIEW)
SRBICK1
SDIN1
AINL5
77
24
BICKI
AINR4
78
23
LRCKI
AINL4
79
80
22
21
JX0
GP1
XTO
XTI
VSS2
DVDD
SDIN5
GBICK
TESTI1
GLRCK
VSS1
LFLT
AVDD
AINL1P
AINR1P
AINL1N
AINR1N
AINL2P
AINR2P
AINL2N
AINL3
AINR2N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AINR3
pin
Input
Output
I/O
Power
MS1328-E-00
5
2011/09
[AK7722]
PIN FUNCTION
No.
1
2
3
4
5
6
7
8
9
10
11
Name
AINL3
AINR2N
AINR2P
AINL2N
AINL2P
AINR1N
AINR1P
AINL1N
AINL1P
AVDD
VSS1
I/O
I
I
I
I
I
I
I
I
I
O
12 LFLT
13 TESTI1
14
15
16
17
18
GLRCKI
GBICKI
SDIN5
DVDD
VSS2
I
I
I
I
-
19 XTI
I
20 XTO
O
21 GP1
O
22 JX0
I
23 LRCKI
24 BICKI
25 SDIN1
SDIN2
26
JX1
27 SRLRCK1
28 SRBICK1
MS1328-E-00
Function
Classification
ADC1 Lch Single-ended Input 3 Pin.
Analog Input
ADC1 Inverted Rch Differential Input 2 Pin
Analog Input
ADC1 Non-inverted Rch Differential Input 2 Pin
Analog Input
ADC1 Inverted Lch Differential Input 2 Pin
Analog Input
ADC1 Non-inverted Lch Differential Input 2 Pin
Analog Input
ADC1 Inverted Rch Differential Input 1 Pin
Analog Input
ADC1 Non-inverted Rch Differential Input 1 Pin
Analog Input
ADC1 Inverted Lch Differential Input 1 Pin
Analog Input
ADC1 Non-inverted Lch Differential Input 1 Pin
Analog Input
Analog Power Supply Pin 3.0 ~ 3.6V
Power Supply
Analog Ground Pin 0V
Power Supply
R and C Component Connect Pin for PLL
Refer to “7. LFLT Pin External Connection”. This pin outputs “L” during Analog Output
initial reset.
Test 1 Pin (Internal pull-down)
Test
This pin must be connected to VSS.
Frame Clock Input Pin for Voice Guidance
Digital Input
Bit Clock Input Pin for Voice Guidance
Digital Input
Serial Audio Input Pin for Voice Guidance
Digital Input
Digital Power Supply Pin 3.0~3.6V
Power Supply
Ground Pin 0V
Power Supply
Crystal oscillator input pin
Clock
Connect a crystal oscillator between this pin and the XTO pin, or input an
external clock to the XTI pin.
Crystal Oscillator Output Pin
When a crystal oscillator is used, connect it between XTI and XTO. When
Clock
an external clock is used, leave this pin open. During initial reset, the output
of this pin is not determinable.
Programmable Bit Output Pin
Digital Output
This pin outputs “L” during initial reset.
Conditional Jump Pin0
The conditional jump pin (JX0) is valid by setting control register (JX0E) to Conditional Input
“1”.
LR Channel Select Clock Pin 1
LR clock should be input to this pin in slave mode.
Serial Bit Clock Input Pin 1
I
BITCLOCK (48fs or 64fs) should be input to this pin in slave mode.
I
System Clock
Input
System Clock
Input
I Serial Data Input 1 Pin
Digital Input
I Serial Data Input 2 Pin
Digital Input
Conditional Jump Pin1
I
The conditional jump pin (JX1) is valid by setting control register (JX1E) to Conditional Input
“1”.
System Clock
I LR Channel Select Clock Pin 1 (for SRC)
Input
System Clock
I Serial Bit Clock Input Pin 1 (for SRC)
Input
6
2011/09
[AK7722]
No.
Name
29 SRIN1
SDIN3
30 RDY
31
RQN
CAD1
32
SCLK
SCL
33
SI
CAD0
34 SO
35 SDA
36 DVDD
37 VSS3
38 CLKO
39 LRCKO
40 BICKO
41
SDOUT1
GP0
42 SDOUT2
SDOUT3
43
IRPT
44 STO
Function
Classification
I/O
I Serial Data Input Pin 1 (for SRC)
Digital Input
I Serial Data Input Pin 3
Data Write Ready Output Pin for Microprocessor Interface
Microprocessor
O
This pin outputs RDY, and outputs “H” during initial reset.
Microprocessor Interface Write Request Pin (I2CSEL pin = “L”)
Interface
When initial reset state and Microcomputer interface are not in use, leave
I
RQN pin= “H”.
I I2C Bus Address Setting Pin 1 (I2CSEL pin = “H”)
I2C
Microprocessor
I Serial Data Clock Pin for Microprocessor Interface (I2CSEL pin = “L”)
When SCLK is not used, tie the SCLK pin = “H”.
Interface
2
I I C Bus Data Clock Pin (I2CSEL pin = “H”)
I2C
Microprocessor
I Serial Data Input Pin for Microprocessor Interface (I2CSEL pin = “L”)
When SI is not used, tie the SI pin = “L”.
Interface
I I2C Bus Address Setting Pin 0 (I2CSEL pin = “H”)
I2C
Serial Data Output Pin for Microprocessor Interface
Microprocessor
O
Outputs “L” during initial reset.
Interface
O I2CSEL pin = “L”
Open
Leave this pin Open. SDA outputs “L”.
2
I/O I C Bus Data Clock Pin (I2CSEL pin = “H”)
I2C
Outputs “Hi-z” during initial reset.
- Digital Power Supply Pin 3.0~3.6V
Power Supply
- Ground Pin 0V
Power Supply
Clock Output Pin
O
Clock Output
This pin outputs “L” during initial reset.
LR Channel Select Output Pin
System Clock
O
This pin outputs “L” during initial reset in master mode.
Output
Serial Bit Clock Output Pin
System Clock
O
This pin outputs “L” during initial reset in master mode.
Output
Serial Data Output1 Pin
Digital Output
O
This pin outputs “L” during initial reset.
O Programmable Bit Output Pin
Serial Data Output2 Pin
O
This pin outputs “L” during initial reset.
Serial Data Output3 Pin
O
This pin outputs “L” during initial reset.
O Interrupt Status Output Pin
Status Output Pin
O
This pin outputs “H” during initial reset.
45 SRLRCK2
I LR Channel Select Clock Pin 2 (for SRC)
46 SRBICK2
I Serial Bit Clock Input Pin 2 (for SRC)
47
SRIN2
SDIN4
48 SRLRCK3
MS1328-E-00
Digital Output
Digital Output
Digital Output
Digital Output
Status
System Clock
Input
System Clock
Input
I Serial Data Input Pin 2 (for SRC)
I Serial Data Input Pin 4
Digital Input
I LR Channel Select Clock Pin 3 (for SRC)
System Clock
Input
7
2011/09
[AK7722]
No.
Name
49 SRBICK3
SRIN3
50
JX2
51 UNLOCK
52 INITRSTN
53 I2CSEL
54 TESTI2
55 AVDRV
56 VSS4
57 DVDD
58 SRCLFLT
59 VSS5
60 AVDD
61 AOUTR2N
62 AOUTR2P
63 AOUTL2N
64 AOUTL2P
65 AOUTR1N
66 AOUTR1P
67 AOUTL1N
68 AOUTL1P
69 AVDD
70 VCOM
MS1328-E-00
Function
I/O
I Serial Bit Clock Input Pin 3 (for SRC)
Classification
System Clock
Input
Digital Input
I Serial Data Input Pin 3 (for SRC)
I Conditional Jump Pin2
The conditional jump pin (JX2) is valid by setting control register (JX2E) to Conditional Input
“1”.
SRC UNLOCK State Output Pin
O
SRC Status
This pin outputs “H” during initial reset.
Reset Pin (for Initialization)
I
Use to initialize the AK7722. Set this pin to “L” when power-up the
System
AK7722.
I2C BUS Select Pin (Internal pull-down)
I2CSEL pin = “L”: 4-wired Interface
I
I2C Select
I2CSEL pin = “H”: I2CBus selected mode. SCL and SDA are active.
I2CSEL should be connected to “L” (VSS) or “H” (DVDD).
Test Input 2 Pin (Internal pull-down)
I
Test
This pin must be connected to VSS4.
O AVDRV Pin
Connect a 1μF capacitor between this pin and VSS4 pin. No external
Analog Output
circuits should be connected to this pin. This pin outputs “L” during initial
reset.
- Ground Pin 0V
Power Supply
- Digital Power Supply Pin 3.0~3.6V
Power Supply
Capacitor Connect Pin for SRCPLL
Connect a 1μF capacitor between this pin and VSS4 pin. This pin outputs Analog Output
O
“L” during initial reset.
- Ground Pin 0V
Power Supply
- Analog Power Supply Pin 3.0~3.6V
Power Supply
DAC2 Inverted Rch Differential Analog Output Pin
Analog Output
O
“Hi-Z” output during initial reset
DAC2 Non-inverted Rch Differential Analog Output Pin
Analog Output
O
“Hi-Z” output during initial reset
DAC2 Inverted Lch Differential Analog Output Pin
Analog Output
O
“Hi-Z” output during initial reset
DAC2 Non-inverted Lch Differential Analog Output Pin
Analog Output
O
“Hi-Z” output during initial reset
DAC1 Inverted Rch Differential Analog Output Pin
Analog Output
O
“Hi-Z” output during initial reset
DAC1 Non-inverted Rch Differential Analog Output Pin
Analog Output
O
“Hi-Z” output during initial reset
DAC1 Inverted Lch Differential Analog Output Pin
Analog Output
O
“Hi-Z” output during initial reset
DAC1 Non-inverted Lch Differential Analog Output Pin
Analog Output
O
“Hi-Z” output during initial reset
- Analog Power Supply Pin 3.0~3.6V
Power Supply
Analog
Common
Voltage
Output
pin
O
Connect 0.1μF and 2.2μF capacitors between this pin and the VSS6 pin. No
Analog Output
external circuits should be connected to this pin. This pin outputs “L”
during initial reset.
8
2011/09
[AK7722]
No.
71
72
73
74
75
76
77
78
79
80
Name
VSS6
A2INR
A2INL
AINR6
AINL6
AINR5
AINL5
AINR4
AINL4
AINR3
I/O
I
I
I
I
I
I
I
I
I
Function
Classification
Power Supply
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Ground Pin 0V
ADC2 Rch Single-ended Input Pin
ADC2 Lch Single-ended Input Pin
ADC1 Rch Single-ended Input Pin 6
ADC1 Lch Single-ended Input Pin 6
ADC1 Rch Single-ended Input Pin 5
ADC1 Lch Single-ended Input Pin 5
ADC1 Rch Single-ended Input Pin 4
ADC1 Lch Single-ended Input Pin 4
ADC1 Rch Single-ended Input Pin 3
■ Handling of Unused Pin
The following table illustrates recommended states for open pins:
Classification
Analog
Digital
Pin Name
ANL1P, AINL1N, AINR1P, AINR1N, AINL2P, AINL2N, AINR2P
AINR2N, AINL3, AINR3, AINL4, AINR4, AINL5, AINR5, AINL6, AINR6
AOUTL1P, AOUTL1N, AOUTR1P, AOUTR1N
AOUTL2P, AOUTL2N, AOUTR2P, AOUTR2N
XTO, GP1, RDY, SO, SDA(I2CSEL= “L”), CLKO, LRCKO, BICKO, SDOUT1
SDOUT2, SDOUT3, STO, UNLOCK
TESTI1, GLRCK, GBICK, SDIN5, XTI, JX0, LRCKI, BICKI, SDIN1, SDIN2
SRLRCK1, SRBICK1, SRIN1, RQN, SI, SRLRCK2, SRBICK2, SRIN2,
SRLRCK3
SRBICK3, SRIN3, TESTI2
The relationship between the I2CSEL pin and SDA pin
I2CSEL
Micro controller
L
Interface
L
I2C-bus support
H
H
MS1328-E-00
9
INITRSTN
L
H
L
H
Setting
Leave Open
Leave Open
Connect to VSS
SDA
L
L
“Hi-Z”
function
2011/09
[AK7722]
ABSOLUTE MAXIMUM RATINGS
(VSS1~VSS6=0V: Note 1)
Parameter
Symbol
Power Supply Voltage
Analog
AVDD
Digital
DVDD
Input Current (except for power supply pin )
IIN
Analog Input Voltage
VINA
Digital Input Voltage
VIND
Operating Ambient Temperature
Ta
Storage Temperature
Tstg
Note 1. All indicated voltages are with respect to ground.
Note 2. VSS1-6 must be connected to the same ground plane.
min
max
Unit
-0.3
-0.3
–
-0.3
-0.3
-40
-65
4.3
4.3
±10
AVDD+0.3
DVDD+0.3
85
150
V
V
mA
V
V
ºC
ºC
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1~VSS6=0V: Note 1)
Parameter
Symbol
min
typ
max
Unit
Power Supply Voltage
Analog
AVDD
3.0
3.3
3.6
V
Digital
DVDD
3.0
3.3
3.6
V
Note 3. The power supply sequence for AVDD and DVDD is not critical but all power supplies must be On before start
operating the AK7722.
Note 4. Do not turn off the power supply of the AK7722 with the power supply of the surrounding device turned on.
DVDD must not exceed the pull-up of SDA and SCL of I2C BUS. (The diode exists for DVDD in the SDA and
SCL pins.)
WARNING: AKM assumes no responsibility for the usage beyond the conditions in the datasheet.
MS1328-E-00
10
2011/09
[AK7722]
ANALOG CHARACTERISTICS (CODEC)
■ ADC Characteristics
1. ADC1
(Ta=25ºC; AVDD=DVDD=3.3V, BITCLK=64fs; Signal frequency 1kHz; Measurement frequency = 20Hz~20kHz
@fs=48kHz; CKM mode0 (CKM[2:0]=000); BITFS[1:0]=00(64fs); with Differential Input; in SRC reset, Unless
otherwise specified.)
Parameter
min
typ
max
Unit
Resolution
24
Bits
ADC
Section
Dynamic Characteristics
S/(N+D) (-1dBFS)
82
90
dB
Dynamic Range (A-weighted)
(Note 5)
96
dB
88
S/N (A-weighted)
96
dB
88
Inter-Channel Isolation (fin=1kHz) (Note 6)
90
110
dB
DC accuracy
Channel Gain Mismatch
0.0
0.3
dB
Analog Input
Input Voltage (Differential)
(Note 7)
Vp-p
±2.00
±2.20
±2.40
Input Voltage (Single-ended)
(Note 8)
2.00
2.20
2.40
Vp-p
Input Impedance
41
62
kΩ
Note 5. S/(N+D) when -60dB FS signal is applied.
Note 6. Inter-channel isolation between AINR and AINL with –1dB FS signal input.
Note 7. AINL1P, AINL1N, AINR1P, AINR1N, AINL2P, AINL2N, AINR2P and AINR2N pins
Note 8. AINL3, AINR3, AINL4, AINR4, AINL5, AINR5, AINL6 and AINR6 pins.
Full scale output voltage is FS=AVDD×2.2/3.3.
2. ADC2
(Ta=25ºC; AVDD=DVDD=3.3V, BITCLK=64fs; Signal frequency 1kHz; Measurement frequency =20Hz~20kHz
@fs=48kHz; CKM mode0 (CKM[2:0]=000); BITFS[1:0]=00(64fs); in SRC reset, Unless otherwise specified.)
Parameter
min
typ
max
Unit
Resolution
24
Bits
ADC
Section
Dynamic Characteristics
S/(N+D) (-1dBFS)
88
dB
80
Dynamic Range (A-weighted)
(Note 9)
95
dB
87
S/N (A-weighted)
95
dB
87
Inter-Channel Isolation (fin=1kHz) (Note 10)
90
110
dB
DC accuracy
Channel Gain Mismatch
0.1
0.3
dB
Analog Input
Input Voltage
(Note 11)
2.00
2.20
2.40
Vp-p
Input Impedance
41
62
kΩ
Note 9. S/(N+D) when -60dB FS signal is applied.
Note 10. Inter-channel isolation between AINR and AINL with –1dB FS signal input.
Note 11. Full scale output voltage is FS=AVDD×2.2/3.3.
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[AK7722]
■ DAC1/2 Characteristics
(Ta=25ºC; AVDD=DVDD=3.3V; VSS1~VSS6=0V; Signal frequency 1kHz; Measurement frequency =20Hz~20kHz
@fs=48kHz; CKM[2:0]=000, BITFS[1:0]=00, in SRC Reset) Unless otherwise specified.)
Parameter
min
typ
max
Unit
Resolution
24
Bits
DAC1
DAC2
Dynamic Characteristics
S/(N+D)
(0 dBFS)
82
90
dB
Dynamic Range (A-weighted) (Note 12)
98
108
dB
S/N (A-weighted)
98
108
dB
Inter-channel Isolation (f=1kHz) (Note 13)
90
110
dB
DC accuracy
Channel Gain Mismatch
0.0
0.5
dB
Analog output
Output Voltage
(Note 14)
3.78
4.16
4.53
Vp-p
Load Resistance
5
kΩ
Load Capacitance
30
pF
Note 12. S/(N+D) when -60dBFS signal is applied.
Note 13. Indicates isolation between each DAC’s of Lch and Rch when -1dBFS signal is applied.
Note 14. Full scale differential output voltage.
SRC CHARACTERISTICS
(Ta=25ºC; AVDD = DVDD=3.3V; VSS1~VSS6=0V, data = 24bit; measurement bandwidth = 20Hz~ FSO/2; unless
otherwise specified.)
Parameter
Symbol
min
typ
max
Unit
Resolution
24
Bits
Input Sample Rate
FSI
7.35
96
kHz
Output Sample Rate
FSO
7.35
48
kHz
THD+N
(Input= 1kHz, 0dBFS)
FSO/FSI=44.1kHz/48kHz
-112
dB
FSO/FSI=44.1kHz/96kHz
-104
dB
FSO/FSI=48kHz/44.1kHz
-112
dB
FSO/FSI=48kHz/96kHz
-112
dB
FSO/FSI=48kHz/8kHz
-111
-103
dB
FSO/FSI=8kHz/48kHz
-113
dB
FSO/FSI=8kHz/44.1kHz
-100
dB
Dynamic Range (Input= 1kHz, -60dBFS)
FSO/FSI=44.1kHz/48kHz
113
dB
FSO/FSI=44.1kHz/96kHz
113
dB
FSO/FSI=48kHz/44.1kHz
113
dB
FSO/FSI=48kHz/96kHz
113
dB
FSO/FSI=48kHz/8kHz
109
112
dB
FSO/FSI=8kHz/48kHz
113
dB
FSO/FSI=8kHz/44.1kHz
113
dB
Dynamic Range (Input= 1kHz, -60dBFS, A-weighted
FSO/FSI=44.1kHz/48kHz
115
dB
Ratio between Input and Output Sample Rate
FSO/FSI
0.167
6
-
MS1328-E-00
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2011/09
[AK7722]
DC CHARACTERISTICS
(Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V)
Parameter
Symbol
min
High Level Input Voltage
(Note 15)
VIH
80%DVDD
Low Level Input Voltage
(Note 15)
VIL
SCL,SDA High Level Input Voltage
VIH
70%DVDD
SCL,SDA Low Level Input Voltage
VIL
VOH
DVDD-0.5
High Level Output Voltage Iout=-100μA
VOL
Low Level Output Voltage Iout=100μA (Note 16)
SDA Low Level Output Voltage Iout=3mA
VOL
Input Leak Current
(Note 17)
Iin
Input Leak Current (pull-down pin)
(Note 18)
Iid
Input Leak Current (XTI pin)
Iix
typ
max
20%DVDD
30%DVDD
0.5
0.4
±10
22
26
Unit
V
V
V
V
V
V
V
μA
μA
μA
Note 15. SCL and SDA pins are not included. (SCLK pins are included)
Note 16. The SDA pin is not included.
Note 17. Pull-down pins, and the XTI pin is not included.
Note 18. TESTI1 and TESTI2 pins are internal pulled-down pin. (Typ150kΩ)
POWER CONSUMPTION
(Ta=25ºC; AVDD=DVDD=3.0~3.6V (when typ=3.3V, max=3.6V))
Parameter
min
typ
max
Unit
Power Supply Current
(Note 19)
55
AVDD
mA
65
DVDD
mA
120
AVDD+DVDD
180
mA
2
INITRSTN pin= “L” (reference) (Note 20)
mA
Note 19. The current of DVDD changes depending on the system frequency and contents of the DSP program.
Note 20. This is a reference value when using a crystal oscillator. Since most of the current are applied to the oscillator
section in the initial reset state, the value may vary according to the crystal type and the external circuit. This is
a “reference data” only.
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[AK7722]
DIGITAL FILTER CHARACTERISTICS
■ ADC Block (ADC1/2)
1. fs=48kHz
(Ta=-40ºC ~85ºC, AVDD=DVDD=3.0~3.6V, fs=48kHz, Note 21)
Parameter
Symbol
min
typ
max
Unit
Passband (±0.1dB) (Note 22)
0
18.9
PB
kHz
(-1.0dB)
kHz
20.0
(-3.0dB)
kHz
23.0
Stopband
SB
kHz
28
Passband Ripple
(Note 22)
PR
dB
±0.04
Stopband Attenuation (Note 23, Note 24)
SA
dB
68
Group Delay Distortion
ΔGD
0
μs
Group Delay
(Ts=1/fs)
GD
16
Ts
Note 21. The passband and stopband frequencies are proportional to fs (system sampling rate). High-pass filter
characteristics are not included.
Note 22. The passband is from DC to 18.9kHz when fs=48kHz.
Note 23. The stopband is 28kHz to 3.044MHz when fs=48kHz.
Note 24. When fs = 48kHz, the analog modulator samples the input signal at 512kHz. There is no attenuation of an
input signal in band (n x 3.072MHz ±28kHz; n=0, 1, 2, 3…) of integer times of the sampling frequency by the
digital filter.
■ DAC1-2
(Ta=-40 ºC ~85 ºC; AVDD=DVDD=3.0~3.6V; fs=48kHz)
Parameter
Symbol
min
typ
max
Unit
Passband (±0.05dB) (Note 25)
PB
0
21.7
kHz
(-6.0dB)
24
kHz
Stopband
(Note 25)
SB
26.2
kHz
Passband Ripple
PR
±0.01
dB
Stopband Attenuation
SA
64
dB
Group Delay (Ts=1/fs) (Note 26)
GD
24
Ts
Digital Filter + Analog Filter
Amplitude Characteristics 20Hz~20.0kHz
±0.5
dB
Note 25. The pass band and stop band frequencies are proportional to “fs” (system sampling rate), and represents
PB=0.4535fs (@±0.05dB) and SB=0.5465fs, respectively.
Note 26. The digital filter delay is calculated as the time from setting data into the input register until an analog signal is
output.
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2011/09
[AK7722]
■ SRC
(Ta=-40ºC ~85ºC; AVDD=DVDD=3.0~3.6V)
Parameter
Symbol
min
typ
max
Unit
Passband
0.980≤FSO/FSI≤6.000
PB
0
0.4583FSI
kHz
0.900≤FSO/FSI<0.990
PB
0
0.4167FSI
0.450≤FSO/FSI<0.910
PB
0
0.2177FSI
0.225≤FSO/FSI<0.455
PB
0
0.0917FSI
0.167≤FSO/FSI<0.227
PB
0
0.0917FSI
Stopband
0.980≤FSO/FSI≤6.000
SB
0.5417FSI
kHz
0.900≤FSO/FSI<0.990
SB
0.5021FSI
0.450≤FSO/FSI<0.910
SB
0.2813FSI
0.225≤FSO/FSI<0.455
SB
0.1573FSI
0.167≤FSO/FSI<0.227
SB
0.1354FSI
Passband Ripple
0.225≤FSO/FSI<0.455
PR
±0.0100
dB
0.167≤FSO/FSI<0.227
PR
±0.0612
Stopband Attenuation
SA
92.3
dB
Group Delay (Ts=1/fs) (Note 27)
GD
56
Ts
Note 27. This delay is the a period from the rising edge of SRLRCKn, just after the data is input, to the rising edge of
LRCLKO, just after the data is output, when there is no phase difference between SRLRCKn and LRCLKO.
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[AK7722]
SWITCHING CHARACTERISTICS
■ System Clock
(Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V, VSS1~VSS6=0V)
Parameter
Symbol
min
XTI CKM[2:0]=000, 001, 010
a) with a Crystal Oscillator:
fXTI
CKM[2:0]=000 fs=44.1kHz
fs=48kHz
fXTI
CKM[2:0]=001 fs=44.1kHz
fs=48kHz
b) with an External Clock
Duty Cycle
40
fXTI
CKM[2:0]=000, 010 fs=44.1kHz
11.0
fs=48kHz
fXTI
CKM[2:0]=001 fs=44.1kHz
16.5
fs-48kHz
LRCKI Frequency
(Note 28)
fs
7.35
typ
max
Unit
11.2896
12.288
16.9344
18.432
-
MHz
-
MHz
50
11.2896
12.288
16.9344
18.432
60
%
MHz
12.4
18.6
48
MHz
kHz
BICKI Frequency
High Level Width
tBCLKH
64
ns
Low Level Width
tBCLKL
64
ns
Frequency
0.23
3.072
3.1
MHz
fBCLK
Note 28. LRCKI frequency and sampling rate (fs) should be the same.
Note 29. When BICKI is the source of master clock, it should be synchronized to LRCKI and the frequency is stable.
MS1328-E-00
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2011/09
[AK7722]
■ SRC Input Clock
(Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V; VSS1~VSS6=0V)
Parameter
Symbol
min
fs
7.35
SRLRCKn Frequency
typ
max
96
Unit
kHz
3.072
6.144
MHz
ns
ns
(Ta=-40 ºC ~85 ºC; AVDD=DVDD=3.0~3.6V; VSS1~VSS6=0V)
Parameter
Symbol
min
fs
7.35
GLRCK Frequency
typ
max
12
Unit
kHz
GBICK Frequency
Frequency
High Level Width
Low Level Width
SRBICKn Frequency
Frequency
High Level Width
Low Level Width
fBCLK
tBCLKH
tBCLKL
0.23
32
32
■ GSRC Input Clock
fBCLK
tBCLKH
tBCLKL
230
100
100
512
780
kHz
ns
ns
(Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V)
Parameter
Symbol
INITRSTN
(Note 30)
tRST
Note 30. It must be “L” when power-up the AK7722.
min
600
typ
max
Unit
ns
■ Reset
MS1328-E-00
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2011/09
[AK7722]
■ Audio Interface (SDIN1-2, SRIN1-3, SDOUT1-3)
(Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V, CL=20pF)
Parameter
DSP Section Input SDIN1-2, SRIN1-3
(Note 31)
Delay Time from BICKI “↑” to LRCKI
(Note 32)
Symbol
tBLRD
min
typ
max
Unit
20
ns
Delay Time from LRCKI to BICKI “↑”
(Note 32)
tLRBD
20
Serial Data Input Latch Setup Time
tBSIDS
80
Serial Data Input Latch Hold Time
tBSIDH
80
SRC Section Input SRIN1-3
(Note 33)
Delay Time from SRBICK1-3 “↑” to SRLRCK1-3
(Note 34)
tBLRD
20
Delay Time from SRLRCK1-3 to SRBICK1-3 “↑”
(Note 34)
tLRBD
20
Serial Data Input Latch Setup Time
tBSIDS
40
Serial Data Input Latch Hold Time
tBSIDH
40
Output SDOUT1-3
(Note 31)
BICKO Frequency
fBCLK
64
BICKO Duty Factor
50
Delay Time from BICKO “↓” to LRCKO
(Note 35)
tBLRD
-20
40
Delay Time from LRCKI to Serial Data Output
(Note 36)
tLRD
80
Delay Time from BICKI to Serial Data Output
(Note 33)
tBSOD
80
Delay Time from LRCKO to Serial Data Output
(Note 36)
tLRD
80
Delay Time from BICKO to Serial Data Output
(Note 33)
tBSOD
80
SDINn → SDOUTn (n=1-2)
(Note 37)
Delay Time from SDINn to SDOUTn Data Output
tIOD
60
Note 31. BICKI=SRBICKn (n=1, 2, 3) in CKM mode 4.
Note 32. BICKI edge must not occur at the same time as LRCKI edge. The BICKI polarity is inverted in PCM mode
0/2.
Note 33. Except CKM mode 4
Note 34. SRBICK1-3 edge must not occur at the same time as SRLRCK1-3 edge. When BIEDGE bit= “1”, this value is
for SRBICK1-3 “↓” since SRBICK1-3 are polarity reversal.
Note 35. When SELBCK bit= “1”, this value is for BICKO “↑” since BICKO is polarity reversal.
Note 36. Except I2S.
Note 37. SDIN1 → SDOUT1: Control Register Setting, SELDO1[1:0]=1h, OUT1E bit= “1”
SDIN2/JX1 → SDOUT2: Control Register Setting, SELDO2[1:0]=1h, OUT2E bit= “1”
SRIN1/SDIN3 → SDOUT3: Control Register Setting, SELDI3 bit = “1”, SELDO3[1:0]=1h, OUT3E bit= “1”
MS1328-E-00
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2011/09
ns
ns
ns
ns
ns
ns
ns
fs
%
ns
ns
ns
ns
ns
ns
[AK7722]
■ Microprocessor Interface
(Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V; CL=20pF)
Parameter
Symbol
Microprocessor Interface Signal
RQN Fall Time
tWRF
RQN Rise Time
tWRR
SCLK Fall Time
tSF
SCLK Rise Time
tSR
SCLK Frequency
fSCLK
SCLK Low Level Width
tSCLKL
SCLK High Level Width
tSCLKH
Microprocessor → AK7722
RQN High Level Width
tWRQH
From RQN “↓” to SCLK “↓”
tWSC
From SCLK “↑” to RQN “↑”
tSCW
SI Latch Setup Time
tSIS
SI Latch Hold Time
tSIH
AK7722 → Microprocessor
Delay Time from SCLK “↓”to SO Output
tSOS
Hold Time from SCLK “↑” to SO Output (Note 38)
tSOH
Note 38. Except for, when writing to 8th bit of command code.
min
typ
max
Unit
30
30
30
30
2.1
200
200
ns
ns
ns
ns
MHz
ns
ns
500
500
800
200
200
ns
ns
ns
ns
ns
200
ns
ns
200
■ I2C BUS Interface
(Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V)
Parameter
I2C Timing
SCL clock frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first Clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed
by Input Filter
Capacitive load on bus
Note 39. I2C-bus is a trademark of NXP B.V.
MS1328-E-00
Symbol
min
typ
max
Unit
400
fSCL
tBUF
1.3
kHz
μs
tHD:STA
0.6
μs
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
1.3
0.6
0.6
0
0.1
μs
μs
μs
μs
μs
μs
μs
μs
tSP
0.3
0.3
0.6
0
Cb
19
0.9
50
ns
400
pF
2011/09
[AK7722]
■ Timing Diagram
1/fXTI
1/fXTI
tXTI=1/fXTI
XTI
VIH
VIL
1/fs
ts=1/fs
1/fs
LRCKI
VIH
VIL
1/fBCLK
1/fBCLK
tBCLK=1/fBCLK
VIH
BICKI
VIL
tBCLKH
tBCLKL
Figure 3. System Clock
INITRSTN
tRST
VIL
Figure 4. Reset
Note 40. The INITRSTN pin must be “L” when power-up/power-down the AK7722.
MS1328-E-00
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[AK7722]
1) Audio Interface
VIH
VIL
LRCKI
tBLRD
tLRBD
VIH
VIL
BICKI
tBSIDS
tBSIDH
VIH
VIL
SDINn
n=1, 2
Figure 5. DSP Block Input Interface in Slave Mode
50%DVDD
LRCKO
tMBL
tMBL
BICKO
50%DVDD
tBSIDS
tBSIDH
VIH
VIL
SDINn
n=1, 2
Figure 6. DSP Block Input Interface in Master Mode
VIH
VIL
SRLRCKn
tBLRD
tLRBD
VIH
VIL
SRBICKn
tBSIDS
tBSIDH
VIH
VIL
SRINn
Figure 7. SRC Block Input Interface
MS1328-E-00
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[AK7722]
VIH
VIL
GLRCK
tBLRD
tLRBD
VIH
VIL
GBICK
tBSIDS
tBSIDH
VIH
VIL
SDIN5
Figure 8. GSRC Block Input Interface
VIH
VIL
LRCKI
tLRD
VIH
VIL
BICKI
tLRD
tBSOD
SDOUTn
n=1, 2, 3
tBSOD
50%DVDD
Figure 9. Output Interface in Slave Mode
MS1328-E-00
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[AK7722]
2) Micro-controller Interface
VIH
VIL
RQN
tWRF
tWRR
tSF
tSR
VIH
VIL
SCLK
tSCLKL
tSCLKH
1/fSCLK
1/fSCLK
INITRSTN
VIH
VIL
RQN
VIH
VIL
tRST
tIRRQ
Figure 10. Micro-controller Interface Signal
VIH
tWRQH
RQN
VIL
VIH
SI
VIL
tSIS
tSIH
VIH
SCLK
VIL
tWSC
tSCW
tWSC
tSCW
Figure 11. Micro-controller → AK7722
MS1328-E-00
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2011/09
[AK7722]
VIH
SCLK
VIL
VIH
SO
VIL
tSOH
tSOS
Figure 12. AK7722 → Micro-controller
3) I2C-Bus Interface
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
2
Figure 13. I C-bus Interface
MS1328-E-00
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2011/09
[AK7722]
OPERATION OVERVIEW
■ System Clock
CKM[2:0] Clock Mode Select Pin
Master/Slave mode switching, MCLK/ICLK (internal master clock/generated clock) clock source pin select, and ICLK
frequency change are controlled by CKM [2:0] clock mode select pins. CKM[2:0] pins can only be set during initial
reset or clock reset.
CKM
Mode
0
1
2
3
4
CKM
[2:0]
000
001
010
011
100
Master
Slave
Master
Master
Slave
Slave
Slave
MCLK source
XTI
XTI
XTI
BICKI
SRBICKn
Sampling Frequency
fs (Note 41, Note 42)
DFS[1:0] bits
DFS[1:0] bits
DFS[1:0] bits
DFS[1:0] bits
DFS[1:0] bits
Input pin(s) required for Use of crystal
system clock
oscillator
XTI 256fs
Available
XTI 384fs
Available
XTI, BICKI, LRCKI
Not Available
BICKI, LRCKI
Not Available
SRBICKn, SRLRCKn
Not Available
(N/A: Not available)
Note 41. The sampling frequency is set by DFS[1:0] bits.
Note 42. In CKM mode2 and 3, BITFS[1:0] bits control the sampling frequency of BICKI.
Note 43. In CKM mode4, BITFS[1:0] bits control the sampling frequency of SRBICKn.
Note 44. In CKM mode 0 and 1, the sampling frequency of BICKO is fixed to 64fs regardless of the BITFS[1:0] bits
setting.
Note 45. DSEL[1:0] bits selects SRBICKn and SRLRCKn.
Note 46. In CKM mode 2, XTI, BICKI and LRCKI must be synchronized but the phase is not critical.
Note 47. CKM mode 7 is for testing purpose only. It cannot be used.
[Description rule]
Regarding the input / output levels in this Datasheet, the low level is represented as “L” and the high level is
represented as “H”. The registers or bus pins (such as CKM[2:0] is represented “0” and “1”.
##h means hexadecimal code. (# = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F)
MS1328-E-00
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2011/09
[AK7722]
■ Relationship between MCLK Generating Clock (ICLK) and MCLK
ICLK
XTI Pin
CKM mode 0/1/2
REFCLK
Divider
MCLK
PLL
(MCLK source)
ICLK
BICKI Pin
CKM mode 3
REFCLK
Divider
MCLK
PLL
(MCLK source)
ICLK
SRBICKn Pin
CKM mode 4
REFCLK
Divider
MCLK
PLL
(MCLK source)
MCLK 73.728MHz(@fs=48kHz)
Figure 14. Relationship between MCLK generating clock (ICLK) and MCLK
1. Master Mode (Using XTI Input Clock, CKM Mode 0/ 1)
CKM
Mode
0
1
CKM
[2:0]
000
001
XTI
fs=48kHz
12.288MHz
18.432MHz
fs=44.1kHz
11.2896MHz
16.9344MHz
fs: sampling frequency
Input frequency range
Use of crystal
(MHz)
oscillator
11.0~12.4
16.5~18.6
Available
Available
Input system clock to the XTI pin. The internal counter which is synchronized to XTI generates LRCKO(1fs) and
BICKO(64fs). BITFS[1:0] bits setting is ignored. LRCKO and BICKO are not output during system reset state. The
sampling frequency is determined by control register CONT0 DFS[1:0] (D3 and D2) bits.
The system clock for the AK7722 can be supplied to the XTI pin by following ways.
1) By connecting a proper crystal oscillator between XTI and XTO pins,
2) By supplying appropriate system clock to the XTI pin.
XTI
XTI
External Clock
XTO
XTO
AK7722
AK7722
Figure 15. Using Crystal Oscillator (CKM Mode 0/1)
Figure 16. Using External System Clock (CKM Mode 0/1)
MS1328-E-00
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2011/09
[AK7722]
2. Slave Mode (XTI Input Clock, CKM Mode 2)
CKM
Mode
CKM
[2:0]
2
010
XTI
fs=48kHz
12.288MHz
fs=44.1kHz
11.2896MHz
fs: sampling frequency
Input Frequency Range
Use of Crystal
(MHz)
Unit
11.0~12.4
-
Required System Clocks are XTI, LRCKI and BICKI. XTI and LRCKI must be synchronized, but the phase between
these clocks is not important.
XTI
External Clock
XTO
Figure 17. Using External System Clock (CKM Mode 2)
3. Slave Mode (BICKI Input, CKM Mode 3)
In CKM mode 3, required system clocks are BICKI and LRCKI. In this mode, BICKI is used for clock source instead of
XTI. This clock is multiplied directly by a PLL, therefore burst clock or the clock with two different frequencies can not
be used. BICKI and LRCKI must be synchronized.
DFS
[1:0]
0
0
0
1
1
1
2
2
2
3
3
3
MS1328-E-00
BITFS
Fs
48kHz
48kHz
48kHz
32kHz
32kHz
32kHz
16kHz
16kHz
16kHz
8kHz
8kHz
8kHz
[1:0]
2
1
0
2
1
0
2
1
0
2
1
0
BICKI
32fs
48fs
64fs
32fs
48fs
64fs
32fs
48fs
64fs
32fs
48fs
64fs
BICKI
Frequency
fs=44.1kHz
1.4112MHz
2.1168MHz
2.8224MHz
0.9408MHz
1.4112MHz
1.8816MHz
470.4kHz
705.6kHz
940.8kHz
Not Available
Not Available
Not Available
27
fs: sampling frequency
Input Frequency
fs=48kHz
1.536MHz
2.304MHz
3.072MHz
1.024MHz
1.536MHz
2.048MHz
512kHz
786kHz
1024kHz
256kHz
384kHz
512kHz
Range
1.368~1.582MHz
2.053~2.373MHz
2.737~3.164MHz
0.912~1.054MHz
1.368~1.582MHz
1.825~2.109MHz
456kHz~527kHz
684kHz~791kHz
912kHz~1054kHz
248kHz~263kHz
372kHz~395kHz
496kHz~527kHz
2011/09
[AK7722]
BITFS=0
@(DIFPCM=0 & DIFI2S=0)
LRCKI
Right ch
Left ch
BICKI
32×BICK
BITFS=2
32×BICK
@(DIFPCM=0 & DIFI2S=0)
LRCKI
Right ch
Left ch
BICKI
16×BICK
BITFS=1
16×BICK
@(DIFPCM=0 & DIFI2S=0)
LRCKI
Right ch
Left ch
BICKI
24×BICK
24×BICK
* DIFPCM is set by CONT01: D7, and DIFI2S is set by CONT01: D6.
* The sampling rate is determined by control register CONT0 DFS mode settings.
* In applications which do not need the XTI pin of the AK7722 or an external crystal oscillator, set the XTI pin= “L”
(DVSS).
MS1328-E-00
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2011/09
[AK7722]
4. Slave Mode (SRBICKn Input, CKM Mode 4)
This mode is the same slave mode as CKM mode 3 but the required clocks are different. SRBICKn is used instead of
BICKI and SRLRCKn is used instead of LRCKI (n=1, 2, 3). This mode is available when the SRC is not used. Control
register SRCRST bit should be set to “1” (SRC reset). In this mode, SRBICKn is used for clock source. This clock is
multiplied directly by a PLL, therefore burst clock or the clock with two different frequencies can not be used. SRBICKn
and SRLRCKn must be synchronized.
DFS
BITFS
[1:0]
0
0
0
1
1
1
2
2
2
3
3
3
Fs
48kHz
48kHz
48kHz
32kHz
32kHz
32kHz
16kHz
16kHz
16kHz
8kHz
8kHz
8kHz
[1:0]
2
1
0
2
1
0
2
1
0
2
1
0
BITFS=0
@(DIFPCM=0 & DIFI2S=0)
SRLRCKn
SRBICKn
32fs
48fs
64fs
32fs
48fs
64fs
32fs
48fs
64fs
32fs
48fs
64fs
fs: sampling frequency
Input Frequency
Range
SRBICKn
Frequency
fs=44.1kHz
1.4112MHz
2.1168MHz
2.8224MHz
0.9408MHz
1.4112MHz
1.8816MHz
470.4kHz
705.6kHz
940.8kHz
Not Available
Not Available
Not Available
fs=48kHz
1.536MHz
2.304MHz
3.072MHz
1.024MHz
1.536MHz
2.048MHz
512kHz
786kHz
1024kHz
256kHz
384kHz
512kHz
1.368~1.582MHz
2.053~2.373MHz
2.737~3.164MHz
0.912~1.054MHz
1.368~1.582MHz
1.825~2.109MHz
456kHz~527kHz
684kHz~791kHz
912kHz~1054kHz
248kHz~263kHz
372kHz~395kHz
496kHz~527kHz
Right ch
Left ch
SRBICKn
32×SRBICKn
BITFS=2
32×SRBICKn
@(DIFPCM=0 & DIFI2S=0)
SRLRCKn
Right ch
Left ch
SRBICKn
16×SRBICKn
BITFS=1
16×SRBICKn
@(DIFPCM=0 & DIFI2S=0)
SRLRCKn
Right ch
Left ch
SRBICKn
24×SRBICKn
24×SRBICKn
* DIFPCM is set by CONT01: D7, and DIFI2S is set by CONT01: D6.
MS1328-E-00
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2011/09
[AK7722]
■ Control Register Setting
The AK7722 control register settings are executed through a microcontroller interface. All registers are initialized by
INITRSTN pin = “L” initial reset. When power-up the AK7722, initial reset must always be made. Since control
registers CONT00, CONT01 and CONT0B are related to clock generation, they must be changed during clock reset
(CKRSTN bit = “0”). CONT0C, CONT0D, CONT0E, CONT10-CONT17 can be written during an operation. The other
control registers must be changed during clock reset or system reset (CRSTN and DSPRSTN bits = “0”) to avoid errors
and noises. Registers with * marking in the beginning of their register name are “1” at default, and the others are “0” at
default.
CONT00-CONT0E
Name
W
D7
D6
D5
D4
D3
D2
D1
D0
Default
R
C0h
40h
CONT00
Reserved
CKM[2]
CKM[1]
CKM[0]
DFS[1]
DFS[0]
BITFS[1]
BITFS[0]
00h
C1h
41h
CONT01
DIFPCM
DIFI2S
PCM[1]
PCM[0]
TEST
TEST
TEST
TEST
00h
C2h
42h
CONT02
Reserved
Reserved
BANK[1]
BANK[0]
JX1E
JX2E
SS[1]
SS[0]
00h
C3h
43h
CONT03
POMODE
DATARAM
WDTEN
WAVM
WAVP[1]
WAVP[0]
EFEN
CRCE
00h
C4h
44h
CONT04
DIF2[1]
DIF2[0]
DIF1[1]
DIF1[0]
TEST
TEST
TEST
TEST
00h
C5h
45h
CONT05
DOF3[1]
DOF3[0]
DOF2[1]
DOF2[0]
DOF1[1]
DOF1[0]
SELDO5[1]
SELDO5[0]
00h
C6h
46h
CONT06
BICKOE
LRCKOE
OUTS
SELBCK
SELDI5
SELDI4
SELDI3
Reserved
00h
C7h
47h
CONT07
CLKOE
CLKS[2]
CLKS[1]
CLKS[0]
CLKOP
OUT3E
OUT2E
OUT1E
00h
C8h
48h
CONT08
SELDO3[1]
SELDO3[0]
SELDO2[1]
SELDO2[0]
SELDO1[1]
SELDO1[0]
SELDO4[1]
SELDO4[0]
00h
C9h
49h
CONT09
MUX2E
MUX2[2]
MUX2[1]
MUX2[0]
Reserved
MUX1[2]
MUX1[1]
MUX1[0]
00h
CAh
4Ah
CONT0A
BIEDGE
IDIF[2]
IDIF[1]
IDIF[0]
BIFS[1]
BIFS[0]
SEMIAUTO
AUTOSEL
00h
CBh
4Bh
CONT0B
Reserved
TEST
DSEL[1]
DSEL[0]
Reserved
Reserved
Reserved
SETSRC
00h
CCh
4Ch
CONT0C
TEST
ASEL[2]
ASEL[1]
ASEL[0]
TEST
GIDIF[2]
GIDIF[1]
GIDIF[0]
00h
CDh
4Dh
CONT0D
AD2RST
AD1RST
ATSPAD
GSRCRST
DA2RST
DA1RST
ATSPDA
SRCRST
00h
CEh
4Eh
CONT0E
AD2SMUTE
AD1SMUTE
DA2SMUTE
DA1SMUTE
SRCSMUTE
CRSTN
DSPRSTN
CKRSTN
00h
CONT10 - CONT17
Name
W
D7
D6
D5
D4
D3
D2
D1
D0
Default
R
D0h
50h
CONT10
VOLA1L[7]
VOLA1L[6]
*VOLA1L[5]
*VOLA1L[4]
VOLA1L[3]
VOLA1L[2]
VOLA1L[1]
VOLA1L[0]
30h
D1h
51h
CONT11
VOLA1R[7]
VOLA1R[6]
*VOLA1R[5]
*VOLA1R[4]
VOLA1R[3]
VOLA1R[2]
VOLA1R[1]
VOLA1R[0]
30h
D2h
52h
CONT12
VOLA2L[7]
VOLA2L[6]
*VOLA2L[5]
*VOLA2L[4]
VOLA2L[3]
VOLA2L[2]
VOLA2L[1]
VOLA2L[0]
30h
D3h
53h
CONT13
VOLA2R[7]
VOLA2R[6]
*VOLA2R[5]
*VOLA2R[4]
VOLA2R[3]
VOLA2R[2]
VOLA2R[1]
VOLA2R[0]
30h
D4h
54h
CONT14
VOLD1L[7]
VOLD1L[6]
VOLD1L[5]
*VOLD1L[4]
*VOLD1L[3]
VOLD1L[2]
VOLD1L[1]
VOLD1L[0]
18h
D5h
55h
CONT15
VOLD1R[7]
VOLD1R[6]
VOLDA1R[5]
*VOLD1R[4]
*VOLD1R[3]
VOLD1R[2]
VOLD1R[1]
VOLD1R[0]
18h
D6h
56h
CONT16
VOLD2L[7]
VOLD2L[6]
VOLD2L[5]
*VOLD2L[4]
*VOLD2L[3]
VOLD2L[2]
VOLD2L[1]
VOLD2L[0]
18h
D7h
57h
CONT17
VOLD2R[7]
VOLD2R[6]
VOLD2R[5]
*VOLD2R[4]
*VOLD2R[3]
VOLD2R[2]
VOLD2R[1]
VOLD2R[0]
18h
MS1328-E-00
30
2011/09
[AK7722]
1. CONT00: Input Interface Select
Write during control reset.
W
C0h
R
40h
Name
CONT00
D7
Reserved
D6
CKM[2]
D5
CKM[1]
D4
CKM[0]
D3
DFS[1]
D2
DFS[0]
D1
BITFS[1]
D0
BITFS[0]
Default
00h
D7: Reserved
0: Normal operation (default)
Write “0” into this bit.
D6, D5, D4: CKM[2:0] Clock Mode Select
CKM CKM Master MCLK Source
Mode [2:0] Slave
0
000 Master XTI
1
001 Master XTI
2
010 Slave
XTI
3
011 Slave
BICKI
4
100 Slave
SRBICKn
5
101 6
110 7
111 CKM mode 5~7 cannot be reserved.
Input Frequency
System Clock Input Pins
12.288MHz
18.432MHz
12.288MHz
Set by DFS[1:0],BITFS[1:0]
Set by DFS[1:0],BITFS[1:0]
-
XTI (Crystal Available)
XTI (Crystal Available)
XTI BICKI LRCKI
BICKI, LRCKI
SRBICKn, SRLRCKn
-
(default)
D3, D2: DFS[1:0] Sampling Frequency Setting
DFS
Mode
0
1
2
3
DFS
[1:0]
00
01
10
11
D1, D0: BITFS[1:0] BITCLK
BITFS
Mode
0
1
2
3
BITFS[1:0]
00
01
10
11
Sampling Frequency (kHz)
fs=48kHz
fs=44.1kHz
48
44.1
32
29.4
16
14.7
8
7.35
(default)
fs Select
BITCLK
64fs
48fs
32fs
N/A
(default)
The AK7722 only supports 64fs (BITFS Mode 0) in master mode. Despite this setting is invalid in master mode,
BITFS[1:0] bits should be set to Mode 0.
MS1328-E-00
31
2011/09
[AK7722]
2. CONT01: Control
Write during control reset.
W
C1h
R
41h
Name
CONT01
D7
DIFPCM
D6
DIFI2S
D5
PCM[1]
D4
PCM[0]
D3
TEST
D2
TEST
D1
TEST
D0
TEST
Default
00h
D7: DIFPCM Audio Interface Select
0: MSB justified, LSB justified and I2S format (default)
1: PCM format
PCM format setting is not available when I2S mode is selected.
D6: DIFI2S In/Output Setting Interface I2S Select
0: Except I2S mode (default)
1: I2S mode
DIF2[1:0], DIF1[1:0], DOF3[1:0], DOF2[1:0] and DOF1[1:0] should be set in MSB justified.
I2S mode is not available when PCM format is selected.
D5, D4: PCM[1:0] PCM Format Select (only available in Slave mode)
PCM[1:0] bits control interface format when DIFPCM bit= “1”.
PCM PCM BITCLK
BITCLK edge against
Mode [1:0] (FRAME) LRCLK edge.
0
00
short(SF) Rising edge (RE)
(default)
1
01
short(SF) Falling edge (FE)
2
10
long(LF)
Rising edge (RE)
3
11
long(LF)
Falling edge (FE)
Refer to “p58 PCM format” for details. CONT00: BITFS[1:0] bits set fs.
D3, D2, D1, D0: TEST
Do not change default setting “0”.
MS1328-E-00
32
2011/09
[AK7722]
3. CONT02: RAM Control
Write during control or system reset.
W
C2h
R
42h
Name
CONT02
D7
Reserved
D6
Reserved
D5
BANK[1]
D4
BANK[0]
D3
JX1E
D2
JX2E
D1
SS[1]
D0
SS[0]
Default
00h
D7: Reserved
0: Normal operation (default)
Write “0” into this bit.
D6: Reserved
0: Normal operation (default)
Write “0” into this bit.
D5, D4: BANK[1:0] DLRAM Mode Setting
DLRAM Mode
0
1
2
3
BANK[1:0]
00
01
10
11
DLRAM1
Ring 20.4f
5120word
3072word
2048word
1024word
DLRAM2
Ring 20.4f
DLRAM1
Linear 20.4f
(default)
2048word
2048word
2048word
1024word
2048word
D3: JX1E
0: JX1 Disable (default)
1: JX1 Enable
D2: JX2E
0: JX2 Disable (default)
1: JX2 Enable
D1, D0: SS[1:0] DLRAM Sampling Setting
SS Mode
SS[1:0]
Sampling Setting
0
00
The address is updated in every sampling
(default)
1
01
The address is updated in every 2 samplings *
2
10
The address is updated in every 4 samplings *
3
11
The address is updated in every 8 samplings *
* When SS mode 1/2/3 is selected, aliasing noise may be generated. DLRAM mode 1/2/3 affects to the Ring 20.4f of
DLRAM2 only. DLRAM mode 0 affects to the Ring 20.4f of DLRAM1.
MS1328-E-00
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2011/09
[AK7722]
4. CONT03: RAM Control
Write during control or system reset.
W
R
Name
C3h
43h
CONT03
D7
D6
D5
D4
D3
D2
D1
D0
Default
POMODE
DATARAM
WDTEN
WAVM
WAVP[1]
WAVP[0]
EFEN
CRCE
00h
D7: POMODE
DLYRAM pointer0 Select
0: OFREG (default)
1: DBUS direct
D6: DATARAM
DATARAM
Mode
0
1
Pointer
DATA RAM Addressing Select
A(000h-3FFh)
1024word
Ring Addressing
Ring Addressing
DP0
B(400h-7FFh)
1024word
Ring Addressing
Linear Addressing
DP1
(default)
D5: WDTEN
0: WDTE Enable (default)
1: WDTE Disable
D4: WAVM CRAM WAV Mode Select
0: 1/4 mode (default)
1: 1/2 mode
1/4 mode has an advantage of CRAM memory size but calculation precision drops down.
D3, D2: WAVP[1:0] CRAM Memory Assignment
WAVP Mode
WAVP[1:0] WAVM= “0”
0
00
33word
1
01
65word
2
10
129word
3
11
257word
WAVM= “1”
65word
129word
257word
513word
FFT Point
128
256
512
1024
(default)
D1: EFEN Instruction EF, SJ, IN Enable
0: EF, SJ, IN Disable (default)
1: EF, SJ, IN Enable
D0: CRCE
0: CRC Disable (default)
1: CRC Enable
The STO pin outputs only WDT result when CRCE bit= “0”, and outputs WDT and CRC results when CRCE
bit = “1”.
MS1328-E-00
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2011/09
[AK7722]
5. CONT04: In/Output Interface Clock Select
Write during control or system reset.
W
C4h
R
44h
Name
CONT04
D7
DIF2[1]
D6
DIF2[0]
D5
DIF1[1]
D4
DIF1[0]
D3
TEST
D2
TEST
D1
TEST
D0
TEST
Default
00h
D7, D6: DIF2[1:0] DSP DIN2 Input Format Select
DIF Mode
DIF2[1:0]
Input Data Format
0
00
MSB justified (24Bits)
(default)
1
01
LSB justified 24Bits
2
10
LSB justified 20Bits
3
11
LSB justified 16Bits
Set to DIF mode0 when DIFI2S bit=“1”, set to DIF mode3 when BITFS[1:0] bits=“10”. DSP DIN3, DSP DIN4,
DSP DIN5, DAC1 SDINDA1, DAC2 SDINDA2 and MUX2 inputs are fixed to MSB justified.
D5, D4: DIF1[1:0] DSP DIN1 Input Format Select
DIF Mode
DIF1[1:0]
Input Data Format
0
00
MSB justified (24Bits)
(default)
1
01
LSB justified 24Bits
2
10
LSB justified 20Bits
3
11
LSB justified 16Bits
Set to DIF mode0 when DIFI2S bit=“1”, set to DIF mode3 when BITFS[1:0] bits=“10”. DSP DIN3, DSP DIN4,
DSP DIN5, DAC1 SDINDA1, DAC2 SDINDA2 and MUX2 inputs are fixed to MSB justified.
D3, D2: TEST
00: Normal operation (default)
Write “00” into this bit.
D1, D0: TEST
00: Normal operation (default)
Write “00” into this bit.
MS1328-E-00
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2011/09
[AK7722]
6. CONT05: Output Interface Setting
Write during control or system reset.
W
R
Name
C5h
45h
CONT05
D7
D6
D5
D4
D3
D2
D1
D0
Default
DOF3[1]
DOF3[0]
DOF2[1]
DOF2[0]
DOF1[1]
DOF1[0]
SELDO5[1]
SELDO5[0]
00h
D7, D6: DOF3[1:0] DSP DOUT3 Output Format Select
DOF3 Mode
DOF3[1:0]
Output Data Format
0
00
MSB justified (24Bits)
(default)
1
01
LSB justified 24Bits
2
10
LSB justified 20Bits
3
11
LSB justified 16Bits
Set to DIF mode0 when DIFI2S bit=“1”, set to DIF mode3 when BITFS[1:0] bits=“10”. DSP DOUT5, DSP
DOUT4, SRC SRCO, ADC1 SDOUTAD1 and ADC2 SDOUTAD2 are fixed to MSB justified.
D5, D4: DOF2[1:0] DSP DOUT2 Output Format Select
DOF2 Mode
DOF2[1:0]
Output Data Format
0
00
MSB justified (24Bits)
(default)
1
01
LSB justified 24Bits
2
10
LSB justified 20Bits
3
11
LSB justified 16Bits
Set to DIF mode0 when DIFI2S bit=“1”, set to DIF mode3 when BITFS[1:0] bits=“10”. DSP DOUT5, DSP
DOUT4, SRC SRCO, ADC1 SDOUTAD1 and ADC2 SDOUTAD2 are fixed to MSB justified.
D3, D2: DOF1[1:0] DSP DOUT1 Output Format Select
DOF1 Mode
DOF1[1:0]
Output Data Format
0
00
MSB justified (24Bits)
(default)
1
01
LSB justified 24Bits
2
10
LSB justified 20Bits
3
11
LSB justified 16Bits
Set to DIF mode0 when DIFI2S bit=“1”, set to DIF mode3 when BITFS[1:0] bits=“10”. DSP DOUT5, DSP
DOUT4, SRC SRCO, ADC1 SDOUTAD1 and ADC2 SDOUTAD2 are fixed to MSB justified.
D1, D0: SELDO5[1:0] DAC2 Output Data Select
SELDO5 Mode
SELDO5[1:0]
Output Data Select
0
00
DSP DOUT5
1
01
SELDI3 OUT
2
10
ADC2 SDOUTAD2
3
11
ADC1 SDOUTAD1
DAC2 SDINDA2 input format is fixed to MSB justified.
MS1328-E-00
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(default)
2011/09
[AK7722]
7. CONT06: DSP Output Select
Write during control or system reset.
W
C6h
R
46h
Name
CONT06
D7
BICKOE
D6
LRCKOE
D5
OUTS
D4
SELBCK
D3
SELDI5
D2
SELDI4
D1
SELDI3
D0
DIF3SEL
Default
00h
D7: BICKOE
0: BICKO pin = “L” (default)
1: Output Enable
The BICKO output can be set to “L”.
D6: LRCKOE
0: LRCKO pin= “L” (default)
1: Output Enable
The LRCKO output can be set to “L”.
D5: OUTS LRCKO and BICKO Outputs Select in Slave Mode
0: Bypass output of LRCKI and BICKI via buffer. (default)
1: LRCKI and BICKI are output.
When BICKI/SRBICKIn is 64fs (BITFS mode 0), LRCKO is “H” for 32cycles of BICKI/SRBICKn and “L”
for next 32cycles of BICKI/ SRBICKn.
When BICKI/SRBICKn is 48fs (BITFS mode 0), LRCKO is “H” for 24cycles of BICKI/SRBICKn and “L”
for next 24cycles of BICKI/ SRBICKn.
When BICKI/SRBICKn is 32fs (BITFS mode 0), LRCKO is “H” for 16cycles of BICKI/SRBICKn and “L”
for next 16cycles of BICKI/SRBICKn.
The OUTS bit setting is ignored in master mode.
Refer to ■ Audio Interface.
D4: SELBCK BICKO Polarity Select
0: BICKO Normal Output (default)
1: BICKO Invert the polarity
The polarity is inverted regardless of master mode or slave mode.
D3: SELDI5 DSP DIN5 Input Select
0: MUX1 OUT (default)
1: SDIN5
D2: SELDI4 DSP DIN4 Input Select
0: ADC1 SDOUTAD1 (default)
1: SRIN2
D1: SELDI3 DSP DIN3 Input Select
0: SRCO (default)
1: SRIN1
D0: DIF3SEL DSP DIN3 Corresponding LSB justified Setting
DIF3SEL
DIF1[1:0]
DSP DIN3 Input Data Format
00
0
MSB justified (24Bits)
Except 00
00
(default)
1
Except 00
LSB justified 24Bits
When DSP DIN1 input data format is LSB justified, data input in LSB justified is available for DSP DIN3.
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[AK7722]
8. CONT07: Output Setting
Write during control or system reset.
W
C7h
R
47h
Name
CONT07
D7
CLKOE
D6
CLKS[2]
D5
CLKS[1]
D4
CLKS[0]
D3
CLKOP
D2
OUT3E
D1
OUT2E
D0
OUT1E
Default
00h
D7: CLKOE
0: CLKO pin= “L” (default)
1: CLKO Output Enable
D6, D5, D4: CLKS[2:0]: CLKO Output Clock Select
CLKS CLKS[2:0]
fs=48kHz
fs=44.1kHz
CLKOP (*)
Mode
(CONT7 D1)
0
000
12.288MHz
11.2896MHz
0
(default)
1
001
6.144MHz
5.6448MHz
1
2
010
3.072MHz
2.8224MHz
1
3
011
8.192MHz
7.5264MHz
1
4
100
4.096MHz
3.7632MHz
1
5
101
2.048MHz
1.8816MHz
1
6
110
18.432MHz
16.9344MHz
0
7
111
1
256fs
256fs
* CLKOP bit should be set to “1” in CLKS mode 1-5.
* During system reset, the CLKO output is enable if CLKS mode is 0-6 and disable if CLKS mode is 7.
D3: CLKOP CLKO Output Select
0: CLKS[2:0] (CONT3) =0h,6h (default)
1: CLKS[2:0] (CONT3) =1-5h
It controls the output buffer level.
D2: OUT3E
0: SDOUT3/IRPT pin= “L” (default)
1: SDOUT3/IRPT Output Enable
D1: OUT2E
0: SDOUT2 pin= “L” (default)
1: SDOUT2 Output Enable
D0: OUT1E
0: SDOUT1 pin = “L” (default)
1: SDOUT1 Output Enable
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[AK7722]
9. CONT08: DSP Output Setting
Write during control or system reset.
W
R
Name
C8h
48h
CONT08
D7
D6
D5
D4
D3
D2
D1
D0
Default
SELDO3
SELDO3
SELDO2
SELDO2
SELDO1
SELDO1
SELDO4
SELDO4
00h
[1]
[0]
[1]
[0]
[1]
[0]
[1]
[0]
D7, D6: SELDO3[1:0] SDOUT1 Output Select
SELDO3 Mode
SELDO3[1:0]
0
00
1
01
2
10
3
11
Output Data Select
DSP DOUT3
SRCO/SRIN1
DSP IRPT
DSP DOUT5
D5, D4: SELDO2[1:0] SDOUT2 Output Select
SELDO1 Mode
SELDO2[1:0]
0
00
1
01
2
10
3
11
Output Data Select
DSP DOUT2
SDIN2
DSP DOUT4
ADC2 SDOUTAD2
D3, D2: SELDO1[1:0] SDOUT1 Output Select
SELDO1 Mode
SELDO3[1:0]
0
00
1
01
2
10
3
11
Output Data Select
DSP DOUT1
SDIN1
ADC1 SDOUTAD1
DSP GP0
D1, D0: SELDO4[1:0] MUX2 Output Select
SELDO1 Mode
SELDO3[1:0]
0
00
1
01
2
10
3
11
MUX2 input format is fixed to MSB justified.
MS1328-E-00
Output Data Select
DSP DOUT4
SDIN1
ADC1 SDOUTAD1
ADC2 SDOUTAD2
39
(default)
(default)
(default)
(default)
2011/09
[AK7722]
10. CONT09: MUX Setting
Write during control or system reset.
W
R
Name
C9h
49h
CONT09
D7
D6
D5
D4
D3
D2
D1
D0
Default
MUX2E
MUX2[2]
MUX2[1]
MUX2[0]
Reserved
MUX1[2]
MUX1[1]
MUX1[0]
00h
D7: MUX2E
0: MUX2 Disable (default)
1: MUX2 Enable
1[1/fs] group delay occurs when MUX2 is enabled.
The signal selected by SELDO4[1:0] is output when MUX2 is disabled.
D6, D5, D4: MUX2[2:0] MUX2 Output Setting
MUX2[2:0]
MUX2 Output
Lch
Rch
000
DO4L
DO4R
001
M1L
DO4R
010
DO4L
M1L
011
DO4L/2+M1L/2
DO4R
100
DO4L
DO4R/2+M1L/2
101
DO4L/2+M1L/2
DO4R/2+M1L/2
110
M1L
M1L
111
M1L
M1R
DO4L/R: Lch/Rch of selected signal by SELDO4[1:0] bits.
M1L/R: Lch/Rch of MUX1 output
D3: Reserved
0: Normal operation (default)
Write “0” into this bit.
D2, D1, D0: MUX1[2:0] MUX1 Output Setting
MUX1[2:0]
MUX1 Output
Lch
000
ADC2L
001
ADC2R
010
GSRC
011
ADC2L/2+GSRC/2
100
ADC2R/2+GSRC/2
101
ADC2L/2+ADC2R/2
110
ADC2L
111
GSRC
ADC2L/R: Lch/Rch of ADC2 output
GSRC: Guidance SRC output
MS1328-E-00
Rch
ADC2R
ADC2L
GSRC
ADC2R
ADC2L
GSRC
GSRC
ADC2R
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2011/09
[AK7722]
11. CONT0A: SRC Setting
Write during control or system reset.
W
CAh
R
4Ah
Name
CONT0A
D7
BIEDGE
D6
IDIF[2]
D5
IDIF[1]
D4
IDIF[0]
D3
BIFS[1]
D2
BIFS[0]
D1
SEMIAUTO
D0
AUTOSEL
Default
00h
D7: BIEDGE SRBICKn edge select when using SRC
0: Falling edge against SRLRCKn edge. (default)
1: Rising edge against SRLRCKn edge.
This setting is enable only when SRC input interface is PCM mode (IDIF mode 6/7)
(Refer to IDIF[2:0] D6~D4)
D6, D5, D4: IDIF[2:0]
SRIN1-3 Input Interface Select
fsi: SRC input sampling rate
IDIF Mode
IDIF[2:0]
Input Format
SRBICKn(SRC)
0
000
LSB justified 16bit
≥ 32fsi
(default)
1
001
LSB justified 20bit
≥ 40fsi
2
010
MSB justified 24/20bit
≥ 48fsi
3
011
I2S Compatible 24/16bit
≥ 48fsi or 32fsi
4
100
LSB justified 24bit
≥ 48fsi
5
101
N/A
6
110
PCM SHORT
BIFS[1:0] Setting
7
111
PCM LONG
BIFS[1:0] Setting
When operating PLL by SRBICKn clock (SETSRC bit = “0”), SRBICKn input frequency is only valid at the value
of BIFS[1:0] setting. Therefore, when using 48fsi SRBICK (with SRC), the SETSRC bit must be set to “1”.
D3, D2: BIFS[1:0] SRBICKn (n=1, 2, 3) select when using SRC
BIFS Mode
BIFS[1]
BIFS[0]
SRBICKn (n=1, 2, 3)
0
0
0
32fsi
(default)
1
0
1
64fsi
2
1
0
128fsi
3
1
1
N/A
This setting is necessary when PLL for SRC is operated by SRBICKn (CONT0B D0: SETSRC bit = “0”) and when
IDIF mode6/7 is selected.
D1: SEMI_AUTO SRC soft mute semi_auto function Enable
0: SEMIAUTO OFF (default)
1: SEMIAUTO ON
D0: AUTOSEL SRC soft mute semi_auto mode exiting time setting
0: 2205/fso (default)
1: 8820/fso
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[AK7722]
12. CONT0B: MUX Setting
Write during control reset.
W
CBh
R
4Bh
Name
CONT0B
D7
Reserved
D6
TEST
D5
DSEL[1]
D4
DSEL[0]
D3
Reserved
D2
Reserved
D1
Reserved
D0
SETSRC
Default
00h
D7: Reserved
0: Normal operation (default)
Write “0” into this bit.
D6: TEST
0: Normal operation (default)
Write “0” into this bit.
D5, D4: DSEL[1:0] SRC Input Select
DSEL[1:0] SRC Input
00
SRIN1, SRBICK1, SRLRCK1
01
SRIN2, SRBICK2, SRLRCK2
10
SRIN3, SRBICK3, SRLRCK3
11
N/A
D3: Reserved
0: Normal operation (default)
Write “0” into this bit.
D2: Reserved
0: Normal operation (default)
Write “0” into this bit.
D1: Reserved
0: Normal operation (default)
Write “0” into this bit.
D0: SETSRC Clock select for SRC PLL
0: SRBICKn (default)
1: SRLRCKn
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[AK7722]
13. CONT0C: ADC Setting
W
CCh
R
4Ch
Name
CONT0C
D7
TEST
D6
ASEL[2]
D5
ASEL[1]
D4
ASEL[0]
D3
TEST
D2
GDIF[2]
D1
GIDIF[1]
D0
GIDIF[0]
Default
00h
D7: TEST
0: Normal operation (default)
Write “0” into this bit.
D6, D5, D4: ASEL[2:0] ADC Input Select
ASEL Mode
ASEL1[2:0]
Selected Input Pin
0
000
AIN1LP, AIN1LN, AIN1RP, AIN1RN (default)
1
001
AIN2LP, AIN2LN, AIN2RP, AIN2RN
2
010
AIN3L, AIN3R
3
011
AIN4L, AIN4R
4
100
AIN5L, AIN5R
5
101
AIN6L, AIN6R
6
110
No connection
7
111
No connection
An external mute circuit should be put since a switching noise occurs when changing this setting during operation.
D3: TEST
0: Normal operation (default)
Write “0” into this bit.
D2, D1, D0: GIDIF[2:0] GSRC Input Format Select
GIDIF Mode
0
1
2
3
4
5
6
7
MS1328-E-00
GIDIF[2:0]
000
001
010
011
100
101
110
111
Fsi: GSRC input sampling rate
Input Format
GBICK
LSB justified 16bit
≥ 32fsi
(default)
LSB justified 20bit
≥ 40fsi
MSB justified 24/20bit
≥ 48fsi/40fsi
I2S Compatible 24/16bit
≥ 48fsi or 32fsi
LSB justified 24bit
≥ 48fsi
N/A
N/A
N/A
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2011/09
[AK7722]
14. CONT0D: Reset
W
R
Name
CDh
4Dh
CONT0D
D7
D6
D5
D4
D3
D2
D1
D0
Default
AD2RST
AD1RST
ATSPAD
GSRCRST
DA2RST
DA1RST
ATSPDA
SRCRST
00h
D7: AD2RST ADC2 Reset
0: ADC2 Reset Release (default)
1: ADC2 Reset
In a system applications which do not need ADC2, set AD2RST bit = “1” for power saving.
D6: AD1RST ADC1 Reset
0: ADC1 Reset Release (default)
1: ADC1 Rest
In a system applications which do not need ADC1, set AD1RST bit = “1” for power saving.
D5: ATSPAD ADC1/ADC2 Volume Attenuation Time Setting
0: 1/fs (default)
1: 4/fs
D4: GSRCRST Guidance SRC Reset
0: Guidance SRC Reset Release (default)
1: Guidance SRC Reset
In a system applications which do not need GSRC, set GSRCRST bit = “1” for power saving.
D3: DA2RST DAC2 Reset
0: DAC2 Reset Release (default)
1: DAC2 Reset
In a system applications which do not need DAC2, set DAC2RST bit = “1” for power saving.
D2: DA1RST DAC1 Reset
0: DAC1 Reset Release (default)
1: DAC1 Reset
In a system applications which do not need DAC1, set DAC1RST bit = “1” for power saving.
D1: ATSPDA DAC1/DAC2 Volume Attenuation Time Setting
0: 1/fs (default)
1: 4/fs
D0: SRCRST SRC Reset
0: SRC Reset Release (default)
1: SRC Reset
In a system applications which do not need SRC, set SRCRST bit = “1” for power saving.
In CKM mode 4/6, SRCRST bit should be set to “1”.
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[AK7722]
15. CONT0E: Reset, Soft Mute
W
R
Name
D7
D6
D5
D4
D3
CEh
4Eh
CONT0E
AD2
AD1
DA2
DA1
SRC
SMUTE
SMUTE
SMUTE
SMUTE
SMUTE
D2
CRSTN
D1
DSPRSTN
D0
CKRSTN
Default
00h
D7: AD2SMUTE ADC2 SMUTE Setting
0: ADC2 SMUTE Release (default)
1: ADC2 SMUTE
D6: AD1SMUTE ADC2 SMUTE Setting
0: ADC2 SMUTE Release (default)
1: ADC2 SMUTE
D5: DA2SMUTE DAC2 SMUTE Setting
0: DAC2 SMUTE Release (default)
1: DAC2 SMUTE
D4: DA1SMUTE DAC2 SMUTE Setting
0: DAC2 SMUTE Release (default)
1: DAC2 SMUTE
D3: SRCSMUTE SRC SMUTE Setting
0: SRC SMUTE Release (default)
1: SRC SMUTE
D2: CRSTN CODEC Reset Setting (Active Low)
0: CODEC Reset (default)
1: CODEC Reset Release
CODEC means ADC, DAC, SRC and GSRC.
D1: DSPRSTN DSP Reset Setting (Active Low)
0: DSP Reset (default)
1: DSP Reset Release
D0: CKRSTN Clock Reset Setting (Active Low)
0: Clock Reset (default)
1: Clock Reset Release
Clock reset must be executed when changing CKM mode or input clock frequency. Control registers are not
initialized by this clock reset.
MS1328-E-00
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[AK7722]
16. CONT10-13: ADC1, ADC2 Volume Setting
Name
W
D0h
D1h
R
50h
51h
CONT10
CONT11
D7
D6
D5
D4
D3
D2
D1
D0
Default
VOLA1L
VOLA1L
*VOLA1L
*VOLA1L
VOLA1L
VOLA1L
VOLA1L
VOLA1L
30h
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
VOLA1R
VOLA1R
*VOLA1R
*VOLA1R
VOLA1R
VOLA1R
VOLA1R
VOLA1R
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
VOLA2R
*VOLA2R
*VOLA2R
VOLA2R
VOLA2R
VOLA2R
VOLA2R
D2h
52h
CONT12
VOLA2R
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
D3h
53h
CONT13
VOLA2R
VOLA2R
*VOLA2R
*VOLA2R
VOLA2R
VOLA2R
VOLA2R
VOLA2R
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
30h
30h
30h
Note 48. Refer to ADC Digital Volume.
17. CONT14-17: DAC1, DAC2 Volume Setting
Name
W
D4h
D5h
D6h
D7h
R
54h
55h
56h
57h
CONT14
CONT15
CONT16
CONT17
D7
D6
D5
D4
D3
D2
D1
D0
Default
VOLD1L
VOLD1L
*VOLD1L
*VOLD1L
VOLD1L
VOLD1L
VOLD1L
VOLD1L
30h
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
VOLD1R
VOLD1R
*VOLD1R
*VOLD1R
VOLD1R
VOLD1R
VOLD1R
VOLD1R
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
VOLD2R
VOLD2R
*VOLD2R
*VOLD2R
VOLD2R
VOLD2R
VOLD2R
VOLD2R
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
VOLD2R
VOLD2R
*VOLD2R
*VOLD2R
VOLD2R
VOLD2R
VOLD2R
VOLD2R
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Note 49. Refer to DAC Digital Volume.
MS1328-E-00
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2011/09
30h
30h
30h
[AK7722]
■ Power Up/Down Sequence
1. Power Up Sequence
The AK7722 should be powered up when the INITRSTN pin= “L”. The analog REF voltage generator and power
supply circuits for internal digital circuits are powered up by the INITRSTN pin = “H” after all power supplies are fed.
The power up sequence between AVDD and DVDD is not critical. Control register settings are available in 1ms after
the INITRSTN pin = “H”.
The main PLL starts operation and generates internal main clock (MCLK) by CKRSTN bit = “1” when appropriate
system clocks are input (in CKM mode 2-4) or when a crystal oscillator is connected (in CKM mode 0/1). Interfacing
with the AK7722 should be made after main PLL oscillation is stabilized, except control register settings. Normally, the
initialization by the INITRSTN pin is required at power-up only.
Note System clock (XTI) must not be stopped, except at initial reset (INITRSTN pin = “L”) or at clock reset.
DVDD, AVDD
INITRSTN pin
AVDRV pin
RQN pin(I2CSEL= “L”)
SCLK pin(I2CSEL= “L”)
SCL pin(I2CSEL= “H”)
SI pin (I2CSEL pin= “L”)
SDA pin (I2CSEL pin= “H”)
CONT Reg. Setting
DSP Program
CONT Reg. Setting
DSP Program
CKRSTN bit
DSPRSTN bit
CRSTN bit
XTI pin CKM0-2
(SR)BICK(n) pin CKM3,4
Stable Clock
(Internal Master Clock)
100us(min)
1ms(min)
Before PLL stable oscillation
Not permitted access
(50ms)
Command code and
DSP program download
(No time limitation)
Figure 18. Power Up Sequence
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[AK7722]
2. Power Down Sequence
It is recommended to execute initial reset (INITRSTN pin = “L”) before power-down the AK7722. Do not input any
external signal after power-down the AK7722. (Current may flow via the protection diode.)
DVDD, AVDD
INITRSTN (pin)
Power OFF
Figure 19. Power Down Sequence Example
3. LDO (Regulator for Internal circuit driving)
The AK7722 has a regulator (LDO) to drive internal digital circuits. Connect a 1uF capacitor (±30%) between the
AVDRV pin and VSS4. The LDO starts operation by initial reset release, and the control register setting is available in
1ms after initial reset release.
The AK7722 has an over current protection circuit for abnormal heat in case of the AVDRV pin shorts to the ground
and etc. It also has an over voltage protection circuit. When over current or over voltage is detected, the STO pin
outputs “L” and the internal circuits stop operations. In this case, the AK7722 needs to be restarted by initial reset after
removing the problem.
■ Reset
1. Definition of Reset State
The AK7722 has three types of reset function that are Initial reset, Clock reset and System reset. Operating condition
(RUN state) is defined as when these reset are released. The AK7722 is in initial reset condition when the INITRSTN
pin= “L”, and all blocks ADC1, ADC2, DAC1, DAC2, DSP, SRC and etc. are in sleep mode. The AK7722 is in system
reset condition when the INITRSTN pin= “H”, CRSTN bit = DSPSTN bit = “0”. In this condition, PLL and VREF
blocks are in operation but ADC1, ADC2, DAC1, DAC2, DSP, SRC are not in operation. Clock reset is one of the
System reset but CKRSTN bit is “0”. This mode can be used for changing a main clock or clock source when PLL and
internal clock are stopped.
2. Initial Reset
Initial reset is required to initialize all AK7722 blocks. As INITRSTN pin= “L”, all control registers are initialized,
internal counters, ADC1, ADC2, DAC1, DAC2, SRC, PLL, etc. are stopped. The INITRSTN pin should be “L” when
power-up the AK7722. Changing the INITRSTN pin to “H” after 100us (min) from power-up starts REF circuit
(Analog reference voltage) and power supply circuit for digital circuit operations, and control register writing become
valid after 1ms from this initial reset release. Normally, initial reset is used only when power-up/down the AK7722.
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[AK7722]
3. System Reset
System reset is defined as when CRSTN bit = “0” (CONT0E D2) and DSPRSTN bit = “0” (CONT0E D1) after initial
reset is released (INITRSTN pin = “L” → “H”). The state when CKRSTN bit = “0” (CONT0E D0) in system reset is
called clock reset.
When initial reset is released, the AK7722 is in both system and clock reset states. At this time, all internal blocks of the
AK7722, except REF circuit and power supply block for digital circuits are in power save mode. Even the PLL for
master clock generation is not in operation. Control register settings should be made in this clock reset or system reset.
Write control registers 1ms after the initial reset release. Clock generating control registers, CONT00, CONT01 and
CONT0B must be set during clock reset. The other control registers can be set in both clock reset and system reset.
A control register is configured with an 8-bit command code and 8-bit data, and it becomes valid on the 16th rising edge
of SCLK (■ Micro Control Interface). In I2C bus mode, control register settings become valid by an acknowledgement
after receiving data (■ I2C-bus Interface, 1-4. Acknowledge).
RQN
8 9
1
16
SCLK
D7
SI
Command
Data
* *
Setting (Internal)
Fixed
Figure 20. Control Register Writing
The PLL for internal master clock starts an operation and generating master clock when the clock reset state is released
(CKRST bit = “1”).
System Reset
RQN
SCLK
SI
System Reset
(Internal Node)
D7
System Reset Release
D7
D7
Command CEh
Data
01h
Command
D7
CEh
Data
07h
(“L”=Reset) System Reset state is showed as internal Noe for simplifying.
Figure 21. Write Sequence Example of System Reset
MS1328-E-00
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2011/09
[AK7722]
4. Clock Reset
CKM[2:0] bits setting and Input clock ICLK ([email protected] Mode 0-2 or [email protected] Mode 3, [email protected]
mode 4 or [email protected] mode 5, [email protected] mode6) can be also changed during the clock reset as well as
during initial reset. By this reset, both the PLL and the internal clocks stop and clock selection can be safely done
during system reset. After system reset, the AK7722 enters clock reset condition by setting the CKRSTN bit = “0”.
Change pin settings and input clock frequency during clock reset. The PLL re-starts by exiting the clock reset condition
(CKRSTN bit = “0” to “1”) after those changes are made and the input clock settles to its final setting. Transmission of
DSP program, Coefficient Data and other data from an external microcontroller is prohibited until the PLL reaches
stable oscillation ([email protected] mode0-4). After transferring DSP program, coefficient data and other data, the AK7722
returns to normal operation by bringing CRSTN or DSPRSTN bit to “1”.
CKM mode3
CKM mode0
XTI
BICKI
600ns(min)
RQN
SCLK (Simplified)
SI
DSPRSTN
CRSTN
CKRSTN
CEh
01h
CEh 00h
DSPRSTN bit = “0”: System Reset
CRSTN bit = “0”
DSPRSTN bit = “1”: System Reset Release
CRSTN bit = “1”
CKRSTN bit = “0”: Clock Reset Release
CKRSTN bit = “1”: Clock Reset
C0h
3×h
CEh
01h
CEh 07h
PLL Oscillation
stabilized
Transferable time of Command
code and DSP program
Input Clock Change
Figure 22. Clock Set Sequence (Ex: CKM Mode 0 → CKM Mode 3)
■ RAM Clear
The AK7722 has a RAM clear function. After the system reset release (during RUN), DRAM and DLRAM are cleared
by writing “0” to DRAM and DLRAM bits. The internal PLL must have stable oscillation before system reset release.
The required time to clear RAM is about 200µs. In the RAM clear sequence, it is possible to order command to DSP.
(DSP is stopped during RAM clear sequence. The ordered command is accepted automatically after this sequence is
completed.)
INITRSTN(Pin)
DSPRSTN (Reg.)
CRSTN (Reg.)
RAM Clear
DSP Start
RAM Clear Period
DSP Program
Start
Figure 23. RAM Clear Sequence
MS1328-E-00
50
2011/09
[AK7722]
■
Status Output Pin
The STO (status output) pin outputs “H” during the INITRSTN pin is “L” if the AK7722 is powered-up. After initial
reset is released, WDT (watchdog timer) error and CRC error status can be output from this pin by LDO shutdown
signal and control register settings. WDT status is output by LDO shutdown signal and instruction setting when the
control register settings are in the default value.
INITRSTN
pin
L
H
CRCE bit
CONT03 D0
0
WDTEN bit
CONT03 D5
0
0
1
1
0
1
1
LDO
Stop
Normal Operation
ABEND
Normal Operation
ABEND
Normal
Operation
ABEND
Normal Operation
ABEND
STO
pin
H
WDTERRN
L
H
L
CRCERRN
WDTERRN
L
CRCERRN
L
Note
Needs instruction setting
(default)
Needs instruction setting
Table 1. STO pin Output
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2011/09
[AK7722]
■ Audio Data Interface (Figure 1)
Serial audio data pins; the SDIN1, SDIN2, SDIN3, SDIN4, SDIN5, SDOUT1, SDOUT2, SDOUT3 pins, are interfaced
with an external system, by LRCKI and BICKI (LRCKO and BICKO). Control register settings are needed to use these
interfaces (Refer to the ■ Block Diagram). The data format is 2's compliment MSB first. I/O format supports MSB
justified, LSB justified and I2S compatible. (In I2S compatible mode, all audio data in/output pins are I2S format.) In
slave mode, PCM format is also supported.
The input formats of SDIN1-2 are 24bit MSB justified at default. 24bit/20bit/16bit LSB justified formats are selectable
by control register settings. The default input format of SDIN3 is MSB justified, however, LSB justified 24bit input
format can be selected by control register setting when the input data format of SDIN1 is LSB justified. The input
formats of SDIN4-5 signals and SDINDA1-2 signals of DAC1-2 inputs are fixed to MSB justified.
The Output formats of SDOUT1-3 are 24bit MSB justified at default. 24bit/16bit LSB justified formats are selectable
by control register settings. The ADC1-2 outputs, SDOUTAD1-2 output formats are fixed to MSB justified.
Input Pin
DIFPCM
SDIN1
DSP DIN1
Necessary Settings for the Path
Selection
None
SDIN2/JX1
SDOUT1 pin
DAC1
SDINDA1
DSP DIN2
SELDO1[1:0] bits= “01”
SELDO4[1:0] bits= “01”
MUX2[2:0] (Refer to P.40)
JX1E bit= “0”
0
DIFI2S
0
Input To
SDOUT2 pin
OUT2E bit= “1”
SRIN1/SDIN3
DSP DIN3
SELDI3 bit= “1”
SRIN2/SDIN4
DSP DIN4
SELDI4 bit= “1”
SDIN5
DSP DIN5
SELDI5 bit= “1”
Supported Input Formats when DIFPCM bit = “0”and DIFI2S bit = “0”
Input Pin
DIFI2S
Input To
Depends on DIF1[1:0] setting
(Refer to P.35)
MSB justified
MSB justified
Depends on DIF2[1:0] setting
(Refer to P.35)
MSB justified / (LSB justified)
MSB justified
MSB justified
MSB justified
Necessary Settings for the Path
Selection
SDIN1
DSP DIN1
None
SDOUT1 pin
SELDO1[1:0] bits= “01”
DAC1
SELDO4[1:0] bits= “01”
SDINDA1
MUX2[2:0] (Refer to P.40)
SDIN2/JX1
DSP DIN2
JX1E bit= “0”
0
1
SDOUT2 pin
OUT2E bit= “1”
SRIN1/SDIN3
DSP DIN3
SELDI3 bit= “1”
SRIN2/SDIN4
DSP DIN4
SELDI4 bit= “1”
SDIN5
DSP DIN5
SELDI5 bit= “1”
Supported Input Formats when DIFPCM bit= “0” and DIFI2S bit = “1”
MS1328-E-00
DIFPCM
Supported Input Formats
52
Supported Input Formats
I2S
2011/09
[AK7722]
Input Pin
Necessary Settings for the
Path Selection
SDIN1
DSP DIN1
None
SDOUT1 pin
SELDO1[1:0] bits= “01”
DAC1
SELDO4[1:0] bits= “01”
SDINDA1
MUX2[2:0] (Refer to P.41)
SDIN2/JX1
DSP DIN2
JX1E bit= “0”
1
0
SDOUT2 pin
OUT2E bit= “1”
SRIN1/SDIN3
DSP DIN3
SELDI3 bit= “1”
SRIN2/SDIN4
DSP DIN4
SELDI4 bit= “1”
SDIN5
DSP DIN5
SELDI5 bit= “1”
Supported Input Formats when DIFPCM bit = “1” and DIFI2S bit = “0”
Output Pin
DIFPCM
DIFI2S
Input To
Necessary Settings for
the Path Selection
SDOUT1/GP0
DSP DOUT1
SELDO1[1:0] bits= “00”
OUT1E bit = “1”
SDIN1 Pin
SELDO1[1:0] bits = “01”
OUT1E bit= “1”
ADC1
SELDO1[1:0] bits= “10”
SDOUTAD1
OUT1E bit= “1”
SDOUT2
DSP DOUT2
SELDO2[1:0] bits = “00”
OUT2E bit= “1”
SDIN2 pin
SELDO2[1:0] bits= “01”
OUT2E bit= “1”
0
0
DSP DOUT4
SELDO2[1:0] bits= “10”
OUT2E bit= “1”
ADC2
SELDO2[1:0] bits= “11”
SDOUTAD2
OUT2E bit= “1”
SDOUT3/IRP
DSP DOUT3
SELDO3[1:0] bits= “00”
T
OUT3E bit= “1”
SRIN1 pin/SRCO SELDO3[1:0] bits= “10”
OUT3E bit= “1”
DSP DOUT5
SELDO3[1:0] bits= “11”
OUT3E bit= “1”
Supported Output Formats when DIFPCM bit = “0” and DIFI2S bit = “0”
MS1328-E-00
DIFPCM
DIFI2S
Output From
53
Supported Input Formats
Depends on PCM[1:0]
settings
(Refer to P.32)
Supported Output Formats
Depends on DOF1[1:0] settings
(Refer to P.36)
MSB justified
MSB justified
Depends on DOF2[1:0] settings
(Refer to P.36)
MSB justified
MSB justified
MSB justified
Depends on DOF3[1:0] settings
(Refer to P.36)
MSB justified
MSB justified
2011/09
[AK7722]
Output Pin
DIFPCM
Necessary Settings for the
Path Selection
SDOUT1/GP0
DSP DOUT1
SELDO1[1:0] bits= “00”
OUT1E bit= “1”
SDIN1 pin
SELDO1[1:0] bits= “01”
OUT1E bit= “1”
ADC1
SELDO1[1:0] bits= “10”
SDOUTAD1
OUT1E bit= “1”
SDOUT2
DSP DOUT2
SELDO2[1:0] bits= “00”
OUT2E bit= “1”
SDIN2 pin
SELDO2[1:0] bits= “01”
OUT2E bit= “1”
0
1
DSP DOUT4
SELDO2[1:0] bits= “10”
OUT2E bit= “1”
ADC2
SELDO2[1:0] bits= “11”
SDOUTAD2
OUT2E bit= “1”
SDOUT3/IRPT
DSP DOUT3
SELDO3[1:0] bits= “00”
OUT3E bit= “1”
SRIN1 pin/SRCO
SELDO3[1:0] bits= “10”
OUT3E bit= “1”
DSP DOUT5
SELDO3[1:0] bits= “11”
OUT3E bit= “1”
Supported Output Formats when DIFPCM bit = “0” and DIFI2S bit = “1”
Supported Output
Format
Output Pin
Supported Output
Format
DIFI2S
Output From
Necessary Settings for
the Path Selection
SDOUT1/GP0
DSP DOUT1
SELDO1[1:0] bits= “00”
OUT1E bit= “1”
SDIN1 pin
SELDO1[1:0] bits= “01”
OUT1E bit= “1”
ADC1
SELDO1[1:0] bits= “10”
SDOUTAD1
OUT1E bit= “1”
SDOUT2
DSP DOUT2
SELDO2[1:0] bits= “00”
OUT2E bit= “1”
SDIN2 pin
SELDO2[1:0] bits= “01”
OUT2E bit= “1”
1
0
DSP DOUT4
SELDO2[1:0] bits= “10”
OUT2E bit= “1”
ADC2
SELDO2[1:0] bits= “11”
SDOUTAD2
OUT2E bit= “1”
SDOUT3/IRPT
DSP DOUT3
SELDO3[1:0] bits= “00”
OUT3E bit= “1”
SRIN1 pin/SRCO
SELDO3[1:0] bits= “10”
OUT3E bit= “1”
DSP DOUT5
SELDO3[1:0] bits= “11”
OUT3E bit= “1”
Supported Output Formats when DIFPCM bit = “1” and DIFI2S bit = “0”
MS1328-E-00
DIFPCM
DIFI2S
Output From
54
I2S
Depends of PCM[1:0]
settings
(Refer to P.32)
2011/09
[AK7722]
1. MSB, LSB justified Formats
1) Master Mode (CKM Mode 0, 1) MSB justified (24bit), BICKO=64fs
CONT01 D7
DIFPCM
0
CONT01 D6
DIFI2S
0
CONT01 D5
PCM[1]
0
CONT01 D4
PCM[0]
0
CONT00 D1,D2
BITFS
00
Left ch
LRCKO
Right ch
BICKO
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1, 2
DIF Mode 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
M: MSB, L: LSB
SDOUT1~3
DOF Mode 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
M: MSB, L: LSB
2) Master Mode (CKM mode 0, 1) LSB justified, BICKO=64fs
CONT01 D7
DIFPCM
0
CONT01 D6
DIFI2S
0
CONT01 D5
PCM[1]
0
CONT01 D4
PCM[0]
0
CONT00 D1,D2
BITFS
00
Left ch
LRCKO
Right ch
BICKO
31 30
23 22 21 20 19 18 17 16 15 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
SDIN1, 2 (SDIN3)
DIF Mode 1
Don’t care M 22 21 20 19 18 17 16 15 14
1 L Don’t care M 22 21 20 19 18 17 16 15 14
1 L
SDIN1, 2
DIF Mode 2
Don’t care
M 18 17 16 15 14
1 L Don’t care
M 18 17 16 15 14
1 L
SDIN1, 2
DIF Mode 3
Don’t care
M 14
1 L Don’t care
M 14
1 L
M: MSB, L: LSB
SDOUT1, 2, 3
DOF Mode 1
MSB
22 21 20 19 18 17 16 15 14
1 L
MSB
22 21 20 19 18 17 16 15 14
1 L
SDOUT1, 2, 3
DOF Mode 2
MSB
18 17 16 15 14
1 L
MSB
18 17 16 15 14
1 L
SDOUT1, 2, 3
DOF Mode 3
MSB
14
1 L
MSB
14
1 L
SDIN3-5 pins do not support this mode. The SDIN3 pin only supports 24bit LSB justified input format when CONT06:
D0= “1” and SDIN1 is in DIF mode 1-3.
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[AK7722]
3) Slave Mode (CKM Mode 2, 3, 4) MSB justified (24bit), BICK/SRBICKn=64fs
CONT01 D7
DIFPCM
0
CONT01 D6
DIFI2S
0
CONT01 D5
PCM[1]
0
CONT01 D4
PCM[0]
0
CONT00 D1,D2
BITFS
00
Left ch
LRCKI/SRLRCKn
Right ch
BICKI/SRBICKn
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1, 2
DIF Mode 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
M: MSB, L: LSB
SDOUT1~3
DOF Mode 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
M: MSB, L: LSB
4) Slave Mode (CKM Mode2, 3, 4) LSB Justfied, BITCLK64fs
CONT01 D7
DIFPCM
0
CONT01 D6
DIFI2S
0
CONT01 D5
PCM[1]
0
CONT01 D4
PCM[0]
0
CONT00 D1, D2
BITFS
00
Left ch
LRCKI/SRLRCKn
Right ch
BICKI/SRBICKn
31 30
23 22 21 20 19 18 17 16 15 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
SDIN1, 2 (SDIN3)
DIF Mode 1
Don’t care M 22 21 20 19 18 17 16 15 14
1 L Don’t care M 22 21 20 19 18 17 16 15 14
1 L
SDIN1, 2
DIF Mode 2
Don’t care
M 18 17 16 15 14
1 L Don’t care
M 18 17 16 15 14
1 L
SDIN1, 2
DIF Mode 3
Don’t care
M 14
1 L Don’t care
M 14
1 L
M: MSB, L: LSB
SDOUT1, 2, 3
DOF Mode 1
MSB
22 21 20 19 18 17 16 15 14
1 L
MSB
22 21 20 19 18 17 16 15 14
1 L
SDOUT1, 2, 3
DOF Mode 2
MSB
18 17 16 15 14
1 L
MSB
18 17 16 15 14
1 L
SDOUT1, 2, 3
DOF Mode 3
MSB
14
1 L
MSB
14
1 L
SDIN3-5 pins do not support this mode. The SDIN3 pin only supports 24bit LSB justified input format when CONT06:
D0= “1” and SDIN1 is in DIF mode 1-3.
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[AK7722]
2. I2S Compatible Format
1) Master Mode (CKM Mode 0, 1)
CONT01 D7
DIFPCM
0
CONT01 D6
DIFI2S
1
CONT01 D5
PCM[1]
0
CONT01 D4
PCM[0]
0
CONT00 D1, D2
BITFS
00
Left ch
LRCKO
Right ch
BICKO
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1, 2
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
M: MSB, L: LSB
SDOUT1, 2, 3
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
M: MSB, L: LSB
When using this mode, set all input and output formats to 24-bit MSB-justified.
2) Slave Mode (CKM Mode 2, 3, 4)
CONT01 D7
DIFPCM
0
CONT01 D6
DIFI2S
1
CONT01 D5
PCM[1]
0
CONT01 D4
PCM[0]
0
CONT00 D1, D2
BITFS
00
Left ch
LRCKI
Right ch
BICKI
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1, 2
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
M: MSB, L: LSB
SDOUT1, 2, 3
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
M: MSB, L: LSB
When using this mode, set all input and output formats to 24-bit MSB-justified.
MS1328-E-00
57
2011/09
[AK7722]
3. PCM Format
1) PCM Mode 0 (CKM Mode 2, 3, 4)
CONT01 D7
DIFPCM
1
LRCKI
CONT01 D6
DIFI2S
0
CONT01 D5
PCM[1]
0
CONT01 D4
PCM[0]
0
CONT00 D1,D2
BITFS
00
tBICK
SF
BICKI
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
SDIN1, 2
M 22 21 20 19
2 1 L
SDOUT1, 2, 3
M 22 21 20 19
2 1 L
M: MSB, L: LSB
Left ch
10 9 8 7 6 5 4 3 2 1 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
Right ch
MSB-justified 24-bit Input / Output Data case is shown above for reference.
2) PCM Mode 1 (CKM Mode 2, 3, 4)
CONT01 D7
DIFPCM
1
LRCKI
CONT01 D6
DIFI2S
0
CONT01 D5
PCM[1]
0
CONT01 D4
PCM[0]
1
CONT00 D1,D2
BITFS
00
tBICK
SF
BICKI
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
SDIN1, 2
M 22 21 20 19
2 1 L
SDOUT1, 2, 3
M 22 21 20 19
2 1 L
M: MSB, L: LSB
Left ch
10 9 8 7 6 5 4 3 2 1 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
Right ch
MSB-justified 24-bit Input / Output Data case is shown above for reference.
MS1328-E-00
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[AK7722]
3) PCM Mode 2 (CKM Mode 2, 3, 4)
CONT01 D7
DIFPCM
1
CONT01 D6
DIFI2S
0
CONT01 D5
PCM[1]
1
CONT01 D4
PCM[0]
0
CONT00 D1,D2
BITFS
00
1 ≤ tBICK ≤ 60
LRCKI
LF
BICKI
63 62 61 60 59
SDIN1, 2
SDOUT1, 2, 3
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
tBICK
M: MSB, L: LSB
10 9 8 7 6 5 4 3 2 1 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
Left ch
Right ch
tBICK × 32
tBICK × 32
MSB-justified 24-bit Input / Output Data case is shown above for reference.
4) PCM Mode 3 (CKM Mode 2, 3, 4)
CONT01 D7
DIFPCM
1
CONT01 D6
DIFI2S
0
CONT01 D5
PCM[1]
1
CONT01 D4
PCM[0]
1
CONT00 D1,D2
BITFS
00
1 ≤ tBICK ≤ 60
LRCKI
LF
BICKI
63 62 61 60 59
SDIN1, 2
SDOUT1, 2, 3
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M 22 21 20 19
2 1 L
tBICK
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
M: MSB, L: LSB
M 22 21 20 19
2 1 L
Left ch
Right ch
tBICK × 32
tBICK × 32
MSB-justified 24-bit Input / Output Data case is shown above for reference.
MS1328-E-00
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[AK7722]
4. General Purpose Output
The AK7722 has tow ports for general purpose outputs (GP0 and GP1 pins). SELDO1[1:0] bits (CONT08 D3, D2)
switch the control of the SDOUT1/GP0 pin. Output control can be done by the DSP programs. The GP0 and GP1 pins
output “L” at default.
SELDO1 Mode
0
1
2
3
■
SELDO3[1:0]
Output Data Select
00
DSP DOUT1
01
SDIN1
10
ADC1 SDOUTAD1
11
DSP GP0
Table 2. SDOUT1/GP0 pin Switching
(default)
Microcontroller Interface (I2CSEL pin= “L”)
1. Configuration
The access format is: Command code(8bit) + Address + Data (MSB First)
Bit
Length
Command
8
MSB bit is R/W flag. The followed 7bit indicates access area such as PRAM /
CRAM / registers.
Address
16 / 0
Valid only for those cases where accessed areas have addresses such as PRAM /
CRAM / OFREG. When no address is assigned, there is no data.
Data
later
Write data or Read data
section
Note 50. The Address of PRAM is fixed to “0”.
RQN
SCLK
SI
SO
don’t care
(L/H)
Low
MS1328-E-00
Command (8bit)
Address (16bit or 0bit )
Data ( write )
don’t care
(L/H)
Data ( read )
Low or Echo back
60
2011/09
[AK7722]
2. Command Code
BIT7
R/W flag
BIT6
BIT5
BIT4
Area to be accessed
BIT3
BIT2
BIT1
BIT0
Accompanying data to the access area
R/W Flag
Write at “1”, Read at “0”.
Access data and accompanying data
BIT6
BIT5
BIT4 BIT3~0
0
0
0
number of write
0
0
1
number of write
0
1
0
0100/0010
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1000/0100/0010
Register address
Register address
0000
0000
0010
0100
0110
1000
1010
1100
Write preparation to CRAM during RUN
Write preparation to OFREG during RUN
Write operation to CRAM/OFREG during RUN
Write preparation confirmation
Write operation to PRAM/CRAM/OFREG during system reset
Registers 00~0C
Registers 10~17
Device Identification (Read only)
Error Status Read
CRC write/read
Write operation of JX code
Read operation from MIC1
Read operation from MIC2
Read operation from MIC3
Read operation from MIC4
3. Address
Address description is always LSB justified.
Accessing command code BIT[6:4]= “000” to “011” requires 16bit address.
Accessing command code BIT[6:4]= “100” to “111” requires no address.
MS1328-E-00
61
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[AK7722]
4. Data
Length of write data is depending on the writing area size. When accessing RAM, data may be written from sequential
address locations by reading data continuously.
■Write
Command
Code
Address
Data Length
80h~8Fh
16bit
24bit × n
90h~9Fh
16bit
24bit × n
A2h
A4h
B2h
B4h
B8h
C0h~CEh
D0h~D7h
F2h
F4h
16bit
16bit
16bit
16bit
16bit
none
none
none
none
none
none
24bit × n
24bit × n
40bit × n
8bit
8bit
16bit
8bit
Description
Write preparation to CRAM during RUN.
BIT3 ~ BIT0 of the command code assign # of write operation (80h:1,
81h:2,…, 8Fh:16).
Write operation exceeding the assigned # of write, abandons the data.
Write preparation to OFREG during RUN.
BIT3 ~ BIT0 of the command code assign # of write operation (90h:1,
91h:2,…, 9Fh:16).
Write operation exceeding the assigned # of write, abandons the data.
Write operation to OFREG during RUN. Address is ignored.
Write operation to CRAM during RUN. Address is ignored.
Write operation to OFREG during system reset
Write operation to CRAM during system reset
Write operation to PRAM during system reset
Write operation to Register 00h~0Eh
Write operation to Register 10h~17h
Write operation of CRC
Write operation of JX code
Length of the read data is depending on the reading area size. When accessing RAM, data may be read from sequential
address locations by reading data continuously. Writing other than the above-mentioned command code are prohibited.
■Read
Command
Code
24h
32h
34h
38h
40h~4Eh
50h~57h
60h
70h
72h
Address Data Length
none
16bit
16bit
16bit
ALL0
none
none
none
none
none
Description
24bit × n
24bit × n
24bit × n
Write preparation confirm for CRAM and OFREG (during RUN)
Read operation from OFREG during system reset.
Read operation from CRAM during system reset.
40bit × n
Read operation from PRAM during system reset.
Read operation from Register 00h~0Ch
Read operation from Register 10h~17h
Device Identification
Error Status Read
CRC result Dread
Read operation from MIR1
76h
none
32bit
28-bit is upper-bit justified. Lower 4-bits are for validity flags. Valid at 0000.
Read operation from MIR2
78h
none
32bit
28-bit is upper-bit justified. Lower 4-bits are for validity flags. Valid at 0000.
Read operation from MIR3
7Ah
none
32bit
28-bit is upper-bit justified. Lower 4-bits are for validity flags. Valid at 0000.
Read operation from MIR4
7Ch
none
32bit
28-bit is upper-bit justified. Lower 4-bits are for validity flags. Valid at 0000.
Reading other than the above-mentioned command code is prohibited.
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5. Echo-Back Mode
The AK7722 has an Echo-back mode where written-data is output on the SO pin one after another.
1. Write
RQN
SI
COMMAND
SO
OLD ECHO
ADDRESS1
COMMAND
ADDRESS2
ADDRESS1
DATA1
DATA2
ADDRESS2
“L” or “H” Fix
DATA1
COMMAND
ADDRESS1
DATA2
COMMAND
Data is output on SO delaying the time for 8bit from SI input.
Figure 24. Echo-Back Mode Writing1
RQN
SI
SO
COMMAND
OLD ECHO
ADDRESS1
ADDRESS2
COMMAND
ADDRESS1
DATA1
ADDRESS2
DATA2
Dummy 8bit
DATA1
DATA2
It is possible to write 8bit dummy data in order to verify the written data. During PRAM writing, if the dummy data is
more than 40bit, this dummy data is accepted. (more than 24bit when CRAM and OFREG writing)
Figure 25. Echo-Back Mode Writing2
2. Read
RQN
SI
SO
COMMAND
OLD ECHO
ADDRESS1
COMMAND
“L” or “H” Fix
ADDRESS2
ADDRESS1
READ DATA
READ DATA
COMMAND
ADDRESS1
“L” or “H” Fix
COMMAND
Echo-back is not completely performed when reading, and read data output is prioritized. The figure above is when
reading PRAM.
Figure 26. Echo-Back Mode Reading
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6. Format
6-1. Write Operation during System Reset
1. Program RAM (PRAM) Writing (during System Reset)
(1) COMMAND
B8h
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
(4) DATA1
0 0 0 0 D35 D34 D33 D32
(5) DATA2
D31~D24
(6) DATA3
D23~D16
(7) DATA4
D15~D8
(8) DATA5
D7~D0
Five bytes of data may be written continuously for each address.
2. Coefficient RAM (CRAM) Writing (during System Reset)
(1) COMMAND
B4h
(2) ADDRESS1
0 0 0 0 A11 A10 A9 A8
(3) ADDRESS2
A7~A0
(4) DATA1
D23~D16
(5) DATA2
D15~D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
3. Offset REG(OFREG) Writing (during System Reset)
(1) COMMAND
B2h
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 A5 A4 A3 A2 A1 A0
(4) DATA1
00000000
(5) DATA2
0 0 0 D12 D11 D10 D9 D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
6-2. Write Operation during System Reset and Run
1. Control Register Writing (during System Reset and Run)
Input
(1) COMMAND
C0h~CDh, D0h~D7h
(2) DATA
D7~D0
Note 51. Write operation may be limited depending on register settings.
2. External Conditional Jump Code Writing (during Reset and Run)
Input
(1) COMMAND
F4h
(2) DATA
D7~D0
3. CRC Code Writing (during System Reset and RUN)
SI
(1) COMMAND
F2h
(2) DATA
D15~D8
(3) DATA
D7~D0
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6-3. Write Operation during Run
1. Coefficient RAM (CRAM) writing (during Run)
Input
(1) COMMAND
80h~8Fh (one data at 80h, sixteen data at 8Fh)
(2) ADDRESS1
0 0 0 0 A11 A10 A9 A8
(3) ADDRESS2
A7~A0
(4) DATA1
D23~D16
(5) DATA2
D15~D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
Execute
Input
(1) COMMAND
A4h
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
Note 52. The COMMAND determines the length of the data. If the written data exceeds the allotted amount, the
excess data is ignored.
2. Offset REG(OFREG) Writing (during Run)
Preparation
Input
(1) COMMAND
90h~9Fh (one data at 90h, sixteen data at 9Fh)
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 A5 A4 A3 A2 A1 A0
(4) DATA1
00000000
(5) DATA2
0 0 0 D12 D11 D10 D9 D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
Execute
Input
(1) COMMAND
A2h
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
Note 53. The COMMAND determines the length of the data. If the written data exceeds the allotted amount, the
excess data is ignored.
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6-4. Read Operation during System Reset
1. Program RAM (PRAM) Reading (during System Reset)
Input
Output
(1) COMMAND
38h
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
(4) DATA1
0 0 0 0 D35 D34 D33 D32
(5) DATA2
D31~D24
(6) DATA3
D23~D16
(7) DATA4
D15~D8
(8) DATA5
D7~D0
Five bytes of data may be written continuously for each address.
2. Coefficient RAM (CRAM) Reading (during System Reset)
Input
Output
(1) COMMAND
34h
(2) ADDRESS1
0 0 0 0 A11 A10 A9 A8
(3) ADDRESS2
A7~A0
(4) DATA1
D23~D16
(5) DATA2
D15~D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
3. Offset REG(OFREG) Reading (during System Reset)
Input
Output
(1) COMMAND
32h
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 A5 A4 A3 A2 A1 A0
(4) DATA1
00000000
(5) DATA2
0 0 0 D12 D11 D10 D9 D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
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6-5. Read Operation during System Reset and Run
1. Control Register Reading (during System Reset and Run)
Input
(1) COMMAND
40h~4Dh, 50h~57h
(2) DATA
2. Device Identification (during System Reset and Run)
Input
(1) COMMAND
60h
(2) DATA
D7
0
Output
D7~D0
Output
D6
0
D5
1
2
D4
0
D3
0
D2
0
2
D1
1
D0
0
3. CRC Result Reading (during System Reset and RUN)
Write data
Readout data
(1) COMMAND
0x72
(2) DATA
D15~D8
(3) DATA
D7~D0
4. Error Status Reading (during System Reset and RUN)
Write data
Readout data
(1) COMMAND
0x70
(2) DATA
D7
D6
CRCERRN
WDTERRN
D5
D4
GPO0
GPO1
D3
0
D2
0
D1
0
D0
0
6-6. Read Operation during Run
1. CRAM/OFREG Write Preparation Reading (during RUN)
Input
(1) COMMAND
24h
(2) ADDRESS1
A15~A8
(3) ADDRESS2
A8~A0
(4) DATA1
D23~D16
(5) DATA2
D15~D8
(6) DATA3
D7~D0
Output
2. MIRI1/2/3/4 Reading (during RUN)
Input
Output
(1) COMMAND
76h (MIR1 Read)
78h (MIR2 Read)
7Ah (MIR3 Read)
7Ch (MIR4 Read)
(2) DATA1
D19~D12
(3) DATA2
D11~D4
(4) DATA3
D3~D0 0 0 0 0
(5) DATA4
Exp3~Exp0 (flag) (flag) (flag) (flag)
Note 54. Data is valid only when all flags are zero. When all flag bits are “1”, the data is invalid.
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7. Timing
7-1. RAM Writing Timing during System Reset
Write to Program RAM (PRAM), Coefficient RAM (CRAM) and Offset REG (OFREG) during System Reset in the
order of Command code, Address and Data. The PRAM address is fixed to 0h. When writing Data to consecutive
address locations, continue to input data only. When writing data at separated address locations, set the RQN pin to
“L” from “H” and then input command code, address and data in this order. Writing data to PRAM consecutive
address locations is not possible.
DSPRSTN
(Control Register Setting is Omitted)
CRSTN
SCLK
SI
don’tcare
(L/H)
Command
Address
DATA
DATA
DATA
DATA
DATA
don’tcare
(L/H)
DATA
don’tcare
(L/H)
RDY = “H”
Figure 27. Writing to RAM at Consecutive Address Locations
DSPRSTN
(Contorl Register Setting is Omitted)
CRSTN
SCLK
SI
don’tcare
(L/H)
Command
don’tcare
(L/H)
Address DATA
Command
Address
RDY = “H”
Figure 28. Writing to RAM at separate Address Locations
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7-2. RAM Writing Timing during RUN
Use this operation to rewrite Coefficient RAM (CRAM) and Offset REG(OFREG) during RUN.
1. Write Preparation
After inputting the assigned command code (8-bit) to select the number of data from 1 to 16, input the Starting
Address of write (16-bit all 0) and the number of data assigned by command code in this order.
2. Write Preparation Data Confirmation
After write preparation, prepared data for writing can be confirmed. Address and Data are read in this order by
write preparation data confirmation command “24h”. The data will be “0x000001” when reading more than write
preparation data. Execute write preparation again when the address and data are garbled by external noise.
3. Write Execution
Upon completion of write preparation, execute RAM write during RUN by inputting the corresponding command
code and address (16-bit all 0) in this order.
Note 55. Execute Write preparation before a write execution. When writing to RAM without write preparation
sequence, a malfunction occurs. Access operation by microcontroller is prohibited until RDY changes to
“H”.
Write modification of RAM contents is executed whenever the RAM address for modification is assigned. For
example, when 5 Data are written, from RAM address “10”, it is executed as shown below.
RAM execution address
7
8
9
Write execution position
10
↓
○
11
↓
○
13
16
↑
11
12
↓
○
13
↓
○
14
↓
○
15
Note: Address “13” is not executed until rewriting address “12”.
DSPRSTN= “1”
RQN
Ex.) When # of DATA is 4
OFRAM Command 0x93
CRAM Command 0x83
SCLK
SI
don’tcare
(L/H)
RDY = “H”
Command
Address DATA
DATA
DATA
DATA
CRAM
0x80(# of DATA: 1)~0x8F(# of DATA: 16)
OFREG
0x90(# of DATA: 1)~0x9F(# of DATA: 16)
don’tcare
(L/H)
Figure 29. CRAM, OFREG Write Preparation
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RQN
SCLK
don’t care
(L/H)
SI
SO
don’t care
(L/H)
24h
Echo back output
Address
DATA
DATA
DATA
DATA
DATA
RDY= “H”
Figure 30. CRAM, OFREG Write Preparation Confirm
DSPRSTN= “1”
RQN
SCLK
SI
don’tcare
(L/H)
Command
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
don’tcare
(L/H)
max 400ns
CRAM0xA4,OFREG0xA2
RDY
RDYLG (Note 56)
Note 56. If the DSP program is designed to refer all coefficients which may be changed by an external microcontroller,
RDY signal rises to high within 2LRCK after a writing command. No further access to DSP is permitted until
this write operation is completed. However, while the RQN pin is “L” level, RDY signal keeps “L” level.
Figure 31. CRAM, OFREG Write Execution
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7-3. External Conditional Jump
External Conditional Jump Code Writing (during System Reset and RUN)
(1) COMMAND
F4h
(2) DATA
D7~D0
External Conditional Jump code can be input during both DSP Reset and RUN. Input data is set to the designated
register on the rising edge of LRCKO. The RDY pin changes to “L” when the command code is transferred, and it
changes to “H” when write operations are completed. When any single bit of “1” data in 8-bit External Jump code
matches an “1” bit data in the IFCON field, a Jump instruction is executed. Then, the RDY pin changes to “H”
when the rise of LRCKO is captured. Access operation by microcontroller is prohibited until the RDY pin changes
to “H”. IFCON field is the area where the external conditions are written. This Jump code is reset to 00h by setting
the INITRSTN pin to “L”, but it is not reset by System Reset.
7
■
4
3
2
1
0
■ ■ ■
■
■
↑
Check if “1” of IFCON field corresponds with External Condition Jump Code including Jump pins by at least one at the
same location.
16
↓
9
IFCON Field
♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦
External Conditional Jump Code
6
■
5
■
DSPRSTN (Control Resiter Setting is Omitted)
SCLK
SI
don’tcare
(L/H)
F4h
D7…D0
don’tcare
(L/H)
Lch
RQN
Rch
LRCKO
RDY
Next command write is available
Figure 32. External Conditional Jump Timing (at System Reset)
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DSPRSTN= “1”
SCLK
SI
don’tcare
(L/H)
F4h
D7 … D0
don’tcare
(L/H)
RQN
L ch
R ch
LRCKO
max 2LRCK
RDY
max0.25LRCK
Figure 33. External Conditional Jump Timing (during RUN)
7-4. RAM Reading Timing during System Reset
Read Program RAM (PRAM), Coefficient RAM (CRAM) and Offset REG (OFREG) during System Reset in the
order of input Command code and Address. PRAM address is fixed to 0h. After writing the Command, the data
comes out from the SO pin synchronous with falling edge of SCLK. (The SI pin input data is “Don’t care”) When
reading Data at consecutive address locations, continue to input SCLK as is.
DSPRSTN
(Contorl Register Setting is Omitted
RQN
SCLK
SI
don’t care
(L/H)
SO
Command
Address
Echo back Output
don’t care
(L/H)
DATA
DATA
DATA
DATA
DATA
RDY = “H”
Figure 34. RAM Reading at Consecutive Address
7-5. RAM Reading Timing during System Reset and RUN
Input the Control register, device identifies code and error status during both RUN time and System Reset state.
These codes are input in the order of Command and Address.
After completing Command code write, the data comes out from the SO pin synchronous with falling edge of
SCLK. (The SI pin input data is “Don’t care”)
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DSPRSTN
(Control Register Setting is Omitted
RQN
SCLK
SI
don’tcare
(L/H)
SO
Command
Address
don’tcare
(L/H)
DATA
Echo Back Output
RDY = “H”
Figure 35. RAM Reading during System Reset and RUN
■ I2C Bus Interface (I2CSEL= “H”)
Access to the AK7722 registers and RAM is processed by I²C bus. The format of the I²C is complement with fast mode
(max: 400kHz). The AK7722 does not support HS mode. (max: 3.4MHz).
1. Data Transfer
In order to access any IC devices on the I2C BUS, input a start condition first, followed by a single Slave address which
includes the Device Address. IC devices on the BUS compare this Slave address with their own addresses and the IC
device which has an identical address with the Slave-address generates an acknowledgement. An IC device with the
identical address then executes either a read or write operation. After the command execution, input a Stop condition.
1-1. Data Change
Change the data on the SDA line while SCL line is “L”. SDA line condition must be stable and fixed while the clock is
“H”. Change the Data line condition between “H” and “L” only when the clock signal on the SCL line is “L”. Change
the SDA line condition while SCL line is “H” only when the start condition or stop condition is input.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 36. Data Change
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1-2. Start condition and Stop Condition
A Start condition is generated by the transition of “H” to “L” on the SDA line while the SCL line is “H”. All
instructions are initiated by a Start condition. A Stop condition is generated by the transition of “L” to “H” on SDA line
while SCL line is “H”. All instructions end by a Stop condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 37. Start Condition and Stop Condition
1-3. Repeated Start Condition
When Start condition is received again instead of Stop condition, the bus changes to Repeated Start condition. Repeated
Start condition is functionally the same as Start condition.
SCL
SDA
START CONDITION
Repeated Start CONDITION
Figure 38. Repeated Start Condition
1-4. Acknowledge
An external device that is sending data to the AK7722 releases the SDA line (“H”) after receiving one-byte of data. An
external device that receives data from the AK7722 then sets the SDA line to “L” at the next clock. This operation is
called “acknowledgement”, and it enables verification that the data transfer has been properly executed. The AK7722
generates an acknowledgement upon receipt of a Start condition and Slave address. For a write instruction, an
acknowledgement is generated whenever receipt of each byte is completed. For a read instruction, succeeded by
generation of an acknowledgement, the AK7722 releases the SDA line after outputting data at the designated address,
and it monitors the SDA line condition. When the Master side generates an acknowledgement without sending a Stop
condition, the AK7722 outputs data at the next address location. When no acknowledgement is generated, the AK7722
ends data output (not acknowledged).
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Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
not acknowledge
acknowledge
START
CONDITION
Figure 39. Generation of Acknowledgement
1-5. The First Byte
The First Byte which includes the Slave-address is input after the Start condition is set, and a target IC device that will
be accessed on the bus is selected by the Slave-address. The Slave-address is configured with the upper 7-bits. Data of
the upper 5-bits is “00110”. The next 2 bits are address bits that select the desired IC which are set by the CAD1 and
CAD0 pins. When the Slave-address is inputted, an external device that has the identical device address generates an
acknowledgement and instructions are then executed. The 8th bit of the First Byte (lowest bit) is allocated as the R/W
Bit. When the R/W Bit is “1”, the read instruction is executed, and when it is “0”, the write instruction is executed.
Note 57. In this document, there is a case that describes a “Write Slave-address assignment” when both address bits
match and a Slave-address at R/W Bit = “0” is received. There is a case that describes “Read Slave-address
assignment” when both address bits matches and a Slave-address at R/W Bit = “1” is received.
0
0
1
1
0
CAD1
CAD0
R/W
(CAD1, CAD0 are set by pins)
Figure 40. First Byte Configuration
1-6. The Second and Succeeding Bytes
The data format of the second and succeeding bytes of the AK7722 Transfer / Receive Serial data (command code,
address and data in microcontroller interface format) on the I2C BUS are all configured with a multiple of 8-bits. When
transferring or receiving those data on the I2C BUS, they are divided into an 8-bit data stream segment and they are
transferred / received with the MSB side data first with an acknowledgement in-between.
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Example)
When transferring / receiving A1B2C3 (hex) 24-bit serial data in microprocessor interface format:
2
(1) Microcomputer interface format
A1
B2
(1) I C format
C3
A1
B2
A
24BIT
8BIT
C3
A
8BIT
8BIT
A …Acknowledge
Figure 41. Division of Data
Note 58. In this document, there is a case that describes a write instruction command code which is received at the
second byte as “Write Command”. There is a case that describes a read instruction command code which is
received at the second byte as “Read Command”
2. Write Sequence
In the AK7722, when a “Write-Slave-address assignment” is received at the first byte, the write command at the second
byte and data at the third and succeeding bytes are received. At the data block, address and write data are received in a
single-byte unit each in accordance with a command code. The number of write data bytes (*1 in Figure 42) is fixed by
the received command code.
Usable command codes in write sequence are listed below as “(Table 3) List of Usable Command Codes in Write
Sequence”.
S
SLAD
W
A
Cmd
A
Data
A
Stp
repeat N times (*1)
Figure 42. Write Sequence
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Command
Code
80h-8Fh
Address
2byte
3byte × n
90h-9Fh
2byte
3byte × n
A2h
A4h
B2h
B4h
B8h
2byte
2byte
2byte
2byte
2byte
ALL0
none
none
none
3byte × n
3byte × n
5byte × n
C0h~CEh
Data length
Description
Write preparation to CRAM during RUN.
BIT3 ~ BIT0 of the command code assign # of write operation
(80h:1, 81h:2,…, 8Fh: 16).
Write operation exceeding the assigned # of write, abandons the
data.
Write preparation to OFREG during RUN.
BIT3 ~ BIT0 of the command code assign # of write operation
(90h:1, 91h:2,…, 9Fh: 16).
Write operation exceeding the assigned # of write, abandons the
data.
Write execution to OFREG during RUN. Address is ignored.
Write execution to CRAM during RUN. Address is ignored.
Write operation to OFREG during system reset
Write operation to CRAM during system reset
Write operation to PRAM during system reset
1byte
Write operation to Register 00h~0Dh
(Write operation may be limited depending on register settings.)
D0h~D7h
none
1byte
Write operation to Register 10h~17h
F2h
none
1byte
Write operation of CRC
F4h
none
1byte
Write operation of JX code
Note 59. Length of write data is variable with the areas to be written. When accessing RAM for writing, it is possible to
write data at sequential address locations by writing data continuously. Command code writings other than
shown above are prohibited.
Table 3. List of Usable Command Codes in Write Sequence
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3. Read Sequence
In the AK7722, when a “write- slave-address assignment” is received at the first byte, the read command at the second
byte and the data at the third and succeeding bytes are received. At the data block, the address is received in a single
byte unit in accordance with a read command code. In a command code without address assignment, the sequence does
not have to be repeated (*2 in Figure 43).
When the last address byte (or command code if no address assignment is specified) is received and an
acknowledgement is transferred, the read command waits for the next restart condition. When a “read slave-address
assignment” is received at the first byte, data is transferred at the second and succeeding bytes. The number of readable
data bytes (*3 in Figure 43) is fixed by the received read command.
After reading the last byte, assure that a “not acknowledged” signal is received. If this “not acknowledged” signal is not
received, the AK7722 continues to send data regardless whether data is present or not, and since it did not release the
BUS, the stop condition cannot be properly received.
Usable command codes in read sequence are listed in Table 4: List of Usable Read Command Codes in Read Sequence.
S
SLAD
W
A
Cmd
A
Data
A
rS
SLAD
Repeat N times ( *2 )
R
A
Data
A
Data
Na
Stp
Repeat N-1 times ( *3 )
Figure 43. Read Sequence
Command
Code
24h
32h
34h
38h
40h~4Eh
50h~57h
60h
70h
72h
76h
Address
none
2byte
2byte
2byte
ALL0
none
none
none
none
none
none
Data
Length
3byte × n
3byte × n
3byte × n
5byte × n
Description
Write Preparation Data Read
Read operation from OFREG during system reset
Read operation from CRAM during system reset
Read operation from PRAM during system reset
Read operation from Register 00h~0Eh
Read operation from Register 10h~17h
Device Identification
Error Status Reading
CRC Result Reading
Read operation from MIR1.
28-bit data is upper-bit-justified. Lower 4-bits are for validity flags. Valid
at 0000.
78h
none
4byte
Read operation from MIR2.
28-bit data is upper-bit-justified. Lower 4-bits are for validity flags. Valid
at 0000.
7Ah
none
4byte
Read operation from MIR3.
28-bit data is upper-bit-justified. Lower 4-bits are for validity flags. Valid
at 0000.
7Ch
none
4byte
Read operation from MIR4.
28-bit data is upper-bit-justified. Lower 4-bits are for validity flags. Valid
at 0000.
Note 60. Length of data is variable with the area to be read. As for access to RAM, it is possible to read data at
sequential address locations by reading data continuously.
Note 61. Command code readings other than showed above are prohibited. Command codes ox70 is Error Status read
out.
Table 4. List of Usable Read Command Codes in Read Sequence
MS1328-E-00
1byte
1byte
1byte
1byte
2byte
4byte
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[AK7722]
4. Acknowledgement Polling
The AK7722 cannot receive instructions while the RDY pin (Data Write Ready pin) is at a low level. The
maximum transition time of the RDY pin from low level to high level is specified in the “■ Microcontroller
Interface (I2CSEL= “L”)” section, but it is possible to confirm in a faster cycle that the RDY pin has become high
by checking the AK7722 internal condition, which is made by verifying the acknowledgement.
4-1. Generation of “Not Acknowledged”
The AK7722 does not accept command codes until the RDY pin is set to a high level, when a command is
received to set the RDY pin to a low level. In order to confirm the RDY pin condition, a “Write Slave-Address
assignment” should be sent after the Start condition. If the RDY pin is then at a low level, “Acknowledgement”
is not generated at the succeeding clock (generation of “Not Acknowledged”). After sending “Not
Acknowledged”, The BUS is released and all receiving data are ignored until the next start condition (behaves
as if it received Slave address of other device).
Refer to item (2) of “Figure 44 RDY Pin Condition and Acknowledgement “.
4-2. RDY condition after receiving Slave-address
The RDY pin condition is valid only when a Slave-address is received. If a Slave-address is received, internal
circuit operates normally and a proper acknowledgement is generated even if the RDY pin is forced low by the
received command code instruction in the second byte.
For example, when data succeeding the command code is received while RDY is at low level (caused by
external write condition), a proper acknowledgement is generated.
Refer to item (1) in “Figure 44 RDY Pin Condition and Acknowledgement”.
4-3. Confirmation of RDY pin to be high level
If the RDY pin changes to high just before receiving a Slave-address, an acknowledgement is generated after the
receipt of the “Write-Slave-Address assignment”.
Note 62. “Not Acknowledged” is generated when the RDY pin changes to high in the middle of receiving a
“Write-Slave-Address assignment”. Refer to items (3) and (4) at “Figure 44 RDY pin condition and
acknowledgement”.
(1)After Slave-address
matching is confirmed,
RDY condition is
ignored
…
Data
A
(2)while RDY is low,
(3)“ Not Acknowledged ” (4)“ Acknowledgement ”
“ Not Acknowledged ” is is generated as RDY is is generated as RDY is
generated after
already “L” at the
already “H” at the
receiving Slave-address Receive Start point of
Receive Start point of
Slave-address
Slave-address
Stp
S
SLAD
W Na
…
S
SLAD
W Na
…
S
SLAD
W
A
…
RDY
Figure 44. RDY Pin Condition and Acknowledgement
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2011/09
[AK7722]
4-4. When Read Slave-address assignment is received without receiving Read command code
Data read in the AK7722 can be made only in the previously documented Read sequence. Data cannot be read
out without receiving a read command code. In the AK7722, a “Not Acknowledged” is generated when a “Read
Slave-address Assignment” without proper receipt of read command is received. Under this condition, which
occurs when the RDY pin shifts from low level to high level after a “Write Slave-address assignment” in the
read sequence and before a “Read Slave-address assignment”, “Not Acknowledged” is generated in return.
Note 63. This condition may be avoided by assigning a read Slave-address only when the acknowledgement is
confirmed, by utilizing the acknowledge-polling feature.
Slave-address writing assignment
II2C BUS
S
SLAD
W Na
Cmd
Slave-address reading assignment
Na
xxx
Na
rS
SLAD
R Na
Read Command Code is not
received
Repeated N times
RDY
Without receiving read command code, “ Not
Acknowledged ” is transmitted even when “ Read
Slave-address assignment ” is received at RDY = “H”
Figure 45. Read Slave-Address Assignment without Receiving Read Command Code
Limitation in use of I2C Interface
The I2C Interface does not support the following features.
(1) No operation in Hs mode (max = 3.4 MHz)
(Supports FAST-mode (max = 400 kHz)
(2) Echo-Back function in Microcontroller Interface format.
(3) Error Status Read
Note 64. Do not turn off the power of the AK7722 during the power supplies of surrounding devices are turned on. The
pull-up of SDA and SCL of I2C bus must not exceed the DVDD. (Diodes exist for DVDD in the SDA and SCL
pins.)
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[AK7722]
Note: The meaning of symbols in I2C format figures.
SLAD
…Slave Address (7 bits)
Cmd
…Command Code (8 bits)
S
…Start Condition
rS
…Repeated Star tCondition
Stp
…Stop Condition
W
…R / W bit, the lowest bit of the first byte is at write (= 0) condition, Write ( 1 bit )
R
…R / W bit, the lowest bit of the first byte is at read (= 1) condition, Read ( 1 bit )
A
…Acknowledge (1 bit)
Na
…Not Acknowledge (1 bit)
(Gray)
(White)
MS1328-E-00
(Gray) where it is controlled by Master device.
…(White) where it is controlled by Slave device. It is done by the AK7722.
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[AK7722]
■ ADC Block
1. ADC High-pass filter
The AK7722 ADC has digital High Pass Filter (HPF) for DC offset cancellation. The cut-off frequency of the HPF is
approximately 1Hz (at fs=48kHz). This cut-off frequency is shown below.
Sampling frequency (fs)
Cut-off frequency
48kHz
0.93Hz
44.1kHz
0.86Hz
8kHz
0.16Hz
2. ADC1 Input Selector
ADC1 of the AK7722 has an input selector for 2 stereo differential input and 4 stereo single-ended input. ASEL[2:0]
safe guards (e.g. mute output)bits (CONT 0C D6, D5, D4) control input channels. In case that these registers are
changed while an operation, mute output signal to reduce switching noise as needed. (5. ADC1 Input selector switching
sequence)
D6, D5, D4: ASEL[2:0] ADC Input Select
ASEL Mode
ASEL1[2:0]
Selected Input Pin
0
000
AIN1LP, AIN1LN, AIN1RP, AIN1RN (default)
1
001
AIN2LP, AIN2LN, AIN2RP, AIN2RN
2
010
AIN3L, AIN3R
3
011
AIN4L, AIN4R
4
100
AIN5L, AIN5R
5
101
AIN6L, AIN6R
6
110
No connection
7
111
No connection
In case that these registers are changed while an operation, mute output signal to reduce switching noise.
3. ADC Soft Mute
The ADC block has digital soft mute circuits for ADC1 and ADC2 independently. When the AD1SMUTE or
AD2SMUTE bit becomes “1”, the output signal is attenuated by -∞ during VOLA** x ATT Speed time from the
current ATT level. When the AD1SMUTE or AD2SMUTE bit is returned to “0”, the mute is cancelled and the output
attenuation gradually changes to the ATT level in VOLA** x ATT Speed time. If the soft mute is cancelled before
attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same
cycle. The soft mute is effective for changing the signal source without stopping the signal transmission. The transition
time is 912 LRCK clock (depends on DATT register setting).
The soft mute function works when the ADC is in operation. Attenuation value is initialized by the INITRSTN pin=
“L”. (VOLA**=VOLA1L, VOLA1R, VOLA2L, VOLA2R)
ADSMUTE Register Value
Group Delay (GD)
0dB
Attenuation
Group Delay (GD)
912LRCK
-∞dB
(max)
912LRCK
(max)
Output Image
Figure 46. Soft Mute
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[AK7722]
4. ADC (ADC1, ADC2) Digital Volume
The AK7722 has channel-independent digital volume control ( 256 levels, 0.5dB step).
ADC1 Lch
VOLA1L [7:0]
ADC2 Lch
VOLA2L [7:0]
00h
01h
02h
:
2Fh
30h
31h
:
FDh
FEh
FFh
ADC1 Rch
VOLA1R [7:0]
ADC2 Rch
VOLA2R [7:0]
00h
01h
02h
:
2Fh
30h
31h
:
FDh
FEh
FFh
Attenuation Level
Attenuation Level
+24.0dB
+23.5dB
+23.0dB
:
+0.5dB
0.0dB
-0.5dB
:
-102.5dB
-103.0dB
Mute (-∞)
(default)
Table 5. ADC (ADC1, ADC2) Digital Volume Level Setting
Transition time between set values can be selected by ATSPAD bit. Transition time setting of ADC1 and ADC2 are in
common. They cannot be changed independently.
MODE
0
1
ATSPAD bit
0
1
ATT speed
1/fs
4/fs
(default)
Table 6. ADC Transition Time Setting
The transition between set values is soft transition of 1021 levels in Mode 0. It takes 1021/fs ([email protected]=48kHz) from
00H to FFH(MUTE). If the INITRSTN pin goes to “L”, the VOLA1L/R[7:0] and VOLA2L/R[7:0] bits are initialized to
30h.
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2011/09
[AK7722]
CODE
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
dB
24.0
23.5
23.0
22.5
22.0
21.5
21.0
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
CODE
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
dB
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
-5.5
-.6.0
-6.5
-7.0
-7.5
CODE
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
dB
-8.0
-8.5
-9.0
-9.5
-10.0
-10.5
-11.0
-11.5
-12.0
-12.5
-13.0
-13.5
-14.0
-14.5
-15.0
-15.5
-16.0
-16.5
-17.0
-17.5
-18.0
-18.5
-19.0
-19.5
-20.0
-20.5
-21.0
-21.5
-22.0
-22.5
-23.0
-23.5
CODE
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
dB
-24.0
-24.5
-25.0
-25.5
-26.0
-26.5
-27.0
-27.5
-28.0
-28.5
-29.0
-29.5
-30.0
-30.5
-31.0
-31.5
-32.0
-32.5
-33.0
-33.5
-34.0
-34.5
-35.0
-35.5
-36.0
-36.5
-37.0
-37.5
-38.0
-38.5
-39.0
-39.5
CODE
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
dB
-40.0
-40.5
-41.0
-41.5
-42.0
-42.5
-43.0
-43.5
-44.0
-44.5
-45.0
-45.5
-46.0
-46.5
-47.0
-47.5
-48.0
-48.5
-49.0
-49.5
-50.0
-50.5
-51.0
-51.5
-52.0
-52.5
-53.0
-53.5
-54.0
-54.5
-55.0
-55.5
CODE
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
dB
-56.0
-56.5
-57.0
-57.5
-58.0
-58.5
-59.0
-59.5
-60.0
-60.5
-61.0
-61.5
-62.0
-62.5
-63.0
-63.5
-64.0
-64.5
-65.0
-65.5
-66.0
-66.5
-67.0
-67.5
-68.0
-68.5
-69.0
-69.5
-70.0
-70.5
-71.0
-71.5
CODE
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
DB
-72.0
-72.5
-73.0
-73.5
-74.0
-74.5
-75.0
-75.5
-76.0
-76.5
-77.0
-77.5
-78.0
-78.5
-79.0
-79.5
-80.0
-80.5
-81.0
-81.5
-82.0
-82.5
-83.0
-83.5
-84.0
-84.5
-85.0
-85.5
-86.0
-86.5
-87.0
-87.5
CODE
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
dB
-88.0
-88.5
-89.0
-89.5
-90.0
-90.5
-91.0
-91.5
-92.0
-92.5
-93.0
-93.5
-94.0
-94.5
-95.0
-95.5
-96.0
-96.5
-97.0
-97.5
-98.0
-98.5
-99.0
-99.5
-100.0
-100.5
-101.0
-101.5
-102.0
-102.5
-103.0
Mute
Table 7. ADC (ADC1/2) Digital Volume Setting List
MS1328-E-00
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[AK7722]
5. ADC1 Input selector switching sequence
The input selector should be changed after soft mute to avoid the switching noise of the input selector (Figure 49).
· Input selector switching sequence.
1. Enable the soft mute before changing channel.
2. Change channel.
3. Disable the soft mute.
ADSMUTE
(2)
(1)
(1)
DATT Level
(3)
Attenuation
-∞
Channel
AINL1/AINR1
AINL2/AINR2
Figure 47. Input Channel Switching Sequence Example
The period of (1) varies in the setting value of DATT. It takes 1021/fs to mute when DATT value is +24dB.
Transition time of attenuation amount from 0dB to -∞ is shown below.
ATSPAD
(CONT0D D5)
0
1
LRCLK cycle
912LRCLK
912LRCLKx4
Period (1) (max)
fs=48kHz
fs=44.1kHz
19ms
20.68ms
76ms
82.72ms
fs=8kHz
114ms
456ms
When changing channels, the input channel should be changed during (2). The period of (2) should be around 200ms
because there is some DC difference between the channels (3).
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[AK7722]
■ DAC Blocks
1. DAC Digital Volume Control
The DACs of the AK7722 have channel-independent digital volume control (256 levels, 0.5dB step). The
VOLDA1L[7:0], VOLDA1R[7:0] (DAC1), VOLDA2L[7:0] and VOLDA2R[7:0] (DAC2) bit set the volume level of
each DAC channel. (Table 8)
DAC2 Lch
VOLDA2L
[7:0]
00h
01h
02h
:
17h
18h
19h
:
FDh
FEh
FFh
DAC2 Rch
VOLDA2R
[7:0]
00h
01h
02h
:
17h
18h
19h
:
FDh
FEh
FFh
DAC1 Lch
VOLDA1L
[7:0]
00h
01h
02h
:
17h
18h
19h
:
FDh
FEh
FFh
DAC1 Rch
VOLDA1R
[7:0]
00h
01h
02h
:
17h
18h
19h
:
FDh
FEh
FFh
Attenuation
Level
+12.0dB
+11.5dB
+11.0dB
:
+0.5dB
0.0dB
-0.5dB
:
-114.5dB
-115.0dB
Mute (-∞)
(default)
Table 8. DAC1 and DAC2 Digital Volume Level Setting
Transition time between set values can be selected by ATSPDA bits. Transition time setting of DAC1 and DAC2 are in
common. They cannot be changed independently.
MODE
ATSPDA
ATT speed
0
1
0
1
1/fs
4/fs
(default)
Table 9. DAC1 and DAC2 Volume Transition Time
The transition between set values is soft transition of 1021 levels in Mode 0. It takes 1021/fs ([email protected]=48kHz) from
00H to FFH (MUTE) in Mode 0. If the INITRSTN pin is set to “L”, the VOLDA2L[7:0], VOLDA2R[7:0],
VOLDA1L[7:0] and VOLDA1R[7:0] bits are initialized to 18h.
MS1328-E-00
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[AK7722]
CODE
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
dB
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
CODE
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
dB
-4.0
-4.5
-5.0
-5.5
-.6.0
-6.5
-7.0
-7.5
-8.0
-8.5
-9.0
-9.5
-10.0
-10.5
-11.0
-11.5
-12.0
-12.5
-13.0
-13.5
-14.0
-14.5
-15.0
-15.5
-16.0
-16.5
-17.0
-17.5
-18.0
-18.5
-19.0
-19.5
CODE
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
dB
-20.0
-20.5
-21.0
-21.5
-22.0
-22.5
-23.0
-23.5
-24.0
-24.5
-25.0
-25.5
-26.0
-26.5
-27.0
-27.5
-28.0
-28.5
-29.0
-29.5
-30.0
-30.5
-31.0
-31.5
-32.0
-32.5
-33.0
-33.5
-34.0
-34.5
-35.0
-35.5
CODE
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
dB
-36.0
-36.5
-37.0
-37.5
-38.0
-38.5
-39.0
-39.5
-40.0
-40.5
-41.0
-41.5
-42.0
-42.5
-43.0
-43.5
-44.0
-44.5
-45.0
-45.5
-46.0
-46.5
-47.0
-47.5
-48.0
-48.5
-49.0
-49.5
-50.0
-50.5
-51.0
-51.5
CODE
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
dB
-52.0
-52.5
-53.0
-53.5
-54.0
-54.5
-55.0
-55.5
-56.0
-56.5
-57.0
-57.5
-58.0
-58.5
-59.0
-59.5
-60.0
-60.5
-61.0
-61.5
-62.0
-62.5
-63.0
-63.5
-64.0
-64.5
-65.0
-65.5
-66.0
-66.5
-67.0
-67.5
CODE
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
dB
-68.0
-68.5
-69.0
-69.5
-70.0
-70.5
-71.0
-71.5
-72.0
-72.5
-73.0
-73.5
-74.0
-74.5
-75.0
-75.5
-76.0
-76.5
-77.0
-77.5
-78.0
-78.5
-79.0
-79.5
-80.0
-80.5
-81.0
-81.5
-82.0
-82.5
-83.0
-83.5
CODE
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
dB
-84.0
-84.5
-85.0
-85.5
-86.0
-86.5
-87.0
-87.5
-88.0
-88.5
-89.0
-89.5
-90.0
-90.5
-91.0
-91.5
-92.0
-92.5
-93.0
-93.5
-94.0
-94.5
-95.0
-95.5
-96.0
-96.5
-97.0
-97.5
-98.0
-98.5
-99.0
-99.5
CODE
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
dB
-100.0
-100.5
-101.0
-101.5
-102.0
-102.5
-103.0
-103.5
-104.0
-104.5
-105.0
-105.5
-106.0
-106.5
-107.0
-107.5
-108.0
-108.5
-109.0
-109.5
-110.0
-110.5
-111.0
-111.5
-112.0
-112.5
-113.0
-113.5
-114.0
-114.5
-115.0
Mute
Table 10. DAC Digital Volume Level Setting
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2. DAC Soft Mute Control
The DACs have a soft mute function. The soft mute operation is performed at digital domain. When the DA1SMUTE
and DA2SMUTE bits go to “1”, the output signal is attenuated by -∞ during VOLDA** × ATT Speed transition time
from the current ATT level. When the DA1SMUTE and DA2SMUTE bits are returned to “0”, the mute is cancelled
and the output attenuation gradually changes to the ATT level in VOLDA** × ATT Speed transition time. If the soft
mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to
ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal
transmission.
The soft mute function operates effectively when the DAC section is in operation. After the output signal is attenuated
by -∞ , CRSTN bit = “0”, DA12RST bit = “1” or DA2RST bit= “1” resets the DAC part. As some click noise occurs at
the edge of RSTN signal, the analog output should be muted externally if click noise aversely affect system
performance. The attenuation value is initialized by the INITRSTN pin = “L”. (VOLA**=VOLDA1L, VOLDA1R,
VOLDA2L, VOLDA2R)
SMUTE Register
Setting+2LRCK(max)
Setting+2LRCK(max)
0dB
Attenuation
-∞dB
GD
GD
AOUT
Figure 48. DAC Soft Mute Control
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[AK7722]
■ SRC Block
1. Sampling rate
The AK7722 includes a stereo digital sampling rate converter (SRC). The input sampling rate is supported from
7.35kHz to 96kHz(FSI). The output sampling frequency (FSO) is 7.35kHz ~ 48kHz. When sampling rate ratio FSO/FSI
is more than 1, the output sampling rate is converted to 7.35kHz ~ 48kHz. Available sampling rate ratio FSO/FSI =
0.167~6.0.
[1] Up sampling (0.98≤FSO/FSI≤6.00)
As following sampling ratios are supported.
FSO
FSI
FSO/FSI
48kHz
48kHz
1.00
48kHz
44.1kHz
1.09
48kHz
32kHz
1.50
48kHz
24kHz
2.00
48kHz
16kHz
3.00
48kHz
12kHz
4.00
48kHz
8kHz
6.00
44.1kHz
44.1kHz
1.00
44.1kHz
32kHz
1.38
44.1kHz
24kHz
1.84
44.1kHz
16kHz
2.76
44.1kHz
12kHz
3.68
44.1kHz
8kHz
5.51
32kHz
32kHz
1.00
8kHz
8kHz
1.00
Note 65. The passband and stopband are proportional to FSI.
Pass Band
22.00kHz
20.21kHz
14.67kHz
11.00kHz
7.33kHz
5.50kHz
3.67kHz
20.21kHz
14.67kHz
11.00kHz
7.33kHz
5.50kHz
3.67kHz
14.67kHz
3.67kHz
Stop Band
26.00kHz
23.89kHz
17.33kHz
13.00kHz
8.67kHz
6.50kHz
4.33kHz
23.89kHz
17.33kHz
13.00kHz
8.67kHz
6.50kHz
4.33kHz
17.33kHz
4.33kHz
[2] Down Sampling (0.167≤FSO/FSI≤0.99)
Supported sampling ratios (FSO/FSI) are 0.919, 0.50, 0.25, 0.181 and 0.167.
FSO
FSI
FSO/FSI
Pass Band
Stop Band
48kHz
96kHz
0.50
19.25kHz
26.23kHz
44.1kHz
88.2kHz
0.50
17.69kHz
24.10kHz
44.1kHz
48kHz
0.919
20.00kHz
24.10kHz
16kHz
32kHz
0.50
6.42kHz
8.74kHz
8kHz
48kHz
0.167 (Note 67)
4.40kHz
6.50kHz
8kHz
44.1KHz
0.181 (Note 68)
4.04kHz
5.97kHz
8kHz
32kHz
0.25
2.93kHz
3.98kHz
8kHz
16kHz
0.50
3.21kHz
4.37kHz
Note 66. The passband and stopband are proportional to FSI.
Note 67. The pass-band and stop-band are in high frequency when in/output sampling frequencies are FSO=8kHz
and FSI=48kHz because it is designed on the assumption that signal over 4kHz is attenuated sufficiently
with the fs=8kHz input signal.
Note 68. The pass-band and stop-band are in high frequency when in/output sampling frequencies are FSO=8kHz
and FSI=44.1kHz because it is designed on the assumption that signal over 4kHz is attenuated sufficiently
with the fs=8kHz input signal.
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2. SRC Input/Output Interface
2-1. Input Interface Format
The AK7722 has three input ports for SRC (SRIN1-3 pins). DSEL[1:0] bits (CONT 0B D5, D4) control the input ports
switching. An internal system clock is generated by the internal PLL using SRBICK1-3 (SETSRC bit =“0”) or
SRLRCK1-3 (SETSRC bit = “1”).
The setting should be made during a system reset state. This audio interface supports MSB first, 2’s complement
format.
CONT 0B
D5, D4: DSEL[1:0] SRC Input Select
DSEL[1:0] SRC Input
00
SRIN1, SRBICK1, SRLRCK1
01
SRIN2, SRBICK2, SRLRCK2
10
SRIN3, SRBICK3, SRLRCK3
11
N/A
CONT 0A
D7: BIEDGE SRBICKn (n=1, 2, 3) Select
0: Falling at SRLRCK1-3 edge (default)
tBICK
SF
SRLRCK1-3
SRBICK1-3
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
1: Rising at SRLRCK1-3 edge
tBICK
SF
SRLRCK1-3
SRBICK1-3
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
Figure 49. SRBICK1-3 Edge
D6, D5, D4: IDIF[2:0]
SRC Interface Select
fsi: SRC input sampling rate
IDIF Mode
IDIF[2]
IDIF[1]
IDIF[0] Input format
SRBICK1-3
0
0
0
0
16bit, LSB justified
(default)
≥ 32fsi
1
0
0
1
20bit, LSB justified
≥ 40fsi
2
0
1
0
24/20bit, MSB Justified
≥ 48fsi
3
0
1
1
24/16bit ,I2S Compatible
≥ 48fsi or 32fsi
4
1
0
0
24bit, LSB justified
≥ 48fsi
5
1
0
1
N/A
6
1
1
0
PCM SHORT(24bit)
BIFS[1:0] Setting
7
1
1
1
PCM LONG(24bit)
BIFS[1:0] Setting
Note 69. When Operating PLL by SRBICK1-3 pins (SETSRC bit= “0”), SRBICK1-3 input frequency is only valid at
BIFS[1:0] setting value. Therefore the SETSRC bit must be set to “1” when SRBICK1-3 is 48fsi.
Table 11. SRC Input Interface Select
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[AK7722]
D3, D2: BIFS[1:0] SRBICK1-3 Select
BIFS Mode
BIFS[1]
BIFS[0]
SRBICK1-3
0
0
0
32fsi
(default)
1
0
1
64fsi
2
1
0
128fsi
3
1
1
N/A
Note 70. This setting is necessary when operating PLL by SRBICK1-3 pins (SETSRC bit= “0”) or in IDIF mode6/7.
128fsi supports to fsi=48kHz.
Table 12. SRBICK1-3 Select
Left ch
SRLRCK1-3
Right ch
SRBICK1-3
31 30
23 22 21 20 19 18 17 16 15 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
SRIN1-3
IDIF mode 4
Don’t care M 22 21 20 19 18 17 16 15 14
1 L Don’t care M 2221 20 19 18 17 16 15 14
1 L
SRIN1-3
IDIF mode 1
Don’t care
M 18 17 16 15 14
1 L Don’t care
M 18 17 16 15 14
1 L
SRIN1-3
IDIF mode 0
Don’t care
M 14
1 L Don’t care
M 14
1 L
M: MSB, L: LSB
Figure 50. IDIF Mode 0/1/4 @BIEDGE bit= “0”, SRBICK1-3 64fs
Left ch
SRLRCK1-3
Right ch
SRBICK1-3
SRIN1-3
IDIF mode 2
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M 22 21 20 19
2 1 L
2 1 L
M 22 21 20 19
M: MSB ,L: LSB
Figure 51. IDIF Mode 2 @BIEDGE bit= “0”, SRBCK1-3 64fs
SRLRCK1-3
Left ch
Right ch
SRBICLK1-3
23 22 21 20 19 18 17 16 23 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0
SRIN1-3
IDIF mode 2
M 22 21 20 19 18 17 16 7 6 5 4 3 2 1 L M 22 21 20 19 18 17 16 7 6 5 4 3 2 1 L
M: MSB
L: LSB
Figure 52. IDIF Mode 2 @BIEDGE bit= “0”, SRBCK1-3 48fs (available when only SETSRC bit = “1”)
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Left ch
SRLRCK1-3
Right ch
SRBICK1-3
31 30 29 28 27
SRIN1-3
IDIF mode 3
M 22 21 20
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
3 2 1 L
3 2 1 L
M 22 21 20
M: MSB, L: LSB
Figure 53. IDIF Mode 3 @BIEDGE bit= “0”, SRBICK1-3 64fs
SRLRCK1-3
tBICK
SF
SRBICK1-3
SRIN1-3
IDIF mode 6
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
M 22 21 20 19
2 1 L
L ch
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
2 1 L
R ch
tBICK × 32
Figure 54. IDIF Mode 6 @BIEDGE bit= “1”, BIFS[1:0]=1h
SRLRCK1-3
tBICK
SF
SRBICK1-3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRIN1-3
IDIF mode 6
M: MSB
L: LSB
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L
tBICK × 16
Lch
R ch
Figure 55. IDIF Mode 6 @BIEDGE bit= “1”, BIFS[1:0]=0h
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1 ≤ tBICK ≤ 60
SRLRCK1-3
LF
SRBICK1-3
SRIN1-3
IDIF mode 7
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
M 22 21 20 19
2 1 L
tBCLK M 22 21 20 19
L ch
10 9 8 7 6 5 4 3 2 1 0
2 1 L
M: MSB, L: LSB
R ch
tBICK × 32
Figure 56. IDIF Mode 7 @BIEDGE bit= “1”, BIFS[1:0]=1h
LF
tBCLK
1 ≤ tBICK ≤ 28
SRLRCK1-3
SRBICK1-3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRIN1-3
IDIF mode 7
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L
L ch
M: MSB
L: LSB
R ch
tBICK × 16
Figure 57. IDIF Mode 7 @BIEDGE bit= “1”, BIFS[1:0]=0h
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2-2. Output Interface Format
The SRC output format is fixed to MSB justified 24-bit 2’s complement. It outputs a data synchronizing with internal
clock LRCKO and BICKO. The output sampling rate is fs=48kHz or fs=44.1kHz. I²S compatible format is available by
setting a control register CONT0 DIFI2S bit = “1”.
CONT0 DIFI2S bit= “0”
Left ch
LRCKO
Right ch
BICKO
31 30 29 28 27
SRCO
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
2 1 L
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
2 1 L
M: MSB, L: LSB
CONT0 DIFI2S bit = “1”
Left ch
LRCKO
Right ch
BICKO
31 30 29 28 27
SRCO
M 22 21 20
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
3 2 1 L
M 22 21 20
10 9 8 7 6 5 4 3 2 1 0
3 2 1 L
M: MSB, L: LSB
Figure 58. SRC Output Interface Format
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3. Soft Mute Operation
3-1. Manual Mode
The soft mute operation is performed in the digital domain of the SRC output. When SRCSMUTE bit is set to “1”,
the SRC output data are attenuated by −∞ during 1024 LRCLKO cycles. When the SRCSMUTE bit is set to “0” the
mute is cancelled and the output attenuation gradually changes to 0dB during 1024 LRCLKO cycles. If the soft mute
is cancelled before mute state, the attenuation is discontinued and returned to 0dB by the same cycles. The soft mute
is effective for changing the signal source.
SRCSMUTE
0dB
Attenuation Level
at SRCO
-∞dB
(2)
(1)
(1)
(1) The output data is attenuated by −∞ during 1024 LRCLKO cycles (1024/fso).
(2) The digital output corresponding to the digital input has group delay, GD. If the soft mute is cancelled before
attenuating to −∞, the attenuation is discontinued and returned to 0dB by the same number of clock cycles.
Figure 59. Soft Mute Manual Mode
3-2. Semi-Auto Mode
The soft mute is released automatically by the setting of SRCRST bit “1” → “0”, after the AK7722 detects the falling
edge of the SRCRST bit and the mute is continued during 50ms (SETSRC bit= “0”) or 200ms (SETSRC bit= “1”)
@FSO=44.1kHz. If the SRCSMUTE bit is “1”, the soft mute is not cancelled by SRCRST bit = “1” → “0”. The mute
time is shown in the table below. AUTOSEL bit is set by FSO and SETSRC bits.
FSO
(fso)
8kHz
44.1kHz
48kHz
Mute Time
Comment
Bit
AUTOSEL
SETSRC
1
1103ms
8820/fso
1
0
276ms
2205/fso
0
1
200 ms
8820/fso
1
0
50 ms
2205/fso
0
1
184ms
8820/fso
1
0
46ms
2205/fso
0
(AUTOSEL bit=“0”: 2205/fso, AUTOSEL bit=“1”: 8820/fso)
Table 13. Semi-Auto Mode Setting
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SRCRST
“H”
SRCSMUTE
Don’t Care
“L”
2205/fso(SAUTOSEL=0)
@44.1kHz,48kHz
8820/fso(SAUTOSEL=1)
@44.1kHz,48kHz
0dB
Attenuation
(1)
-∞
(2)
GD
SRCO
(1) The output data is attenuated by 0dB during 1024LRCKO cycles (1024/fso).
(2) The digital output corresponding to the digital input has group delay, GD.
Figure 60. Soft Mute Semi-Auto Mode
4. SRC System Reset
Bringing the SRCRST bit = “1” sets the SRC of the AK7722 reset mode and initializes the digital filters. When
SRCRST bit = “1”, the SRCO output is “L”. The SRC output the data within 50ms (SETSRC bit= “0”) or 200ms
(SETSRC bit= “1”) by releasing the SRC reset after a clock input. Until then, the SRCO outputs “L”. Before
releasing the SRCRST bit to “0”, the SRC setting should be completed, and the system reset must be released.
Case 1
External clocks
(Input port)
Don’t care
Input Clocks 1
Input Clocks 2
Don’t care
SRCI(SRINn)
Don’t care
Input Data 1
Input Data 2
Don’t care
LRCKO
BICKO
(Output port)
Don’t care
Output Clocks 1
Output Clocks 2
Don’t care
(Internal state) Power-down
SRCO
< 200ms(SETSRC=”1”)
< 200ms(SETSRC=”1”)
< 50ms(SETSRC=”0”)
SRCRST
“0” data
PLL lock &
fs detection
< 50ms(SETSRC=”0”)
Normal
operation
PD
Normal data
PLL lock &
fs detection
“0” data
Normal
operation
Power-down
Normal data
“0” data
SRC UNLOCK
Figure 61. System Reset 1
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[AK7722]
Case 2
External clocks
(Input port)
(No Clock)
SRCI
External clocks
(Output port)
Input Clocks
Don’t care
(Don’t care)
Input Data
Don’t care
(Don’t care)
Output Clocks
Don’t care
< 200ms(SETSRC=”1”)
< 50ms(SETSRC=”0”)
SRCRST
(Internal state) Power-down
PLL lock &
fs detection
PLL Unlock
SRCO
“0” data
Normal
operation
Power-down
Normal data
“0” data
SRC UNLOCK
Figure 62. System Reset 2
5. Clock Change
5-1. Internal Reset Function for Clock Change
The SRC part of the AK7722 executes internal reset automatically when the in/output clock is stopped. Normal
data will be output within 50ms (SETSRC bit= “0”) or 200ms (SETSRC bit= “1”) after the clock is restarted.
5-2. Sequence of changing Clocks
The sequence of changing clock for SRC is shown in Figure 63.
clocks
(input or output)
state 1
(unknown)
< 200ms(SETSRC bit=”1”)
< 50ms(SETSRC bit=”0”)
SRCRST
(interlal state)
SRCO
normal operation Power down PLL locktime
& fs detection
normal operation
Note 1
normal data
SRCSMUTE
(Note2,recommended)
Att.Level
state 2
normal data
1024/fso
1024/fso
0dB
-∞dB
Figure 63. Clock Change Sequence
Note:
1.
2.
The data on SRCO may cause a clicking noise. To prevent this, set SRCI (SRINn = 1, 2, 3) to “0” from GD
before SRCRST bit goes to “1”, which will keep the data on SRCO as “0”.
The click noise of Note 1 can be removed by SRCMUTE bit = “1”.
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6. SRCPLL
6-1. SETSRC bit
SETSRC bit (CONT0: D0) selects a locked clock of SRCPLL. Normally this setting is fixed. PLL lock can be
applied to SRBICK1-3 when BIFS[1:0] bits (CONT0A: D3, D2) setting is 32fsi, 64fsi or 128fsi.
SETSRC Mode
0
1
SETSRC bit
0
1
PLL Lock Pin
SRBICKn (n=1, 2, 3)
SRLRCKn (n=1, 2, 3)
6-2. SRC PLL Loop Filter
An 1μF±30% capacitor (C) should be connected in between the SRCLFLT pin and VSS. Any noise must not be put
on the SRCLFLT pin.
AK7722
SRCLFLT
C
VSS
Figure 64. PLL Loop Filter
(1) Applying PLL lock to SRBICK1-3 (SETSRC bit = “0”)
The data will be output within 50ms after SRC reset release.
(2) Applying PLL lock to SRLRCK1-3 (SETSRC bit = “1”)
The data will be output within 200ms after SRC reset release.
Note 71. SRBICK1-3 must not be stopped except when changing the clock.
Note 72. SRBICK1-3 = 32fsi supports only 16bit LSB justified and I2S Compatible formats.
Note 73. SRBICK1-3 must be N-times clock (32/64/128fs) when applying PLL lock to SRBICK1-3.
7. UNLOCK
PLL lock states of the SRC is output from the UNLOCK pin. When the PLL of SRC in the AK7722 is locked, the
UNLOCK pin outputs “L”, and it outputs “H” when the PLL of SRC is unlocked. The UNLOCK pin also outputs “H”
in SRC reset state (SRCRST bit = “1”).
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[AK7722]
■ GSRC (Up-convertor for Guidance Voice Interruption)
1. General
1-1. Sampling Rate
The AK7722 has a Guidance SRC (GSRC) for up-converting mono voice data. It converts the sampling rate of
guidance or phone call voice from 7.35kHz~12kHz (FSI) to 44.1kHz/48kHz (FSO).
[Up-sampling]
Supported sampling rate is shown below.
FSO
FSI
FSO/FSI
Pass Band
48kHz
7.35kHz
1.00
22.00kHz
48kHz
12kHz
1.09
20.21kHz
44.1kHz
44.1kHz
1.00
20.21kHz
44.1kHz
7.35kHz
1.38
14.67kHz
44.1kHz
12kHz
1.84
11.00kHz
Pass-band and stop-band frequencies are proportional to FSI.
Stop Band
26.00kHz
23.89kHz
23.89kHz
17.33kHz
13.00kHz
1-2. GSRC Input Interface
[Input Interface Format]
Data is input via the SDIN5 pin for GSRC and clock are input via GLRCK and GBICK pins. The AK7722 only accepts
SRC input data in slave mode. GIDF[2:0] bits (CONT0) select the input interface of the GSRC. Normally, this is set
during system reset. Input data format is MSB first and 2’complement.
D2, D1, D0: GIDIF[2:0] GSRC Input Format Select
fsi: GSRC Input Sampling Rate
GIDIF Mode
GIDIF[2:0] Input Format
GBICK
0
000
16bit LSB justified
≥ 32fsi
(default)
1
001
20bit LSB justified
≥ 40fsi
2
010
24/20bit MSB justified
≥ 48fsi/40fsi
3
011
24/16bit I2S compatible ≥ 48fsi or 32fsi
4
100
24bit LSB justified
≥ 48fsi
5
101
N/A
6
110
N/A
7
111
N/A
Left ch
GLRCK
Right ch
GBICK
31 30
SDIN5
GIDIF Mode 0
Don’t care
23 22 21 20 19 18 17 16 15 14
M 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
1 L
M: MSB, L: LSB
Figure 65. GIDIF Mode 0 @GBICK 64fs
MS1328-E-00
99
2011/09
[AK7722]
Right ch
Left ch
GLRCK
GBICK
SDIN5
IDIF Mode 1
Don’t care
M 18 17 16 15 14
1 L
M: MSB, L: LSB
Figure 66. GIDIF Mode 1 @GBICK 64fs
Left ch
GLRCK
Right ch
GBICK
31 30 29 28 27
SDIN5
GIDIF Mode 2
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1
0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M: MSB, L: LSB
2 1 L
Figure 67. GIDIF Mode 2 @GBICK 64fs
Left ch
GLRCK
Right ch
GBICK
31 30 29 28 27
SDIN5
GIDIF Mode 3
M 22 21 20
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M: MSB, L: LSB
3 2 1 L
Figure 68. GIDIF Mode 3 @GBICK 64fs
Left ch
GLRCK
Right ch
GBICK
31 30
SDIN5
IDIF Mode 4
23 22 21 20 19 18 17 16 15 14
Don’t care M 22 21 20 19 18 17 16 15 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
1 L
Figure 69. GIDIF Mode 4 @GBICK 64fs
MS1328-E-00
100
2011/09
[AK7722]
■ MUX1
GSRC and ADC2 serial data are output from MUX1. These signals can be switched by MUX1[2:0] bits. The delay time
of GSRC and ADC2 serial outputs via MUX1 is 1Ts (1/fs).
MUX1[2:0]
MUX1 Output
Lch
000 (Default) ADC2L
001
ADC2R
010
GSRC
011
ADC2L/2+GSRC/2
100
ADC2R/2+GSRC/2
101
ADC2L/2+ADC2R/2
110
ADC2L
111
GSRC
ADC2L/R: Lch/Rch of ADC2 output
GSRC: Guidance SRC output
Rch
ADC2R
ADC2L
GSRC
ADC2R
ADC2L
GSRC
GSRC
ADC2R
■ MUX2
MUX2[1:0] bits select output signals between SELDI5 bit setting and SELDO4[1:0] setting. Set MUX2E bit to “1” to
enable the MUX2 output. 1Ts (1/fs) delay occurs when using the MUX2 port. Therefore other signals that need to be
synchronized with MUX2 output should be programmed to delay 1Ts (1/fs).
MUX2 Output
Lch
0 (Default)
Don’t care
DO4L
000 (Default)
DO4L
001
M1L
010
DO4L
011
DO4L/2+M1L/2
1
100
DO4L
101
DO4L/2+M1L/2
110
M1L
111
M1L
DO4L/R: Lch/Rch of selected signal by SELDO4[1:0] bits.
M1L/R: Lch/Rch of MUX1 output
MUX2E
MS1328-E-00
MUX2[2:0]
101
Rch
DO4R
DO4R
DO4R
M1L
DO4R
DO4R/2+M1L/2
DO4R/2+M1L/2
M1L
M1R
Delay Time
0Ts
1Ts
2011/09
[AK7722]
SYSTEM DESIGN
Figure 70 and Figure 71 shows the system connection diagram. An evaluation board (AKD7722) is available which
demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.
<Serial Interface Mode>
Digital +3.3V
0.1μ
0.1μ
17
CLKO
BICKO
LRCKO
SDOUT1
SDOUT2
SDOUT3
38
40
39
41
42
43
CLOCK
27
28
29
SRLRCK1
SRBICK1
SRIN1
45
46
47
SRLRCK2
SRBICK2
SRIN2
48
49
50
58
0.1μ
36
DVDD × 3
AK7722
10μ
57
I2CSEL
53
SCLK
32
SDA
35
SI
33
RQN
31
SO
34
STO
44
RDY
30
“L”
Micom
I/F
&
Audio I/F
Digital Ground
Analog Ground
INITRSTN
52
TESTI1
13
SRLRCK3
SRBICK3
SRIN3
TESTI2
54
SRCLFLT
XTO
20
XTI
AINL1P, AINL1N
9,8
AINR1P, AINR1N
7,6
AINR1P, AINR2N
AINL2P, AINL2N
5,4
AINL2P, AINL2N
AINR2P, AINR2N
3,2
AINR2P, AINR2N
AINL3, AINR3
1,80
AINL3, AINR3
AINL4, AINR4
79,78
AINL4, AINR4
AINL5, AINR5
77,76
AINL5, AINR5
AINL6, AINR6
75,74
AINL6, AINR6
10μ
0.1μ
Analog +3.3V
68,67
AOUTR1P, AOUTR1N
66,65
AOUTL2P, AOUTL1N
64,63
AOUTR2P, AOUTR2N
62,61
A2INL, A2INR
AVDD
GBICK
69
AVDD
GLRCK
VCOM
AVDD
16
A2INL, A2INR
SDIN5
15
GBICKI
14
GLRCKI
70
0.1μ
0.1μ
11,59,71
73,72
LFLT
SDIN5
60
10μ
CL=22pF
AOUTL1P, AOUTL1N
8.2k
10
0.1μ
19
AINL1P, AINL1N
12
10μ
CL=22pF
Rd
1μ
33n
RESET
CONTROL
VSS
VSS
2.2μ
18,37,56
Figure 70. Typical Connection Diagram (I2CSEL pin = “L”)
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[AK7722]
2
<I C Mode>
Digital +3.3V
0.1μ
0.1μ
17
0.1μ
36
DVDD × 3
10μ
57
I2CSEL
CLKO
BICKO
LRCKO
SDOUT1
SDOUT2
SDOUT3
38
40
39
41
42
43
CLOCK
27
28
29
SRLRCK1
SRBICK1
SRIN1
45
46
47
SRLRCK2
SRBICK2
SRIN2
SCL
SDA
CAD0
AK7722
CAD1
53
“H”
32
35
Micom
33
31
SO
34
STO
44
I/F
&
Audio I/F
INITRSTN
TESTI1
Digital Ground
48
49
50
SRLRCK3
SRBICK3
SRIN3
TESTI2
58
SRCLFLT
XTO
52
RESET
CONTROL
13
54
20
CL=22pF
Rd
Analog Ground
1μ
XTI 19
AINL1P, AINL1N
9,8
AINL1P, AINL1N
AINR1P, AINR1N
7,6
AINR1P, AINR2N
AINL2P, AINL2N
5,4
AINL2P, AINL2N
AINR2P, AINR2N
3,2
AINR2P, AINR2N
AINL3, AINR3
1,80
AINL3, AINR3
AINL4, AINR4
79,78
AINL4, AINR4
AINL5, AINR5
77,76
AINL5, AINR5
AINL6, AINR6
75,74
AINL6, AINR6
CL=22pF
AOUTL1P, AOUTL1N
AOUTR1P, AOUTR1N
AOUTL2P, AOUTL1N
AOUTR2P, AOUTR2N
A2INL, A2INR
68,67
66,65
64,63
62,61
73,72
A2INL, A2INR
12 LFLT
33n
8.2k
SDIN5
10
10μ
GBICK
0.1μ
Analog +3.3V
60
10μ
SDIN5
AVDD
GLRCK
15
GBICKI
14
GLRCKI
0.1μ
69
10μ
16
AVDD
VCOM
AVDD
0.1μ
0.1μ
11,59,71
70
VSS
VSS
2.2μ
18,37,56
Figure 71. Typical Connection Diagram (I2CSEL pin = “H”)
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[AK7722]
(2) Peripheral Circuits
1. Ground and Power Supply
To minimize digital noise coupling, AVDD and DVDD should be individually de-coupled at the AK7722. System analog
power is supplied to AVDD. VSS1-6 should be connected to the same analog ground. Decoupling capacitors, particularly
ceramic capacitors of small capacity, should be connected at positions as close as possible to the AK7722. VSS and the system
digital ground must be connected to the same ground plane.
2. Reference Voltage
The AVDD voltage controls analog signal range. VCOM is a common voltage of this chip and the VCOM pin outputs
AVDD/2. A 2.2µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor attached between the VCOM pin and VSS
eliminates the effects of high frequency noise. Especially a ceramic capacitor should be connected as close as possible to the
pin.
Do not take load current from the VCOM pin. Digital signal lines, especially clock signal line should be kept away as far as
possible from this pin in order to avoid unwanted coupling into the AK7722.
3. Analog Input
The analog input signal is single-ended. The input voltage is FS = (AVDD - VSS) x 2.0/3.3. When AVDD = 3.3V and VSS =
0.0V, the input voltage range is 2.00Vpp. The output code format is 2's complements. Input DC offset is canceled by an
integrated high-pass filter.
After initial reset is released, the internal operating point level AVDD/2 occurs on analog input pins of the AK7722.
Concerning the internal operating point formation circuit, each input pin has impedance of 35kΩ (typ @fs=48kHz). The pins
that are connected to AC coupling capacitors require start up time (time constant).
The AK7722 samples the analog inputs at 3.072MHz when fs=48kHz. The digital filter rejects noise from 30kHz to 3.042MHz.
The AK7722 includes an anti-aliasing filter (RC filter) to attenuate a noise around 3.042MHz~3.072MHz. No external low-pass
filter is needed in front of the ADC for normal audio signal. However, an external low-pass filter should be connected before
the ADC for the signal which has large out-of-band noise such as D/A converted signals.
The analog source voltage to the AK7722 is +3.3V typical. Voltage of AVDD + 0.3V or more, voltage of VSS - 0.3V or less,
and current of 10mA or more must not be applied to analog input pins. Excessive current will damage the internal protection
circuit and will cause latch-up, damaging the IC. Accordingly, if the external analog circuit voltage is ±15V, the analog input
pins must be protected from signals which are the absolute maximum rating or more.
10k
Signal
22μ
+
+12V
10k
68p
10k
+
2k
+12V
10k
2.20Vpp
68p
+
2k
+
LME49720MA
+
10k
2.2μ
10μ
10k
+
AIN+
2.2μ
AIN2.20Vpp
0.1μ
Figure 72. Input Buffer Circuit Example (Differential)
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[AK7722]
4. Analog Output
8.2k
2.08Vpp
+
AOUT-
8.2k
300
22u
22u
AOUT+
4.16Vpp
+12V
2.2n
+
8.2k
+12V
+
300
8.2k
270p
22u
+
LME49720MA
270p
220
VAOUT
10k
4.7k
2.08Vpp
4.7k
10u +
0.1u
Figure 73. External LPF Circuit Example
The analog output is full differential. The output range is ±2.08Vpp (typ.) centered on AVDD/2 (typ). The differential outputs are
summed externally, VAOUT = (AOUT+) - (AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the output range is
4.16Vpp.
The bias voltage of the external summing circuit is supplied externally. The input code format is in 2’s complement. The output
voltage is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is VCOM
voltage for 000000H(@24bit).
DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of AVDD/2 + a few mV.
Figure 73 shows an example of output buffer circuit..
5. Connection to Digital Circuit
To minimize the noise from digital circuits, the digital output of the AK7722 must be connected to CMOS or low voltage logic
ICs such as 74HC and 74AC for CMOS and 74LV, 74LV-A, 74ALVC and 74AVC for low voltage logic ICs.
6. Cristal Oscillator
The resistor and capacitor values for the oscillator RC circuit are shown in Table 14.
CKM Mode
0
1
MS1328-E-00
R1 max
C0 max
XTI, XTO pin Capacity
70Ω
5pF
22pF
50Ω
5pF
10pF or 15pF
Table 14. Crystal Oscillator Parameters
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2011/09
[AK7722]
7. LFLT Pin External Connection
The LFLT pin should be connected a capacitor with the following specification.
CKM Mode
DFS[1:0]
BITFS[1:0]
R
C1
0, 1, 2
0, 1, 2, 3
0, 1, 2
8.2[kΩ]
33[nF]
3, 4
0
0, 1
±5%
±30%
0
2
1, 2
0, 1, 2
C2
None
None or
0.1[nF] ±30%
LFLTpin
R
C2
C1
AVSS
8. SRCLFLT Pin External Connection
The SRCLFLT pin should be connected a capacitor with the following specification.
C
1µF± 30%
MS1328-E-00
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2011/09
[AK7722]
PACKAGE
80pin LQFP (Unit: mm)
1.60 Max.
14.0±0.2
12.0
40
12.0
61
14.0±0.
0.05~0.15
41
60
80
21
20
1
0.5
0.22±0.05
0.09~0.20
0.10 M
1.0
S
0°~10°
0.60±0.15
0.10 S
■ Materials and Lead Specification
Package:
Lead frame:
Lead-finish:
MS1328-E-00
Epoxy
Copper
Soldering (Pb free) plate
- 107 -
2011/09
[AK7722]
MARKING
AK7722VQ
XXXXXXX
1) Pin#1 indication
2) Date Code: XXXXXXX (7 digits)
3) Marking Code: AK7722VQ
REVISION HISTORY
Date (YY/MM/DD)
11/09/09
MS1328-E-00
Revision
00
Reason
First Edition
Page
- 108 -
Contents
2011/09
[AK7722]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this document are
provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible
for the incorporation of these external circuits, application circuits, software and other related information in the design of
your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of
these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in
the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or
strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other
hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with
the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to r
esult, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system conta
ining it, and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to fun
ction or perform may reasonably be expected to result in loss of life or in significant injury or damage to
person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the
product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or
distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims
arising from the use of said product in the absence of such notification.
MS1328-E-00
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2011/09