AK5393 English Datasheet

ASAHI KASEI
[AK5393]
AK5393
Enhanced Dual Bit ∆Σ 96kHz 24-Bit ADC
GENERAL DESCRIPTION
The AK5393 is a 24bit, 128x oversampling 2ch A/D Converter for professional digital audio systems. The
modulator in the AK5393 uses the new developed Enhanced Dual Bit architecture. This new architecture
achieves the wide dynamic range, while keeping much the same superior distortion characteristics as
conventional Single Bit way. The AK5393 performs 117dB dynamic range, so the device is suitable for
professional studio equipment such as digital mixer, digital VTR etc.
FEATURES
p Enhanced Dual Bit ADC
p Sampling Rate: 1kHz~108kHz
p Full Differential Inputs
p S/(N+D): 105dB
p DR: 117dB
p S/N: 117dB
p High Performance Linear Phase Digital Anti-Alias filter
• Passband: 0~21.768kHz(@fs=48kHz)
• Ripple: 0.001dB
• Stopband: 110dB
p Digital HPF & Offset Calibration for Offset Cancel
p Power Supply: 5V±5%(Analog), 3~5.25V(Digital)
p Power Dissipation: 470mW
p Package: 28pin SOP
p AK5392 Pin compatible
SMODE1 SMODE2
12
VREFL
GNDL
VCOML
AINL+
AINLZCAL
AINR+
AINRVCOMR
VREFR
GNDR
1
SCLK
LRCK
FSYNC
14
13
16
11
2
15
Serial Output
Interface
Voltage
Reference
SDATA
3
4
5
6
25
24
Delta-Sigma
Modulator
Decimation
Filter
HPF
Delta-Sigma
Modulator
Decimation
Filter
HPF
19
HPFE
17
18
MCLK
DFS
26
28
27
23
VA
Voltage
Reference
22
AGND
Controller
21
BGND
9
CAL
M0038-E-04
10
RST
Calibration
SRAM
7
VD
8
DGND
2000/4
-1-
ASAHI KASEI
[AK5393]
n Ordering Guide
AK5393-VS
AKD5393
–10 ~ +70°C
28pin SOP
AK5393 Evaluation Board
n Pin Layout
VREFL
1
28
VREFR
GNDL
2
27
GNDR
VCOML
3
26
VCOMR
AINL+
4
25
AINR+
AINL-
5
24
AINR-
ZCAL
6
23
VA
VD
7
22
AGND
DGND
8
21
BGND
CAL
9
20
TEST
RST
10
19
HPFE
SMODE2
11
18
DFS
SMODE1
12
17
MCLK
LRCK
13
16
FSYNC
SCLK
14
15
SDATA
Top
View
n Compatibility with AK5392
Pin 18
fs (max)
MCLK (DFS ="L"@fs=48kHz)
MCLK (DFS ="H"@fs=96kHz)
AK5392
AK5393
CMODE
54kHz
256fs/384fs
N/A
DFS
108kHz
256fs
128fs
M0038-E-04
2000/4
-2-
ASAHI KASEI
[AK5393]
PIN/FUNCTION
No.
Pin Name
I/O
Function
1
VREFL
O
2
GNDL
-
Lch Reference Voltage Pin, 3.75V
Normally connected to GNDL with a 10µF electrolytic capacitor and
a 0.1µF ceramic capacitor.
Lch Reference Ground Pin, 0V
3
4
VCOML
AINL+
O
I
Lch Common Voltage Pin, 2.75V
Lch Analog positive input Pin
5
6
AINLZCAL
I
I
7
VD
-
Lch Analog negative input Pin
Zero Calibration Control Pin
This pin controls the calibration reference signal.
"L" :VCOML and VCOMR
"H" : Analog Input Pins (AINL±, AINR±)
Digital Power Supply Pin, 3.3V
8
9
DGND
CAL
O
10
RST
I
11
12
SMODE2
SMODE1
13
LRCK
I
I
I/O
Digital Ground Pin, 0V
Calibration Active Signal Pin
"H" means the offset calibration cycle is in progress. Offset calibration starts
when RST goes "H". CAL goes "L" after 8704 LRCK cycles for DFS="L",
17408 LRCK cycles for DFS ="H".
Reset Pin
When "L", Digital section is powered-down. Upon returning "H", an
offset calibration cycle is started. An offset calibration cycle should always
be initiated after power-up.
Serial Interface Mode Select Pin
MSB first, 2's compliment.
SMODE2 SMODE1
MODE
LRCK
L
L
Slave mode : MSB justified
: H/L
L
H
Master mode : Similar to I2S
: H/L
H
L
Slave mode : I2S
: L/H
H
H
Master mode : I2S
: L/H
Left/Right Channel Select Clock Pin
LRCK goes "H" at SMODE2="L" and "L" at SMODE2="H" during reset
when SMODE1 "H".
M0038-E-04
2000/4
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ASAHI KASEI
[AK5393]
14
SCLK
I/O
15
SDATA
O
16
FSYNC
I/O
17
MCLK
I
18
DFS
I
19
HPFE
I
20
TEST
I
21
22
23
24
25
26
27
28
BGND
AGND
VA
AINRAINR+
VCOMR
GNDR
VREFR
I
I
O
O
Serial Data Clock Pin
Data is clocked out on the falling edge of SCLK.
Slave mode:
SCLK requires more than 48fs clock.
Master mode:
SCLK outputs a 128fs(DFS="L") or 64fs(DFS="H") clock.
SCLK stays "L" during reset.
Serial Data Output Pin
MSB first, 2's complement. SDATA stays "L" during reset.
Frame Synchronization Signal Pin
Slave mode:
When "H", the data bits are clocked out on SDATA. In I2S mode, FSYNC is
don’t care.
Master mode:
FSYNC outputs 2fs clock. FSYNC stays "L" during reset.
Master Clock Input Pin
256fs at DFS="L", 128fs at DFS="H".
Double Speed Sampling Mode Pin
"L": Normal Speed
"H": Double Speed
High Pass Filter Enable Pin
"L": Disable
"H": Enable
Test Pin (pull-down pin)
Should be connected to GND.
Substrate Ground Pin, 0V
Analog Ground Pin, 0V
Analog Supply Pin, 5V
Rch Analog negative input Pin
Rch Analog positive input Pin
Rch Common Voltage Pin, 2.75V
Rch Reference Ground Pin, 0V
Rch Reference Voltage Pin, 3.75V
Normally connected to GNDR with a 10µF electrolytic capacitor and a 0.1µF
ceramic capacitor
Note: All digital inputs should not be left floating.
M0038-E-04
2000/4
-4-
ASAHI KASEI
[AK5393]
ABSOLUTE MAXIMUM RATINGS
(AGND,BGND,DGND=0V; Note 1)
Parameter
Symbol
min
max
Units
Power Supplies:
Analog
Digital
|BGND-DGND| (Note 2)
Input Current, Any Pin Except Supplies
Analog Input Voltage
VA
VD
∆GND
IIN
VINA
-0.3
-0.3
-0.3
6.0
6.0
0.3
±10
VA+0.3
V
V
V
mA
V
Digital Input Voltage
Ambient Temperature (power applied)
Storage Temperature
VIND
Ta
Tstg
-0.3
-10
-65
VD+0.3
70
150
V
°C
°C
Notes: 1. All voltages with respect to ground.
2. AGND, BGND and DGND must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND,BGND,DGND=0V; Note 1)
min
typ
max
Units
Power Supplies:
Analog
VA
4.75
(Note 3)
Digital
VD
3.0
Notes: 1. All voltages with respect to ground.
3. The power up sequence between VA and VD is not critical.
Parameter
Symbol
5.0
3.3
5.25
5.25
V
V
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
M0038-E-04
2000/4
-5-
ASAHI KASEI
[AK5393]
ANALOG CHARACTERISTICS
(Ta=25°C; VA=5.0V; VD=3.3V; AGND,BGND,DGND=0V; fs=48kHz; Signal Frequency=1kHz;
24bit Output; Measurement frequency=10Hz~20kHz; unless otherwise specified)
Parameter
min
typ
max
Units
Resolution
Analog Input Characteristics:
S/(N+D)
fs=48kHz
24
-1dBFS
-20dBFS
-60dBFS
fs=96kHz
-1dBFS
BW=40kHz
-20dBFS
-60dBFS
Dynamic Range (-60dBFS with A-Weighted )
S/N
( A-Weighted )
Interchannel Isolation
Interchannel Gain Mismatch
Gain Drift
Offset Error
after calibration, HPF=OFF
after calibration, HPF=ON
Offset Drift
(HPF=OFF)
Offset Calibration Range
(HPF=OFF)
98
96
112
112
110
Input Voltage (AIN+)-(AIN-)
Input Impedance
±2.3
2.4
-
Power Supplies
Power Supply Current
VA
VD (fs=48kHz; DFS="L")
(fs=96kHz; DFS="H")
Power Dissipation
Power Supply Rejection
(Note 4)
105
94
54
103
85
45
117
117
120
0.1
±200
±1
±10
±50
0.5
150
±1000
-
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
ppm/°C
LSB24
LSB24
LSB24/°C
mV
±2.45
4
±2.6
V
kΩ
90
6
9
470
70
130
9
14
680
mA
mA
mA
mW
dB
Note: 4. DC to 26kHz. 110dB(typ) beyond 26kHz.
M0038-E-04
2000/4
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ASAHI KASEI
[AK5393]
FILTER CHARACTERISTICS(fs=48kHz)
(Ta=25°C; VA=5.0V±5%; VD=3.0~5.25V; fs=48kHz, DFS="L")
Parameter
Symbol
min
typ
ADC Digital Filter(Decimation LPF):
Passband
(Note 5)
PB
0
Stopband
(Note 5)
SB
26.232
Passband Ripple
PR
Stopband Attenuation
(Note 6)
SA
110
Group Delay Distortion
∆GD
0
Group Delay
(Note 7)
GD
38.7
ADC Digital Filter(HPF):
Frequency response
(Note 5)
-3dB
FR
1.0
-0.1dB
6.5
FILTER CHARACTERISTICS(fs=96kHz)
(Ta=25°C; VA=5.0V±5%; VD=3.0~5.25V; fs=96kHz, DFS="H")
Parameter
Symbol
min
typ
ADC Digital Filter(Decimation LPF):
Passband
(Note 5)
PB
0
Stopband
(Note 5)
SB
52.464
Passband Ripple
PR
Stopband Attenuation
(Note 8)
SA
110
Group Delay Distortion
∆GD
0
Group Delay
(Note 7)
GD
38.8
ADC Digital Filter(HPF):
Frequency response
(Note 5)
-3dB
-0.1dB
FR
2.0
13.0
max
Units
21.768
kHz
kHz
dB
dB
us
1/fs
±0.001
Hz
Hz
max
Units
43.536
kHz
kHz
dB
dB
us
1/fs
±0.003
Hz
Hz
Notes: 5. The passband and stopband frequencies scale with fs.
6. The analog modulator samples the input at 6.144MHz for an output word rate of 48kHz.
There is no rejection of input signals which are multiples of the sampling frequency
(that is: there is no rejection for n x 6.144MHz ± 21.768kHz, where n=1,2,3···).
7. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal
to setting the 24bit data of both channels to the output register.
40.7/fs(DFS="L"),40.8/fs(DFS="H")typ. at HPF:ON.
8. The analog modulator samples the input at 6.144MHz for an output word rate of 96kHz.
There is no rejection of input signals which are multiples of the sampling frequency
(that is: there is no rejection for n x 6.144MHz ± 43.536kHz, where n=1,2,3···).
M0038-E-04
2000/4
-7-
ASAHI KASEI
[AK5393]
DIGITAL CHARACTERISTICS
(Ta=25°C; VA=5.0V±5%; VD=3.0 ~ 5.25V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%VD
Low-Level Input Voltage
VIL
High-Level Output Voltage Iout=-20µA
VOH
VD-0.1
Low-Level Output Voltage Iout=20µA
VOL
Input Leakage Current
Iin
-
typ
-
max
30%VD
0.1
±10
Units
V
V
V
V
µA
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=5.0V±5%; VD=3.0 ~ 5.25V; CL=20pF)
Parameter
Control Clock Frequency
Master Clock
256fs:
Pulse width Low
Pulse width High
Serial Data Output Clock (SCLK)
Channel Select Clock (LRCK)
duty cycle
Serial Interface Timing
(Note 9)
Slave Mode(SMODE1="L")
SCLK Period
SCLK Pulse width Low
Pulse width High
SCLK falling to LRCK Edge
(Note 10)
LRCK Edge to SDATA MSB Valid
SCLK falling to SDATA Valid
SCLK falling to FSYNC Edge
Master Mode(SMODE1="H")
SCLK Frequency (DFS="L")
SCLK Frequency (DFS="H")
duty cycle
FSYNC Frequency
duty cycle
SCLK falling to LRCK Edge
LRCK Edge to FSYNC rising
SCLK falling to SDATA Valid
SCLK falling to FSYNC Edge
Reset/Calibration timing
RST Pulse width
RST falling to CAL rising
RST rising to CAL falling (Note 11)
RST rising to SDATA Valid (Note 11)
Symbol
min
typ
max
Units
fCLK
tCLKL
tCLKH
fSLK
fs
0.256
29
29
12.288
13.824
6.144
48
6.912
108
75
MHz
ns
ns
MHz
kHz
%
tSLK
tSLKL
tSLKH
tSLR
tDLR
tDSS
tSF
144.7
65
65
-45
45
45
45
45
ns
ns
ns
ns
ns
ns
ns
1
25
-45
128fs
64fs
50
2fs
50
fSLK
fSLK
fFSYNC
tSLR
tLRF
tDSS
tSF
-20
tRTW
tRCR
tRCF
tRTV
150
20
1
45
20
-20
50
8704
8960
Hz
Hz
%
Hz
%
ns
tslk
ns
ns
ns
ns
1/fs
1/fs
Notes: 9. Refer to Serial Data interface.
10. Specified LRCK edges not to coincide with the rising edges of SCLK.
11. The number of the LRCK rising edges after RST brought high at DFS="L". The value is in master mode.
In slave mode it becomes one LRCK clock(1/fs) longer. When DFS="H", tRCF=17408 and tRTV=17920.
M0038-E-04
2000/4
-8-
ASAHI KASEI
[AK5393]
n Timing Diagram
tSLK
LRCK
tSLKL
tSLKH
tSLR
SCLK
tDSS
tDLR
MSB
SDATA
MSB-1
MSB-2
Serial Data Timing (Slave Mode, FSYNC="H")
LRCK
tSLR
SCLK
tSF
tSF
FSYNC
tDSS
tDLR
MSB
SDATA
D1
D0
Serial Data Timing (Slave Mode)
tSLK
LRCK
tSLKL
tSLKH
tSLR
SCLK
tDSS
MSB
SDATA
tDSS
MSB-1
Serial Data Timing (I2S Slave Mode, FSYNC = Don't Care)
M0038-E-04
2000/4
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ASAHI KASEI
[AK5393]
LRCK
tSLR
SCLK
tSF
FSYNC
tSF
tLRF
tDSS
SDATA
MSB
MSB-1
Serial Data Timing (Master Mode & I2S Master Mode, DFS ="L")
tRTW
tRTV
RST
tRCF
CAL
tRCR
SDATA
Reset & Calibration Timing
M0038-E-04
2000/4
- 10 -
ASAHI KASEI
[AK5393]
OPERATION OVERVIEW
n System Clock Input
The external clocks which are required to operate the AK5393 are MCLK, LRCK(fs), SCLK. MCLK should be
synchronized with LRCK but the phase is free of care. MCLK should be 256fs in normal sampling mode(DFS="L") and
double sampling mode needs 128fs as MCLK. Table 2 illustrates standard audio word rates and corresponding frequencies
used in the AK5393.
As the AK5393 includes the phase detect circuit for LRCK, the AK5393 is reset automatically when the synchronization
is out of phase by changing the clock frequencies. Therefore, the reset is only needed for power-up.
All external clocks must be present unless RST ="L", otherwise excessive current may result from abnormal operation of
internal dynamic logic.
Speed
Normal(DFS ="L")
Double(DFS ="H")
54kHz
~128fs
256fs
108kHz
~64fs
128fs
LRCK (max)
SCLK
MCLK
Table 1. System Clocks
fs
MCLK
SCLK
32.0kHz
44.1kHz
48.0kHz
96.0kHz
8.1920MHz
11.2896MHz
12.2880MHz
12.2880MHz
4.0960MHz
5.6448MHz
6.1440MHz
6.1440MHz
Table 2. Examples of System Clock Frequency
n Serial Data Interface
The AK5393 supports four serial data formats which can be selected via SMODE1 and SMODE2 pins(Table 3). The data
format is MSB-first, 2's complement.
Figure
Figure 1
Figure 2
Figure 3
Figure 4
SMODE2
L
L
H
H
SMODE1 Mode
L
H
L
H
Slave Mode
Master Mode
I2S Slave Mode
I2S Master Mode
LRCK
Lch = H, Rch =L
Lch =H, Rch =L
Lch =L, Rch =H
Lch =L, Rch =H
Table 3. Serial I/F Format
M0038-E-04
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ASAHI KASEI
[AK5393]
LRCK(i)
0
1
2
3
20
21
22
23
24
25
15
0
1
2
3
20
21
22
23
24
25
0
1
SCLK(i)
FSYNC(i)
SDATA(o)
23 22 21
4
3
2
0
1
23 22
21
7
4 3
Lch Data
2
1
0
23
2
1
24
25
22
Rch Data
FSYNC(i)
SDATA(o)
23
22
5
4
3
2
1
0
23
22
5
4
3
0
23
23:MSB,0:LSB
Figure 1. Serial Data Timing (Slave Mode)
LRCK(o)
0
1
2
3
20
21
22
23
24
25
15
33
34
0
1
2
3
20
21
22
23
33
34
0
1
SCLK(o)
FSYNC(o)
SDATA(o)
23 22
5
4
3
1
2
0
23 22
5
4
3
2
1
0
23
Rch Data
Lch Data
23:MSB,0:LSB
Figure 2. Serial Data Timing (Master mode, DFS="L")
LRCK(i)
0
1
2
3
19
20
21
22
23
24
0
1
2
3
19
20
21
22
23
24
0
1
SCLK(i)
SDATA(o)
23 22
6
5
4
3
2
1
0
23
22
6
5
4
3
2
1
0
23
Rch Data
Lch Data
23:MSB,0:LSB
Figure 3. Serial Data Timing (I2S Slave mode, FSYNC: Don’t care.)
LRCK(o)
0
1
2
3
20
21
22
23
24
25
15
33
34
0
1
2
3
20
21
22
23
24
25
33
34
0
1
SCLK(o)
FSYNC(o)
SDATA(o)
23 22
5
4
3
2
1
0
23
Lch Data
23 22
5
4
3
2
1
0
23
Rch Data
23:MSB,0:LSB
Figure 4. Serial Data Timing (I2S Master mode, DFS="L")
M0038-E-04
2000/4
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ASAHI KASEI
[AK5393]
n Offset Calibration
When RST pin goes to "L", the digital section is powered-down. Upon returning "H", an offset calibration cycle is
started. An offset calibration cycle should always be initiated after power-up.
During the offset calibration cycle, the digital section of the part measures and stores the values of calibration input of each
channel in registers. The calibration input value is subtracted from all future outputs. The calibration input may be
obtained from either the analog input pins (AIN+/-) or the VCOM pins depending on the state of the ZCAL pin. With
ZCAL "H", the analog input pin voltages are measured, and with ZCAL "L", the VCOM pin voltages are measured. The
CAL output is "H" during calibration.
n Digital High Pass Filter
The AK5393 also has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 1Hz at fs=48kHz
and also scales with sampling rate(fs).
M0038-E-04
2000/4
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ASAHI KASEI
[AK5393]
SYSTEM DESIGN
Figure 5 and 6 show the system connection diagram. An evaluation board[AKD5393] is available which demonstrates
the optimum layout, power supply arrangements and measurement results.
10µ 0.1µ
+
1
VREFL
VREFR
28
2
GNDL
GNDR
27
3
VCOML
VCOMR
26
Lch+
4
AINL+
AINR+
25
Rch+
Lch-
5
AINL-
AINR-
24
Rch-
6
ZCAL
VA
23
0.22µ
+3.3~5V
Digital
+
0.1µ
10µ
0.22µ
AK5393
0.1µ
+
10µ
7
VD
AGND
8
DGND
BGND
21
9
CAL
TEST
20
HPFE
19
+5V
Analog
+
10µ
22
0.1µ
Reset &
Cal Control
10
RST
Mode
11
SMODE2
DFS
18
Select
12
SMODE1
MCLK
17
13
LRCK
FSYNC
16
SCLK
SDATA
15
fs
System
Controller
14
[email protected]=48k
System Ground
Analog Ground
Figure 5. Typical Connection Diagram
Notes:
- LRCK = fs, SCLK=64fs.
- Power lines of VA and VD should be distributed separately from the point
with low impedance of regulator etc.
- GND, BGND and DGND must be connected to the same analog ground plane.
- All input pins except pull-down/pull-up pins should not be left floating.
Digital Ground
Analog Ground
System
Controller
1
VREFL
VREFR
28
2
GNDL
GNDR
27
3
VCOML
VCOMR
26
4
AINL+
AINR+
25
5
AINL-
AINR-
24
6
ZCAL
VA
23
7
VD
AGND
22
8
DGND
BGND
21
9
CAL
TEST
20
HPFE
19
10
RST
AK5393
11
SMODE2
DFS
18
12
SMODE1
MCLK
17
13
LRCK
FSYNC
16
14
SCLK
SDATA
15
Figure 6 Ground layout
M0038-E-04
2000/4
- 14 -
ASAHI KASEI
[AK5393]
1. Grounding and Power Supply Decoupling
The AK5393 requires careful attention to power supply and grounding arrangements. Analog ground and digital ground
should be separate and connected together near to where the supplies are brought onto the printed circuit board.
Decoupling capacitors should be as near to the AK5393 as possible, with the small value ceramic capacitor being the
nearest.
2. On-chip voltage reference and VCOM
The reference voltage for A/D converter is a differential voltage between the VREFL/R output voltage and the GNDL/R
input voltage. The GNDL/R are connected to AGND and a 10µF electrolytic capacitor parallel with a 0.1µF ceramic
capacitor between the VREFL/R and the GNDL/R eliminate the effects of high frequency noise. Especially a ceramic
capacitor should be as near to the pins as possible. And all digital signals, especially clocks, should be kept away from the
VREFL/R pins in order to avoid unwanted coupling into the AK5393. No load current may be taken from the VREFL/R
pins.
VCOM is a common voltage of the analog signal. In order to eliminate the effects of high frequency noise, a 0.22µF
ceramic capacitor should be connected as near to the VCOM pin as possible. And all signals, especially clocks, should be
kept away from the VCOM pin in order to avoid unwanted coupling into the AK5393. No load current may be drawn from
the VCOM pin.
3. Analog Inputs
Analog signal is differentially input into the modulator via the AIN+ and the AIN- pins. The input voltage is the difference
between AIN+ and AIN- pins. The full-scale of each pin is nominally ± 2.45Vpp(typ). The AK5393 can accept input
voltages from AGND to VA. The ADC output data format is 2's complement. The output code is 7FFFFFH(@24bit) for
input above a positive full scale and 800000H(@24bit) for input below a negative full scale. The ideal code is 000000H
(@24bit) with no input signal. The DC offset is removed by the offset calibration.
The AK5393 samples the analog inputs at 128fs(6.144MHz @fs=48kHz,DFS="L"). The digital filter rejects noise above
the stop band except for multiples of 128fs. A simple RC filter may be used to attenuate any noise around 128fs and most
audio signals do not have significant energy at 128fs.
The AK5393 accepts +5V supply voltage. Any voltage which exceeds the upper limit of VA+0.3V and lower limit of
AGND-0.3V and any current beyond 10mA for the analog input pins(AIN+ /-) should be avoided. Excessive currents to the
input pins may damage the device. Hence input pins must be protected from signals at or beyond these limits. Use caution
specially in case of using ±15V in other analog circuits.
M0038-E-04
2000/4
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ASAHI KASEI
[AK5393]
Figure 7shows an input buffer circuit example 1. This is a full-differential input buffer circuit with an inverted-amp
(gain :-10dB). The capacitor of 10nF between AIN+ /- decreases the clock feed through noise of modulator, and composes
a 1st order LPF(fc=360kHz) with 22ohm resistor before the capacitor. This circuit also has a 1st order LPF(fc=370kHz)
composed of op-amp. In this example, the internal offset is removed by self calibration. The evaluation board should be
referred about the detail.
910
4.7k
4.7k
Analog In
VP+
+
8.1Vpp
AK5393
470p
47µ
3k
Bias
VP-
22
+
2.45Vpp
AIN+
910
NJM5532
10n
470p
47µ
3k
VA+
22
-
VA=±5V
AIN-
+
VP=±15V
10k
Bias
Bias
2.45Vpp
CAL
+
10k
0.1 µ
10µ
"L" at self calibration
ZCAL
Figure 7 Differential Input Buffer Example 1
Figure 8 shows an input buffer circuit example 2. (1st order HPF; fc=0.66Hz, Table 4, 1st order LPF; fc=590kHz, gain=14dB, Table 5). The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2 for BNC input, open
JP1 and JP2 for XLR input). The input level of this circuit is +/-12.4Vpp (AK5393: +/-2.45Vpp Typ.).
12.4Vpp
BNC
JP1
22u
Vin+
1k
180
-
AK5393 AIN+
+
2.45Vpp
NJM5534
VA
10k
XLR
4.7k
0.1u
4.7k
4.7k
4.7k
10u
NJM5534
180
-
2.45Vpp
+
Vin-
+
100
10k
JP2
-
1.5n
Bias
22u
12.4Vpp
1k
NJM5534
AK5393 AIN-
Figure 8 Differential Input Buffer Example 2
fin
1Hz
10Hz
Frequency Response
-1.56dB
-0.02dB
Table 4. Frequency Response of HPF
fin
Frequency Response
20kHz
-0.005dB
40kHz
-0.02dB
6.144MHz
-15.6dB
Table 5. Frequency Response of LPF
M0038-E-04
2000/4
- 16 -
ASAHI KASEI
[AK5393]
PACKAGE
1.095TYP
18.7±0.3
2.2 ± 0.1
+0.1
0.15-0.05
+0.1
0.1-0.05
1.27
0.75 ± 0.2
10.4 ± 0.3
7.5 ± 0.2
28pin SOP (Unit: mm)
0.10
0.4±0.1
0.12 M
0-10°
n Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder plate
M0038-E-04
2000/4
- 17 -
ASAHI KASEI
[AK5393]
MARKING
AKM JAPAN
AK5393VS
XXXBYYYYC
Contents of XXXBYYYYC
XXXB:
YYYYC:
Lot # (X : numbers, B : alphabet )
Data Code (Y : numbers, C : alphabet)
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application
or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support,
or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except
with the express written consent of the Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function
or perform may reasonably be expected to result in loss of life or in significant injury or damage to person
or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing
it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise
places the product with a third party to notify that party in advance of the above content and conditions, and
the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless
from any and all claims arising from the use of said product in the absence of such notification.
M0038-E-04
2000/4
- 18 -