Data Sheet

[AK4120]
AK4120
Sample Rate Converter with Mixer and Volume
GENERAL DESCRIPTION
The AK4120 is a stereo asynchronous sample rate converter. The input sample rate range is from 8kHz
to 48kHz. The output sample rate is fixed at 32kHz, 44.1kHz, 48kHz or 96kHz. AK4120 includes a
digital mixer and digital volume control. Applications for this device include pro audio mastering,
consumer format conversion and desktop audio production and playback.
FEATURES
† Stereo Asynchronous Sample Rate Converter
† Digital Mixer
† Digital Volume
† Input Sample Rate Range (FSI): 8kHz to 48kHz
† Output Sample Rate (FSO): 32kHz, 44.1kHz, 48kHz and 96kHz
† Input to Output Sample Rate Ratio: FSO/FSI = 0.667 to 6
† THD+N: –113dB at 1kHz input
† I/F format: MSB justified (20bit), LSB justified (16bit/20bit), I2S
† Master clock: 256/512fs
† 3-wire Serial or I2C Bus µP I/F for mode setting
† Power Supply: 2.7 to 3.6V
I2C
SDTI1
ILRCK1
I2S
PDN
VDD
Input#1
Audio
I/F
Sample
Rate
Converter
VSS
Volume#1
TEST
IBICK1
IMCLK1
OMCLK
IMCLK2
SDTI2
ILRCK2
Input#2
Audio
I/F
Volume#2
Output
Audio
I/F
IBICK2
SDTO
OLRCK
OBICK
μ P I/F
I2MODE
CAD0
CSN/CAD1 CCLK/SDL CDTI/SDA
MS0134-E-01
OMODE
2008/06
-1-
[AK4120]
■ Ordering Guide
AK4120VF
AKD4120
-40 ∼ +85°C
24pin VSOP (0.65mm pitch)
Evaluation Board for AK4120
■ Pin Layout
IMCLK1
1
24
IMCLK2
SDTI1
2
23
SDTI2
IBICK1
3
22
IBICK2
ILRCK1
4
21
ILRCK2
TEST
5
20
I2MODE
I2S
6
19
VDD
I2C
7
18
VSS
CAD0
8
17
OMODE
CSN/CAD1
9
16
OMCLK
CCLK/SCL
10
15
SDTO
CDTI/SDA
11
14
OBICK
PDN
12
13
OLRCK
Top
View
MS0134-E-01
2008/06
-2-
[AK4120]
PIN/FUNCTION
No.
1
2
3
Pin Name
IMCLK1
SDTI1
IBICK1
I/O
I
I
I
4
ILRCK1
I
L/R Clock Pin for Input#1
5
TEST
I
6
I2S
I
7
8
I2C
CAD0
CSN
CAD1
I
I
I
I
CCLK
I
SCL
I
CDTI
I
SDA
I/O
12
PDN
I
13
14
15
16
OLRCK
OBICK
SDTO
OMCLK
I/O
I/O
O
I
17
OMODE
I
18
19
VSS
VDD
I
I
20
I2MODE
I
21
22
23
24
ILRCK2
IBICK2
SDTI2
IMCLK2
I/O
I/O
I
I
Test Pin. Connect to VSS.
Audio I/F Select Pin
“L”: Set by Register, “H”: I2S
2
I C Select Pin. “L”: 3-wire, “H”: I2C
Chip Address 0 Pin
Chip Select Pin in 3wire serial control mode in 3-wire Serial Control Mode.
Chip Address 1 Pin in I2C control mode.
Control Data Clock Pin in 3wire serial control mode in 3-wire Serial Control
Mode.
Control Data Clock Pin in I2C control mode.
Control Data Input Pin in 3wire serial control mode in 3-wire Serial Control
Mode.
Control Data Pin in I2C serial control mode in I2C control mode.
Power-Down pin
When “L”, the AK4120 is powered-down and reset.
L/R Clock Pin for Output
Audio Serial Data Clock Pin for Output
Audio Serial Data Pin for Output
Master Clock Pin for Output
Master/Slave select pin for Output Audio Data
“L”: Slave,
“H”: Master
Digital Ground Pin
Digital Power Supply Pin, 3.3V
Master/Slave select pin for Input Audio Data #2
“L”: Slave,
“H”: Master
L/R Clock Pin for Input#2
Audio Serial Data Clock Pin for Input#2
Audio Serial Data Input Pin for Input#2
Master Clock Input Pin for Input#2
9
10
11
Function
Master Clock Input Pin for Input#1
Audio Serial Data Input Pin for Input#1
Audio Serial Data Clock Pin for Input#1
MS0134-E-01
2008/06
-3-
[AK4120]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter
Power Supplies
Input Current, Any Pin Except Supplies
Input Voltage
Ambient Temperature (Power applied)
Storage Temperature
Symbol
VDD
min
-0.3
max
4.6
Units
V
IIN
VIN
Ta
Tstg
-0.3
-40
-65
±10
VDD+0.3
85
150
mA
V
°C
°C
Note 1: All voltages with respect to ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 2)
Parameter
Symbol
min
typ
Power Supplies
VDD
2.7
3.3
Note 2: All voltages with respect to ground.
max
3.6
Units
V
WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
SRC PERFORMANCE
(Ta=-40∼ 85°C; VDD = 2.7∼3.6V; data = 20bit; measurement bandwidth = 20Hz~ FSO/2; unless otherwise specified.)
Parameter
Symbol
min
typ
max
Units
Resolution
20
Bits
Input Sample Rate (Note 3)
FSI
8
48
kHz
Output Sample Rate (Note 4)
FSO
32
96
kHz
Dynamic Range (Input= 1kHz, -60dBFS, Note 5)
dB
115
FSO/FSI=44.1kHz/48kHz
dB
116
FSO/FSI=48kHz/44.1kHz
dB
114
FSO/FSI=32kHz/48kHz
dB
119
FSO/FSI=96kHz/32kHz
dB
112
Worst Case (FSO/FSI=32kHz/48kHz)
Dynamic Range (Input= 1kHz, -60dBFS, A-weighted, Note 5)
dB
117
FSO/FSI=44.1kHz/48kHz
THD+N
(Input= 1kHz, 0dBFS, Note 5)
FSO/FSI=44.1kHz/48kHz
-112
dB
FSO/FSI=48kHz/44.1kHz
-113
dB
FSO/FSI=32kHz/48kHz
-111
dB
FSO/FSI=96kHz/32kHz
-111
dB
Worst Case (FSO/FSI=48kHz/8kHz)
-103
dB
Ratio between Input and Output Sample Rate
FSO/FSI
(FSO/FSI, Note 6, Note 7)
0.667
6
Note 3. 32kHz~96kHz for INPUT#2 at Path Mode 0. 8kHz~96kHz at Path Mode 2 and 3.
Note 4. Min = 8kHz at Path Mode 2 and 3.
Note 5. Measured by Rohde & Schwarz UPD04, Rejection Filter= wide, 8192point FFT. Refer Figure 1 and Figure 2.
Note 6. The “0.667” is the ratio of FSO/FSI when FSI is 48kHz and FSO is 32kHz
Note 7. The “6” is the ratio when FSI is 8kHz and FSO is 48kHz.
MS0134-E-01
2008/06
-4-
[AK4120]
THD+N [dB]
-101
-103
-105
-107
-109
-111
-113
-115
32
37
42
47
FSI [kHz]
Figure 1: Input Sample Rate (FSI) vs. THD+N (FSO=48kHz)
-80
-85
THD+N [dB]
-90
-95
-100
-105
-110
-115
-120
10
100
1000
10000
100000
Input Frequency [Hz]
Figure 2: Input Frequency vs. THD+N (FSI=44.1kHz, FSO=48kHz)
MS0134-E-01
2008/06
-5-
[AK4120]
DIGITAL FILTER
(Ta=-40∼ 85°C; VDD=2.7∼3.6V; FSO=FSI=fs)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 8)
-0.001dB
PB
0
0.4583fs
kHz
Stopband
(Note 8)
SB
0.5417fs
kHz
Passband Ripple
PR
dB
± 0.01
Stopband Attenuation
SA
97
dB
Group Delay
(Note 9)
GD
56.5
1/fs
Note 8. The passband and stopband frequencies scale with fs (system sampling rate).
Note 9. This value is the time from the rising edge of LRCK after data is input to rising edge of LRCK after data is
output, when LRCK for Output data corresponds with LRCK for Input.(at 20bit MSB justified, 16bit and 20bit
LSB justified)
DC CHARACTERISTICS
(Ta=-40∼85°C; VDD=2.7~3.6V)
Parameter
Symbol
min
Power Supply Current
Normal operation: (PDN = “H”, Path Mode 0)
FSI=FSO=48kHz at Slave Mode
(I2MODE= OMODE = “L”): VDD=3.3V
FSI=48kHz,FSO=96kHz at Master Mode
(I2MODE=OMODE= “H”) : VDD=3.3V
: VDD=3.6V
Power down: PDN = “L”
(Note 10)
High-Level Input Voltage
VIH
0.7xVDD
Low-Level Input Voltage
VIL
VOH
High-Level Output Voltage
(Iout=-400μA)
Low-Level Output Voltage
VOL
(Except SDA pin: Iout=400μA);
VOL
(
SDA pin: Iout= 3mA)
Input Leakage Current
Iin
Note 10. All digital inputs including clock pins are held VSS.
MS0134-E-01
typ
Max
Units
8.5
-
mA
10.2
11.5
10
-
20
100
0.3xVDD
mA
mA
μA
V
V
VDD-0.4
-
-
V
-
-
0.4
0.4
± 10
V
V
μA
2008/06
-6-
[AK4120]
SWITCHING CHARACTERISTICS
(Ta=-40∼ 85°C; VDD=2.7~3.6V; CL=20pF)
Parameter
Symbol
min
Master Clock Input (IMCLK1)
2.048
Frequency
fCLK
40
Duty Cycle (at FSI > 33kHz)
dCLK
28
dCLK
Duty Cycle (at FSI ≤ 33kHz)
Master Clock Input (IMCLK2)
2.048
fCLK
Frequency
40
dCLK
Duty Cycle (at FSI > 33kHz)
28
dCLK
Duty Cycle (at FSI ≤ 33kHz)
Master Clock Input (OMCLK)
8.192
fCLK
Frequency (Note 11)
40
dCLK
Duty Cycle (at FSI > 33kHz)
28
dCLK
Duty Cycle (at FSI ≤ 33kHz)
L/R clock for Input data #1 (ILRCK1)
Frequency
fs
8
Duty Cycle
Duty
48
L/R clock for Input data #2 (ILRCK2)
Frequency
(Note 12)
fs
8
Duty Cycle
Slave Mode
Duty
48
Master Mode
Duty
L/R clock for Output data (OLRCK)
Frequency
(Note 13)
fs
32
Duty Cycle
Slave Mode
Duty
48
Master Mode
Duty
Audio Interface Timing
(Note 14)
Input#1 at Path Mode 0 and 2
Input#2 (Slave Mode) at Path Mode 1
325
tBCK
BICK Period
130
tBCKL
BICK Pulse Width Low
130
tBCKH
BICK Pulse Width High
45
tBLR
LRCK Edge to BICK “↑” (Note 15)
45
tLRB
BICK “↑” to LRCK Edge (Note 15)
40
tSDH
SDTI1-2, Hold Time from BICK “↑”
25
tSDS
SDTI1-2, Setup Time to BICK “↑”
Input#2 (Slave Mode) at Path Mode 0 and 3
BICK Period
tBCK
162
BICK Pulse Width Low
tBCKL
65
BICK Pulse Width High
tBCKH
65
tBLR
45
LRCK Edge to BICK “↑” (Note 15)
tLRB
45
BICK “↑” to LRCK Edge (Note 15)
tSDH
40
SDTI2, Hold Time from BICK “↑”
tSDS
25
SDTI2, Setup Time to BICK “↑”
Output (Slave Mode)
tBCK
162
OBICK Period
tBCKL
65
OBICK Pulse Width Low
tBCKH
65
OBICK Pulse Width High
tBLR
45
OLRCK Edge to OBICK “↑” (Note 15)
tLRB
45
OBICK “↑” to OLRCK Edge (Note 15)
tLRS
OLRCK to SDTO (MSB)
tBSD
OBICK “↓” to SDTO
MS0134-E-01
typ
50
50
50
50
50
max
Units
24.576
60
72
MHz
%
%
24.576
60
72
MHz
%
%
24.576
60
72
MHz
%
%
48
52
kHz
%
96
52
kHz
%
%
96
52
kHz
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
40
ns
ns
ns
ns
ns
ns
ns
2008/06
-7-
[AK4120]
Parameter
Symbol
min
Audio Interface Timing
Input#2(Master Mode) at Path Mode 1
BICK Frequency
fBCK
BICK Duty
dBCK
BICK “↓” to LRCK
−25
tMBLR
tBSD
BICK “↓” to SDTO
−25
tSDH
50
SDTI2 Hold Time from BICK “↑”
tSDS
50
SDTI2 Setup Time to BICK “↑”
Input#2 (Master Mode) at Path Mode0 and 3
Output (Master Mode)
fBCK
BICK Frequency
dBCK
BICK Duty
tMBLR
−20
BICK “↓” to LRCK
tBSD
−20
BICK “↓” to SDTO
tSDH
40
SDTI2 Hold Time from BICK “↑”
tSDS
25
SDTI2 Setup Time to BICK “↑”
Note 11. Min is 2.048MHz at Path Mode 2 and 3.
Note 12. Max is 48kHz at Path Mode 1
Note 13. Min is 8kHz at Path Mode 2 and 3.
Note 14. BICK means all audio serial data clocks (IBICK1, IBICK2 and OBICK).
LRCK means all L/R clocks (ILRCK1, ILRCK2 and OLRCK).
Note 15. BICK rising edge must not occur at the same time as LRCK edge.
MS0134-E-01
typ
max
Units
25
40
Hz
%
ns
ns
ns
ns
20
30
Hz
%
ns
ns
ns
ns
64fs
50
64fs
50
2008/06
-8-
[AK4120]
Parameter
Symbol
min
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
tCSS
50
CSN “↓” to CCLK “↑”
tCSH
50
CCLK “↑” to CSN “↑”
Control Interface Timing (I2C® Bus mode):
fSCL
SCL Clock Frequency
4.7
tBUF
Bus Free Time Between Transmissions
4.0
tHD:STA
Start Condition Hold Time (prior to first clock pulse)
4.7
tLOW
Clock Low Time
4.0
tHIGH
Clock High Time
4.7
tSU:STA
Setup Time for Repeated Start Condition
0
tHD:DAT
SDA Hold Time from SCL Falling
(Note 16)
0.25
tSU:DAT
SDA Setup Time to SCL Rising
tR
Rise Time of Both SDA and SCL Lines
tF
Fall Time of Both SDA and SCL Lines
4.0
tSU:STO
Setup Time for Stop Condition
tSP
Maximum Pulse Width of Spike Noise Suppressed by
Input Filter
Power-down & Reset Timing
PDN Pulse Width
(Note 17)
tPD
150
Note 16. Data must be held long enough to bridge the 300 ns transition time of SCL.
Note 17. The AK4120 can be reset by bringing the PDN pin “L” upon power-up.
Note 18. I2C is a registered trademark of Philips Semiconductors.
MS0134-E-01
typ
max
Units
ns
ns
ns
ns
ns
ns
ns
ns
100
1.0
0.3
30
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
2008/06
-9-
[AK4120]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tLRS
tBSD
70%VDD
SDTO
30%VDD
tSDS
tSDH
VIH
SDTI
VIL
Audio Interface Timing at Slave Mode
Note: MCLK means IMCLK1, IMCLK2 and OCLK.
BICK means IBICK1,IBICK2 and OBICK.
LRCK means ILRCK1,ILRCK2 and OLRCK.
SDTI means SDTI1 and SDTI2.
MS0134-E-01
2008/06
- 10 -
[AK4120]
LRCK
50%VDD
tMBLR
dBCK
50%VDD
BICK
tBSD
50%VDD
SDTO
tSDS
tSDH
VIH
VIL
SDTI
Audio Interface Timing at Master Mode
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
C1
CDTI
tCDH
C0
R/W
VIH
A4
VIL
WRITE Command Input Timing (3-wire Serial mode)
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
WRITE Data Input Timing (3-wire Serial mode)
MS0134-E-01
2008/06
- 11 -
[AK4120]
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
2
I C Bus mode Timing
tPD
VIH
PDN
VIL
tPDV
70%VDD
SDTO
30%VDD
Power-down & Reset Timing
MS0134-E-01
2008/06
- 12 -
[AK4120]
OPERATION OVERVIEW
■ I/O Data flow
The AK4120 has two input audio data interfaces (Input#1 and Input#2). The AK4120 has four modes of operation, each
corresponding to a different internal audio path as shown in Table 1. These path modes are selected by the PATH1-0
bits.
Path Mode
0
(see Figure 3)
PATH1-0 bits
“00”
1
(see Figure 4)
“01”
2
(see Figure 5)
3
(see Figure 6)
“10”
“11”
Output Data
The sample rate of Input#1 data is converted by SRC block. This converted
data paths through Volume#1 and Input#2 data is paths through Volume#2.
These data are mixed and this mixed data is output. The sample rata of
Input#1 is defined by IMCLK1 and the sample rate of Output data is
defined by OMCLK. The sample rate of Input#2 should be same as Output
data.
The sample rate of Input#2 data is converted by SRC block. This converted
data volume is controlled by Volume#1 and this data is output. The sample
rata of Input#2 is defined by IMCLK2 and the sample rate of Output data is
defined by OMCLK.
Input#1 data paths through Volume#2 and is output. Output data should
synchronous with IMCLK.
Input#2 data paths through Volume#2 and is output. Input#2 should
synchronous with OMCLK.
Table 1. Path Mode
Note: When Path Mode is changed, the AK4120 should be powered down using the “PW” bit
MS0134-E-01
2008/06
- 13 -
[AK4120]
I2C
SDTI1
ILRCK1
I2S
PDN
VDD
Input#1
Audio
I/F
Sample
Rate
Converter
VSS
Volume#1
TEST
IBICK1
IMCLK1
OMCLK
IMCLK2
SDTI2
ILRCK2
Input#2
Audio
I/F
Output
Audio
I/F
Volume#2
IBICK2
SDTO
OLRCK
OBICK
μ P I/F
I2MODE
CAD0
CSN/CAD1 CCLK/SDL CDTI/SDA
OMODE
Figure 3. Path Mode 0 (Input#1 SRC + Mixer)
I2C
I2S
PDN
VDD
SDTI1
Sample
Rate
Converter
ILRCK1
VSS
Volume#1
TEST
IBICK1
IMCLK1
OMCLK
IMCLK2
SDTI2
ILRCK2
Input#2
Audio
I/F
Output
Audio
I/F
IBICK2
SDTO
OLRCK
OBICK
μ P I/F
I2MODE
CAD0
CSN/CAD1 CCLK/SDL CDTI/SDA
OMODE
Figure 4. Path Mode 1 (Input#2 SRC)
MS0134-E-01
2008/06
- 14 -
[AK4120]
I2C
SDTI1
ILRCK1
I2S
PDN
VDD
Input#1
Audio
I/F
VSS
TEST
IBICK1
IMCLK1
OMCLK
IMCLK2
SDTI2
ILRCK2
Input#2
Audio
I/F
Output
Audio
I/F
Volume#2
IBICK2
SDTO
OLRCK
OBICK
μ P I/F
I2MODE
CAD0
CSN/CAD1 CCLK/SDL CDTI/SDA
OMODE
Figure 5. Path Mode 2 (Input#1 through output)
I2C
I2S
PDN
VDD
SDTI1
VSS
ILRCK1
TEST
IBICK1
IMCLK1
OMCLK
IMCLK2
SDTI2
ILRCK2
Input#2
Audio
I/F
Volume#2
Output
Audio
I/F
IBICK2
SDTO
OLRCK
OBICK
μ P I/F
I2MODE
CAD0
CSN/CAD1 CCLK/SDL CDTI/SDA
OMODE
Figure 6. Path Mode 3 (Input#2 through output)
MS0134-E-01
2008/06
- 15 -
[AK4120]
■ System Clock
The external clocks required to operate the AK4120 in each mode are shown in Table 3 and Table 4. The Input#1 port
works in slave mode only. The Input#2 and Output ports have both slave and master modes that are selected by the
IMODE2 and OMODE pins. The required external clock shown in Table 2 should be always present whenever the
AK4120 is in a normal operating mode (PDN pin= “H”).
Path Mode
0
1
2
3
Synchronizing
SRC
Synchronizing
Group A
Group B
SDTI1
Active
SDTI2, SDTO
SDTI2
Active
SDTO
SDTI1, SDTO
(Not used)
SDTI2, SDTO
(Not used)
Table 2. Clock Synchronization
Path Mode
0
1
2
3
Path Mode
0
1
2
3
ILRCK1,
IBICK1
Input
(Not used)
Input
(Not used)
IMCLK1
IMCLK2
Input
(Not used)
(Not used)
Input
Input
(Not used)
(Not used)
(Not used)
Table 3. Master Clock
ILRCK2, IBICK2
I2MODE = “L” I2MODE = “H”
(Not used)
Output
Input
Output
(Not used)
(Not used)
(Not used)
Output
Table 4. LRCK/BICK
(Not used)
SDTI1
SDTI2
SDTI1
OMCLK
Input
Input
(Not used)
Input
OLRC, OBICK
OMODE= “L”
OMODE= “H”
Input
Output
Input
Output
(Not used)
Output
Input
Output
(1) Path Mode 0
IMCLK1 does not need to be synchronized with OMCLK when using Path Mode 1. IMCLK1 should be synchronized
with ILRCK1 (clock phase is not important). STDI2 should be synchronized with OLRCK and OBICK. When the
output is slaved, OMCLK should be synchronized with OLRCK (clock phase is not important). When input#2 is in
slave mode, OLRCK and OBICK are used while ILRCK2 and IBICK2 are not.
(2) Path Mode 1
IMCKL2 does not need to be synchronized with OMCLK. When Input#2 port is in slave mode, IMCLK2 should be
synchronized with ILRCK2 (clock phase is not important). When Output#2 port is in slave mode, OMCLK should be
synchronized with OLRCK (clock phase is not important).
(3) Path Mode 2
IMCLK1 should be synchronized with ILRCK1 (clock phase is not important). SDTO should be synchronized with
ILRCK1 and IBICK1. When the Output is in slave mode, the OLRCK and OBICK pins are not used. In master mode,
ILRCK1 is output through OLRCK and IBICK1 is output through OBICK.
(4) Path Mode 3
OMCLK should be synchronized with OLRCK (clock phase is not important). SDTI2 should be synchronized with
OLRCK and OBICK. When Input#2 is in slave mode, ILRCK2 and IBICK2 pins are not used. In master mode, OLRCK
is output through ILRCK2 and OBICK is output through IBICK2.
MS0134-E-01
2008/06
- 16 -
[AK4120]
The frequency of IMCLK1, IMCLK2, and OMCLK are fixed based on the sampling rate and clock speed (256fs/512fs).
IMCKS1, IMCKS2 and OMCKS bits in register 01H select clock speed.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96kHz
MCLK (MHz)
256fs
512fs
8.1920
16.384
11.2896
22.5792
12.2880
24.576
22.5792
N/A
24.5760
N/A
Table 5. System Clock Example
BICK (MHz)
64fs
2.0480
2.8224
3.0720
5.6448
6.1440
■ Volume Control
AK4120 has two digital volumes (Volume#1 and Volume#2). Volume#1 can control the volume level of data from
Input#1 while in Path Mode 0 or from Input#2 while in Path Mode 1. It then passes this data through SRC block.
Volume#2 can control the volume level of data from Input#2 while in Path Mode 0 and Path Mode 3, or from Input#1
in Path Mode 2. These volume ranges are from –83.25dB to 12dB in 0.75dB steps. The volume level and mute of each
channel can be controlled by register 3-6H.
MS0134-E-01
2008/06
- 17 -
[AK4120]
■ Audio Serial Interface Format
Four serial data modes can be selected by the I2S pin and D5-D0 bits in register 00H as shown in Table 6∼8. In all
modes the serial audio data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of
BICKO and the SDTI1 and SDTI2 are latched on the rising edge of BICKI1 and BICKI2.
I2S pin
L
L
L
L
H
DIFI11
DIFI10
SDTI1
LRCK
0
0
20bit, MSB justified
H/L
0
1
20bit, I2S
L/H
1
0
20bit, LSB justified
H/L
1
1
16bit, LSB justified
H/L
L/H
X
X
20bit, I2S
Table 6. Audio data formats for Input#1 port (X: Don’t care)
I2S pin
L
L
L
L
H
DIFI21
DIFI20
SDTI2
LRCK
0
0
20bit, MSB justified
H/L
0
1
20bit, I2S
L/H
1
0
20bit, LSB justified
H/L
1
1
16bit, LSB justified
H/L
X
X
20bit, I2S
L/H
Table 7. Audio data formats for Input#2 port (X: Don’t care)
I2S pin
L
L
L
L
H
DIFO1
DIFO0
SDTO
LRCK
0
0
20bit, MSB justified
H/L
0
1
20bit, I2S
L/H
1
0
20bit, LSB justified
H/L
1
1
16bit, LSB justified
H/L
X
X
20bit, I2S
L/H
Table 8. Audio data formats for Output port (X: Don’t care)
Default
Default
Default
Note: When the Audio Serial Interface Mode is changed, the AK4120 should be powered down using the PW bit.
(PW bit= “0”)
MS0134-E-01
2008/06
- 18 -
[AK4120]
LRCK
0
1
12
13
14
15
16
31
0
1
12
13
14
15
16
31
0
1
0
1
BICK
(64fs)
SDTI
16bit
Don’t care
15
0
Don’t care
15
0
Don’t care
15
0
15
0
15:MSB, 0:LSB
SDTI
20bit
19
Don’t care
18
17
16
19
18
16
17
19:MSB, 0:LSB
Lch Data
Rch Data
Figure 7. LSB justified Timing
LRCK
0
1
2
18
19
20
30
31
0
1
2
18
19
20
30
31
BICK
(64fs)
SDTI
19
18
1
0
Don’t care
19
18
1
0
Don’t care
19
18
0
1
20:MSB, 0:LSB
Lch Data
Rch Data
Figure 8. MSB justified Timing
LRCK
0
1
2
3
19
20
21
31
0
1
2
3
19
20
21
31
BICK
(64fs)
SDTI
19
18
1
0
Don’t care
19
18
1
0
Don’t care
19
19:MSB, 0:LSB
Lch Data
Rch Data
2
Figure 9. I S Timing
MS0134-E-01
2008/06
- 19 -
[AK4120]
■ Serial Control Interface
The AK4120 is controlled via registers. Internal registers can be written using one of two control modes, I2C or 3-wire,
that are selected via I2C pin. PDN pin= “L” initializes the registers to their default values. When the I2C pin is changed,
the AK4120 should be reset using the PDN pin.
* When PDN= “L”, internal registers cannot be written.
* The AK4120 does not support the read command while using the 3-wire Serial Control Mode.
(1) 3-wire Serial Control Mode (I2C = “L”)
Internal registers may be written to using the 3 wire µP interface pins (CSN, CCLK and CDTI). The data on this
interface consists of a Chip address that is fixed to “10” and a Read/Write status (1bit, Fixed to “1”; Write only).
Also a Register address (MSB first, 5bits) and Control data (MSB first, 8bits) are used. Address and data is
clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is
latched after a low-to-high transition of CSN. The clock speed of CCLK is 5MHz(max)
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0
1
A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
Chip Address (C1:1,C0:CAD0)
R/W:
Read/Write (Fixed to “1” : Write only)
A4-A0:
Register Address
D7-D0:
Control Data
Figure 10. 3-wire Serial Control I/F Timing
Note: Do not write to the address except 00H through 06H.
MS0134-E-01
2008/06
- 20 -
[AK4120]
2) I2C-bus Control Mode (I2C= “H”)
The AK4120 supports the standard I2C-bus interface (max:100kHz). Then AK4120 cannot support fast-mode I2C (max:
400kHz).
(2)-1. WRITE Operations
Figure 11 shows the data transfer sequence in I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 17). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction
bit (R/WN). The most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and
CAD0 (device address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1
pin and CAD0 pin) set them (Figure 12). If the slave address matches that of the AK4120, the AK4120 generates the
acknowledge and the operation is executed. The master must generate an acknowledge-related clock pulse and release
the SDA line (HIGH) during the acknowledge clock pulse (Figure 18). A “1” for R/WN bit indicates that the read
operation is to be executed. A “0” indicates that the write operation is to be executed.
The second byte is the control register address of the AK4120. The format is MSB first, and three most significant bits
are fixed to zero (Figure 13). Subsequent bytes contain control data. The format is MSB first, 8-bits (Figure 14). The
AK4120 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP
condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP
condition (Figure 17).
The AK4120 is capable of more than one byte write operation per sequence. After receipt of the third byte, the AK4120
generates an acknowledge, and awaits the next data. The master can transmit multiple bytes rather than terminating the
write cycle after the first data byte is transferred. After the receipt of each data, the internal 5-bit address counter is
incremented by one, and the next data is taken into next address automatically. If the address exceeds 06H prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. (If an
address greater than 07H is set, this function will not work properly.)
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 19) except for START and STOP conditions.
S
T
A
R
T
SDA
S
S
T
O
P
R/WN= “0”
Slave
Address
Sub
Address(n)
A
C
K
Data(n+1)
Data(n)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 11. Data transfer sequence at the I2C-bus mode
0
0
1
0
0
CAD1
CAD0
R/WN
(Those CAD1/0 should match with CAD1/0 pins)
Figure 12. The first byte
0
0
0
A4
A3
A2
A1
A0
D2
D1
D0
Figure 13. The second byte
D7
D6
D5
D4
D3
Figure 14. Byte structure after the second byte
MS0134-E-01
2008/06
- 21 -
[AK4120]
(2)-2. READ Operations
To enable a READ operation in the AK4120, set R/WN bit = “1”. After transmission of data, the master can read the
next data address by generating an acknowledge instead of terminating the write cycle after the receipt the first data
word. After the receipt of each data, the internal 5-bit address counter is incremented by one, and the next data is taken
into next address automatically. If the address exceeds 06H prior to generating the stop condition, the address counter
will “roll over” to 00H and the previous data will be overwritten. If an address greater than 07H is set, this function will
not work properly.)
The AK4120 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4120 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address “n”, the next CURRENT READ operation
would access data from the address “n+1”. After receipt of the slave address with R/WN bit set to “1”, the AK4120
generates an acknowledge, transmits 1data byte whose address is set by the internal address counter and increments the
internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a the
stop condition, the AK4120 ceases transmission
S
T
A
R
T
SDA
S
S
T
O
P
R/WN= “1”
Slave
Address
Data(n+1)
Data(n)
A
C
K
A
C
K
Data(n+2)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 15. CURRENT ADDRESS READ
(2)-3-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/WN bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start
request, slave address(R/WN=“0”) and the register address to read. After the register address’s acknowledged, the
master immediately reissues the start request and the slave address with the R/WN bit set to “1”. The AK4120 generates
a stop condition instead of an acknowledge, an acknowledge, 1byte data and increments the internal address counter by
1. If the master generates a stop condition instead of an acknowledge, the AK4120 stops transmitting.
S
T
A
R
T
SDA
S
S
T
A
R
T
R/WN= “0”
Slave
Address
Sub
Address(n)
A
C
K
S
A
C
K
S
T
O
P
R/WN= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 16. RANDOM ADDRESS READ
MS0134-E-01
2008/06
- 22 -
[AK4120]
SDA
SCL
S
P
start condition
stop condition
Figure 17. START and STOP conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 18. Acknowledge on the I2C-bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 19. Bit transfer on the I2C-bus
Note: Only addresses 00H through 06H are valid write addresses. All others should not be read from or written to.
MS0134-E-01
2008/06
- 23 -
[AK4120]
■ System Reset
The AK4120 is reset by bringing the power down pin “PDN” =“L”. The digital filters are also reset when this occurs.
The AK4120 should be reset once by bringing the PDN pin =“L” upon power-up. After a reset, the required clocks
shown in Table 2 must be input.
The SRC block starts 2*LRCK1 or 2*LRCK2 after a reset. The SRC block starts outputting data 2053*ORCK after a
reset occurs. Before 2053*ORCK, the SRC block outputs “L”.
■ Zero Cross Detection Function of Volume
When ZELM bit=“0”, the Zero Cross detection function is enabled. Then, if a Volume value is written to the register,
the volume will not change until a Zero crossing is detected or this process times out. The ZTM1-0 bits in 01H set this
timeout. When ZELM bit=“1”, Volume changes soon after volume value is written.
(3) Zero crossing timeout(ZTM1-0)
(1)
(2)
Figure 20. Zero crossing process
(1) At this point, volume value is written in register.
(2) This is a zero crossing point. At this point, volume is changed.
(3) This is time of Zero crossing timeout that is set by ZTM1-0.
MS0134-E-01
2008/06
- 24 -
[AK4120]
■ Mapping of Program Registers
Addr
00H
01H
02H
03H
04H
05H
06H
Register Name
Control 1
Control 2
Control 3
Lch Volume#1 Control
Rch Volume#1 Control
Lch Volume#2 Control
Lch Volume#2 Control
D7
PW
D6
D5
D4
D3
0
0
ZELM
DIFO1
DIFO0
ZTM1
ZTM0
DIFI21
0
0
GAIN3
GAIN3
GAIN3
GAIN3
MUTE2R
MUTE2L
MUTE1R
MUTE1L
0
0
0
0
GAIN6
GAIN6
GAIN6
GAIN6
GAIN5
GAIN5
GAIN5
GAIN5
GAIN4
GAIN4
GAIN4
GAIN4
D2
D1
D0
Default
80H
20H
00H
10H
10H
10H
10H
DIFI20
DIFI11
DIFI10
OMCKS
IMCKS2
IMCKS1
0
GAIN2
GAIN2
GAIN2
GAIN2
PATH1
GAIN1
GAIN1
GAIN1
GAIN1
PATH0
GAIN0
GAIN0
GAIN0
GAIN0
Note: When the PDN goes to “L”, the registers are initialized to their default values.
Data must not be written to the address except 00H through 06H.
■ Register Definitions
Addr
00H
Register Name
Control 1
Default
D7
PW
1
D6
D5
D4
D3
D2
D1
D0
0
DIFO1
DIFO0
DIFI21
DIFI20
DIFI11
DIFI10
0
0
0
0
0
0
0
D4
ZTM0
0
D3
D2
D1
D0
0
OMCKS
IMCKS2
IMCKS1
0
0
0
0
DIFI11-0: Audio Data Formats for Input#1 port (See Table 6).
DIFI21-0: Audio Data Formats for Input#2 port (See Table 7).
DIFO1-0: Audio Data Formats for Output port (See Table 8).
PW: Power down control
0: Power Down
At PW bit= “0”, internal registers can be written.
1: Normal Operation (Default)
Addr
01H
Register Name
Control 2
Default
D7
0
0
D6
ZELM
0
D5
ZTM1
1
IMCKS1: Master Clock Speed of the Master Clock for Input#1 (IMCLK1)
0: 256fs(default)
1: 512fs
IMCKS2: Master Clock Speed of the Master Clock for Input#2 (IMCLK2)
0: 256fs(default)
1: 512fs
OMCKS: Master Clock Speed of the Master Clock for Output (OMCLK)
0: 256fs(default)
1: 512fs
Note: Set the PW bit= “0” when those master clocks are changed.
MS0134-E-01
2008/06
- 25 -
[AK4120]
ZTM1-0:Duration of zero-crossing timeout when ZELM bit= “0”
Time of Timeout
ZTM1
ZTM0
48kHz
44.1kHz
0
0
513/fs
10.7ms
11.6ms
0
1
1025/fs 21.4ms
23.2ms
1
0
2049/fs 42.7ms
46.5ms
1
1
4097/fs 85.4ms
92.9ms
Note: Fs is the output sample rate
Table 9. Time of Timeout
32kHz
16.0ms
32.0ms
64.0ms
128.0ms
Default
ZELM: Select Zero Crossing Enable
0: Enable (Default)
1: Disable
Addr
02H
Register Name
Control 3
Default
D7
D6
D5
D4
D3
D2
D1
D0
MUTE2R
MUTE2L
MUTE1R
MUTE1L
0
0
PATH1
PATH0
0
0
0
0
0
0
0
0
PATH1-0: Path Mode Select (See Table 1 and Figure 3-4)
MUTE1L: Mute control for Lch of Volume#1
0: Mute off (Default)
1: Mute On
MUTE1R: Mute control for Rch of Volume#1
0: Mute off (Default)
1: Mute On
MUTE2L: Mute control for Lch of Volume#2
0: Mute off (Default)
1: Mute On
MUTE2R: Mute control for Rch of Volume#2
0: Mute off (Default)
1: Mute On
MS0134-E-01
2008/06
- 26 -
[AK4120]
Addr
03H
04H
05H
06H
Register Name
Lch Volume#1 Control
Rch Volume#1 Control
Lch Volume#2 Control
Rch Volume#2 Control
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
GAIN6
GAIN6
GAIN6
GAIN6
GAIN5
GAIN5
GAIN5
GAIN5
GAIN4
GAIN4
GAIN4
GAIN4
GAIN3
GAIN3
GAIN3
GAIN3
GAIN2
GAIN2
GAIN2
GAIN2
GAIN1
GAIN1
GAIN1
GAIN1
GAIN0
GAIN0
GAIN0
GAIN0
0
0
0
1
0
0
0
0
GAIN6-0: Volume control shown in Table 10 .
Volume Range: -83.25dB ∼12dB(Step 0.75dB)
GAIN6-0
00H
01H
02H
:
9H
10H
11H
:
7DH
7EH
7FH
Volume Level
12dB
11.25dB
10.5dB
:
0.75dB
0dB
Default
-0.75dB
:
-81.75
-82.50
-83.25
Table 10. Output Volume level
Note: |Gain error| < 0.3dB, |Step error| < 0.1dB.
MS0134-E-01
2008/06
- 27 -
[AK4120]
SYSTEM DESIGN
Figure 21 illustrates a typical system connection diagram. An evaluation board is available which demonstrates this
application circuit, the optimum layout, power supply arrangement and performance measurement results.
Condition: VDD=3.3V, 3-wire serial control mode, Chip Address = “10”
Path Mode 0, Input#2 and Output are slave mode
Digital
Audio
Source
(DIR)
IMCLK2
24
SDTI1
SDTI2
23
3
IBICK1
IBICK2
22
4
ILRCK1
ILRCK2
21
5
TEST
I2MODE
20
6
I2S
VDD
19
7
I2C
VSS
18
8
CAD0
OMODE
17
16
1
IMCLK1
2
AK4120
Top View
9
CSN/CAD1
OMCLK
10
CCLK/SCL
SDTO
15
11
CDTI/SDA
OBICK
14
12
PDN
OLRCK
13
ADC
Analog
Input
3.3V Supply
0.1u
uP
Audio
DSP
Figure 21. Example of a typical design
MS0134-E-01
2008/06
- 28 -
[AK4120]
PACKAGE
24pin VSOP (Unit: mm)
1.25±0.2
*7.8±0.15
13
A
7.6±0.2
*5.6±0.2
24
12
1
0.22±0.1
0.65
0.15±0.05
0.1±0.1
0.5±0.2
Detail A
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder plate (Pb free)
MS0134-E-01
2008/06
- 29 -
[AK4120]
MARKING
AKM
AK4120VF
AAXXXX
Contents of AAXXXX
AA:
Lot#
XXXX:
Date Code
REVISION HISTORY
Date (YY/MM/DD)
02/01
08/06
Revision
00
01
Reason
First Edition
Error Correct
Page
Contents
9
Note 17 was corrected.
MPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application
or use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support,
or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the
use approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it,
and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and
the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless
from any and all claims arising from the use of said product in the absence of such notification.
MS0134-E-01
2008/06
- 30 -