ASAHI KASEI [AK4341] AK4341 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output AK4341 2Vrms24 DACΔΣ (SCF) 192kHz Set-Top-Box, DVD, AC-3 16pin TSSOP : 8kHz ∼ 192kHz 128 64 2 32 4 24 8 FIR SCF 2 LPF 2Vrms 2 I/F : 24, I S : 256fs, 384fs, 512fs, 768fs or 1152fs 256fs or 384fs 2 128fs or 192fs 4 THD+N: -86dB Dynamic Range: 100dB : +3.0 ∼ +3.6V (DAC), +8.55 ∼ +12.6V (Output Buffer) Ta = -20 to 85°C : 16pin TSSOP (6.4mm x 5.0mm) MCLK PDN GAIN VDD SMUTE DEM DIF Control Interface De-emphasis Control HVDD Clock Divider VCOM ACKS VSS LRCK BICK SDTI Audio Data Interface 8X Interpolator ΔΣ Modulator SCF LPF AOUTL 8X Interpolator ΔΣ Modulator SCF LPF AOUTR MS0558-J-01 2007/03 -1- ASAHI KASEI [AK4341] ■ AK4341ET AKD4341 -20 ∼ +85°C AK4341 16pin TSSOP (0.65mm pitch) ■ MCLK 1 16 GAIN BICK 2 15 VCOM SDTI 3 14 VDD LRCK 4 13 VSS PDN 5 12 HVDD SMUTE 6 11 AOUTL ACKS 7 10 AOUTR DIF 8 9 DEM Top View MS0558-J-01 2007/03 -2- ASAHI KASEI No. Pin Name [AK4341] I/O Function Master Clock Input Pin 1 MCLK I An external TTL clock should be input on this pin. 2 BICK I Audio Serial Data Clock Pin 3 SDTI I Audio Serial Data Input Pin 4 LRCK I L/R Clock Pin Power-Down Mode Pin When at “L”, the AK4341 is in the power-down mode, held in reset and 5 PDN I AOUTL/R are held in VCOM. The AK4341 must be reset once upon power-up. Soft Mute Pin in parallel control mode 6 SMUTE I “H”: Enable, “L”: Disable Auto Setting Mode Pin 7 ACKS I “L”: Manual Setting Mode, “H”: Auto Setting Mode Audio Data Interface Format Pin 8 DIF I “L”: 24 bit MSB Justified, “H”: I2S 9 DEM I De-emphasis Enable Pin “H”: Enable, “L”: Disable Rch Analog Output Pin 10 AOUTR O When PDN pin = “L”, outputs VCOM voltage. Lch Analog Output Pin 11 AOUTL O When PDN pin = “L”, outputs VCOM voltage. Output Buffer Power Supply Pin Normally connected to VSS with a 0.1μF ceramic capacitor in parallel with a 12 HVDD 10μF electrolytic cap. 13 VSS Ground Pin 14 VDD DAC Power Supply Pin DAC Common Voltage Pin 15 VCOM O Normally connected to VSS with a 10μF electrolytic cap. Outputs VCOM VDD voltage either PDN pin = “L” or “H”. Gain Control Pin. “H”: +6dB, “L”: 0dB, open: +12dB. When PDN=“H”, the Gain pin is connected to VDD and VSS with 50 16 GAIN I resisters and held to VDD/2 when open. When PDN=“L”, connected to VSS with 50kresister. Note: All input pins except for the GAIN pin should not be left floating. MS0558-J-01 2007/03 -3- ASAHI KASEI [AK4341] (VSS=0V; Note 1) Parameter Power Supply DAC Output Buffer Input Current (any pins except for supplies) Input Voltage Ambient Operating Temperature Storage Temperature Note 1. Symbol VDD HVDD IIN VIND Ta Tstg min -0.3 -0.3 -0.3 -20 -65 max +6.0 +14 ±10 VDD+0.3 85 150 Units V V mA V °C °C : (VSS=0V; Note 1) Parameter Power Supply DAC Output Buffer Symbol VDD HVDD min +3.0 +8.55 typ +3.3 +9 max +3.6 +12.6 Units V V : MS0558-J-01 2007/03 -4- ASAHI KASEI [AK4341] ( Ta = 25°C; VDD = +3.3V, HVDD = +9.0V; fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ, GAIN =0dB) Parameter min typ max Units Resolution 24 Bits Dynamic Characteristics (Note 2) THD+N (0dBFS) fs=44.1kHz, BW=20kHz -86 -80 dB fs=96kHz, BW=40kHz -86 dB fs=192kHz, BW=40kHz -86 dB Dynamic Range (-60dBFS with A-weighted, Note 3) 94 100 dB S/N (A-weighted, Note 4) 94 100 dB Interchannel Isolation (1kHz) 90 dB Interchannel Gain Mismatch 0.3 dB DC Accuracy Gain Drift 100 ppm/°C Output Voltage (Note 5) 1.85 2 2.15 Vrms Load Capacitance (Note 6) 25 pF Load Resistance 5 kΩ Power Supplies Power Supply Current: (Note 7) Normal Operation (PDN pin = “H”, fs≤96kHz) 10 mA VDD 7 mA HVDD Normal Operation (PDN pin = “H”, fs=192kHz) 12 18 mA VDD 7 11 mA HVDD Power-Down Mode (PDN pin = “L”, Note 8) 10 100 VDD μA 10 100 HVDD μA Note 2. Audio Precision (System Two) Note 3. 98dB at 16bit data Note 4. S/N Note 5. (0dB) VDD AOUT (typ.@ 0dB, GAIN =0dB) = 2Vrms × VDD/3.3. Note 6. Note 7. VDD pin or HVDD pin Note 8. (MCLK, BICK, LRCK) VDD VSS GAIN pin “L” open MS0558-J-01 2007/03 -5- ASAHI KASEI [AK4341] (Ta = 25°C; VDD = +3.0 ∼ +3.6V, HVDD = +8.55 ∼ +12.6V; fs = 44.1kHz; DEM = OFF, GAIN =0dB) Parameter Symbol min typ max Digital filter PB 0 20.0 Passband ±0.05dB (Note 9) 22.05 -6.0dB Stopband (Note 9) SB 24.1 Passband Ripple PR ± 0.02 Stopband Attenuation SA 54 Group Delay (Note 10) GD 19.3 De-emphasis Filter (DEM = ON) De-emphasis Error fs = 32kHz –1.5/0 (Relative to 0Hz) fs = 44.1kHz –0.2/+0.2 fs = 48kHz 0/+0.6 Digital Filter + LPF Frequency Response 20.0kHz fs=44.1kHz FR ± 0.05 40.0kHz fs=96kHz FR ± 0.05 80.0kHz fs=192kHz FR ± 0.05 Note 9. fs ( PB=0.4535×fs(@±0.05dB) SB=0.546×fs Note 10. 16/24 Units kHz kHz kHz dB dB 1/fs dB dB dB dB dB dB ) DC (Ta = 25°C; VDD = +3.0 ∼ +3.6V, HVDD = +8.55 ∼ +12.6V) Parameter Symbol High-Level Input Voltage (except for GAIN pin) VIH Low-Level Input Voltage (except for GAIN pin) VIL High-Level Input Voltage (for GAIN pin) VIH Low-Level Input Voltage (for GAIN pin) VIL Open (for GAIN pin, Note 11) open Input Leakage Current (Note 12) Iin Note 11. Gain pin VDD VSS 50k(typ) Note 12. Gain pin pin MS0558-J-01 min 70%VDD 90%VDD - typ VDD/2 - max 30%VDD 10%VDD ± 10 Units V V V V V μA 2007/03 -6- ASAHI KASEI [AK4341] (Ta = 25°C; VDD = +3.0 ∼ +3.6V, HVDD = +8.55 ∼ +12.6V) Parameter Symbol fCLK Master Clock Frequency dCLK Duty Cycle LRCK Frequency Normal Speed Mode fsn Double Speed Mode fsd Quad Speed Mode fsq Duty Cycle Duty Audio Interface Timing BICK Period tBCK Normal Speed Mode tBCK Double Speed Mode tBCK Quad Speed Mode tBCKL BICK Pulse Width Low tBCKH Pulse Width High tBLR BICK “↑” to LRCK Edge (Note 13) tLRB LRCK Edge to BICK “↑” (Note 13) tSDH SDTI Hold Time tSDS SDTI Setup Time Reset Timing tPD PDN Pulse Width (Note 14) Note 13. LRCK BICK “↑” Note 14. PDN pin “L” “H” MS0558-J-01 min 2.048 40 8 60 120 45 typ 11.2896 max 36.864 60 Units MHz % 48 96 192 55 kHz kHz kHz % 1/128fsn 1/64fsd 1/64fsq 30 30 20 20 20 20 ns ns ns ns ns ns ns ns ns 150 ns 2007/03 -7- ASAHI KASEI [AK4341] ■ 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDH tSDS VIH SDTI VIL Serial Interface Timing tPD PDN VIL Power-down Timing MS0558-J-01 2007/03 -8- ASAHI KASEI [AK4341] ■ MCLK, LRCK, BICK MCLK (ACKS = “L”) (MCLK) MCLK Manual Setting Mode Auto Setting Mode Normal SpeedMCLK MCLK (PDN pin = “H”) VCOM “↑”) L Manual Setting Mode Auto Setting Mode (ACKS = “H”) (Table 1) AK4341 MCLK,LRCK (PDN pin = ON MCLK, LRCK ACKS pin H MCLK,LRCK MCLK,LRCK (PDN pin = “L”) (LRCK) ΔΣ LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 32.0kHz 44.1kHz 48.0kHz 128fs 22.5792 24.5760 192fs 33.8688 36.8640 256fs 22.5792 24.5760 - - - 8.1920 11.2896 12.2880 MCLK (MHz) 384fs 512fs 16.3840 22.5792 24.5760 33.8688 36.8640 12.2880 16.9344 18.4320 16.3840 22.5792 24.5760 768fs 24.5760 33.8688 36.8640 - 1152fs 36.8640 - 24.5760 33.8688 36.8640 36.8640 - Sampling Speed Normal Double Quad Normal Table 1. ACKS pin ■ BICK LRCK MSB 16/20 Mode 0 1 SDTI 2’s complement LSB “0” 2 DIF L H BICK ≥48fs ≥48fs (Table 2) DIF pin BICK SDTI Format 24bit 24bit I2S Figure Figure 1 Figure 2 Table 2. MS0558-J-01 2007/03 -9- ASAHI KASEI [AK4341] LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1 BICK (64fs) SDTI 23 22 1 0 Don’t care 23 22 0 1 Don’t care 23 22 0 1 23:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0 Timing LRCK 0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 BICK (64fs) SDTI 23 22 1 0 Don’t care 23 22 1 0 Don’t care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1 Timing ■ IIR (50/15μs ) DEM pin = “H” ON Quad Speed Mode Double Speed Mode OFF DEM pin H L De-emphasis Filter ON OFF Table 3. (Normal Speed Mode) MS0558-J-01 2007/03 - 10 - ASAHI KASEI [AK4341] ■ GAIN pin AOUTL/AOUTR pin GAIN pin GAIN Input Level L 0dB 0dBFS H +6.0dB -6dBFS open +12dB -12dBFS Note 15. AOUTL/AOUTR pin 2Vrms Output Level (VDD=3.3V) 2Vrms (typ) 2Vrms (typ) 2Vrms (typ) 2Vrms (Note 15) (Note 15) Table 4. ■ SMUTE pin SMUTE pin “L”∞ 1024LRCK “H” 1024LRCK -∞ 1024LRCK -∞ (“0”) 0dB 0dB SMUTE pin 1024/fs 1024/fs (1) 0dB (3) Attenuation -∞ GD (2) GD AOUT : (1) 1024LRCK(1024/fs) (2) (3) 1024LRCK -∞(“0”) (GD) 0dB Figure 3. ■ ON PDN pin LRCK “↑” “L” MCLK LRCK MS0558-J-01 2007/03 - 11 - ASAHI KASEI [AK4341] ■ PDN pin L” VCOM(VDD) Figure 4 PDN Internal State Normal Operation Power-down D/A In (Digital) Normal Operation “0” data GD D/A Out (Analog) (1) GD (3) (2) (3) (1) (4) Clock In Don’t care MCLK, LRCK, BICK External MUTE (5) Mute ON : (1) (2) (3) PDN (4) (5) VCOM (GD) (VDD) (“↑ ↓”) (PDN pin = “L”) (MCLK, BICK, LRCK) (3) Figure 4. / MS0558-J-01 2007/03 - 12 - ASAHI KASEI [AK4341] ■ (PDN pin = “H”) VCOM(VDD) LRCK MCLK or LRCK MCLK and LRCK BICK AK4341 MCLK or MCLK and LRCK BICK (1) PDN pin Internal State Power-down D/A In (Digital) Power-down Normal Operation Normal Operation (3) GD D/A Out (Analog) Reset (2) GD (4) Hi-Z (2) (4) VCOM (4) <Case1:MCLK Stop> Clock In (5) MCLK Stop MCLK, BICK, LRCK External MUTE (6) (6) (6) <Case2:LRCK Stop> Clock In (5) (7) LRCK Stop MCLK, BICK, LRCK External MUTE (6) (6) (6) : (1) (2) (3) (4) PDN pin (5) (6) (7) MCLK 150ns PDN pin “L” (GD) “0” (“↑”)MCLK MCLK or LRCK 20usec20usec(3 MCLK or LRCK (MCLK or LRCK) (4) 2048fs LRCK MCLK and LRCK 4LRCK) 20usec (MCLK, BICK, LRCK) LRCK LRCK Figure 5. MS0558-J-01 2007/03 - 13 - ASAHI KASEI [AK4341] Figure 6 (AKD4341) Master Clock 1 MCLK GAIN 16 64fs 2 BICK VCOM 15 24bit Audio Data 3 SDTI VDD 14 + 10u 0.1u fs 4 LRCK Reset & Power down 5 PDN 6 ModeSetting Digital Ground + 10u Analog Supply 3.3V VSS 13 HVDD 12 SMUTE AOUTL 11 Lch Out 7 ACKS AOUTR 10 Rch Out 8 DIF DEM 9 AK4341 0.1u + 10u Analog Supply 9.0V Analog Ground Figure 6. Typical Connection Diagram (GAIN=0dB) MS0558-J-01 2007/03 - 14 - ASAHI KASEI [AK4341] 1. VDD HVDD VSS VDD HVDD VDD pin VSS pin VDD HVDD 2. 3.3V(typ) ΔΣ (CTF) ( ) 1 2’s complement (2 800000H(@24bit) 2Vrms(typ, @VDD=3.3V) (SCF) LPF(Figure 7) ) 7FFFFFH(@24bit) 000000H(@24bit) VAOUT VCOM AK4341 10u 470 Analog Out AOUT 2Vrms (typ) 22k 2.2nF ( = 154kHz, gain = -0.28dB @ 40kHz, gain = -1.04dB @ 80kHz) Figure 7. External 1st order LPF Circuit Example MS0558-J-01 2007/03 - 15 - ASAHI KASEI [AK4341] 16pin TSSOP (Unit: mm) *5.0±0.1 9 A 8 1 0.22±0.1 0.13 M 6.4±0.2 *4.4±0.1 16 1.05±0.05 0.65 0.17±0.05 Detail A 0.5±0.2 0.1±0.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° ■ : : : MS0558-J-01 2007/03 - 16 - ASAHI KASEI [AK4341] AKM 4341ET XXYYY 1) 2) 3) 4) Pin #1 indication Date Code: XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code: 4341ET Asahi Kasei Logo MS0558-J-01 2007/03 - 17 - ASAHI KASEI Date (YY/MM/DD) 06/10/30 07/03/26 [AK4341] Revision 00 01 Reason Page 3 Contents / No.8 “L”: Left Justified Æ 24 bit MSB Justified • • • • • • MS0558-J-01 2007/03 - 18 -