AK4671 Japanese Datasheet

[AK4671]
AK4671
Stereo CODEC with MIC/RCV/HP-AMP
AK4671
AK4671
Stereo CODEC
2
PCM I/F
Bluetooth
57pin BGA
1.
(Stereo CODEC)
•4
x 2ch
•4
(
) or 2
(
)
•
: +30dB ∼ −12dB, 3dB step
• Digital ALC (Automatic Level Control): +36dB ∼ −54dB, 0.375dB Step, Mute
•
•
• 5-band Programmable Notch Filter
• Audio Interface Format : 16bit
, I2S, DSP Mode
2.
(Stereo CODEC)
•
(+12dB ∼ −115.0dB, 0.5dB Step, Mute)
• Digital ALC (Automatic Level Control): +36dB ∼ −54dB, 0.375dB Step, Mute
•
• 5-band EQ
•
•
- BTL Output
: [email protected] (AVDD=3.3V)
•
: [email protected] (AVDD=3.3V)
•
:4
• Audio Interface Format : 16bit
, 16bit
, 16-24bit I2S, DSP Mode
3. Dual PCM I/F for Baseband & Bluetooth Interface
• Sample Rate Converter (Up sample: up to x6: Down sample: down to x1/6)
• Sample Rate: 8kHz
• Digital Volume
• Audio Interface Format:
- 16bit Linear, 8bit A-law, 8bit μ-law
- Short/Long Frame, I2S, MSB justified
4. 10bit SAR ADC
• 3 Input Selector
5.
6.
:
(1) PLL Mode
•
: 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz,
26MHz, 27MHz (MCKI pin)
1fs (LRCK pin)
32fs or 64fs (BICK pin)
(2)
•
: 256fs, 384fs, 512fs, 768fs or 1024fs (MCKI pin)
7.
: 32fs/64fs/128fs/256fs
8.
(Stereo CODEC):
• PLL Slave Mode (LRCK pin): 8kHz ∼ 48kHz
MS0666-J-02
2010/06
-1-
[AK4671]
• PLL Slave Mode (BICK pin): 8kHz ∼ 48kHz
• PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• EXT Master/Slave Mode:
8kHz ∼ 48kHz (256fs, 384fs), 8kHz ∼ 26kHz (512fs, 768fs),
8kHz ∼ 13kHz (1024fs)
(Ver 1.0, 400kHz Fast Mode)
μP
: 4-wire Serial / I2C
9.
10.
11. Ta = −30 ∼ 85°C
12.
:
• AVDD, PVDD, SAVDD: 2.2 ∼ 3.6V
• DVDD, TVDD2, TVDD3: 1.6 ∼ 3.6V
13.
: 57pin BGA (5mm x 5mm, 0.5mm pitch)
■
AVDD
VSS1
SAIN1 SAIN2 SAIN3
VCOM
SAVDD
VSS3
DVDD
VSS4
GPO1
GPO2
PMSAD
MDT
PMMP
MPWR
CSN
A/D
MIC Power
Supply
Control
Register
MIC-Amp
PMADL or PMADR
RIN1/IN1−
A/D
LIN2/IN2+
External
MIC
CDTO
PMMICL
LIN1/IN1+
Internal
MIC
I2C
HPF
PDN
PMMICR
PFSEL=0
PMADL
or
PMADR
RIN2/IN2−
LIN3/IN3+
PFSEL=1
PMDAL
or
PMDAR
or
PMSRA
RIN3/IN3−
LIN4/IN4+
PMLOOPR
PMLOOPL
PMAINR3
PMAINR4
PMAINL4
PMAINL3
PMAINR2
PMAINL2
PMAINL1
PMAINR1
RIN4/IN4−
PMLO1
LOUT1/RCP
HPF
LPF
BICK
Stereo
Separation
Audio
I/F
5-band
Notch
ALC
LRCK
SDTO
SDTI
MIX
PMDAL
or
PMDAR
SVOLA
PMDAL or PMDAR or PMSRA
D/A
Stereo Line Out
or
Mono Receiver
CCLK/SCL
CDTI/SDA
M DATT 5-band
I SMUTE
EQ
X
S
E
L
MCKI
MCKO
PMRO1
ROUT1/RCN
PMPLL
PLL
PMLO2
PMLO2S
PMPCM
VCOC
VCOCBT
LOUT2
Headphone Out
PMRO2
PLLBT
PMSRA
PMRO2S
ROUT2
SRC-A
BICKA
MUTET
SVOLB
PCM
I/F A
PMSRB
SDTOA
PMLO3
SRC-B
LOUT3/LOP
Stereo Line Out
SDTIA
DATT-B
DATT-C
PMRO3
ROUT3/LON
BVOL
PVDD
VSS2
SYNCA
TVDD2
PCM
I/F B
BICKB
SYNCB
SDTOB
SDTIB
TVDD3
Figure 1.
MS0666-J-02
2010/06
-2-
[AK4671]
■
−30 ∼ +85°C
AK4671
AK4671EG
AKD4671
57pin BGA (0.5mm pitch)
■
9
8
7
6
AK4671
5
Top View
4
3
2
1
A
B
C
D
E
F
G
H
J
9
TEST
LOUT2
ROUT2
VCOM
VCOCBT
VSS2
SDTOA
SYNCA
GPO2
8
AVDD
VSS1
MUTET
VCOC
PVDD
TVDD2
BICKA
CDTI
/SDA
SDTIA
LOUT1
/RCP
ROUT3
/LON
RIN4
/IN4−
LIN3
/IN3+
LIN2
/IN2+
LIN1
/IN1+
ROUT1
/RCN
LOUT3
/LOP
LIN4
/IN4+
RIN3
/IN3−
RIN2
/IN2−
RIN1
/IN1−
VSS4
DVDD
CCLK
/SCL
CSN
/CAD0
I2C
BICK
MCKI
MCKO
PDN
LRCK
MDT
A
7
6
5
4
3
2
1
Top View
NC
SAIN2
SAVDD
TVDD3
SDTOB
BICKB
SDTO
CDTO
MPWR
SAIN3
SAIN1
VSS3
SYNCB
SDTIB
SDTI
GPO1
B
C
D
E
F
G
H
J
MS0666-J-02
2010/06
-3-
[AK4671]
No. Pin Name
A1 MDT
B1 MPWR
C1 SAIN3
C2 SAIN2
D1 SAIN1
D2 SAVDD
E1 VSS3
E2 TVDD3
F2 SDTOB
F1 SYNCB
G2 BICKB
G1 SDTIB
H1 SDTI
J1 GPO1
I/O
I
O
I
I
I
O
I/O
I/O
I
I
O
J2
CDTO
O
H2
SDTO
O
H3
PDN
I
J3
H4
J4
LRCK
MCKI
MCKO
H5
I2C
J5
BICK
CSN
CAD0
CCLK
SCL
VSS4
DVDD
CDTI
SDA
GPO2
SDTIA
BICKA
SYNCA
SDTOA
TVDD2
Function
: typ. 500kΩ)
(
10bit SAR ADC
10bit SAR ADC
10bit SAR ADC
10bit SAR ADC
3
I/O
3
2
1
, 2.2 ∼ 3.6V
, 1.6 ∼ 3.6V
3
B
B
B
B
General Purpose Output 1 Pin
H6
H7
J7
H8
J9
J8
G8
H9
G9
F8
)
“H”:
“L”:
150ns(min)
J6
(I2C pin = “L”: 4
)
Hi-Z (I2C pin = “H”: I2C
“L”
I/O
I
O
I
I/O
I
I
I
I
I
I/O
O
I
I/O
I/O
O
-
“H”: I2C
, “L”: 4
0
(I2C pin = “L”: 4
(I2C pin = “H”: I2C
)
(I2C pin = “L”: 4
(I2C pin = “H”: I2C
)
)
)
4
, 1.6 ∼ 3.6V
(I2C pin = “L”: 4
(I2C pin = “H”: I2C
General Purpose Output 2 Pin
A
A
A
A
I/O
2
, 1.6 ∼ 3.6V
MS0666-J-02
)
)
2010/06
-4-
[AK4671]
No.
F9
E8
Pin Name
VSS2
PVDD
I/O
-
E9
VCOCBT
O
D8
VCOC
O
D9
VCOM
O
C8
MUTET
O
C9
B9
ROUT2
LOUT2
O
O
Function
2
PLLBT
PLLBT
VSS2 pin
PLL
VSS1 pin
, 2.2 ∼ 3.6V
, 0.5 x AVDD
ADC
DAC
VSS1 pin
Rch
Lch
Test Pin
A9 TEST
This pin should be open.
A8 AVDD
, 2.2 ∼ 3.6V
B8 VSS1
1
ROUT1
O
Rch
1
(RCV bit = “0”:
)
B7
RCN
O
(RCV bit = “1”:
)
LOUT1
O
Lch
1
(RCV bit = “0”:
)
A7
RCP
O
(RCV bit = “1”:
)
ROUT3
O
Rch
3
(LODIF bit = “0”:
)
A6
LON
O
(LODIF bit = “1”:
)
LOUT3
O
Lch
3
(LODIF bit = “0”:
)
B6
LOP
O
(LODIF bit = “1”:
)
RIN4
I
Rch
4
(MDIF4 bit = “0”:
)
A5
I
4
(MDIF4 bit = “1”:
)
IN4−
LIN4
I
Lch
4
(MDIF4 bit = “0”:
)
B5
IN4+
I
4
(MDIF4 bit = “1”:
)
RIN3
I
Rch
3
(MDIF3 bit = “0”:
)
B4
I
3
(MDIF3 bit = “1”:
)
IN3−
LIN3
I
Lch
3
(MDIF3 bit = “0”:
)
A4
IN3+
I
3
(MDIF3 bit = “1”:
)
RIN2
I
Rch
2
(MDIF2 bit = “0”:
)
B3
I
2
(MDIF2 bit = “1”:
)
IN2−
LIN2
I
Lch
2
(MDIF2 bit = “0”:
)
A3
IN2+
I
2
(MDIF2 bit = “1”:
)
RIN1
I
Rch
1
(MDIF1 bit = “0”:
)
B2
I
1
(MDIF1 bit = “1”:
)
IN1−
LIN1
I
Lch
1
(MDIF1 bit = “0”:
)
A2
IN1+
I
1
(MDIF1 bit = “1”:
)
No Connect Pin
C3 NC
No internal bonding. This pin should be open or connected to the ground.
Note 1.
(MDT, LIN1/IN1+, RIN1/IN1−, LIN2/IN2+, RIN2/IN2−, LIN3/IN3+, RIN3/IN3−,
LIN4/IN4+, RIN4/IN4−, SAIN1, SAIN2, SAIN3)
SDA pin
I/O pin (LRCK, BICK, SYNCA, BICKA, SYNCB, BICKB)
(P.45)
PCM I/F
(P.105)
SDA pin
(DVDD+0.3)V
MS0666-J-02
2010/06
-5-
[AK4671]
■
Analog
MPWR, MDT, VCOC, ROUT3/LON, LOUT3/LOP,
ROUT2, LOUT2, MUTET, ROUT1/RCN,
LOUT1/RCP, RIN4/IN4−, LIN4/IN4+, RIN3/IN3−,
LIN3/IN3+, RIN2/IN2−, LIN2/IN2+, RIN1/IN1−,
LIN1/IN1+, VCOCBT, SAIN1, SAIN2, SAIN3
MCKO, SDTOA, SDTOB, GPO1, GPO2, CDTO
MCKI, SDTIA, SDTIB
VSS4
VSS4
PMPCM bit
“0”
PCM I/F A(BICKA/SYNCA)
PCM I/F B (BICKB/SYNCB)
Digital
BICKA, SYNCA, BICKB, SYNCB
100kΩ
/
MS0666-J-02
2010/06
-6-
[AK4671]
(VSS1=VSS2=VSS3 =VSS4=0V; Note 2, Note 3)
Parameter
Power Supplies:
Analog
PLLBT
10bit SAR ADC
Digital
Digital I/O 2
Digital I/O 3
Input Current, Any Pin Except Supplies
Analog Input Voltage 1 (Note 4)
Analog Input Voltage 2 (Note 5)
Digital Input Voltage 1 (Note 6)
Digital Input Voltage 2 (Note 7)
Digital Input Voltage 3 (Note 8)
Ambient Temperature (powered applied)
Storage Temperature
Symbol
AVDD
PVDD
SAVDD
DVDD
TVDD2
TVDD3
IIN
VINA1
VINA2
VIND1
VIND2
VIND3
Ta
Tstg
min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−30
−65
max
4.0
4.0
4.0
4.0
4.0
4.0
±10
AVDD+0.3
SAVDD+0.3
DVDD+0.3
TVDD2+0.3
TVDD3+0.3
85
150
Units
V
V
V
V
V
V
mA
V
V
V
V
V
°C
°C
Note 2.
Note 3. VSS1 VSS2, VSS3, VSS4
Note 4. RIN4/IN4−, LIN4/IN4+, RIN3/IN3−, LIN3/IN3+, RIN2/IN2−, LIN2/IN2+, RIN1/IN1−, LIN1/IN1+ pins
Note 5. SAIN1, SAIN2, SAIN3 pins
Note 6. PDN, I2C, CSN/CAD0, CCLK/SCL, CDTI/SDA, SDTI, LRCK, BICK, MCKI pins
SDA, SCL pins
(DVDD+0.3)V
Note 7. BICKA, SYNCA, SDTIA pins
Note 8. BICKB, SYNCB, SDTIB pins
:
(VSS1=VSS2 =VSS3 =VSS4=0V; Note 2)
Parameter
Symbol
Power Supplies Analog
AVDD
(Note 9) PLLBT
PVDD
10bit SAR ADC
SAVDD
Digital
DVDD
Digital I/O 2
TVDD2
Digital I/O 3
TVDD3
Difference
AVDD−PVDD
Note 2.
Note 9. AVDD, PVDD, SAVDD, DVDD, TVDD2, TVDD3
PDN pin = “L”
PDN pin “H”
(
min
2.2
2.2
2.2
1.6
1.6
1.6
−0.1
typ
3.3
3.3
3.3
3.3
3.3
3.3
0
max
3.6
3.6
3.6
3.6
3.6
3.6
+0.1
Units
V
V
V
V
V
V
V
)
DVDD
OFF
(PMVCM, PMMP,
PMMICL, PMMICR, PMADL, PMADR, PMDAL, PMDAR, PMPLL, PMLOOPL, PMLOOPR, PMAINL1,
PMAINR1, PMAINL2, PMAINR2, PMAINL3, PMAINR3, PMAINL4, PMAINR4, PMLO1, PMRO1, PMLO2,
PMRO2, PMLO2S, PMRO2S, PMLO3, PMRO3, PMSRA, PMSRB, PMPCM, PMSAD) “0”
PDN pin = “L”
DVDD OFF
AVDD, PVDD, SAVDD, TVDD2, TVDD3
OFF
DVDD
OFF
10mA
:
MS0666-J-02
2010/06
-7-
[AK4671]
(CODEC)
(Ta=25°C; AVDD=PVDD=SAVDD=DVDD=TVDD2=TVDD3=3.3V; VSS1=VSS2=VSS3=VSS4=0V;
Signal Frequency=1kHz; 16bit Data; fs=44.1kHz, BICK=64fs; Measurement frequency=20Hz ∼ 20kHz; unless
otherwise specified)
Parameter
min
typ
max
Units
MIC Amplifier: LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins; PMAINL1/R1/L2/R2/L3/R3/L4/R4 bits = “0”
Input Resistance
MGNL/R0 bit = “0”
28
42
56
kΩ
MGNL/R0 bit = “1”
20
30
40
kΩ
Gain (Note 10)
Max (MGNL/R3-0 bits = “FH”)
+30
dB
Min (MGNL/R3-0 bits = “1H”)
dB
−12
MIC Power Supply: MPWR pin
Output Voltage (Note 11)
2.47
2.64
2.81
V
Load Resistance
0.5
kΩ
Load Capacitance
30
pF
MIC Detection: MDT pin
0.247
0.165
mV
Comparator Voltage Level (Note 12)
750
250
500
Internal pull down Resistance
kΩ
Stereo ADC Analog Input Characteristics:
LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins → Stereo ADC → IVOL, IVOL=0dB, ALC=OFF
Resolution
16
Bits
(Note 14)
0.150
0.176
0.203
Vpp
Input Voltage (Note 13)
1.68
1.98
2.28
Vpp
(Note 15)
(Note 14)
72
82
dB
S/(N+D) (−1dBFS)
87
dB
(Note 15)
(Note 14)
75
85
dB
D-Range (−60dBFS, A-weighted)
95
dB
(Note 15)
(Note 14)
75
85
dB
S/N (A-weighted)
95
dB
(Note 15)
(Note 14)
75
90
dB
Interchannel Isolation
100
dB
(Note 15)
(Note 14)
0.1
0.8
dB
Interchannel Gain Mismatch
0.1
0.8
dB
(Note 15)
Note 10.
MGAIN=0dB (min), AVDD=2.4V (min)
Note 11.
AVDD
Vout = 0.8 x AVDD (typ)
Note 12.
AVDD
Vth = 0.05 x AVDD (min), 0.075 x AVDD(max).
Note 13.
AVDD
Vin = 0.053 x AVDD (typ)@MGNL3-0=MGNR3-0 bits = “CH” (+21dB),
Vin = 0.6 x AVDD (typ)@MGNL3-0=MGNR3-0 bits = “5H” (0dB).
Note 14. MGNL3-0=MGNR3-0 bits = “CH” (+21dB).
Note 15. MGNL3-0=MGNR3-0 bits = “5H” (0dB).
MS0666-J-02
2010/06
-8-
[AK4671]
Parameter
min
typ
max
Units
Stereo DAC Characteristics:
Resolution
16
Bits
Stereo Line Output Characteristics:
Stereo DAC → LOUT1/ROUT1/LOUT3/ROUT3 pins, ALC=OFF, IVOL=0dB, OVOL=0dB, L1VL=L3VL=0dB,
RCV bit = “0”, RL=10kΩ; unless otherwise specified.
Output Voltage (Note 16)
1.78
1.98
2.18
Vpp
S/(N+D) (0dBFS)
75
85
dB
S/N (A-weighted)
82
92
dB
Interchannel Isolation
85
100
dB
Interchannel Gain Mismatch
0.1
0.8
dB
Load Resistance
10
kΩ
Load Capacitance
30
pF
Mono Receiver-Amp Output Characteristics:
Stereo DAC → RCP/RCN pins, ALC=OFF, IVOL=0dB, OVOL=0dB, L1VL=0dB, RCV bit = “1”, RL=32Ω, BTL;
unless otherwise specified.
Output Voltage (Note 17)
1.76
1.96
2.16
Vpp
−6dBFS, RL=32Ω (Po=15mW)
2.77
Vpp
−3dBFS, RL=32Ω (Po=30mW)
S/(N+D)
40
60
dB
−6dBFS, RL=32Ω (Po=15mW)
20
dB
−3dBFS, RL=32Ω (Po=30mW)
S/N (A-weighted)
82
92
dB
Load Resistance
32
Ω
Load Capacitance (Note 18)
30
pF
Headphone-Amp Characteristics: DAC → LOUT2/ROUT2 pins, ALC=OFF, IVOL=0dB, OVOL=0dB, HPG=0dB,
RL=16Ω
Output Voltage (Note 19)
0.89
0.99
1.09
Vpp
−6dBFS (Po=7.6mW)
0dBFS (Po=30mW)
1.98
Vpp
S/(N+D)
40
60
dB
−6dBFS (Po=7.6mW)
0dBFS (Po=30mW)
40
dB
S/N (A-weighted)
80
90
dB
Interchannel Isolation
65
75
dB
Interchannel Gain Mismatch
0.1
0.8
dB
Load Resistance
16
Ω
C1 in Figure 2
30
pF
Load Capacitance
300
pF
C2 in Figure 2
Note 16.
Note 17.
Note 18.
Note 19.
AVDD
Vout = 0.6 x AVDD (typ).
AVDD
Vout = (RCP) − (RCN) = 0.59 x AVDD (typ)@−6dBFS.
VSS1 Load Capacitance
AVDD
Vout = 0.3 x AVDD (typ)@−6dBFS.
MS0666-J-02
2010/06
-9-
[AK4671]
HP-Amp
LOUT2 pin
ROUT2 pin
C1
Measurement Point
100μ
F
0.22μF
C2
16Ω
10Ω
Figure 2.
Parameter
min
typ
max
Units
Mono Line Output Characteristics: Stereo DAC → LOP/LON pins, ALC=OFF, IVOL=0dB, OVOL=0dB,
L3VL=0dB, LODIF bit = “1”, RL=10kΩ for each pin (Full-differential)
Output Voltage (Note 20)
3.52
3.96
4.36
Vpp
S/(N+D) (0dBFS)
75
85
dB
S/N (A-weighted)
85
95
dB
Load Resistance (LOP/LON pins, respectively)
10
kΩ
Load Capacitance (LOP/LON pins, respectively)
30
pF
(Note 21)
Single-ended Line Input: LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins;
(MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
Maximum Input Voltage (Note 22)
1.98
Vpp
Gain
InputÆLOUT1/ROUT1/LOUT2/ROUT2/LOUT3/ROUT3 (LODIF=RCV bits = “0”)
0
+1
dB
−1
Input Æ RCP/RCN/LOP/LON (LODIF=RCV bits = “1”)
+6
dB
Full-differential Line Input: IN1+/−, IN2+/−, IN3+/−, IN4+/− pins; (MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
Maximum Input Voltage (Note 23)
1.98
Vpp
Gain
InputÆLOUT1/ROUT1/LOUT2/ROUT2/LOUT3/ROUT3 (LODIF=RCV bits = “0”)
0
+1
dB
−1
Input Æ RCP/RCN (LODIF=RCV bits = “1”, Note 24)
+6
dB
Power Supply Current:
Power Up (PDN pin = “H”, All Circuits Power-up)
(Note 25)
21
mA
AVDD+PVDD+DVDD
26)
23
30
mA
(Note
+TVDD2+TVDD3+SAVDD
8
12
mA
(Note 27)
Power Down (PDN pin = “L”) (Note 28)
AVDD+PVDD+DVDD
1
30
μA
+TVDD2+TVDD3+SAVDD
AVDD
Vout = (LOP) − (LON) = 1.2 x AVDD (typ).
VSS1 Load Capacitance
AVDD
Vin = 0.6 x AVDD (typ).
AVDD
Vin = (IN4+) − (IN4−) = 0.6 x
AVDD (typ).
Note 24. Vout = (RCP) − (RCN) at RCV bit = “1”, Vout = (LOP) − (LON) at LODIF bit = “1”.
Note 25. EXT Slave Mode
LP bit = “0”, fs=44.1kHz, PMMICL = PMMICR = PMADL = PMADR = PMDAL =
PMDAR = PMLO1 = PMRO1 = PMLO2 = PMRO2 = PMLO2S = PMRO2S = PMLO3 = PMRO3 =PMSAD =
PMVCM = MUTEN bits = “1”, PMPLL = MCKO = PMMP = M/S = PMSRA = PMSRB = PMPCM bits = “0”
Note 20.
Note 21.
Note 22.
Note 23.
MS0666-J-02
2010/06
- 10 -
[AK4671]
AVDD=13.2mA (typ), PVDD=0mA (typ), DVDD=6.7mA (typ), TVDD2=0mA (typ), TVDD3=0mA (typ),
SAVDD=0.8mA (typ).
Note 26. PLL Master Mode
LP bit = “0”, fs=44.1kHz, PMADL = PMMICL= PMMICR= PMADR = PMDAL =
PMDAR = PMLO1 = PMRO1 = PMLO2 = PMRO2 = PMLO2S = PMRO2S = PMLO3 = PMRO3 =PMSAD =
PMVCM = PMPLL = M/S = PMMP = MUTEN bits = “1”, MCKO = PMSRA = PMSRB = PMPCM bits = “0 ,
MCKI=11.2896MHz
AVDD=14.7mA (typ), PVDD=0mA (typ), DVDD=7.0mA (typ), TVDD2=0mA (typ), TVDD3=0mA (typ),
SAVDD=0.8mA (typ).
Note 27. EXT Slave Mode
LP bit = “1”, fs=8kHz, PMVCM = PMMP = PMMICL = PMADL = PMDAR = RCV =
PMLO1 = PMRO1 = PMSRA = PMSRB = PMPCM bits = “1”
AVDD=5.2mA (typ), PVDD=0.6mA (typ), DVDD=2.2mA (typ), TVDD2=0mA (typ), TVDD3=0mA (typ),
SAVDD=0mA (typ).
Note 28.
(DVDD, TVDD2 or TVDD3)
VSS4
SRC
(Ta=25°C; AVDD=PVDD =SAVDD =DVDD =TVDD2 =TVDD3=3.3V; VSS1=VSS2=VSS3=VSS4=0V;
Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 3.4kHz; unless otherwise specified)
Parameter
Symbol
min
typ
max
SRC Characteristics (Down Sampling: SRC-A): SDTI Æ SRC-A Æ SDTOA/SDTOB
Resolution
16
Input Sample Rate
FSI (fs)
8
48
Output Sample Rate
FSO (fs2)
8
THD+N (Input = 1kHz, −1dBFS, Note 29)
FSO/FSI = 8kHz/44.1kHz
−94
Dynamic Range (Input = 1kHz, −60dBFS, Note 29)
FSO/FSI = 8kHz/44.1kHz
97
Ratio between Input and Output Sample Rate
FSO/FSI
1/6
1
SRC Characteristics (Up Sampling: SRC-B): SDTIA/SDTIB Æ SRC-B Æ SDTO
Resolution
16
Input Sample Rate
FSI (fs2)
8
Output Sample Rate
FSO (fs)
8
48
THD+N (Input = 1kHz, −1dBFS, Note 29)
FSO/FSI = 44.1kHz/8kHz
−95
Dynamic Range (Input = 1kHz, −60dBFS, Note 29)
FSO/FSI = 44.1kHz/8kHz
100
Ratio between Input and Output Sample Rate
FSO/FSI
1
6
Note 29. Audio Precision System Two Cascade
Note 30. fs Stereo CODEC
fs2
Units
Bits
kHz
kHz
dB
dB
Bits
kHz
kHz
dB
dB
-
PCM I/F
MS0666-J-02
2010/06
- 11 -
[AK4671]
(10bit SAR ADC)
(Ta=25°C; AVDD=PVDD =SAVDD =DVDD =TVDD2 =TVDD3=3.3V; VSS1=VSS2=VSS3=VSS4=0V; unless
otherwise specified)
Parameter
min
typ
max
Units
10bit SAR ADC Characteristics
Resolution
10
Bits
No Missing Codes
9
10
Bits
Integral Linearity Error
LSB
±2
DNL
LSB
±1
Analog Input Voltage Range
0
SAVDD
V
Offset Error
LSB
±3
Gain Error
LSB
±2
Accuracy (Note 31)
%
±1
Note 31. SAIN1, SAIN2 or SAIN3 pin
1.1V
(CODEC)
(Ta=25°C; AVDD=PVDD =SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2 =TVDD3=1.6 ∼ 3.6V; fs=44.1kHz; Programmable
Filter=OFF)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
Passband (Note 32)
PB
0
17.3
kHz
±0.16dB
19.4
kHz
−0.66dB
19.9
kHz
−1.1dB
22.1
kHz
−6.9dB
Stopband
SB
25.9
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
69
dB
Group Delay (Note 33)
GD
19
1/fs
Group Delay Distortion
0
ΔGD
μs
DAC Digital Filter (LPF):
Passband (Note 32)
PB
0
17.4
kHz
±0.1dB
20.0
kHz
−1.0dB
21.1
kHz
−3.0dB
Stopband
SB
25.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 33)
GD
19
1/fs
DAC Digital Filter (LPF) + SCF:
FR
dB
Frequency Response: 0 ∼ 20.0kHz
±1.4
Note 32.
fs (
PB=20.0kHz(@−0.7dB)
Note 33.
DAC
)
0.454 x fs
(DAC)
ADC
1kHz
16
16
MS0666-J-02
2010/06
- 12 -
[AK4671]
(SRC)
(Ta=25°C; AVDD=PVDD =SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2 =TVDD3=1.6 ∼ 3.6V; fs2=8kHz, Programmable
Filter=OFF)
Parameter
Symbol
min
typ
max
Units
Down Sampling (SRC-A): fs=8kHz
Passband
PB
0
3.0
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 34)
GD
5
ms
Down Sampling (SRC-A): fs=11.025kHz
Passband
PB
0
3.1
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 34)
GD
4
ms
Down Sampling (SRC-A): fs=12kHz
Passband
PB
0
3.1
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 34)
GD
4
ms
Down Sampling (SRC-A): fs=16kHz
Passband
PB
0
3.1
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 34)
GD
3
ms
Down Sampling (SRC-A): fs=22.05kHz
Passband
PB
0
3.1
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 34)
GD
3
ms
Down Sampling (SRC-A): fs=24kHz
Passband
PB
0
3.1
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 34)
GD
3
ms
Note 34.
16bit
MS0666-J-02
2010/06
- 13 -
[AK4671]
Parameter
Down Sampling (SRC-A): fs=32kHz
Passband
±0.1dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay (Note 34)
Down Sampling (SRC-A): fs=44.1kHz
Passband
±0.1dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay (Note 34)
Down Sampling (SRC-A): fs=48kHz
Passband
±0.1dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay (Note 34)
Note 34.
Symbol
min
typ
max
Units
PB
SB
PR
SA
GD
0
4.7
69
-
3
3.1
±0.1
-
kHz
kHz
dB
dB
ms
PB
SB
PR
SA
GD
0
4.7
69
-
3
3.1
±0.1
-
kHz
kHz
dB
dB
ms
PB
SB
PR
SA
GD
16bit
0
4.7
69
-
3
3.1
±0.1
-
kHz
kHz
dB
dB
ms
MS0666-J-02
2010/06
- 14 -
[AK4671]
Parameter
Up Sampling (SRC-B): fs=8kHz
Passband
±0.1dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay (Note 34)
Up Sampling (SRC-B): fs=11.025kHz
Passband
±0.1dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay (Note 34)
Up Sampling (SRC-B): fs=12kHz
Passband
±0.1dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay (Note 34)
Up Sampling (SRC-B): fs=16kHz
Passband
±0.1dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay (Note 34)
Up Sampling (SRC-B): fs=22.05kHz
Passband
±0.1dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay (Note 34)
Up Sampling (SRC-B): fs=24kHz
Passband
±0.1dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay (Note 34)
Note 34.
Symbol
min
typ
max
Units
PB
SB
PR
SA
GD
0
4.7
68
-
2
3.1
±0.1
-
kHz
kHz
dB
dB
ms
PB
SB
PR
SA
GD
0
4.7
68
-
2
3.1
±0.1
-
kHz
kHz
dB
dB
ms
PB
SB
PR
SA
GD
0
4.7
68
-
2
3.1
±0.1
-
kHz
kHz
dB
dB
ms
PB
SB
PR
SA
GD
0
4.7
68
-
2
3.1
±0.1
-
kHz
kHz
dB
dB
ms
PB
SB
PR
SA
GD
0
4.7
68
-
2
3.1
±0.1
-
kHz
kHz
dB
dB
ms
PB
SB
PR
SA
GD
16bit
0
4.7
68
-
2
3.1
±0.1
-
kHz
kHz
dB
dB
ms
MS0666-J-02
2010/06
- 15 -
[AK4671]
Parameter
Up Sampling (SRC-B): fs=32kHz
Passband
±0.1dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay (Note 34)
Up Sampling (SRC-B): fs=44.1kHz
Passband
±0.1dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay (Note 34)
Up Sampling (SRC-B): fs=48kHz
Passband
±0.1dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay (Note 34)
Note 34.
Symbol
min
typ
max
Units
PB
SB
PR
SA
GD
0
4.7
68
-
2
3.1
±0.1
-
kHz
kHz
dB
dB
ms
PB
SB
PR
SA
GD
0
4.7
68
-
2
3.1
±0.1
-
kHz
kHz
dB
dB
ms
PB
SB
PR
SA
GD
16bit
0
4.7
68
-
2
3.1
±0.1
-
kHz
kHz
dB
dB
ms
MS0666-J-02
2010/06
- 16 -
[AK4671]
DC
(Ta=25°C; AVDD=PVDD =SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2 =TVDD3=1.6 ∼ 3.6V)
Parameter
Symbol
min
Typ
High-Level Input Voltage 1
2.2V≤DVDD≤3.6V
VIH1
70%DVDD
(Note 35)
1.6V≤DVDD<2.2V
VIH1
80%DVDD
Low-Level Input Voltage 1
2.2V≤DVDD≤3.6V
VIL1
(Note 35)
1.6V≤DVDD<2.2V
VIL1
High-Level Input Voltage 2
2.2V≤TVDD2≤3.6V
VIH2
70%TVDD2
(Note 36)
1.6V≤TVDD2<2.2V
VIH2
80%TVDD2
Low-Level Input Voltage 2
2.2V≤TVDD2≤3.6V
VIL2
(Note 36)
1.6V≤TVDD2<2.2V
VIL2
High-Level Input Voltage 3
2.2V≤TVDD3≤3.6V
VIH3
70%TVDD3
(Note 37)
1.6V≤TVDD3<2.2V
VIH3
80%TVDD3
Low-Level Input Voltage 3
2.2V≤TVDD3≤3.6V
VIL3
(Note 37)
1.6V≤TVDD3<2.2V
VIL3
High-Level Output Voltage
(Note 38) (Iout=−200μA) VOH1
DVDD−0.2
(Note 39) (Iout=−200μA) VOH2
TVDD2−0.2
(Note 40) (Iout=−200μA) VOH3
TVDD3−0.2
Low-Level Output Voltage
(Except SDA pin: Iout=200μA) VOL1
(SDA pin, 2.0V≤DVDD≤3.6V: Iout=3mA) VOL2
(SDA pin, 1.6V≤DVDD<2.0V: Iout=3mA) VOL2
Input Leakage Current
(Note 41)
Iind
(Note 42)
Iina
-
max
30%DVDD
20%DVDD
30%TVDD2
20%TVDD2
30%TVDD3
20%TVDD3
Units
V
V
V
V
V
V
V
V
V
V
V
V
-
V
V
V
0.2
0.4
20%DVDD
V
V
V
±2
±2
μA
μA
Note 35. CSN/CAD0, CCLK/SCL, CDTI/SDA, I2C, PDN, BICK, LRCK, SDTI, MCKI pins.
Note 36. BICKA, SYNCA, SDTIA pins.
Note 37. BICKB, SYNCB, SDTIB pins.
Note 38. MCKO, BICK, LRCK, SDTO, CDTO, GPO1, GPO2 pins.
Note 39. BICKA, SYNCA, SDTOA pins.
Note 40. BICKB, SYNCB, SDTOB pins.
Note 41. SYNCB, BICKB, SDTIB, SDTI, LRCK, MCKI, BICK, CSN/CAD0, CCLK/SCL, CDTI/SDA, SDTIA, BICKA,
SYNCA pins. I/O pin (SYNCB, BICKB, LRCK, BICK, SDA, BICKA, SYNCA) Input
Note 42. SAIN1, SAIN2, SAIN3 pins.
MS0666-J-02
2010/06
- 17 -
[AK4671]
(Ta=25°C; AVDD=PVDD =SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2 =TVDD3=1.6 ∼ 3.6V; CL=20pF (except SDA pin) or
400pF (SDA pin); unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
MHz
Pulse Width Low
tCLKL
0.4/fCLK
ns
Pulse Width High
tCLKH
0.4/fCLK
ns
MCKO Output Timing
Frequency
fMCK
0.256
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz
dMCK
40
50
60
%
256fs at fs=32kHz
dMCK
33
%
LRCK Output Timing
Frequency
fs
8
48
kHz
DSP Mode: Pulse Width High
tLRCKH
tBCK
ns
Except DSP Mode: Duty Cycle
Duty
50
%
BICK Output Timing
Period
BCKO bit = “0”
tBCK
1/(32fs)
ns
BCKO bit = “1”
tBCK
1/(64fs)
ns
Duty Cycle
dBCK
50
%
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
MHz
Pulse Width Low
tCLKL
0.4/fCLK
ns
Pulse Width High
tCLKH
0.4/fCLK
ns
MCKO Output Timing
Frequency
fMCK
0.256
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
%
256fs at fs=32kHz, 29.4kHz
dMCK
33
%
LRCK Input Timing
Frequency
fs
8
48
kHz
DSP Mode: Pulse Width High
tLRCKH
tBCK−60
1/fs − tBCK
ns
Except DSP Mode: Duty Cycle
Duty
45
55
%
BICK Input Timing
Period
tBCK
1/(64fs)
1/(32fs)
ns
Pulse Width Low
tBCKL
0.4 x tBCK
ns
Pulse Width High
tBCKH
0.4 x tBCK
ns
MS0666-J-02
2010/06
- 18 -
[AK4671]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
PLL3-0 bits = “0011”
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Slave Mode
MCKI Input Timing
Frequency
256fs
fCLK
384fs
fCLK
512fs
fCLK
768fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Input Timing
Frequency
256fs/384fs
fs
512fs/768fs
fs
1024fs
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Master Mode
MCKI Input Timing
Frequency
256fs
fCLK
384fs
fCLK
512fs
fCLK
768fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Output Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Output Timing
Period
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
MS0666-J-02
min
typ
max
Units
8
tBCK−60
45
-
48
1/fs − tBCK
55
kHz
ns
%
1/(64fs)
130
130
-
1/(32fs)
-
ns
ns
ns
8
tBCK−60
45
-
48
1/fs − tBCK
55
kHz
ns
%
0.4 x tBCK
0.4 x tBCK
1/(32fs)
1/(64fs)
-
-
ns
ns
ns
ns
2.048
3.072
4.096
6.144
8.192
0.4/fCLK
0.4/fCLK
-
12.288
18.432
13.312
19.968
13.312
-
MHz
MHz
MHz
MHz
MHz
ns
ns
8
8
8
tBCK−60
45
-
48
26
13
1/fs − tBCK
55
kHz
kHz
kHz
ns
%
312.5
130
130
-
-
ns
ns
ns
2.048
3.072
4.096
6.144
8.192
0.4/fCLK
0.4/fCLK
-
12.288
18.432
13.312
19.968
13.312
-
MHz
MHz
MHz
MHz
MHz
ns
ns
8
-
tBCK
50
48
-
kHz
ns
%
-
1/(32fs)
1/(64fs)
50
-
ns
ns
%
2010/06
- 19 -
[AK4671]
Parameter
Symbol
Audio Interface Timing (DSP Mode)
Master Mode
tDBF
LRCK “↑” to BICK “↑” (Note 43)
tDBF
LRCK “↑” to BICK “↓” (Note 44)
tBSD
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
BICK “↓” to SDTO (BCKP bit = “1”)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
tLRB
LRCK “↑” to BICK “↑” (Note 43)
tLRB
LRCK “↑” to BICK “↓” (Note 44)
tBLR
BCLK “↑” to LRCK “↑” (Note 43)
tBLR
BICK “↓” to LRCK “↑” (Note 44)
tBSD
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
BICK “↓” to SDTO (BCKP bit = “1”)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Audio Interface Timing (Right/Left justified & I2S)
Master Mode
tMBLR
BICK “↓” to LRCK Edge (Note 45)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
tLRB
LRCK Edge to BICK “↑” (Note 45)
tBLR
BICK “↑” to LRCK Edge (Note 45)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Note 43. MSBS, BCKP bits = “00” or “11”.
Note 44. MSBS, BCKP bits = “01” or “10”.
Note 45.
LRCK
BICK
min
typ
max
Units
0.5 x tBCK − 40
0.5 x tBCK − 40
−70
−70
50
50
0.5 x tBCK
0.5 x tBCK
-
0.5 x tBCK + 40
0.5 x tBCK + 40
70
70
-
ns
ns
ns
ns
ns
ns
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
50
50
-
80
80
-
ns
ns
ns
ns
ns
ns
ns
ns
−40
−70
-
40
70
ns
ns
−70
50
50
-
70
-
ns
ns
ns
50
50
-
-
80
ns
ns
ns
50
50
-
80
-
ns
ns
ns
“↑”
MS0666-J-02
2010/06
- 20 -
[AK4671]
Parameter
Symbol
min
PCM Interface Timing (BICKA, SYNCA, SDTIA, SDTOA pins; Slave Mode):
SYNCA Timing
Frequency
fs2
Serial Interface Timing at Short/long Frame Sync
BICKA Frequency
fBCK2
128
BICKA Period
tBCK2
488
BICKA Pulse Width Low
tBCKL2
200
Pulse Width High
tBCKH2
200
tSYB2
50
SYNCA Edge to BICKA “↓” (Note 46)
tSYB2
50
SYNCA Edge to BICKA “↑” (Note 47)
tBSY2
50
BICKA “↓” to SYNCA Edge (Note 46)
tBSY2
50
BICKA “↑” to SYNCA Edge (Note 47)
SYNCA to SDTOA (MSB) (Except Short Frame)
tSYD2
tBSD2
BICKA “↑” to SDTOA (BCKPA bit = “0”)
tBSD2
BICKA “↓” to SDTOA (BCKPA bit = “1”)
SDTIA Hold Time
tSDH2
50
SDTIA Setup Time
tSDS2
50
SYNCA Pulse Width Low
tSYL2
0.8 x tBCK2
Pulse Width High
tSYH2
0.8 x tBCK2
Serial Interface Timing at MSB justified and I2S
BICKA Frequency
fBCK2
256
BICKA Period
tBCK2
488
BICKA Pulse Width Low
tBCKL2
200
Pulse Width High
tBCKH2
200
tSYB2
50
SYNCA Edge to BICKA “↑”
tBSY2
50
BICKA “↑” to SYNCA Edge
SYNCA to SDTOA (MSB) (Except I2S mode)
tSYD2
tBSD2
BICKA “↓” to SDTOA
SDTIA Hold Time
tSDH2
50
SDTIA Setup Time
tSDS2
50
SYNCA Duty Cycle
dSYC2
45
typ
max
Units
8
-
kHz
-
2048
80
80
80
-
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
2048
80
80
55
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
Note 46. MSBSA, BCKPA bits = “00” or “11”.
Note 47. MSBSA, BCKPA bits = “01” or “10”.
MS0666-J-02
2010/06
- 21 -
[AK4671]
Parameter
Symbol
min
PCM Interface Timing (BICKA, SYNCA, SDTIA, SDTOA pins; Master Mode):
SYNCA Timing
Frequency
fs2
BICKA Timing
Period (BCKO2 bit = “0”)
tBCK2
(BCKO2 bit = “1”)
tBCK2
Duty Cycle
dBCK2
Serial Interface Timing at Short/long Frame Sync
0.5 x tBCK2 − 40
tSYB2
SYNCA Edge to BICKA “↓” (Note 46)
0.5 x tBCK2 − 40
tSYB2
SYNCA Edge to BICKA “↑” (Note 47)
tBSD2
BICKA “↑” to SDTOA (BCKPA bit = “0”)
−70
tBSD2
BICKA “↓” to SDTOA (BCKPA bit = “1”)
−70
SDTIA Hold Time
tSDH2
50
SDTIA Setup Time
tSDS2
50
SYNCA Pulse Width High
tSYH2
Serial Interface Timing at MSB justified and I2S
tMBSY2
BICKA “↓” to SYNCA Edge
−40
SYNCA to SDTOA (MSB) (Except I2S mode)
tSYD2
−70
tBSD2
BICKA “↓” to SDTOA
−70
SDTIA Hold Time
tSDH2
50
SDTIA Setup Time
tSDS2
50
SYNCA Duty Cycle
dSYC2
-
typ
max
Units
8
-
kHz
1/(16fs2)
1/(32fs2)
50
-
ns
ns
%
0.5 x tBCK2
0.5 x tBCK2 + 40
0.5 x tBCK2
0.5 x tBCK2 + 40
tBCK2
70
70
-
ns
ns
ns
ns
ns
ns
ns
50
40
70
70
-
ns
ns
ns
ns
ns
%
Note 46. MSBSA, BCKPA bits = “00” or “11”.
Note 47. MSBSA, BCKPA bits = “01” or “10”.
MS0666-J-02
2010/06
- 22 -
[AK4671]
Parameter
Symbol
min
PCM Interface Timing (BICKB, SYNCB, SDTIB, SDTOB pins; Slave Mode):
SYNCB Timing
Frequency
fs2
Serial Interface Timing at Short/long Frame Sync
BICKB Frequency
fBCK3
128
BICKB Period
tBCK3
488
BICKB Pulse Width Low
tBCKL3
200
Pulse Width High
tBCKH3
200
tSYB3
50
SYNCB Edge to BICKB “↓” (Note 48)
tSYB3
50
SYNCB Edge to BICKB “↑” (Note 49)
tBSY3
50
BICKB “↓” to SYNCB Edge (Note 48)
tBSY3
50
BICKB “↑” to SYNCB Edge (Note 49)
SYNCB to SDTOB (MSB) (Except Short Frame)
tSYD3
tBSD3
BICKB “↑” to SDTOB (BCKPB bit = “0”)
tBSD3
BICKB “↓” to SDTOB (BCKPB bit = “1”)
SDTIB Hold Time
tSDH3
50
SDTIB Setup Time
tSDS3
50
SYNCB Pulse Width Low
tSYL3
0.8 x tBCK3
Pulse Width High
tSYH3
0.8 x tBCK3
Serial Interface Timing at MSB justified and I2S
BICKB Frequency
fBCK3
256
BICKB Period
tBCK3
488
BICKB Pulse Width Low
tBCKL3
200
Pulse Width High
tBCKH3
200
tSYB3
50
SYNCB Edge to BICKB “↑”
tBSY3
50
BICKB “↑” to SYNCB Edge
SYNCB to SDTOB (MSB) (Except I2S mode)
tSYD3
tBSD3
BICKB “↓” to SDTOB
SDTIB Hold Time
tSDH3
50
SDTIB Setup Time
tSDS3
50
SYNCB Duty Cycle
dSYC3
45
typ
max
Units
8
-
kHz
-
2048
80
80
80
-
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
2048
80
80
55
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
Note 48. MSBSB, BCKPB bits = “00” or “11”.
Note 49. MSBSB, BCKPB bits = “01” or “10”.
MS0666-J-02
2010/06
- 23 -
[AK4671]
Parameter
Symbol
min
PCM Interface Timing (BICKB, SYNCB, SDTIB, SDTOB pins; Master Mode):
SYNCB Timing
Frequency
fs2
BICKB Timing
Period (BCKO2 bit = “0”)
tBCK3
(BCKO2 bit = “1”)
tBCK3
Duty Cycle
dBCK3
Serial Interface Timing at Short/long Frame Sync
0.5 x tBCK3 − 40
tSYB3
SYNCB Edge to BICKB “↓” (Note 48)
0.5 x tBCK3 − 40
tSYB3
SYNCB Edge to BICKB “↑” (Note 49)
tBSD3
BICKB “↑” to SDTOB (BCKPB bit = “0”)
−70
tBSD3
BICKB “↓” to SDTOB (BCKPB bit = “1”)
−70
SDTIB Hold Time
tSDH3
50
SDTIB Setup Time
tSDS3
50
SYNCB Pulse Width High
tSYH3
Serial Interface Timing at MSB justified and I2S
tMBSY3
BICKB “↓” to SYNCB Edge
−40
SYNCB to SDTOB (MSB) (Except I2S mode)
tSYD3
−70
tBSD3
BICKB “↓” to SDTOB
−70
SDTIB Hold Time
tSDH3
50
SDTIB Setup Time
tSDS3
50
SYNCB Duty Cycle
dSYC3
-
typ
max
Units
8
-
kHz
1/(16fs2)
1/(32fs2)
50
-
ns
ns
%
0.5 x tBCK3
0.5 x tBCK3 + 40
0.5 x tBCK3
0.5 x tBCK3 + 40
tBCK3
70
70
-
ns
ns
ns
ns
ns
ns
ns
50
40
70
70
-
ns
ns
ns
ns
ns
%
Note 48. MSBSB, BCKPB bits = “00” or “11”.
Note 49. MSBSB, BCKPB bits = “01” or “10”.
MS0666-J-02
2010/06
- 24 -
[AK4671]
Parameter
Control Interface Timing (4-wire Serial mode)
CCLK Period (Note 51)
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN Edge to CCLK “↑” (Note 52)
CCLK “↑” to CSN Edge (Note 52)
CDTO Delay
CSN “↑” to CDTO Hi-Z
Control Interface Timing (I2C Bus mode): (Note 50)
SCL Clock Frequency (Note 53)
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 54)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width (Note 55)
PMADL or PMADR “↑” to SDTO valid (Note 56)
PMSRA “↑” to SDTOA valid (Note 57)
PMSRB “↑” to SDTO valid (Note 58)
Symbol
min
typ
max
Units
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
40
40
150
50
50
-
-
33000
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
tSP
30
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
tPD
tPDV
tPDV2
tPDV3
150
-
1059
21
135
-
ns
1/fs
1/fs2
1/fs
Note 50. I2C-bus NXP B.V.
Note 51. 4-wire Serial Mode
SAR ADC
(CCLK)
(Figure 97)
Note 52.
CSN
CCLK “↑”
Note 53. I2C Bus Mode SAR ADC
ACK
(Figure 104)
Note 54.
300ns (SCL
)
Note 55. AK4671 PDN pin = “L”
Note 56. PMSRB bit = “0”
PMADL bit
PMADR bit
Note 57. PLLBT
Note 58. SDTIA pin
SDTI pin
SRC-B
SRC-A
10bit
2
(SCL)
LRCK
“↑”
SDTOA pin
SDTO pin
MS0666-J-02
2010/06
- 25 -
[AK4671]
■
1/fCLK
VIH1
MCKI
VIL1
tCLKH
tCLKL
1/fs
50%DVDD
LRCK
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
50%DVDD
BICK
tBCKH
tBCKL
dBCK = tBCKH / tBCK x 100
tBCKL / tBCK x 100
1/fMCK
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 3. Clock Timing (PLL/EXT Master mode)
Note 59. MCKO is not available at EXT Master mode.
tLRCKH
LRCK
50%DVDD
tDBF
BICK
(BCKP = "0")
50%DVDD
BICK
(BCKP = "1")
50%DVDD
tBSD
SDTO
MSB
tSDS
50%DVDD
tSDH
VIH1
SDTI
VIL1
Figure 4. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “0”)
MS0666-J-02
2010/06
- 26 -
[AK4671]
tLRCKH
LRCK
50%DVDD
tDBF
BICK
(BCKP = "1")
50%DVDD
BICK
(BCKP = "0")
50%DVDD
tBSD
SDTO
50%DVDD
MSB
tSDS
tSDH
VIH1
SDTI
VIL1
Figure 5. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “1”)
50%DVDD
LRCK
tMBLR
BICK
50%DVDD
tLRD
tBSD
SDTO
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 6. Audio Interface Timing (PLL/EXT Master mode, Except DSP mode)
MS0666-J-02
2010/06
- 27 -
[AK4671]
1/fs
VIH1
LRCK
VIL1
tLRCKH
tBLR
tBCK
VIH1
BICK
(BCKP = "0")
VIL1
tBCKH
tBCKL
VIH1
BICK
(BCKP = "1")
VIL1
Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “0”)
1/fs
VIH1
LRCK
VIL1
tLRCKH
tBLR
tBCK
VIH1
BICK
(BCKP = "1")
VIL1
tBCKH
tBCKL
VIH1
BICK
(BCKP = "0")
VIL1
Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “1”)
MS0666-J-02
2010/06
- 28 -
[AK4671]
1/fCLK
VIH1
MCKI
VIL1
tCLKH
tCLKL
1/fs
VIH1
LRCK
VIL1
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
VIH1
BICK
VIL1
tBCKH
tBCKL
1/fMCK
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 9. Clock Timing (PLL Slave mode; Except DSP mode)
tLRCKH
VIH1
LRCK
VIL1
tLRB
VIH1
BICK
VIL1
(BCKP = "0")
VIH1
BICK
(BCKP = "1")
VIL1
tBSD
SDTO
MSB
tSDS
50%DVDD
tSDH
VIH1
SDTI
MSB
VIL1
Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = “0”)
MS0666-J-02
2010/06
- 29 -
[AK4671]
tLRCKH
VIH1
LRCK
VIL1
tLRB
VIH1
BICK
VIL1
(BCKP = "1")
VIH1
BICK
(BCKP = "0")
VIL1
tBSD
SDTO
50%DVDD
MSB
tSDS
tSDH
VIH1
SDTI
MSB
VIL1
Figure 11. Audio Interface Timing (PLL Slave mode, DSP mode, MSBS = “1”)
1/fCLK
VIH1
MCKI
VIL1
tCLKH
tCLKL
1/fs
VIH1
LRCK
VIL1
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCK
VIH1
BICK
VIL1
tBCKH
tBCKL
Figure 12. Clock Timing (EXT Slave mode)
MS0666-J-02
2010/06
- 30 -
[AK4671]
VIH1
LRCK
VIL1
tLRB
tBLR
VIH1
BICK
VIL1
tBSD
tLRD
SDTO
50%DVDD
MSB
tSDH
tSDS
VIH1
SDTI
VIL1
Figure 13. Audio Interface Timing (PLL/EXT Slave mode, Except DSP mode)
1/fs2
VIH2
SYNCA
VIL2
tSYH2
tSYL2
dSYC2 = tSYH2 x fs2 x 100
tSYL2 x fs2 x 100
tBC K2 = 1/fBC K2
VIH 2
VIL2
BIC KA
tBC KH 2
tBC KL2
Figure 14. Clock Timing of PCM I/F A (Slave mode)
MS0666-J-02
2010/06
- 31 -
[AK4671]
VIH2
SYNCA
VIL2
tBSY2
tSYB2
VIH2
BICKA
VIL2
(BCKPA = “0”)
VIH2
BICKA
VIL2
(BCKPA = “1”)
tSYD2
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 15. PCM I/F A Timing at short and long frame sync (Slave mode; MSBSA = “0”)
VIH2
SYNCA
VIL2
tBSY2
tSYB2
VIH2
BICKA
VIL2
(BCKPA = “1”)
VIH2
BICKA
(BCKPA = “0”)
VIL2
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 16. PCM I/F A Timing at short and long frame sync (Slave mode; MSBSA = “1”)
MS0666-J-02
2010/06
- 32 -
[AK4671]
VIH2
SYNCA
VIL2
tBSY2
tSYB2
VIH2
BICKA
VIL2
tSYD2
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 17. PCM I/F A Timing at MSB justified and I2S (Slave mode)
1/fs2
50%TVDD2
SYNCA
tSYH2
tSYL2
dSYC2 = tSYL2 x fs2 x 100
tBC K2 = 1/fBC K2
50% T VD D 2
BIC KA
tBC KH 2
tBC KL2
dBC K2 = tBC KL2 / tBC K2 x 100
Figure 18. Clock Timing of PCM I/F A (Master mode)
MS0666-J-02
2010/06
- 33 -
[AK4671]
SYNCA
50%TVDD2
tSYB2
BICKA
(BCKPA = “0”)
50%TVDD2
BICKA
50%TVDD2
(BCKPA = “1”)
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 19. PCM I/F A Timing at short and long frame sync (Master mode; MSBSA = “0”)
SYNCA
50%TVDD2
tSYB2
50%TVDD2
BICKA
(BCKPA = “1”)
50%TVDD2
BICKA
(BCKPA = “0”)
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 20. PCM I/F A Timing at short and long frame sync (Master mode; MSBSA = “1”)
MS0666-J-02
2010/06
- 34 -
[AK4671]
50%TVDD2
SYNCA
tMBSY2
50%TVDD2
BICKA
tSYD2
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 21. PCM I/F A Timing at MSB justified and I2S (Master mode)
1/fs2
VIH3
SYNCB
VIL3
tSYH3
tSYL3
dSYC3 = tSYH3 x fs2 x 100
tSYL3 x fs2 x 100
tBC K3 = 1/fBC K3
VIH 3
VIL3
BIC KB
tBC KH 3
tBC KL3
Figure 22. Clock Timing of PCM I/F B (Slave mode)
MS0666-J-02
2010/06
- 35 -
[AK4671]
VIH3
SYNCB
VIL3
tBSY3
tSYB3
VIH3
BICKB
VIL3
(BCKPB = “0”)
VIH3
BICKB
VIL3
(BCKPB = “1”)
tSYD3
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 23. PCM I/F B Timing at short and long frame sync (Slave mode; MSBSB = “0”)
VIH3
SYNCB
VIL3
tBSY3
tSYB3
VIH3
BICKB
VIL3
(BCKPB = “1”)
VIH3
BICKB
(BCKPB = “0”)
VIL3
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 24. PCM I/F B Timing at short and long frame sync (Slave mode; MSBSB = “1”)
MS0666-J-02
2010/06
- 36 -
[AK4671]
VIH3
SYNCB
VIL3
tBSY3
tSYB3
VIH3
BICKB
VIL3
tSYD3
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 25. PCM I/F B Timing at MSB justified and I2S (Slave mode)
1/fs2
50%TVDD3
SYNCB
tSYH3
tSYL3
dSYC3 = tSYL3 x fs2 x 100
tBC K3 = 1/fBC K3
50% T VD D 3
BIC KB
tBC KH 3
tBC KL3
dBC K3 = tBC KL3 / tBC K3 x 100
Figure 26. Clock Timing of PCM I/F B (Master mode)
MS0666-J-02
2010/06
- 37 -
[AK4671]
SYNCB
50%TVDD3
tSYB3
50%TVDD3
BICKB
(BCKPB = “0”)
50%TVDD3
BICKB
(BCKPB = “1”)
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 27. PCM I/F B Timing at short and long frame sync (Master mode; MSBSB = “0”)
SYNCB
50%TVDD3
tSYB3
50%TVDD3
BICKB
(BCKPB = “1”)
50%TVDD3
BICKB
(BCKPB = “0”)
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 28. PCM I/F B Timing at short and long frame sync (Master mode; MSBSB = “1”)
MS0666-J-02
2010/06
- 38 -
[AK4671]
50%TVDD3
SYNCB
tMBSY3
50%TVDD3
BICKB
tSYD3
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 29. PCM I/F B Timing at MSB justified and I2S (Master mode)
VIH1
CSN
VIL1
tCSH
tCCKL
tCSS
tCCKH
VIH1
CCLK
VIL1
tCCK
tCDH
tCDS
VIH1
CDTI
CDTO
C1
C0
R/W
VIL1
Hi-Z
Figure 30. WRITE Command Input Timing
MS0666-J-02
2010/06
- 39 -
[AK4671]
tCSW
VIH1
CSN
VIL1
tCSS
tCSH
VIH1
CCLK
VIL1
VIH1
CDTI
D2
D1
D0
VIL1
Hi-Z
CDTO
Figure 31. WRITE Data Input Timing
VIH1
CSN
VIL1
VIH1
CCLK
VIL1
VIH1
CDTI
A1
A0
VIL1
tDCD
CDTO
Hi-Z
D7
Figure 32. READ
D6
50%DVDD
1
MS0666-J-02
2010/06
- 40 -
[AK4671]
tCSW
VIH1
CSN
VIL1
tCSH
VIH1
CCLK
VIL1
VIH1
CDTI
VIL1
tCCZ
CDTO
D2
D1
Hi-Z
D0
Figure 33. READ
50%DVDD
2
VIH1
SDA
VIL1
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH1
SCL
VIL1
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
Start
tSU:STO
Stop
Figure 34. I2C
MS0666-J-02
2010/06
- 41 -
[AK4671]
PMADL bit
or
PMADR bit
tPDV
SDTO
50%DVDD
Figure 35. Power Down & Reset Timing 1
tPD
PDN
VIL1
Figure 36. Power Down & Reset Timing 2
PMSRA bit
tPDV2
SDTOA
50%TVDD2
Figure 37. Power Down & Reset Timing 3
PMSRB bit
tPDV3
SDTO
50%DVDD
Figure 38. Power Down & Reset Timing 4
MS0666-J-02
2010/06
- 42 -
[AK4671]
■
(Audio I/F)
I/F mode
5
(Table 1 and Table 2)
Mode
PLL Master Mode (Note 60)
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: LRCK or BICK pin)
EXT Slave Mode
EXT Master Mode
Note 60. PLL Master Mode
PMPLL bit
1
M/S bit
1
PLL3-0 bits
See Table 4
Figure
Figure 39
1
0
See Table 4
Figure 40
1
0
See Table 4
0
0
x
0
1
x
M/S bit = “1”, PMPLL bit = “0”, MCKO bit = “1”
Figure 41
Figure 42
Figure 43
Figure 44
MCKO pin
Table 1. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
0
PLL Master Mode
1
0
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
1
MCKO pin
L
PS1-0 bits
MCKI pin
PLL3-0 bits
L
PS1-0 bits
PLL3-0 bits
GND
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
0
L
EXT Slave Mode
0
L
EXT Master Mode
0
L
FS1-0 bits
FS1-0 bits
BICK pin
Output
(BCKO bit
)
LRCK pin
Input
(≥ 32fs)
Input
(1fs)
Input
(PLL3-0
bits
)
Input
(≥ 32fs)
Output
(BCKO bit
)
Output
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
Table 2. Clock pins state in Clock Mode
■
M/S bit
(PDN pin = “L”)
AK4671
M/S bit
“0”
“1”
M/S bit
AK4671
“1”
“1”
AK4671 LRCK, BICK pins
100kΩ
LRCK, BICK pins
Hi-Z
M/S bit
Mode
0
Slave Mode
(default)
1
Master Mode
Table 3. Select Master/Slave Mode
MS0666-J-02
2010/06
- 43 -
[AK4671]
■ PLL Mode (PMPLL bit = “1”)
PMPLL bit = “1”
PLL
PLL FS3-0 bit, PLL3-0 bit
PMPLL bit “0” Æ “1”
Table 4
1) PLL Mode
PLL
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
0
0
0
0
0
LRCK pin
1fs
2
0
0
1
0
BICK pin
32fs
3
0
0
1
1
BICK pin
64fs
4
5
6
7
8
12
13
14
15
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
0
0
1
0
1
VCOC pin
R,C
R[Ω] C[F]
6.8k
220n
10k
4.7n
10k
10n
10k
4.7n
10k
10n
10k
4.7n
10k
4.7n
10k
10n
10k
10n
10k
4.7n
10k
10n
10k
10n
10k
220n
10k
220n
MCKI pin
11.2896MHz
MCKI pin
12.288MHz
MCKI pin
12MHz
MCKI pin
24MHz
MCKI pin
19.2MHz
MCKI pin
13.5MHz
MCKI pin
27MHz
MCKI pin
13MHz
MCKI pin
26MHz
Others
N/A
Table 4. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)
Others
PLL
(max)
160ms
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
40ms
40ms
40ms
60ms
60ms
(default)
2) PLL Mode
Mode
0
1
2
3
5
7
10
11
15
Others
MCKI
FS3 bit
0
0
0
0
0
0
1
1
1
Table 5
FS2 bit
FS1 bit
0
0
0
0
0
1
0
1
1
0
1
1
0
1
0
1
1
1
Others
Sampling Frequency
8kHz
12kHz
16kHz
24kHz
11.025kHz
22.05kHz
32kHz
48kHz
44.1kHz
(default)
N/A
(N/A: Not available)
Table 5. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = MCKI pin)
MS0666-J-02
FS0 bit
0
1
0
1
1
1
0
1
1
2010/06
- 44 -
[AK4671]
LRCK or BICK
(Table 6)
Mode
0
1
2
Others
FS3 bit
0
0
1
FS3-2 bits
FS2 bit
0
1
FS1 bit
FS0 bit
x
x
x
x
x
x
Sampling Frequency Range
8kHz ≤ fs ≤ 12kHz
12kHz < fs ≤ 24kHz
x
(default)
24kHz < fs ≤ 48kHz
Others
N/A
(x: Don’t care, N/A: Not available)
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin)
■ PLL
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PMPLL bit = “0” Æ “1”
MCKO pin
“L”
(Table 7)
bit = “1”
MCKO pin
PLL
BICK
LRCK
PLL
BICK
“L”
LRCK “L”
MCKO bit = “0”
1
MCKO
LRCK, BICK
1fs
PMPLL bit = “0”
LRCK
BICK,
“L”
MCKO pin
BICK pin
LRCK pin
MCKO bit = “0”
MCKO bit = “1”
“L” Output
“L” Output
“L” Output
PMPLL bit “0” Æ “1”
“L” Output
PLL Unlock (
)
“L” Output
1fs Output
See Table 9
See Table 10
PLL Lock
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PLL State
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
PMPLL bit = “0” Æ “1”
PLL
MCKO
Table 9
PLL
MCKO pin
PLL
Stereo ADC
Stereo DAC
Stereo DAC
DACL, DACR, DACH, DACS bits “0”
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
PMPLL bit “0” Æ “1”
“L” Output
PLL Unlock (
)
“L” Output
Output
PLL Lock
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PLL State
MS0666-J-02
2010/06
- 45 -
[AK4671]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz
PLL
MCKO, BICK, LRCK
(MCKO)
PS1-0 bit (Table 9)
MCKO bit ON/OFF
BICK
BCKO bit
32fs or 64fs
(Table 10)
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
DSP or μP
AK4671
MCKI
256fs/128fs/64fs/32fs
MCKO
32fs, 64fs
BICK
1fs
LRCK
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 39. PLL Master Mode
Mode
0
1
2
3
PS1 bit
0
0
1
1
Table 9. MCKO
PS0 bit
MCKO pin
0
256fs
(default)
1
128fs
0
64fs
1
32fs
(PLL mode, MCKO bit = “1”)
BCKO bit
BICK
0
32fs
(default)
1
64fs
Table 10. BICK Output Frequency at Master Mode
MS0666-J-02
2010/06
- 46 -
[AK4671]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
MCKI, BICK or LRCK pin
PLL
PLL
a) PLL
: MCKI pin
MCKO
BICK, LRCK
bit
MCKO LRCK
(MCKO pin) PS1-0 bit (Table 9)
FS3-0 bit
ON/OFF
Audio I/F
AK4671
(Table 4)
PLL3-0 bit
CODEC
BICK LRCK
(
)
MCKI
MCKO
(Table 5)
CODEC
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
AK4671
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 40. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
MS0666-J-02
2010/06
- 47 -
[AK4671]
b) PLL
: BICK or LRCK pin
8kHz ∼ 48kHz
FS3-0 bit
(Table 6)
AK4671
DSP or μP
MCKO
MCKI
BICK
LRCK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 41. PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
AK4671
DSP or μP
MCKO
MCKI
BICK
LRCK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 42. PLL Slave Mode 2 (PLL Reference Clock: LRCK pin)
Stereo ADC or Stereo DAC
MCKI
(PMADL bit = “1”, PMADR bit = “1”, PMDAL bit = “1” or PMDAR bit = “1”)
MCKI
MCKI
(PMADL=PMADR=PMDAL=PMDAR bits = “0”)
MS0666-J-02
2010/06
- 48 -
[AK4671]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PMPLL bit “0”
Stereo ADC, Stereo DAC
MCKI
FS2-0 bit
Audio I/F
Mode
0
1
4
5
6
7
Others
(EXT Mode)
PLL
CODEC
I/F
MCKI (256fs, 384fs, 512fs, 768fs or 1024fs), BICK (≥32fs), LRCK(fs)
MCKI
(Table 11)
LRCK
CODEC
BICK LRCK
(
)
MCKI pin
MCKI
CODEC
MCKI Input
Sampling Frequency
Frequency
Range
x
0
0
0
256fs
8kHz ∼ 48kHz
x
0
0
1
1024fs
8kHz ∼ 13kHz
x
1
0
0
384fs
8kHz ∼ 48kHz
x
1
0
1
768fs
8kHz ∼ 26kHz
x
1
1
0
512fs
8kHz ∼ 26kHz
x
1
1
1
256fs
(default)
8kHz ∼ 48kHz
Others
N/A
N/A
(x: Don’t care, N/A: Not available)
Table 11. EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
MCKI
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Stereo DAC
S/N
S/N
Table 12 Stereo DAC
MCKI
LOUT1/ROUT1 pins
S/N
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs, 384fs
83dB
512fs, 768fs
93dB
1024fs
93dB
Table 12. Relationship between MCKI and S/N of LOUT1/ROUT1 pins
MCKI
Stereo ADC or Stereo DAC
MCKI
(PMADL bit = “1”, PMADR bit = “1”, PMDAL bit = “1” or PMDAR bit = “1”)
MCKI
MCKI
(PMADL=PMADR=PMDAL=PMDAR bits = “0”)
AK4671
DSP or μP
MCKO
MCKI
BICK
LRCK
256fs, 384fs, 512fs,
768fs or 1024fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 43. EXT Slave Mode
MS0666-J-02
2010/06
- 49 -
[AK4671]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
PMPLL bit = “0”
M/S bit = “1”
MCKI pin
PLL
Stereo ADC, Stereo DAC
MCKI (256fs, 384fs, 512fs, 768fs or 1024fs)
MCKI
(Table 13)
Mode
0
1
4
5
6
7
Others
(EXT Master Mode)
FS2-0 bit
MCKI Input
Sampling Frequency
Frequency
Range
x
0
0
0
256fs
8kHz ∼ 48kHz
x
0
0
1
1024fs
8kHz ∼ 13kHz
x
1
0
0
384fs
8kHz ∼ 48kHz
x
1
0
1
768fs
8kHz ∼ 26kHz
x
1
1
0
512fs
8kHz ∼ 26kHz
x
1
1
1
256fs
(default)
8kHz ∼ 48kHz
Others
N/A
N/A
(x: Don’t care, N/A: Not available)
Table 13. EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
MCKI
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Stereo DAC
S/N
S/N
Table 14 Stereo DAC
MCKI
LOUT1/ROUT1 pins
S/N
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs, 384fs
83dB
512fs, 768fs
93dB
1024fs
93dB
Table 14. Relationship between MCKI and S/N of LOUT1/ROUT1 pins
MCKI
Stereo ADC
MCKI
Stereo DAC
(PMADL bit = “1”, PMADR bit = “1”, PMDAL bit = “1” or PMDAR bit = “1”)
MCKI
MCKI
(PMADL=PMADR=PMDAL=PMDAR bits = “0”)
AK4671
DSP or μP
MCKO
MCKI
BICK
LRCK
256fs, 384fs, 512fs,
768fs or 1024fs
32fs or 64fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 44. EXT Master Mode
BCKO bit
BICK
0
32fs
(default)
1
64fs
Table 15. BICK Output Frequency at Master Mode
MS0666-J-02
2010/06
- 50 -
[AK4671]
■
PDN pin
“L”
AK4671
PMADR bit “0” → “1”
[email protected]=44.1kHz
“0”
ADC
PMDAL bit
PMDAR bit “1”
ADC
PMDAL=PMDAR bits = “0”
ADC
ADC
2’s
PMADL bit
Stereo
■
4
(Table 16)
LRCK
Mode
0
1
2
3
DIF1 bit
0
0
1
1
Mode 1, 2, 3
Mode 0 (DSP mode)
17)
DIF1
0
DIF0
BICK
“−1”
SDTO (ADC)
DSP Mode
SDTI (DAC)
DSP Mode
I2S
I2S
Table 16. Audio Interface Format
“↓”
SDTI
BICK
BCKP, MSBS bit
MSBS
BCKP
0
0
0
1
1
0
1
1
0
ADC
MSB
16bit
8bit
“–256”
2’s
BICK
DIF0 bit
0
1
0
1
SDTO
DIF1-0 bit
Figure
Table 17
Figure 49
Figure 50
Figure 51
(default)
“↑”
I/F
(Table
Audio Interface Format
SDTO MSB
LRCK “↑”
1
BICK
“↑”
BICK “↓” SDTI
MSB
SDTO MSB
LRCK “↑”
1
BICK
“↓”
BICK “↑” SDTI
MSB
SDTO MSB
LRCK “↑”
1
BICK
“↓”
BICK “↑”
BICK
“↓” SDTI MSB
SDTO MSB
LRCK “↑”
1
BICK
“↑”
BICK “↓”
BICK
“↑” SDTI MSB
Table 17. Audio Interface Format in Mode 0
8bit
“−1”
BICK
≥ 32fs
≥ 32fs
≥ 32fs
≥ 32fs
8bit
8bit
16bit
“−1”
Figure
Figure 45
(default)
Figure 46
Figure 47
Figure 48
16bit
16bit
DAC
16bit
(128)
MS0666-J-02
2010/06
- 51 -
[AK4671]
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
46
34
47
48
49
50
26
27
26
62
63
30
31
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
2
1
0
15 14
1
0
2
1
0
Rch
Lch
SDTI(i)
2
15 14
15 14
1/fs
15:MSB, 0:LSB
Figure 45. Mode 0 Timing (BCKP = “0”, MSBS = “0”)
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
29
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
34
46
47
48
49
50
62
63
BICK(64fs)
Lch
SDTO(o)
15 14
Rch
2
1
0
2
1
0
15 14
2
1
0
2
1
0
Rch
Lch
SDTI(i)
15 14
15 14
1/fs
15:MSB, 0:LSB
Figure 46. Mode 0 Timing (BCKP = “1”, MSBS = “0”)
MS0666-J-02
2010/06
- 52 -
[AK4671]
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
46
34
47
48
49
50
26
27
26
62
63
30
31
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
15 14
Lch
SDTI(i)
2
1
0
2
1
0
Rch
15 14
2
1
0
15 14
1/fs
15:MSB, 0:LSB
Figure 47. Mode 0 Timing (BCKP = “0”, MSBS = “1”)
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
29
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
34
46
47
48
49
50
62
63
BICK(64fs)
Lch
SDTO(o)
15 14
Rch
2
1
0
Lch
SDTI(i)
15 14
15 14
2
1
0
2
1
0
Rch
2
1
0
15 14
1/fs
15:MSB, 0:LSB
Figure 48. Mode 0 Timing (BCKP = “1”, MSBS = “1”)
MS0666-J-02
2010/06
- 53 -
[AK4671]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
SDTI(i)
1 0
15 14 13
15 14 13
15 14
Don't Care
1 0
1 0
Don't Care
15
15 14
2 1 0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 49. Mode 1 Timing
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14 13
1 0
SDTI(i)
15 14 13
1 0
Don't Care
15 14 13
1 0
15 14 13
1 0
15
Don't Care
15
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 50. Mode 2 Timing
MS0666-J-02
2010/06
- 54 -
[AK4671]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
0 15 14
8 7 6 5 4 3 2 1 0 15 14
8 7 6 5 4 3 2 1 0
SDTI(i)
0 15 14
8 7 6 5 4 3 2 1 0 15 14
8 7 6 5 4 3 2 1 0
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14
2 1 0
SDTI(i)
15 14
2 1 0
Don't Care
15 14
2 1 0
15 14
2 1 0
Don't Care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 51. Mode 3 Timing
MS0666-J-02
2010/06
- 55 -
[AK4671]
■
AK4671
pins
MDIF1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
MDIF1, MDIF2, MDIF3, MDIF4 bit = “0”
INL1-0, INR1-0 bits
MIC-Amp
LIN1/LIN2/LIN3/LIN4
RIN1/RIN2/RIN3/RIN4
MDIF1, MDIF2, MDIF3, MDIF4 bit = “1”
LIN1/RIN1, LIN2/RIN2, LIN3/RIN3, LIN4/RIN4
IN1+/−, IN2+/−, IN3+/−, IN4+/− pins
(Figure 53)
MDIF2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
MDIF3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
0
0
0
MDIF4
INL1
INL0
INR1
INR0
Lch
Rch
0
0
0
0
0
LIN1
RIN1
0
0
0
0
1
LIN1
RIN2
0
0
0
1
0
LIN1
RIN3
0
0
0
1
1
LIN1
RIN4
0
0
1
0
0
LIN2
RIN1
0
0
1
0
1
LIN2
RIN2
0
0
1
1
0
LIN2
RIN3
0
0
1
1
1
LIN2
RIN4
0
1
0
0
0
LIN3
RIN1
0
1
0
0
1
LIN3
RIN2
0
1
0
1
0
LIN3
RIN3
0
1
0
1
1
LIN3
RIN4
0
1
1
0
0
LIN4
RIN1
0
1
1
0
1
LIN4
RIN2
0
1
1
1
0
LIN4
RIN3
0
1
1
1
1
LIN4
RIN4
1
0
0
1
1
LIN1
IN4+/−
1
0
1
1
1
LIN2
IN4+/−
1
1
0
1
1
LIN3
IN4+/−
0
1
0
0
0
RIN1
IN3+/−
0
1
0
0
1
RIN2
IN3+/−
0
1
0
1
1
RIN4
IN3+/−
1
1
0
1
1
IN3+/−
IN4+/−
0
0
0
0
1
LIN1
IN2+/−
0
1
0
0
1
LIN3
IN2+/−
0
1
1
0
1
LIN4
IN2+/−
0
1
0
0
1
IN3+/−
IN2+/−
0
0
0
0
1
RIN2
IN1+/−
0
0
0
1
0
RIN3
IN1+/−
0
0
0
1
1
RIN4
IN1+/−
1
0
0
1
1
IN1+/−
IN4+/−
0
0
0
0
1
IN1+/−
IN2+/−
Others
N/A
Table 18. MIC-Amp Input Signal (N/A: Not available)
MS0666-J-02
(default)
2010/06
- 56 -
[AK4671]
AK4671
INL1-0 bits
LIN1/IN1+ pin
ADC Lch
RIN1/IN1− pin
MDIF1 bit MIC-Amp Lch
MDIF3 bit
INR1-0 bits
LIN2/IN2+ pin
ADC Rch
RIN2/IN2− pin
MDIF2 bit MIC-Amp Rch
MDIF4 bit
LIN3/IN3+ pin
RIN3/IN3− pin
LIN4/IN4+ pin
PMLOOPR bit
PMLOOPL bit
PMAINR4 bit
PMAINL4 bit
PMAINR3 bit
PMAINL3 bit
PMAINR2 bit
PMAINL2 bit
PMAINR1 bit
PMAINL1 bit
RIN4/IN4− pin
Lineout
Figure 52.
AK4671
MPWR pin
1k
MIC-Amp
IN1+ pin
IN1− pin
1k
Figure 53.
(MDIF1/2/3/4 bits = “1”)
AK4671
MIC-Amp
IN1+ pin
IN1− pin
Figure 54.
(MDIF1/2/3/4 bits = “1”)
MS0666-J-02
2010/06
- 57 -
[AK4671]
■
AK4671
(Table 19)
MGNL3-0, MGNR3-0 bits
L/R
MGNL/R0 bit = “0”
typ. 42kΩ MGNL/R0 bit = “1”
typ. 30kΩ
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MGNL3
MGNR3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MGNL2
MGNL1
MGNR2
MGNR1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Table 19.
MGNL0
Input Gain
Input Resistance
MGNR0
0
N/A
N/A
1
−12dB
30kΩ
0
−9dB
42kΩ
1
−6dB
30kΩ
0
−3dB
42kΩ
1
0dB
30kΩ
0
+3dB
42kΩ
1
+6dB
30kΩ
0
+9dB
42kΩ
1
+12dB
30kΩ
0
+15dB
42kΩ
1
+18dB
30kΩ
0
+21dB
42kΩ
1
+24dB
30kΩ
0
+27dB
42kΩ
1
+30dB
30kΩ
(N/A: Not available)
MS0666-J-02
(default)
2010/06
- 58 -
[AK4671]
■
PMMP bit = “1”
(typ)
MPWR pin
min. 0.5kΩ
min. 2kΩ
2
(0.8 x AVDD)V
MPWR pin
(Figure 55)
PMMP bit
MPWR pin
0
Hi-Z
1
Output
Table 20.
(default)
MIC Power
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
MPWR pin
Microphone
LIN1 pin
Microphone
RIN1 pin
Microphone
LIN2 pin
Microphone
RIN2 pin
Figure 55. MIC Block Circuit
MS0666-J-02
2010/06
- 59 -
[AK4671]
■
AK4671
:
CPU
(1)
(2) MPWR pin
(3) GPO2 pin (GPOM bit = “1”
21)
MDT pin
MDT pin
Input Level of MDT pin
≥ 0.075 x AVDD
< 0.050 x AVDD
)
PMMP bit = “1”
DTMIC bit
(Table
(typ. 2.2kΩ)
0.075 x AVDD
0V
GPO2 pin
DTMIC bit
H
1
L
0
Table 21. Microphone Detection Result
MPWR
Result
Mic (Headset)
No Mic (Headphone)
PMMP bit
AK4671
LIN1
LIN2
Headset
G
M
R
MDT
L
DTMIC bit
typ.
500k
or
Headphone
G
R
0.075 x AVDD
L
Figure 56. Microphone Power Supply and Mic Detection
MS0666-J-02
2010/06
- 60 -
[AK4671]
■
Figure 57
PMDAL, PMDAR, PMSRA, PMSRB, PMPCM bits)
SDOL/R bits
SVOLA
(PMADL, PMADR,
HPF
MIX
MIX
PFMXL/R bits
PMADL or PMADR
HPF
A/D
HPFAD
PFSEL
PFSEL=0
PMADL
or
PMADR
PFSEL=1
PMDAL
or
PMDAR
or
PMSRA
HPF
HPF
LPF
LPF
Stereo
Separation
5-band
Notch
FIL3, EQ0,
GN1-0
EQ1-5
ALC
ALC, IVL/R
MIX
ADM
SDOL/R1-0 SDOD
SDTO Lch
SDTO Rch
SVAL/R2-0
SVOLA
DAM, MIXD
D/A
PMDAL
or PMDAR
OVL/R
EQ
SRMXL/R1-0
M DATT 5-band
I SMUTE
EQ
X
PMDAL or PMDAR or PMSRA
S
E
L
SDTI Lch
SDTI Rch
SDIM1-0
PFMXL/R1-0
SRA1-0, MIXD
PMPCM
PMSRA
SDOA
SRC-A
SDOAD
SDTOA
SVOLB
SVB2-0
PMSRB
SRC-B
BVMX1-0
DATT-B
SDTIA
BVL7-0
SBMX1-0
DATT-C
CVL7-0
BIV2-0
BIVOL
SDOBD
SDTOB
SDTIB
Figure 57.
MS0666-J-02
2010/06
- 61 -
[AK4671]
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
ADC: “
”
ADC
Digital Filter (LPF)
DAC: “
”
DAC
Digital Filter (LPF)
HPF: High Pass Filter.
(“Digital Programmable Filter
”
LPF : Low Pass Filter (“Digital Programmable Filter
”
)
Stereo Separation:
(“Digital Programmable Filter
”
EQ0 Gain
5-Band Notch: Equalizer
(“Digital Programmable Filter
)
ALC: ALC
(“
”
“ALC
”
SVOLA:
/
(“
”
)
5-Band EQ:
Equalizer
(“5-band Equalizer”
)
DATT:
(“
”
)
SMUTE:
(“
”
)
DATT-B:
(“
”
)
DATT-C: B/T
(“
)
SVOLB: B/T
(“B/T
”
)
PMADL
1
1
0
1
1
0
0
&
ADC
PMADR
1
0
1
1
0
1
0
Table 22.
2nd Order
1st Order
HPF
LPF
PMDAL
0
0
0
1
1
1
1
Stereo
Separation
PMDAR
0
0
0
1
1
1
1
PFSEL
0
0
0
0
0
0
1
Gain
Compensation
Notch
Gain
Compensation
Notch
)
)
”
)
”
Figure
Figure 58
Figure 59
Figure 60
5 Band
ALC
(Volume)
Figure 58.
ADC
DAC
2nd Order
1st Order
HPF
LPF
DEM
SMUTE
Stereo
Separation
DAC
1st Order
EQ
&
“0” Data
HPF
DEM
ALC
(Volume)
5 Band
DATT
Figure 59.
ADC
5 Band
SMUTE
DATT
5 Band
EQ
ALC
(Volume)
5 Band
EQ
Gain
Compensation
Stereo
Separation
1st Order
1st Order
LPF
HPF
Figure 60.
MS0666-J-02
2010/06
- 62 -
[AK4671]
■ Digital Programmable Filter
(1) High Pass Filter (HPF)
HPF
bits
HPF
2
HPF bit
1
HPF
ON/OFF
HPFAD=HPF bits = “0”
HPF 2
F1A13-0 bits
F1B13-0
HPFAD bit
2
HPF OFF
0dB
PMADL = PMADR = PMDAL = PMDAR bits = “0”
ADC
HPF
fs:
fc:
(Note 61)
HPF: F1A[13:0] bits =A, F1B[13:0] bits =B
(MSB=F1A13, F1B13; LSB=F1A0, F1B0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A=
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
1 − z −1
H(z) = A
1 + Bz −1
fc/fs ≥ 0.0001 (fc min = 4.41Hz at 44.1kHz)
(2) Low Pass Filter (LPF)
1
LPF
F2A13-0 bits
F2B13-0 bits
LPF OFF
0dB
PMADL = PMADR = PMDAL = PMDAR bits = “0”
LPF bit
ON/OFF
LPF bit = “0”
fs:
fc:
(Note 61)
LPF: F2A[13:0] bits =A, F2B[13:0] bits =B
(MSB=F2A13, F1B13; LSB=F2A0, F2B0)
1 − 1 / tan (πfc/fs)
1
A=
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
1 + z −1
H(z) = A
1 + Bz −1
fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz)
MS0666-J-02
2010/06
- 63 -
[AK4671]
(3)
(FIL3)
3D
F3A13-0, F3B13-0 bits
FIL3
Low Pass Filter (LPF)
FIL3 bit
bit = “1”
OFF
0dB
PMADL = PMADR = PMDAL = PMDAR bits = “0”
1) FIL3
F3AS bit = “0”
ON/OFF
High Pass Filter (HPF) F3AS
FIL3 bit = “0”
HPF
fs:
fc:
K:
[dB] (0dB ≥ K ≥ −10dB)
(Note 61)
FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F3A13, F3B13; LSB=F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A = 10K/20 x
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
1 − z −1
H(z) = A
2) FIL3
1 + Bz −1
LPF
fs:
fc:
K:
[dB] (0dB ≥ K ≥ −10dB)
(Note 61)
FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F3A13, F3B13; LSB= F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1
A = 10K/20 x
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
1 + z −1
H(z) = A
1 + Bz −1
MS0666-J-02
2010/06
- 64 -
[AK4671]
(4)
F
EQ0
EQ0 bit
(0dB/+12dB/+24dB)
bits (Table 23)
Equalizer (EQ0)
E0A15-0 bits, E0B13-0 bits, E0C15-0 bits
GN1-0
ON/OFF
EQ0 OFF
0dB
EQ0
EQ0 bit = “0”
PMADL =
EQ0
0dB
PMADR = PMDAL = PMDAR bits = “0”
fs:
fc1:
fc2:
K:
[dB] (
+12dB
)
(Note 61)
E0A[15:0] bits =A, E0B[13:0] bits =B, E0C[15:0] bits =C
(MSB=E0A15, E0B13, E0C15; LSB=E0A0, E0B0, E0C0)
A = 10K/20 x
1 − 1 / tan (πfc1/fs)
1 + 1 / tan (πfc2/fs)
,
1 + 1 / tan (πfc1/fs)
B=
,
C =10K/20 x
1 + 1 / tan (πfc1/fs)
1 − 1 / tan (πfc2/fs)
1 + 1 / tan (πfc1/fs)
A + Cz −1
H(z) =
1 + Bz −1
Gain[dB]
K
fc1
fc2
Frequency
Figure 61. EQ0
GN1
GN0
0
0
0
1
1
x
Table 23. Gain
Gain
0dB
(default)
+12dB
+24dB
(x: Don’t care)
MS0666-J-02
2010/06
- 65 -
[AK4671]
(5) 5-band Notch
Equalizer
5
Equalizer (EQ1, EQ2, EQ3, EQ4, EQ5)
EQ1, EQ2, EQ3, EQ4, EQ5 bits ON/OFF
Equalizer OFF
0dB
EQ1
E1A15-0 bits, E1B15-0 bits, E1C15-0 bits
EQ2
E2A15-0 bits, E2B15-0 bits, E2C15-0 bits
EQ3
E3A15-0 bits, E3B15-0 bits, E3C15-0 bits
EQ4
E4A15-0 bits, E4B15-0 bits, E4C15-0 bits
EQ5
E5A15-0 bits, E5B15-0 bits, E5C15-0 bits
EQ
EQx bit (x=1∼5) “0”
PMADL = PMADR = PMDAL
= PMDAR bits = “0”
fs:
fo1 ~ fo5:
fb1 ~ fb5:
K1 ~ K5 :
3dB
(−1 ≤ Kn ≤ 3)
(Note 61)
EQ1: E1A[15:0] bits =A1, E1B[15:0] bits =B1, E1C[15:0] bits =C1
EQ2: E2A[15:0] bits =A2, E2B[15:0] bits =B2, E2C[15:0] bits =C2
EQ3: E3A[15:0] bits =A3, E3B[15:0] bits =B3, E3C[15:0] bits =C3
EQ4: E4A[15:0] bits =A4, E4B[15:0] bits =B4, E4C[15:0] bits =C4
EQ5: E5A[15:0] bits =A5, E5B[15:0] bits =B5, E5C[15:0] bits =C5
(MSB=E1A15, E1B15, E1C15, E2A15, E2B15, E2C15, E3A15, E3B15, E3C15, E4A15, E4B15, E4C15,
E5A15, E5B15, E5C15; LSB= E1A0, E1B0, E1C0, E2A0, E2B0, E2C0, E3A0, E3B0, E3C0, E4A0, E4B0,
E4C0, E5A0, E5B0, E5C0)
1 − tan (πfbn/fs)
2
tan (πfbn/fs)
An = Kn x
, Bn = cos(2π fon/fs) x
,
1 + tan (πfbn/fs)
1 + tan (πfbn/fs)
Cn =
1 + tan (πfbn/fs)
(n = 1, 2, 3, 4, 5)
H(z) = 1 + h1(z) + h2(z) + h3(z) + h4(z) + h5(z)
1 − z −2
hn (z) = An
1− Bnz −1− Cnz −2
(n = 1, 2, 3, 4, 5)
fon / fs < 0.497
Note 61. [
X=(
X
2
2
) x 213
(2
(2
)
)
]
MSB
MS0666-J-02
2010/06
- 66 -
[AK4671]
■ ALC
ALC
ALC
Table 22
ALC
1.
ALC
ALC
Lch, Rch
LMAT1-0 bit
ZELMN bit = “0”(
)
ZTM1-0 bit
FS
ALC
(Table 26)
(Table 24)
)
IVL, IVR
FS (Full Scale)
L/R
(
: 1/fs)
1 Step
IVL, IVR
ZELMN bit = “1”(
)
ALC
LMAT1-0 bit
ALC bit
LMTH1
0
0
1
1
ALC
IVL, IVR (L/R
(Table 25)
“0”
LMTH0
ALC
0
ALC Output ≥ −2.5dBFS
1
ALC Output ≥ −4.1dBFS
0
ALC Output ≥ −6.0dBFS
1
ALC Output ≥ −8.5dBFS
Table 24. ALC
LMAT1
LMAT0
0
0
1
1
0
1
0
1
ZTM1
ZTM0
0
0
1
1
0
1
0
1
IVL, IVR
1 step
: 1/fs)
ALC
ALC
−2.5dBFS > ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
ALC
ATT
ALC Output
ALC Output
ALC Output
≥ LMTH
≥ FS
≥ FS + 6dB
1
1
1
2
2
2
2
4
4
1
2
4
Table 25. ALC
ATT
128/fs
256/fs
512/fs
1024/fs
Table 26. ALC
(
8kHz
16ms
32ms
64ms
128ms
MS0666-J-02
16kHz
8ms
16ms
32ms
64ms
ALC Output
≥ FS + 12dB
1
2
8
8
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
(default)
(default)
(default)
2010/06
- 67 -
[AK4671]
2.
ALC
ALC
WTM2-0 bits
(Table 27)
(Table 24)
ALC
(Table 29)
ZTM1-0 bits
(Table 26)
RGAIN1-0 bit
(Table 28)
IVL, IVR (L/R
)
WTM2-0
WTM2-0
ZTM1-0
ALC
ALC
IVL, IVR
30H
IVL, IVR
32H
IVL, IVR
bits)
RGAIN1-0 bit = “01”(2 steps)
0.75dB(0.375dB x 2)
ALC
ALC
ZTM1-0
ALC
IVL, IVR
(REF7-0
ALC
(
) ≤ Output Signal < (
(
) > Output Signal
ALC
)
ALC
(
)
RFST1-0 bits
WTM2
WTM1
WTM0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RGAIN1
0
0
1
1
128/fs
256/fs
512/fs
1024/fs
2048/fs
4096/fs
8192/fs
16384/fs
Table 27. ALC
RGAIN0
0
1
0
1
Table 28. ALC
(Table 30)
ALC
8kHz
16ms
32ms
64ms
128ms
256ms
512ms
1024ms
2048ms
16kHz
8ms
16ms
32ms
64ms
128ms
256ms
512ms
1024ms
GAIN STEP
1 step
0.375dB
2 step
0.750dB
3 step
1.125dB
4 step
1.500dB
MS0666-J-02
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
46.4ms
92.9ms
185.8ms
371.5ms
(default)
(default)
2010/06
- 68 -
[AK4671]
REF7-0 bits
F1H
F0H
EFH
:
(default)
E1H
:
92H
91H
90H
:
2H
1H
0H
Table 29. ALC
RFST1 bit
0
0
1
1
Table 30.
GAIN (dB)
+36.0
+35.625
+35.25
:
+30.0
:
+0.375
0.0
−0.375
:
−53.625
−54.0
MUTE
RFST0 bit
0
1
0
1
MS0666-J-02
Step
0.375dB
(default)
4
8
16
N/A
(N/A: Not available)
2010/06
- 69 -
[AK4671]
3.
ALC
Table 31, Table 32
ALC
Register Name
Comment
LMTH1-0
ZELMN
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
* ZTM1-0 bits should be equal to or
shorter than WTM2-0 bits.
Recovery waiting period
Maximum gain at recovery operation
ZTM1-0
WTM2-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
RFST1-0
ALC
Gain of IVOL
Data
01
0
fs=8kHz
Operation
−4.1dBFS
Enable
Data
01
0
fs=44.1kHz
Operation
−4.1dBFS
Enable
01
32ms
11
23.2ms
001
E1H
32ms
+30dB
100
E1H
46.4ms
+30dB
E1H
+30dB
E1H
+30dB
00
00
00
1
(
1 step
1 step
4 times
Enable
)
00
00
00
1
1 step
1 step
4 times
Enable
Limiter ATT step
Recovery GAIN step
Fast Recovery Speed
ALC enable
Table 31. ALC
fs=8kHz
Operation
−4.1dBFS
Enable
32ms
fs=44.1kHz
Operation
−4.1dBFS
Enable
23.2ms
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same data
as ZTM1-0 bits
Maximum gain at recovery operation
001
32ms
100
46.4ms
A1H
+6dB
A1H
+6dB
Gain of IVOL
91H
0dB
91H
0dB
00
00
00
1
(
1 step
1 step
4 times
Enable
)
00
00
00
1
1 step
1 step
4 times
Enable
WTM2-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
RFST1-0
ALC
Data
01
0
01
Limiter ATT step
Recovery GAIN step
Fast Recovery Speed
ALC enable
Table 32. ALC
MS0666-J-02
Data
01
0
11
2010/06
- 70 -
[AK4671]
ALC
bit = “0”)
ALC
(ALC
LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0
Example:
Limiter = Zero crossing Enable
Recovery Cycle = [email protected]
Zero Crossing Timeout Period = [email protected]
Limiter and Recovery Step = 1
Fast Recovery Speed = 4 step
Gain of IVOL = +30dB
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC bit = “1”
Manual Mode
WR (IVL7-0)
(1) Addr=12H, Data=E1H
WR (IVR7-0)
(2) Addr=13H, Data=E1H
WR (REF7-0)
* The value of IVOL should be
(3) Addr=14H, Data=E1H
the same or smaller than REF’s
WR (ZTM1-0, WTM2-0, RFST1-0)
(4) Addr=16H, Data=05H
WR (LMTH1-0, RGAIN1-0, LMAT1-0, ZELMN)
(5) Addr=17H, Data=01H
WR (ALC = “1”)
(6) Addr=18H, Data=03H
ALC Operation
Note : WR : Write
Figure 62. ALC
MS0666-J-02
2010/06
- 71 -
[AK4671]
■
(
)
ALC bits = “0”
1.
2.
ALC
(ZTM1-0, LMTH1-0
ALC
)
3.
IVL7-0, IVR7-0 bits
IVL7-0, IVR7-0 bits
IVL7-0 bits
ZTM1-0 bit
Lch, Rch
Lch, Rch
PMADL = PMADR bits = “0”
ADC
= “1”
IVL7-0, IVR7-0 bits
AK4671
IVOLC bit = “0”
IVOLC bit = “1”
L/R
PMADL bit = “1” or PMADR bit
IVOL
IVL7-0 bits
IVR7-0 bits
F1H
F0H
EFH
:
92H
(default)
91H
90H
:
03H
02H
01H
00H
Table 33.
■
(Table 33)
GAIN (dB)
+36.0
+35.625
+35.25
:
+0.375
0.0
−0.375
:
−53.25
−53.625
−54
MUTE
Step
0.375dB
(SVOLA)
6dB
ALC
5
5-band EQ
ALC
0dB
−24dB
SVAL/R2-0
Gain
0H
0dB
(default)
1H
−6dB
2H
−12dB
3H
−18dB
4H
−24dB
Others
N/A
Table 34. Side Tone Volume A Code Table (N/A: Not available)
MS0666-J-02
2010/06
- 72 -
[AK4671]
■ 5-Band Equalizer
AK4671
•
•
5-Band Equalizer
: 100Hz, 250Hz, 1kHz, 3.5kHz, 10kHz (Note 62, Note 63, Note 64)
: –10.5dB +12dB, 1.5dB step
Note 62: fs=44.1kHz
Note 63: 100Hz
Note 64: 10kHz
EQ bit
bits
fs
100Hz
10kHz
5-Band Equalizer ON/OFF
(Table 35)
EQA3-0:
EQB3-0:
EQC3-0:
EQD3-0:
EQE3-0:
EQA3-0, EQB3-0, EQC3-0, EQD3-0, EQE3-0
Select the boost level of 100Hz
Select the boost level of 250Hz
Select the boost level of 1kHz
Select the boost level of 3.5kHz
Select the boost level of 10kHz
EQx3-0
Boost amount
0H
+12.0dB
1H
+10.5dB
2H
+9.0dB
3H
+7.5dB
:
:
8H
0dB
(default)
:
:
DH
−7.5dB
EH
−9.0dB
FH
−10.5dB
Table 35. Boost amount of 5-Band Equalizer
MS0666-J-02
2010/06
- 73 -
[AK4671]
■
AK4671
MUTE
0.5dB
DAC
OVOLC bit “1”
“0”
Lch, Rch
256/fs
00H(+12dB)
FFH(MUTE)
256
(DATT)
+12dB
OVL7-0 bits
−115dB
Lch, Rch
OVOLC
ATT
1061
OVTM bit = “0”
bit
(default)
OVTM bit
0
1
OVTM bit
1061/fs([email protected]=44.1kHz)
OVL/R7-0
Gain
00H
+12.0dB
01H
+11.5dB
02H
+11.0dB
:
:
18H
0dB
:
:
FDH
−114.5dB
FEH
−115.0dB
FFH
MUTE (−∞)
Table 36. Digital Volume Code Table
OVL/R7-0 bits = 00H
FFH
fs=8kHz
1061/fs
133ms
256/fs
32ms
Table 37.
MS0666-J-02
Step
0.5dB
fs=44.1kHz
24ms
6ms
(default)
2010/06
- 74 -
[AK4671]
■
Stereo DAC
SMUTE bit “1”
SMUTE bit “0”
OVTM bit
−∞
OVL/R7-0 bits
SMUTE bit
−∞(“0”)
−∞
OVTM bit
OVTM bit
OVL/R7-0 bits
(Figure 63)
S M U T E bit
O VTM bit
O VL/R 7-0 bits
O VTM bit
(1)
(3)
A ttenuation
-∞
GD
(2)
GD
A nalog O utput
Figure 63.
(1) OVTM bit
(2)
(3)
−∞(“0”)
(GD)
OVTM bit
OVL/R7-0 bits
MS0666-J-02
2010/06
- 75 -
[AK4671]
■
AK4671
(DATT-B)
MUTE
0.5dB
SRC-B
ATT
256/fs2([email protected]=8kHz)
256
256/fs2
(default)
−115dB
00H(+12dB)
FFH(MUTE)
BVL7-0
Gain
Step
00H
+12.0dB
01H
+11.5dB
02H
+11.0dB
:
:
0.5dB
18H
0dB
:
:
FDH
−114.5dB
FEH
−115.0dB
FFH
MUTE (−∞)
Table 38. Digital Volume B Code Table
■
AK4671
(DATT-B)
+12dB
(DATT-C)
MUTE
0.5dB
SDTOB
ATT
256/fs2([email protected]=8kHz)
(default)
256
256/fs2
CVL7-0
Gain
Step
00H
+12.0dB
01H
+11.5dB
02H
+11.0dB
:
:
0.5dB
18H
0dB
:
:
FDH
−114.5dB
FEH
−115.0dB
FFH
MUTE (−∞)
Table 39. Digital Volume C Code Table
■ B/T
AK4671 6dB
SRC-A
(DATT-C)
+12dB
−115dB
00H(+12dB)
FFH(MUTE)
(SVOLB)
5
DATT-C
B/T
SRC-A
0dB
−24dB
SVB2-0
Gain
0H
0dB
(default)
1H
−6dB
2H
−12dB
3H
−18dB
4H
−24dB
Others
N/A
Table 40. Side Tone Volume B Code Table (N/A: Not available)
MS0666-J-02
2010/06
- 76 -
[AK4671]
■ B/T
AK4671
SDTIB
(BIVOL)
6dB
5
B/T
0dB
−24dB
BIV2-0
Gain
0H
0dB
(default)
1H
−6dB
2H
−12dB
3H
−18dB
4H
−24dB
Others
N/A
Table 41. B/T Mic Volume Code Table (N/A: Not available)
■
(Figure 57.)
PMADL, PMADR bits ADC
(Lch or Rch)
PMADL
0
0
1
1
ch
PMADR
ADC Lch data
0
All “0”
1
Rch Input Signal
0
Lch Input Signal
1
Lch Input Signal
Table 42. ADC
ADC Rch data
All “0”
Rch Input Signal
Lch Input Signal
Rch Input Signal
(default)
PFSEL bit Programmable Filter
PFSEL
Programmable Filter Input
0
ADC Output (selected by Table 42)
1
SDTI Input (selected by Table 48)
Table 43. Programmable Filter
ADM bit = “1”
ALC
(L+R)/2
ADM
Lch
0
L
1
(L+R)/2
Table 44. ALC
SDTO
Rch
R
(L+R)/2
MS0666-J-02
(default)
SVOLA
ch
(default)
2010/06
- 77 -
[AK4671]
SDOL1-0
SDOR1-0 bits
Table 44
SRC-B
L/R
SDTO
SDOL1
0
0
1
1
SDOL0
SDTO Lch
0
Lch Signal selected by Table 44
1
SRC-B
0
(Lch Signal selected by Table 44) + (SRC-B)
1
N/A
Table 45. SDTO Lch
(N/A: Not available)
SDOR1
0
0
1
1
SDOR0
SDTO Rch
0
Rch Signal selected by Table 44
1
SRC-B
0
(Rch Signal selected by Table 44) + (SRC-B)
1
N/A
Table 46. SDTO Rch
(N/A: Not available)
SDOD bit = “1”
SDTO
Disable (“L”
SDOD
0
1
SDIM1-0 bits
(Lch or Rch)
(default)
SVOLA
PFMXR1-0 bits
5-band EQ
Disable
SDTO
Enable (Output) (default)
Disable (“L”)
Table 47. SDTO Disable
SDTI
SDIM1
0
0
1
1
Table 48. SDTI
PFMXL1-0
)
(default)
ch
SDIM0
0
1
0
1
Lch
L
L
R
N/A
Rch
R
L
R
(default)
(N/A: Not available)
Table 48
SVOLA
PFMXL1
0
0
1
1
PFMXL0
5-band EQ Lch Input
0
Lch Signal selected by Table 48
1
SVOLA Lch
0
(Lch Signal selected by Table 48) + (SVOLA Lch)
1
N/A
Table 49. 5-band EQ Lch
1 (N/A: Not available)
PFMXR1
0
0
1
1
PFMXR0
5-band EQ Rch Input
0
Rch Signal selected by Table 48
1
SVOLA Rch
0
(Rch Signal selected by Table 48) + (SVOLA Rch)
1
N/A
Table 50. 5-band EQ Rch
1 (N/A: Not available)
MS0666-J-02
L/R
(default)
(default)
2010/06
- 78 -
[AK4671]
SRMXL1-0
L/R
SRMXR1-0 bits
5-band EQ
Table 49
Table 50
SRC-B
SRMXL1 SRMXL0
5-band EQ Lch Input
0
0
Signal selected by Table 49
(default)
0
1
SRC-B
1
0
(Signal selected by Table 49) + (SRC-B)
1
1
N/A
Table 51. 5-band EQ Lch
2 (N/A: Not available)
SRMXR1 SRMXR0
5-band EQ Rch Input
0
0
Signal selected by Table 50
(default)
0
1
SRC-B
1
0
(Signal selected by Table 50) + (SRC-B)
1
1
N/A
Table 52. 5-band EQ Rch
2 (N/A: Not available)
DAM bit MIXD bit
DAC
DAM
MIXD
0
x
1
0
1
1
Table 53. DAC
SRA1-0 bits
MIXD bit
Rch
R
(default)
L+R
(L+R)/2
(x: Don’t care)
SRC-A
SRA1
SRA0
0
0
0
1
1
0
1
0
1
1
Table 54. SRC-A
SDOA bit
Lch
L
L+R
(L+R)/2
MIXD
SRC-A
x
L
(default)
x
R
0
L+R
1
(L+R)/2
x
N/A
(x: Don’t care, N/A: Not available)
SDTOA
SDOA
0
1
SDOAD bit = “1”
Disable
SDTOA
SDTOA
SRC-A
SDTIB
Table 55. SDTOA
Disable (“L”
(default)
)
SVOLB
SDOAD
SDTOA
0
Enable (Output) (default)
1
Disable (“L”)
Table 56. SDTOA Disable
MS0666-J-02
2010/06
- 79 -
[AK4671]
SBMX1-0 bits
SDTOB
SDTIA
SVOLB
SBMX1
SBMX0
0
0
0
1
1
0
1
1
Table 57. SDTOB
SDOBD bit = “1”
SDTOB
DATT-C
DATT-C Input
SDTIA
(default)
SVOLB
(SDTIA) + (SVOLB)
N/A
(N/A: Not available)
Disable (“L”
)
SDOBD
SDTOB
0
Enable (Output) (default)
1
Disable (“L”)
Table 58. SDTOB Disable
BVMX1-0 bits
SRC-B
SDTIA
(DATT-B
BVMX1
BVMX0
0
0
0
1
1
0
1
1
Table 59. SRC-B
)
SDTIB
(BIVOL
)
SRC-B Input
SDTIA
(default)
SDTIB
(SDTIA) + (SDTIB)
N/A
(N/A: Not available)
MS0666-J-02
2010/06
- 80 -
[AK4671]
■
:
(LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins)
AK4671
(Figure 64)
PMADL bit
PMADR bit “1”
A/D
PMAINL1=PMAINR1=PMAINL2=PMAINR2=PMAINL3=PMAINR3=PMAINL4=PMAINR4=PMMICL=PMMICR
bits = “1”
LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins
MGNL/R0 bit = “0”
typ. 25kΩ MGNL/R0 bit = “1”
typ. 20kΩ
L1G1-0, L2G1-0, L3G1-0, L4G1-0, LPG1-0 bits
(Table 60, Table 61,
Table 62, Table 63, Table 64)
AK4671
INL4-0 bits
LIN1/IN1+ pin
ADC Lch
RIN1/IN1− pin
MDIF1 bit MIC-Amp Lch
MDIF3 bit
INR4-0 bits
LIN2/IN2+ pin
ADC Rch
RIN2/IN2− pin
MDIF2 bit MIC-Amp Rch
MDIF4 bit
LIN3/IN3+ pin
RIN3/IN3− pin
LIN4/IN4+ pin
Figure 57, 58, 60, 61
LOUT1 pin
Figure 63, 64
ROUT1 pin
LOUT2 pin
ROUT2 pin
PMLOOPR bit
PMLOOPL bit
PMAINR4 bit
PMAINL4 bit
PMAINR3 bit
PMAINL3 bit
PMAINR2 bit
PMAINL2 bit
PMAINL1 bit
PMAINR1 bit
RIN4/IN4− pin
Figure 67, 68, 70, 71
LOUT3 pin
ROUT3 pin
Figure 64.
MS0666-J-02
2010/06
- 81 -
[AK4671]
L1G1 bit
L1G0 bit
Gain
0
0
0dB
(default)
0
1
+6dB
1
0
−6dB
1
1
N/A
Table 60. LIN1/RIN1 (or IN1+/−) Mixing Gain (typ) (N/A: Not available)
L2G1 bit
L2G0 bit
Gain
0
0
0dB
(default)
0
1
+6dB
1
0
−6dB
1
1
N/A
Table 61. LIN2/RIN2 (or IN2+/−) Mixing Gain (typ) (N/A: Not available)
L3G1 bit
L3G0 bit
Gain
0
0
0dB
(default)
0
1
+6dB
1
0
−6dB
1
1
N/A
Table 62. LIN3/RIN3 (or IN3+/−) Mixing Gain (typ) (N/A: Not available)
L4G1 bit
L4G0 bit
Gain
0
0
0dB
(default)
0
1
+6dB
1
0
−6dB
1
1
N/A
Table 63. LIN4/RIN4 (or IN4+/−) Mixing Gain (typ) (N/A: Not available)
LPG1 bit
LPG0 bit
Gain
0
0
0dB
(default)
0
1
+6dB
1
0
−6dB
1
1
N/A
Table 64. MIC-Amp Mixing Gain (typ) (N/A: Not available)
■
:
(IN1+/IN1−/IN2+/IN2−/IN3+/IN3−/IN4+/IN4− pins)
MDIF1, MDIF2, MDIF3, MDIF4 bit = “1”
IN1+/−, IN2+/−, IN3+/−, IN4+/− pins
LIN1/RIN1, LIN2/RIN2, LIN3/RIN3, LIN4/RIN4 pins
PMADL bit
PMADR bit “1”
A/D
PMAINL1=PMAINR1=PMAINL2=PMAINR2=PMAINL3=PMAINR3=PMAINL4=PMAINR4=PMMICL=PMMICR
bits = “1”
IN1+/−, IN2+/−, IN3+/−, IN4+/− pins
MGNL/R0 bit = “0”
typ.
typ. 20kΩ
25kΩ MGNL/R0 bit = “1”
L1G1-0, L2G1-0, L3G1-0, L4G1-0, LPG1-0 bits
(Table 60, Table 61,
Table 62, Table 63, Table 64)
MS0666-J-02
2010/06
- 82 -
[AK4671]
■
DACL bit
(LOUT1/ROUT1 pins)
DACR bit
“1”
Stereo DAC Lch, Rch
LOUT1, ROUT1 pins
DACL=DACR bits = “0”
OFF
LOUT1, ROUT1 pins VCOM
min. 10kΩ
PMLO1=PMRO1=LOPS1 bits
VSS1 100kΩ(typ)
LOPS1 bit = “1”
= “0”
LOPS1 bit = “1”
PMLO1, PMRO1 bits
ON/OFF
ON/OFF
Figure 65
C
20kΩ
C=1μF, AVDD=3.3V
300ms
PMLO1=PMRO1 bits = “1”
LOPS1 bit = “0”
L1VL3-0 bits
LOM bit = “1”
Stereo DAC
(L+R)
LOUT1, ROUT1 pins
LOOPM bit = “1”
LOOPL, LOOPR bits
(MIC-Amp
) (L+R)
LOUT1, ROUT1 pins
LOPS1
0
1
LOPS1
0
1
PMLO1
0
1
0
1
Table 65.
Mode
PMRO1
0
1
0
1
Table 66.
Mode
L1VL2-0
6H
5H
4H
3H
2H
1H
0H
Table 67.
LOUT1 pin
Pull-down to VSS1
(default)
Fall down to VSS1
Rise up to VCOM
Lch
ROUT1 pin
Pull-down to VSS1
(default)
Fall down to VSS1
Rise up to VCOM
Rch
Attenuation
+6dB
0dB
−6dB
−12dB
−18dB
−24dB
MUTE
LOUT1
ROUT1
(default)
1μF
220Ω
20kΩ
(
Figure 65.
MS0666-J-02
)
2010/06
- 83 -
[AK4671]
(
)
(2 )
(5 )
P M L O 1 b it
P M R O 1 b it
(1 )
(3 )
(4 )
(6 )
L O P S 1 b it
L O U T 1 p in
R O U T 1 p in
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
Figure 66.
(1)
(2)
(
ON
LOPS1 bit = “1”
PMLO1=PMRO1 bits = “1”
C=1μF, AVDD=3.3V
LOUT1, ROUT1 pins
300ms)
(3) LOUT1, ROUT1 pin
(4)
(5)
ON
)
200ms (max
LOPS1 bit = “0”
LOPS1 bit = “1”
PMLO1=PMRO1 bits = “0”
C=1μF, AVDD=3.3V
LOUT1, ROUT1 pins
300ms)
(6) LOUT1, ROUT1 pins
200ms (max
LOPS1 bit = “0”
MS0666-J-02
2010/06
- 84 -
[AK4671]
ON/OFF
DACL, DACR, LOM, LINL1, RINR1, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4,
LOOPL, LOOPR, LOOPM bits
LINL1 bit
LIN1 pin
+6/0/−6dB
LIN2 pin
+6/0/−6dB
LIN3 pin
+6/0/−6dB
LIN4 pin
+6/0/−6dB
LINL2 bit
LINL3 bit
LINL4 bit
M
LOOPL bit
+6/0/−6dB
I
X
LOUT1 pin
L1VL2-0 bits
LOOPR bit x LOOPM bit
MIC-Amp Lch
DACL bit
Stereo DAC Lch
DATT
0dB
DACR bit x LOM bit
RINR1 bit
RIN1 pin
+6/0/−6dB
RIN2 pin
+6/0/−6dB
RIN3 pin
+6/0/−6dB
RIN4 pin
+6/0/−6dB
RINR2 bit
RINR3 bit
RINR4 bit
M
LOOPL bit x LOOPM bit
I
X
ROUT1 pin
L1VL2-0 bits
LOOPR bit
+6/0/−6dB
DACL bit x LOM bit
MIC-Amp Rch
DACR bit
DATT
Stereo DAC Rch
Figure 67. LOUT1/ROUT1
0dB
(MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
MS0666-J-02
2010/06
- 85 -
[AK4671]
LINL1 bit
+6/0/−6dB
IN1+/− pins
LINL2 bit
LINL3 bit
+6/0/−6dB
IN3+/− pins
LINL4 bit
M
LOOPL bit
+6/0/−6dB
I
X
LOUT1 pin
L1VL2-0 bits
LOOPR bit x LOOPM bit
MIC-Amp Lch
DACL bit
Stereo DAC Lch
DATT
0dB
DACR bit x LOM bit
RINR1 bit
RINR2 bit
+6/0/−6dB
IN2+/− pins
RINR3 bit
RINR4 bit
M
+6/0/−6dB
IN4+/− pins
LOOPL bit x LOOPM bit
I
X
ROUT1 pin
L1VL2-0 bits
LOOPR bit
+6/0/−6dB
DACL bit x LOM bit
MIC-Amp Rch
DACR bit
DATT
Stereo DAC Rch
Figure 68. LOUT1/ROUT1
0dB
(MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
MS0666-J-02
2010/06
- 86 -
[AK4671]
■
(RCP/RCN pins)
RCV bit = “1”
LOUT1/ROUT1 pins
RCP/RCN pins
LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4
(L+R)
BTL
min. 32Ω
PMLO1 = PMRO1 bits = “0”
RCP/RCN pins Hi-Z
PMLO1 = PMRO1 bits = “1”, LOPS1 bit = “1”
PMLO1 = PMRO1 bits = “1”, LOPS1 bit = “0”
L1VL3-0 bits
Stereo DAC
RCP/RCN pins
L1VL2-0
Attenuation
6H
+12dB
5H
+6dB
(default)
4H
0dB
3H
−6dB
2H
−12dB
1H
−18dB
0H
MUTE
Table 68. Mono Receiver Output Volume Setting
PMLO1/RO1
0
1
LOPS1
x
1
0
Mode
RCP
RCN
Power-down
Hi-Z
Hi-Z
Power-save
Hi-Z
VCOM
Normal Operation
Normal Operation Normal Operation
Table 69. Receiver-Amp Mode Setting (x: Don’t care)
(default)
PMLO1 bit
PMRO1 bit
LOPS1 bit
RCP pin
RCN pin
Hi-Z
Hi-Z
Hi-Z
VCOM
VCOM
>1ms
>0
Hi-Z
Figure 69. Power-up/Power-down Timing for Receiver-Amp
MS0666-J-02
2010/06
- 87 -
[AK4671]
ON/OFF
LOOPL, LOOPR bits
MDIF1/2/3/4 bits = “1”
DACL, DACR, LINL1, RINR1, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4,
RINR1/2/3/4 bits = “0”
LINL1 bit
LIN1 pin
+6/0/−6dB
LINL2 bit
LIN2 pin
+6/0/−6dB
LINL3 bit
LIN3 pin
+6/0/−6dB
LIN4 pin
+6/0/−6dB
LINL4 bit
LOOPL bit
+6/0/−6dB
MIC-Amp Lch
RINR1 bit
RIN1 pin
M
+6/0/−6dB
RINR2 bit
RIN2 pin
+6/0/−6dB
I
X
RCP/RCN pins
L1VL2-0 bits
RINR3 bit
RIN3 pin
+6/0/−6dB
RIN4 pin
+6/0/−6dB
RINR4 bit
LOOPR bit
+6/0/−6dB
MIC-Amp Rch
DATT
Stereo DAC Lch
DACL bit
0dB
DACR bit
DATT
Figure 70.
Stereo DAC Rch
0dB
(MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
MS0666-J-02
2010/06
- 88 -
[AK4671]
LINL1 bit
+6/0/−6dB
IN1+/− pins
LINL2 bit
+6/0/−6dB
IN2+/− pins
LINL3 bit
IN3+/− pins
+6/0/−6dB
IN4+/− pins
+6/0/−6dB
LINL4 bit
LOOPL bit
RCP/RCN pins
+6/0/−6dB
MIC-Amp Lch
L1VL2-0 bits
LOOPR bit
M
+6/0/−6dB
I
MIC-Amp Rch
DACL bit
DATT
Stereo DAC Lch
0dB
DATT
Stereo DAC Rch
0dB
X
DACR bit
Figure 71.
(MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
MS0666-J-02
2010/06
- 89 -
[AK4671]
■
(LOUT2/ROUT2 pins)
LOUT2/ROUT2
AVDD
HPG3-0 bits
(Table 70)
LOUT2, ROUT2 pins
(MIC-Amp
) (L+R)
(L+R)
LOOPHR bits
0.5 x AVDD (typ)
16Ω (min)
LOM2 bit = “1”
Stereo DAC
LOOPM2 bit = “1”
LOOPHL,
LOUT2, ROUT2 pins
HPG3-0
Attenuation
DH
+6dB
CH
+3dB
BH
0dB
AH
−3dB
:
:
:
:
2H
−27dB
1H
−30dB
0H
MUTE
Table 70. LOUT2/ROUT2
MUTEN bit
“0”
VCOM
LOUT2/ROUT2
VSS1
AVDD
: MUTET pin
LOUT2/ROUT2
(default)
MUTEN bit
MUTET pin
“1”
MUTET pin
C=1μF, AVDD=3.3V
: 100ms(typ), 250ms(max)
: 500ms(max)
PMLO2, PMRO2, PMLO2S, PMRO2S bits “0”
LOUT2, ROUT2 pin “L” (VSS1)
LOUT2/ROUT2
PMLO2 bit, PMRO2 bit,
PMLO2S bit, PMRO2S bit
MUTEN bit
LOUT2 pin,
ROUT2 pin
(1) (2)
(3)
(4)
Figure 72. LOUT2/ROUT2
(1) LOUT2/ROUT2
(2) LOUT2/ROUT2
(3) LOUT2/ROUT2
(4) LOUT2/ROUT2
(PMLO2, PMRO2, PMLO2S, PMRO2S bits = “1”)
(MUTEN bit = “1”)
(MUTEN bit = “0”)
(PMLO2, PMRO2, PMLO2S, PMRO2S bits = “0”)
LOUT2/ROUT2
MS0666-J-02
VSS1
VSS1
2010/06
- 90 -
[AK4671]
LOUT2/ROUT2
ON/OFF
DACHL, DACHR, LOM2, LINH1, RINH1, LINH2, RINH2, LINH3, RINH3, LINH4,
RINH4, LOOPHL, LOOPHR, LOOPM2 bits
LINH1 bit
LIN1 pin
+6/0/−6dB
LIN2 pin
+6/0/−6dB
LIN3 pin
+6/0/−6dB
LIN4 pin
+6/0/−6dB
LINH2 bit
LINH3 bit
LINH4 bit
M
LOOPHL bit
+6/0/−6dB
I
X
LOUT2 pin
HPG3-0 bits
LOOPHR bit x LOOPM2 bit
MIC-Amp Lch
DACHL bit
DATT
Stereo DAC Lch
0dB
DACHR bit x LOM2 bit
RINH1 bit
RIN1 pin
+6/0/−6dB
RIN2 pin
+6/0/−6dB
RIN3 pin
+6/0/−6dB
RINH2 bit
RINH3 bit
RINH4 bit
RIN4 pin
M
+6/0/−6dB
LOOPHL bit x LOOPM2 bit
I
X
ROUT2 pin
HPG3-0 bits
LOOPHR bit
+6/0/−6dB
DACHL bit x LOM2 bit
MIC-Amp Rch
DACHR bit
Stereo DAC Rch
DATT
Figure 73. LOUT2/ROUT2
0dB
(MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
MS0666-J-02
2010/06
- 91 -
[AK4671]
LINH1 bit
+6/0/−6dB
IN1+/− pins
LINH2 bit
LINH3 bit
+6/0/−6dB
IN3+/− pins
LINH4 bit
M
LOOPHL bit
+6/0/−6dB
I
X
LOUT2 pin
HPG3-0 bits
LOOPHR bit x LOOPM2 bit
MIC-Amp Lch
DACHL bit
DATT
Stereo DAC Lch
0dB
DACHR bit x LOM2 bit
RINH1 bit
RINH2 bit
+6/0/−6dB
IN2+/− pins
RINH3 bit
RINH4 bit
M
+6/0/−6dB
IN4+/− pins
LOOPHL bit x LOOPM2 bit
I
X
ROUT2 pin
HPG3-0 bits
LOOPHR bit
+6/0/−6dB
DACHL bit x LOM2 bit
MIC-Amp Rch
DACHR bit
Stereo DAC Rch
DATT
Figure 74. LOUT2/ROUT2
0dB
(MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
MS0666-J-02
2010/06
- 92 -
[AK4671]
■
3 (LOUT3/ROUT3 pins)
DACSL bit
DACSR bit
“1”
Stereo DAC Lch, Rch
LOUT3, ROUT3 pin
DACSL bit
DACSR bit “0”
OFF
LOUT3, ROUT3 pin VCOM
min. 10kΩ
PMLO3=PMRO3=LOPS3 bits = “0”
VSS1 100kΩ(typ)
LOPS3 bit = “1”
LOPS3 bit = “1”
PMLO3, PMRO3
ON/OFF
ON/OFF
bits
Figure 65
C
20kΩ
C=1μF, AVDD=3.3V
300ms
PMLO3=PMRO3 bits = “1”
LOPS3 bit = “0”
L3VL1-0 bits
LOM3 bit = “1”
Stereo DAC
(L+R)
LOUT3, ROUT3 pins
LOOPSL, LOOPSR bits
LOOPM3 bit = “1”
LOUT3, ROUT3 pins
LOPS3
0
1
PMLO3
0
1
0
1
(MIC-Amp
Mode
)
LOUT3 pin
Pull-down to VSS1
(L+R)
(default)
Fall down to VSS1
Rise up to VCOM
Table 71. LOUT3
LOPS3
0
1
PMRO3
0
1
0
1
Mode
ROUT3 pin
Pull-down to VSS1
(default)
Fall down to VSS1
Rise up to VCOM
Table 72. ROUT3
L3VL1
1
1
0
0
L3VL0
1
0
1
0
Table 73.
Attenuation
+3dB
0dB
−3dB
−6dB
LOUT3
ROUT3
1μF
(default)
220Ω
20kΩ
Figure 75.
3
(
MS0666-J-02
)
2010/06
- 93 -
[AK4671]
(
3
)
(2 )
(5 )
P M L O 3 b it
P M R O 3 b it
(1 )
(3 )
(4 )
(6 )
L O P S 3 b it
L O U T 3 , R O U T 3 p in s
N o r m a l O u tp u t
≥ 300 m s
Figure 76.
(1)
(2)
≥ 300 m s
3
ON
(
LOPS3 bit = “1”
PMLO3=PMRO3 bits = “1”
C=1μF, AVDD=3.3V
LOUT3, ROUT3 pin
300ms)
(3) LOUT3, ROUT3 pin
(4)
(5)
)
200ms (max
LOPS3 bit = “0”
ON
LOPS3 bit = “1”
PMLO3=PMRO3 bits = “0”
C=1μF, AVDD=3.3V
LOUT3, ROUT3 pin
300ms)
(6) LOUT3, ROUT3 pin
200ms (max
LOPS3 bit = “0”
MS0666-J-02
2010/06
- 94 -
[AK4671]
3
ON/OFF
DACSL, DACSR, LOM3, LINS1, RINS1, LINS2, RINS2, LINS3, RINS3, LINS4,
0dB(typ)
RINS4, LOOPSL, LOOPSR, LOOPM3 bits
LINS1 bit
LIN1 pin
+6/0/−6dB
LIN2 pin
+6/0/−6dB
LIN3 pin
+6/0/−6dB
LIN4 pin
+6/0/−6dB
LINS2 bit
LINS3 bit
LINS4 bit
M
LOOPSL bit
+6/0/−6dB
I
X
LOUT3 pin
L3VL1-0 bits
LOOPSR bit x LOOPM3 bit
MIC-Amp Lch
DACSL bit
DATT
Stereo DAC Lch
0dB
DACSR bit x LOM3 bit
RINS1 bit
RIN1 pin
+6/0/−6dB
RIN2 pin
+6/0/−6dB
RIN3 pin
+6/0/−6dB
RIN4 pin
+6/0/−6dB
RINS2 bit
RINS3 bit
RINS4 bit
M
LOOPSL bit x LOOPM3 bit
I
X
ROUT3 pin
L3VL1-0 bits
LOOPSR bit
+6/0/−6dB
DACSL bit x LOM3 bit
MIC-Amp Rch
DACSR bit
Stereo DAC Rch
DATT
Figure 77. LOUT3/ROUT3
0dB
(MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
MS0666-J-02
2010/06
- 95 -
[AK4671]
LINS1 bit
+6/0/−6dB
IN1+/− pins
LINS2 bit
LINS3 bit
+6/0/−6dB
IN3+/− pins
LINS4 bit
M
LOOPSL bit
+6/0/−6dB
I
X
LOUT3 pin
L3VL1-0 bits
LOOPSR bit x LOOPM3 bit
MIC-Amp Lch
DACSL bit
DATT
Stereo DAC Lch
0dB
DACSR bit x LOM3 bit
RINS1 bit
RINS2 bit
+6/0/−6dB
IN2+/− pins
RINS3 bit
RINS4 bit
M
+6/0/−6dB
IN4+/− pins
LOOPSL bit x LOOPM3 bit
I
X
ROUT3 pin
L3VL1-0 bits
LOOPSR bit
+6/0/−6dB
DACSL bit x LOM3 bit
MIC-Amp Rch
DACSR bit
Stereo DAC Rch
DATT
Figure 78. LOUT3/ROUT3
0dB
(MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
MS0666-J-02
2010/06
- 96 -
[AK4671]
■
(LOP/LON pins)
LODIF bit = “1”
LOUT3/ROUT3 pins
LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4
LOP/LON pins
DAC
(L+R)
LOP/LON pins
min. 10kΩ
PMLO3 = PMRO3 bits = “0”
LOP/LON pins VSS1 Pull-down
PMLO3 = PMRO3 bits = “1”, LOPS3 bit = “1”
PMLO3 = PMRO3 bits = “1”, LOPS3 bit = “0”
L3VL1-0 bits
L3VL1-0
Attenuation
3H
+9dB
2H
+6dB
(default)
1H
+3dB
0H
0dB
Table 74. Mono Line Output Gain Setting
LOPS3
PMLO3/RO3
Mode
LOP/LON pins
Pull-down to VSS1
0
1
Fall down to VSS1
0
Rise up to VCOM
1
Table 75. Mono Line Output Mode Setting
0
1
(
(default)
)
(2 )
(5 )
P M L O 3 b it
P M R O 3 b it
(1 )
(3 )
(4 )
(6 )
L O P S 3 b it
L O P , L O N p in s
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
Figure 79.
(1)
(2)
(
ON
LOP, LON pins
LOPS3 bit = “1”
PMLO3 = PMRO3 bits = “1”
C=1μF, AVDD=3.3V
(3) LOP, LON pins
LOP, LON pins
200ms (max 300ms)
LOPS3 bit = “0”
ON
(4)
(5)
)
LOPS3 bit = “1”
PMLO3 = PMRO3 bits = “0”
C=1μF, AVDD=3.3V
(6) LOP, RON pins
200ms (max 300ms)
LOPS3 bit = “0”
MS0666-J-02
2010/06
- 97 -
[AK4671]
ON/OFF
LOOPSL, LOOPSR bits
MDIF1/2/3/4 bits = “1”
DACSL, DACSR, LINS1, RINS1, LINS2, RINS2, LINS3, RINS3, LINS4, RINS4,
0dB(typ)
RINS1/2/3/4 bits = “0”
LINS1 bit
LIN1 pin
+6/0/−6dB
LINS2 bit
LIN2 pin
+6/0/−6dB
LINS3 bit
LIN3 pin
+6/0/−6dB
LIN4 pin
+6/0/−6dB
LINS4 bit
LOOPSL bit
+6/0/−6dB
MIC-Amp Lch
RINS1 bit
RIN1 pin
M
+6/0/−6dB
RINS2 bit
RIN2 pin
+6/0/−6dB
I
X
LOP/LON pins
L3VL1-0 bits
RINS3 bit
RIN3 pin
+6/0/−6dB
RINS4 bit
RIN4 pin
+6/0/−6dB
LOOPSR bit
+6/0/−6dB
MIC-Amp Rch
DACSL bit
DATT
Stereo DAC Lch
0dB
DATT
Stereo DAC Rch
0dB
DACSR bit
Figure 80.
(MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
MS0666-J-02
2010/06
- 98 -
[AK4671]
LINS1 bit
IN1+/− pins
+6/0/−6dB
LINS2 bit
IN2+/− pins
+6/0/−6dB
LINS3 bit
IN3+/− pins
+6/0/−6dB
IN4+/− pins
+6/0/−6dB
LINS4 bit
LOOPSL bit
LOP/LON pins
+6/0/−6dB
MIC-Amp Lch
L3VL1-0 bits
LOOPSR bit
M
+6/0/−6dB
I
MIC-Amp Rch
DACSL bit
DATT
Stereo DAC Lch
0dB
DATT
Stereo DAC Rch
0dB
X
DACSR bit
Figure 81.
(MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
MS0666-J-02
2010/06
- 99 -
[AK4671]
■
(PCM I/F)
SYNCA, BICKA, SYNCB or BICKB pins
PLLBT
PCM I/F
PMPCM bit = “1”
PLLBT
PLLBT
PLLBT3-0 bits
(Table 76) BICKA, BICKB pins
BCKO2 bit
(Table 77) PCM I/F A,B
PCM I/F A,B
PCM I/F A
PCM I/F B
PMPCM bit = “0”
SYNCA, BICKA, SYNCB, BICKB pins Hi-Z
PMPCM bit = “0”
Table 76
Lock Time
SDTOA, SDTOB pins
Table 78
Lock Time
Table 79
Mode
PLLBT3
PLLBT2
PLLBT1
PLLBT0
0
1
2
3
4
5
6
7
11
15
Others
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
1
1
Reference Clock
Input Pin
Frequency
R, C at
VCOCBT pin
R
C
6.8k
220n
10k
4.7n
10k
4.7n
10k
4.7n
6.8k
220n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
SYNCA
1fs2
BICKA
16fs2
BICKA
32fs2
BICKA
64fs2
SYNCB
1fs2
BICKB
16fs2
BICKB
32fs2
BICKB
64fs2
BICKA
48fs2
BICKB
48fs2
N/A
Table 76. PLLBT Reference Clock (N/A: Not available)
Note 65. Mode 1 FMTA1 bit = “0”
Note 66. Mode 5 FMTB1 bit = “0”
Lock
Time
(max)
260ms
40ms
40ms
40ms
260ms
40ms
40ms
40ms
40ms
40ms
(default)
BICKA/BICKB
Output Frequency
0
16fs2
(default)
1
32fs2
Table 77. BICKA/B Output Frequency
BCKO2 bit
Mode
16bit Linear
8bit A-Law
8bit μ-Law
After PMPCM bit = “0” → “1”
& Before SYNCA/SYNCB Input
L
L
L
H
L
H
Table 78. SDTOA, SDTOB pins Output Data
PMPCM bit = “0”
PMPCM bit = “1”
During Locktime
0000H
11010101b
11111111b
Format
SYNCA, SYNCB
BICKA, BICKB
Except for I2S
L
L
I2S
H
L
Table 79. Output Clock during Lock Time
MS0666-J-02
2010/06
- 100 -
[AK4671]
a) PLLBT
: SYNCA or BICKA pin
SYNCA, BICKA
PLLBT
AK4671
SYNCA
BICKA
SYNCB, BICKB
Phone Module
1fs2
≥ 16fs2
SYNC
BICK
SDTOA
SDTI
SDTIA
SDTO
Bluetooth Module
SYNCB
BICKB
Figure 82. P
b) PLLBT
1fs2
16fs2 or 32fs2
SYNC
BICK
SDTOB
SDTI
SDTIB
SDTO
I/F (PLLBT Reference Clock: SYNCA or BICKA pin)
: SYNCB or BICKB pin
SYNCB, BICKB
PLLBT
SYNCA, BICKA
AK4671
SYNCA
BICKA
Phone Module
1fs2
16fs2 or 32fs2
SYNC
BICK
SDTOA
SDTI
SDTIA
SDTO
Bluetooth Module
SYNCB
BICKB
Figure 83. P
SRC-A or SRC-B
“1”)
1fs2
≥ 16fs2
SYNC
BICK
SDTOB
SDTI
SDTIB
SDTO
I/F (PLLBT Reference Clock: SYNCB or BICKB pin)
(PMSRA bit = “1” or PMSRB bit = “1”)
PLLBT
(PMPCM bit =
PLLBT
PLLBT
SRC
(PMSRA=PMSRB bits = “0”)
MS0666-J-02
2010/06
- 101 -
[AK4671]
■ PCM I/F
PCM I/F
B
(PDN pin = “L”)
Hi-Z
PLLBT3-0 bits
PLLBT2 bit
PMPCM bit = “0”
(Table 81)
PCM I/F
PMPCM bit = “1”
PCM I/F
PCM I/F A
Slave Mode
Master Mode
PDN pin
L
H
PCM I/F
(SYNCA, BICKA, SYNCB, BICKB pins)
PMPCM bit = “0”
PDN pin = “H”
PLLBT2 bit
0
1
PCM I/F
(Table 80) PCM I/F A
PCM I/F
Hi-Z
100kΩ
SYNCA, BICKA pins
PCM I/F B
SYNCB, BICKB pins
Input
Master Mode
Output
Output
Slave Mode
Input
Table 80. Select PCM I/F Master/Slave Mode
PMPCM bit
0
1
(default)
SYNCA, BICKA pin
SYNCB, BICKB pin
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PLLBT2 bit I/O
PLLBT2 bit I/O
(Table 80)
(Table 80)
Table 81. PCM I/F Clock I/O State
MS0666-J-02
2010/06
- 102 -
[AK4671]
■ PCM I/F A & B
AK4671 2
μ-Law 3
PCM I/F (PCM I/F A & PCM I/F B)
(Table 82, Table 83)
16bit Linear, 8bit A-Law
Mode
0
1
2
3
LAWA1
LAWA0
Format
0
0
16bit Linear
0
1
N/A
1
0
8bit A-Law
1
1
8bit μ-Law
Table 82. PCM I/F A Mode (N/A: Not available)
Mode
0
1
2
3
LAWB1
LAWB0
Format
0
0
16bit Linear
0
1
N/A
1
0
8bit A-Law
1
1
8bit μ-Law
Table 83. PCM I/F B Mode (N/A: Not available)
PCM I/F A, B
4
84, Table 85) 16bit Linear Mode
8bit A-Law
μ-Law Mode
(default)
(default)
FMTA1-0, FMTB1-0 bits
2’s
MSB
PCM I/F A, B
SYNCA/B, BICKA/B
FMTA1
0
0
1
1
FMTA0
0
1
0
1
Format
BICKA
Short Frame Sync
≥ 16fs2
Long Frame Sync
≥ 16fs2
MSB justified
≥ 32fs2
I 2S
≥ 32fs2
Table 84. PCM I/F A Format
Figure
See Table 86
See Table 88
Figure 92
Figure 93
Mode
0
1
2
3
FMTB1
0
0
1
1
FMTB0
0
1
0
1
Format
BICKB
Short Frame Sync
≥ 16fs2
Long Frame Sync
≥ 16fs2
MSB justified
≥ 32fs2
I 2S
≥ 32fs2
Table 85. PCM I/F B Format
Figure
See Table 87
See Table 89
Figure 92
Figure 93
Mode 0, 1
BICKA
PCM I/F A
(Table
MSB
Mode
0
1
2
3
Mode 2, 3
SDTOA
SDTIB BICKB “↑”
8bit
“↓“ SDTOB BICKB
BCKPA, MSBSA bit
“↓“
(default)
SDTIA
PCM I/F B BCKPB, MSBSB bit
BCKPA bit = “0”
SDTOA BICKA
SDTOA BICKA
BCKPA bit = “1”
SDTOA, SDTIA MSB
MSBSA bit
“↑”
“↓”
BICKA
SDTIA
SDTIA
BICKA
BICKA
“↓”
“↑”
BCKPB bit = “0”
SDTOB BICKB
SDTOB BICKB
BCKPB bit = “1”
SDTOB, SDTIB MSB
MSBSB bit
“↑”
“↓”
BICKB
SDTIB BICKB
SDTIB BICKB
“↓”
“↑”
MS0666-J-02
(default)
BICKA
“↑”
I/F
2010/06
- 103 -
[AK4671]
MSBSA bit
BCKPA bit
0
0
0
1
1
0
1
1
MSBSB bit
BCKPB bit
0
0
0
1
1
0
1
1
MSBSA bit
BCKPA bit
0
0
0
1
1
0
1
1
MSBSB bit
BCKPB bit
0
0
0
1
1
0
1
1
SDTOA
SDTOA
SDTOA
SDTOA
SDTOB
SDTOB
SDTOB
SDTOB
SDTOA
SDTOA
SDTOA
SDTOA
Data Interface Format
MSB
SYNCA “↑”
BICKA
BICKA “↓” SDTIA MSB
MSB
SYNCA “↑”
BICKA
BICKA “↑” SDTIA MSB
MSB
SYNCA “↑”
BICKA
BICKA “↓” SDTIA MSB
MSB
SYNCA “↑”
BICKA
BICKA “↑” SDTIA MSB
Table 86. PCM I/F A Format in Mode 0
Data Interface Format
MSB
SYNCB “↑”
BICKB
BICKB “↓” SDTIB MSB
MSB
SYNCB “↑”
BICKB
BICKB “↑” SDTIB MSB
MSB
SYNCB “↑”
BICKB
BICKB “↓” SDTIB MSB
MSB
SYNCB “↑”
BICKB
BICKB “↑” SDTIB MSB
Table 87. PCM I/F B Format in Mode 0
Figure
“↓”
“↑”
“↑”
“↓”
2
“↑”
2
“↓”
Figure 85
Figure 86
Figure 87
Figure
“↓”
“↑”
“↑”
“↓”
2
“↑”
2
“↓”
Data Interface Format
MSB
SYNCA “↑”
BICKA “↓” SDTIA MSB
MSB
SYNCA “↑”
BICKA “↑” SDTIA MSB
MSB
SYNCA “↑”
1
BICKA “↑”
BICKA “↓” SDTIA MSB
MSB
SYNCA “↑”
1
BICKA “↓”
BICKA “↑” SDTIA MSB
Table 88. PCM I/F A Format in Mode 1
Data Interface Format
SYNCB “↑”
SDTOB MSB
BICKB “↓” SDTIB MSB
SYNCB “↑”
SDTOB MSB
BICKB “↑” SDTIB MSB
SYNCB “↑”
1
BICKB “↑”
SDTOB MSB
BICKB “↓” SDTIB MSB
SYNCB “↑”
1
BICKB “↓”
SDTOB MSB
BICKB “↑” SDTIB MSB
Table 89. PCM I/F B Format in Mode 1
MS0666-J-02
Figure 84
Figure 84
Figure 85
Figure 86
Figure 87
Figure
Figure 88
Figure 89
Figure 90
Figure 91
Figure
Figure 88
Figure 89
Figure 90
Figure 91
2010/06
- 104 -
[AK4671]
1/fs2
SYNCA
BICKA
(16bit Linear)
SDTOA
SDTIA
Don’t Care
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
Don’t Care
D7
D6
Don’t Care D7
D6
Figure 84. Timing of Short Frame Sync (MSBSA bit = “0”, BCKPA bit = “0”)
1/fs2
SYNCA
BICKA
(16bit Linear)
SDTOA
SDTIA
D on’t Care
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D on’t Care
D7
D6
D7
D6
Figure 85. Timing of Short Frame Sync (MSBSA bit = “0”, BCKPA bit = “1”)
1/fs2
SYNCA
BICKA
(16bit Linear)
SDTOA
SDTIA
D on’t Care
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D on’t Care
D7
D6
D7
D6
Figure 86. Timing of Short Frame Sync (MSBSA bit = “1”, BCKPA bit = “0”)
MS0666-J-02
2010/06
- 105 -
[AK4671]
1/fs2
SYNCA
BICKA
(16bit Linear)
SDTOA
SDTIA
D on’t Care
(8bit A-Law/μ-Law)
SDTOA
SDTIA
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
Don’t Care
D on’t Care
Don’t Care
D7
D6
D7
D6
Figure 87. Timing of Short Frame Sync (MSBSA bit = “1”, BCKPA bit = “1”)
1/fs2
SYNCA
BICKA
(16bit Linear)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
Don’t Care D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
SDTOA
SDTIA
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D7
D6
D5
D7
D6
D5
Figure 88. Timing of Long Frame Sync (MSBSA bit = “0”, BCKPA bit = “0”)
1/fs2
SYNCA
BICKA
(16bit Linear)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
Don’t Care D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
SDTOA
SDTIA
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D7
D6
D5
D7
D6
D5
Figure 89. Timing of Long Frame Sync (MSBSA bit = “0”, BCKPA bit = “1”)
MS0666-J-02
2010/06
- 106 -
[AK4671]
1/fs2
SYNCA
BICKA
(16bit Linear)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
Don’t Care D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
SDTOA
SDTIA
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D7
D6
D5
Don’t Care D7
D6
D5
Figure 90. Timing of Long Frame Sync (MSBSA bit = “1”, BCKPA bit = “0”)
1/fs2
SYNCA
(Slave)
BICKA
(16bit Linear)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
Don’t Care D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
SDTOA
SDTIA
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D7
D6
D5
Don’t Care D7
D6
D5
Figure 91. Timing of Long Frame Sync (MSBSA bit = “1”, BCKPA bit = “1”)
MS0666-J-02
2010/06
- 107 -
[AK4671]
SYNCA
BICKA
(32fs2)
SDTOA(o)
SDTIA(i)
BICKA
(64fs2)
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
15 14 13
7 6 5 4 3 2 1 0
15 14 13
7 6 5 4 3 2 1 0
0 1 2 3
15 16 17 18
SDTOA(o)
15 14 13
1 0
SDTIA(i)
15 14 13
1 0
9 10 11 12 13 14 15 0 1
15
Don't Care
31 0 1 2 3
Don't Care
15 16 17 18
15
31 0 1
15
Don't Care
Don't Care
15
15:MSB, 0:LSB
Figure 92. Timing of MSB justified
SYNCA
BICKA
(32fs2)
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
SDTOA(o)
15 14
8 7 6 5 4 3 2 1 0
SDTIA(i)
15 14
8 7 6 5 4 3 2 1 0
BICKA
(64fs2)
0 1 2 3
15 16 17 18
SDTOA(o)
15 14
2 1 0
SDTIA(i)
15 14
2 1 0
31 0 1 2 3
Don't Care
9 10 11 12 13 14 15 0 1
Don't Care
15 16 17 18
31 0 1
Don't Care
15:MSB, 0:LSB
Figure 93. Timing of I2S
MS0666-J-02
2010/06
- 108 -
[AK4671]
■
MIC-Amp
& ALC
A/D
HPF
MIC
HPF
LPF
Stereo
Separation
5-band
Notch
ALC
MIX
SDTO Lch
SDTO Rch
Audio
I/F
SVOLA
D/A
M DATT 5-band
I SMUTE
EQ
X
S
E
L
CPU
SDTI Lch
SDTI Rch
Receiver
Headphone
Speaker
SRC-A
PCM
I/F A
SVOLB
SRC-B
TX
SDTOA
RX
SDTIA
DATT-B
DATT-C
BIVOL
SDTOB
SDTIB
Baseband
PCM
I/F B
B/T
Phone Call TX
Phone Call TX Recording
Phone Call Side Tone
Phone Call RX
Phone Call RX Recording
Figure 94. Internal MIC/SPK or External MIC/HP
MS0666-J-02
&
2010/06
- 109 -
[AK4671]
MIC-Amp
& ALC
A/D
HPF
MIC
HPF
LPF
Stereo
Separation
5-band
Notch
ALC
MIX
SDTO Lch
SDTO Rch
Audio
I/F
SVOLA
D/A
M DATT 5-band
I SMUTE
EQ
X
S
E
L
CPU
SDTI Lch
SDTI Rch
Receiver
Headphone
Speaker
SRC-A
PCM
I/F A
SVOLB
SRC-B
TX
SDTOA
RX
SDTIA
DATT-B
DATT-C
SDTOB
SDTIB
BIVOL
Baseband
PCM
I/F B
B/T
Phone Call TX
Phone Call TX Recording
Phone Call Side Tone
Phone Call RX
Phone Call RX Recording
Figure 95. B/T Headset
MS0666-J-02
&
2010/06
- 110 -
[AK4671]
■ General Purpose Output
AK4671
General Purpose Output Pin (GPO)
GPOM1 bit = “0”
GPOE1 bit = “1”
GPO1 pin
“H”
GPOE1 bit
GPO1 pin
0
L
(default)
1
H
Table 90. General Purpose Output 1 Pin Control (GPOM1 bit = “0”
GPOM1 bit = “1”
A0 bit
GPO1 pin
0.5 x SAVDD
(SAIN1 or SAIN2 pin)
GPOM1 bit = “1”
“H”
SAIN3 pin
SAIN3 pin
SAIN1/2 pin
GPO1 pin
< SAIN3 pin
L
(default)
H
≥ SAIN3 pin
Table 91. General Purpose Output 1 Pin Control (GPOM1 bit = “1”
GPOM2 bit = “0”
GPOE2 bit = “1”
GPO2 pin
GPO2 pin
Input Level of MDT pin
≥ 0.075 x AVDD
< 0.050 x AVDD
)
“H”
GPOE2 bit
GPO2 pin
0
L
(default)
1
H
Table 92. General Purpose Output 2 Pin Control (GPOM2 bit = “0”
GPOM2 bit = “1”
)
)
(Table 21)
GPO2 pin
DTMIC bit
H
1
L
0
Table 21. Microphone Detection Result
MS0666-J-02
Result
Mic (Headset)
No Mic (Headphone)
2010/06
- 111 -
[AK4671]
■
AK4671
10bit ADC
DC
10bit
10bit ADC
(SAR)ADC
Table 93
(AVDD−1.5LSB)
(AVDD−2.5LSB)
~ AVDD
~ (AVDD−1.5LSB)
:
0.5LSB ~ 1.5LSB
0 ~ 0.5LSB
Table 93.
PMSAD bit = “1” 10bit ADC
4
9∼18
10bit
3FFH
3FEH
:
001H
000H
Read
R/W bit
10bit ADC 3
4bit
A/D
“1”
CCLK
A1-0 bits
Mode
0
1
2
3
A1
A0
0
0
0
1
1
0
1
1
Table 94. SAR ADC
Input Channel
SAIN1
SAIN2
SAIN3
N/A
(N/A: Not available)
MS0666-J-02
(default)
2010/06
- 112 -
[AK4671]
SAR ADC
[4
(1) A1-0 bits
(2) R/W bit
(
]
4bit
[I2C mode]
(1) A1-0 bits
(2) Addr=5BH Read
Addr=5CH
(3)
PMSAD bit = “1”
A/D
“1”
SAR ADC
CCLK
(
[4
]
(1) GPOM1 bit = “1”
(2) A0 bit
(3) A0 bit
GPO1 pin “H”
GPO1 pin = “H”
(4) CPU
4bit
10bit
)
GPO1 pin
(SAIN1 pin or SAIN2 pin) DC
SAIN3 pin
GPOM1 bit = “0”, PMSAD bit = “1”
“1”
[I2C mode]
(1) GPOM1 bit = “1”
(2) A0 bit
(3) A0 bit
GPO1 pin “H”
GPO1 pin = “H”
(4) CPU
(5) Addr=5BH Read
Addr=5CH
(6)
9∼18
PMSAD bit = “1” SAR ADC
8bit
2bit
A/D
Read
SAR ADC
(5) R/W bit
)
A/D
Read
A/D
CCLK
SAR ADC
9∼18
10bit
GPO1 pin
(SAIN1 pin or SAIN2 pin) DC
SAIN3 pin
GPOM1 bit = “0”, PMSAD bit = “1”
SAR ADC
8bit
2bit
MS0666-J-02
2010/06
- 113 -
[AK4671]
■
(1) 4
4
(I2C pin = “L”)
(CSN, CCLK, CDTI, CDTO)
I/F
10bit SAR ADC
Register address (MSB first, 7bits)
I/F
Chip address (3bit, “100”
Control Data (MSB first, 8bits)
10bit SAR ADC
I/F
) SAR ADC Data (MSB first, 10bits)
CCLK “↓”
CCLK “↑”
CSN
“↓” 24
Chip address (3bit, “101”
“↑”
CSN
H
), Read/Write (1bit),
), Read/Write (1bit: “0”
CSN
“↑”
Hi-Z
5MHz (max)
CCLK
1
PDN pin
= “L”
CSN
0
CCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 16
17
18
19
20
21
22
23
Clock,
"H" or "L"
Clock,
"H" or "L"
"H" or "L"
CDTI
"H" or "L"
C2 C1 R/W C0
WRITE
0
0
0
0
0
A6
A5
A4
A3
A2
A1
A0 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
A6
A5
A4
A3 A2
A1
A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
CDTO
"H" or "L"
READ
(except for
10bit SAR ADC Data)
CDTI
"H" or "L"
C2 C1 R/W C0
Hi-Z
CDTO
D7 D6
D5 D4 D3 D2 D1 D0
Hi-Z
C2-C0: Chip Address (Fixed to “100”)
R/W: READ/WRITE (0: READ, 1: WRITE)
A6-A0: Register Address
D7-D0: Control Data
Figure 96.
(10bit SAR ADC Data
)
CSN
0
CCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 16
CDTI
CDTO
18
19
20
21
22
23
Clock,
"H" or "L"
"H" or "L"
"H" or "L"
READ
(10bit SAR ADC Data)
17
Clock,
"H" or "L"
C2 C1 R/W C0
Hi-Z
0
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0
D9 D8 D7
D6 D5 D4 D3 D2
D1 D0
0
0
0
0
0
0
Hi-Z
C2-C0: Chip Address (Fixed to “101”)
R/W: READ/WRITE (Fixed to “0”: READ Only)
D9-D0: SAR ADC Data
Figure 97.
(10bit SAR ADC Data)
MS0666-J-02
2010/06
- 114 -
[AK4671]
(2) I2C
AK4671
(I2C pin = “H”)
Fast Mode (max:400kHz)
(DVDD+0.3)V
I 2C
(2)-1. WRITE
I2C
(Start Condition)
(Figure 105)
8
IC
AK4671
SDA
R/W bit “1”
2
SCL
SDA
“L”
Figure 98
“H”
IC
“H”
SDA
“L”
7
(R/W)
6
“001001”
(Figure 99)
CAD0 pin
1
(Acknowledge)
(Figure 106)
(
(Figure 100)
3
(Figure 101)
“0”
MSB first
SDA, SCL pins
)
8
R/W bit
“0”
MSB first
1
8
AK4671
(Stop Condition)
(Figure 105)
“H”
AK4671
SCL
“H”
1
“5AH”
“00H”
“H”
SDA
SCL
“L”
(Figure 107)
“H”
SCL
“L”
“H”
SDA
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
A
C
K
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 98. I2C
0
0
1
0
0
(CAD0
Figure 99.
0
A6
A5
D6
D5
Figure 101.
CAD0
R/W
A3
A2
A1
A0
D3
D2
D1
D0
)
1
A4
Figure 100.
D7
1
2
D4
3
MS0666-J-02
2010/06
- 115 -
[AK4671]
(2)-2. READ
R/W bit “1”
AK4671
READ
“5AH”
“00H”
2
AK4671
READ
(2)-2-1.
AK4671
(10bit SAR ADC Data
AK4671
)
(READ
WRITE
“n+1”
(R/W bit = “1”)
READ
)
“n”
1
READ
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
Data(n+1)
Data(n+2)
MA
AC
SK
T
E
R
A
C
K
MA
AC
SK
T
E
R
Data(n+x)
MA
AC
SK
T
E
R
P
MA
AC
SK
T
E
R
MN
AA
SC
T
EK
R
Figure 102.
(2)-2-2.
READ
(R/W bit = “1”)
WRITE
WRITE
= “0”)
AK4671
(R/W bit= “1”)
READ
(R/W bit
AK4671
1
READ
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
Data(n+x)
MA
AC
S
T K
E
R
MA
AC
S K
T
E
R
A
C
K
MA
AC
S
T K
E
R
(10bit SAR ADC Data
Figure 103.
SAR ADC
)
Addr=5BH
6bit
MSB
R/W="0"
S
T
A
R
T
2
2
Read
10bit
“0”
S
T
A
R
T
SDA
ADC
P
MN
A A
S
TC
E K
R
Slave
S Address
Slave
S Address
Sub
Address(5BH)
A
C
K
S
T
O
P
R/W="1"
A
C
K
Data(D9-2)
A
C
K
Data(D1-0)
MA
AC
SK
T
E
R
P
MN
AA
SC
T
EK
R
(10bit SAR ADC Data)
Figure 104.
MS0666-J-02
2010/06
- 116 -
[AK4671]
SDA
SCL
S
P
start condition
stop condition
Figure 105.
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 106. I2C
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 107. I2C
MS0666-J-02
2010/06
- 117 -
[AK4671]
■
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
Register Name
AD/DA Power Management
PLL Mode Select 0
PLL Mode Select 1
Format Select
MIC Signal Select
MIC Amp Gain
Mixing Power Management 0
Mixing Power Management 1
Output Volume Control
LOUT1 Signal Select
ROUT1 Signal Select
LOUT2 Signal Select
ROUT2 Signal Select
LOUT3 Signal Select
ROUT3 Signal Select
LOUT1 Power Management
LOUT2 Power Management
LOUT3 Power Management
Lch Input Volume Control
Rch Input Volume Control
ALC Reference Select
Digital Mixing Control
ALC Timer Select
ALC Mode Control
Mode Control 1
Mode Control 2
Lch Output Volume Control
Rch Output Volume Control
Side Tone A Control
Digital Filter Select
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
FIL2 Co-efficient 0
FIL2 Co-efficient 1
FIL2 Co-efficient 2
FIL2 Co-efficient 3
D7
PMDAR
FS3
BTCLK
0
MDIF4
D6
PMDAL
FS2
LP
0
MDIF3
D5
PMADR
FS1
BCKO
0
MDIF2
D4
PMADL
FS0
PS1
SDOD
MDIF1
MGNR3
MGNR2
MGNR1
MGNR0
MGNL3
MGNL2
MGNL1
MGNL0
0
0
0
0
0
DTMIC
PMLOOPR
PMLOOPL
PMAINR4
PMAINL4
PMAINR3
PMAINL3
PMAINR2
PMAINL2
PMAINR1
PMAINL1
HPG3
L1G1
L2G1
L3G1
L4G1
LPG1
0
0
0
L3VL1
IVL7
IVR7
REF7
HPG2
L1G0
L2G0
L3G0
L4G0
LPG0
0
0
HPG1
LOOPL
LOOPR
HPG0
LINL4
RINR4
LINH4
RINH4
LINS4
RINS4
LOOPM
IVL4
IVR4
REF4
0
LINL3
RINR3
LINH3
RINH3
LINS3
RINS3
LOM
LOM2
LOM3
IVL3
IVR3
REF3
L1VL2
LINL2
RINR2
LINH2
RINH2
LINS2
RINS2
LOPS1
MUTEN
LOPS3
IVL2
IVR2
REF2
L1VL1
LINL1
RINR1
LINH1
RINH1
LINS1
RINS1
PMRO1
PMRO2
PMRO3
IVL1
IVR1
REF1
L1VL0
DACL
DACR
DACHL
DACHR
DACSL
DACSR
PMLO1
PMLO2
PMLO3
IVL0
IVR0
REF0
LOOPHL
LOOPHR
LOOPSL
LOOPSR
RCV
D2
PMMICL
PLL3
PS0
MSBS
INR1
PLL2
MCKO
BCKP
INR0
D1
PMMP
PLL1
M/S
DIF1
INL1
D0
PMVCM
PLL0
PMPLL
DIF0
INL0
PMRO2S
PMLO2S
L3VL0
IVL6
IVR6
REF6
LODIF
IVL5
IVR5
REF5
SRMXR1
SRMXR0
SRMXL1
SRMXL0
PFMXR1
PFMXR0
PFMXL1
PFMXL0
0
0
DAM
SRA1
OVL7
OVR7
0
GN1
F3A7
F3AS
F3B7
0
E0A7
E0A15
E0B7
0
E0C7
E0C15
F1A7
0
F1B7
0
F2A7
0
F2B7
0
RFST1
ZELMN
MIXD
SRA0
OVL6
OVR6
0
GN0
F3A6
0
F3B6
0
E0A6
E0A14
E0B6
0
E0C6
E0C14
F1A6
0
F1B6
0
F2A6
0
F2B6
0
RFST0
LMAT1
SDIM1
BIV2
OVL5
OVR5
SVAR2
LPF
F3A5
F3A13
F3B5
F3B13
E0A5
E0A13
E0B5
E0B13
E0C5
E0C13
F1A5
F1A13
F1B5
F1B13
F2A5
F2A13
F2B5
F2B13
WTM2
LMAT0
SDIM0
BIV1
OVL4
OVR4
SVAR1
HPF
F3A4
F3A12
F3B4
F3B12
E0A4
E0A12
E0B4
E0B12
E0C4
E0C12
F1A4
F1A12
F1B4
F1B12
F2A4
F2A12
F2B4
F2B12
WTM1
RGAIN1
EQ
BIV0
OVL3
OVR3
SVAR0
EQ0
F3A3
F3A11
F3B3
F3B11
E0A3
E0A11
E0B3
E0B11
E0C3
E0C11
F1A3
F1A11
F1B3
F1B11
F2A3
F2A11
F2B3
F2B11
WTM0
RGAIN0
ADM
SMUTE
OVL2
OVR2
SVAL2
FIL3
F3A2
F3A10
F3B2
F3B10
E0A2
E0A10
E0B2
E0B10
E0C2
E0C10
F1A2
F1A10
F1B2
F1B10
F2A2
F2A10
F2B2
F2B10
ZTM1
LMTH1
IVOLC
OVTM
OVL1
OVR1
SVAL1
HPFAD
F3A1
F3A9
F3B1
F3B9
E0A1
E0A9
E0B1
E0B9
E0C1
E0C9
F1A1
F1A9
F1B1
F1B9
F2A1
F2A9
F2B1
F2B9
ZTM0
LMTH0
ALC
OVOLC
OVL0
OVR0
SVAL0
PFSEL
F3A0
F3A8
F3B0
F3B8
E0A0
E0A8
E0B0
E0B8
E0C0
E0C8
F1A0
F1A8
F1B0
F1B8
F2A0
F2A8
F2B0
F2B8
MS0666-J-02
LOOPM2
LOOPM3
D3
PMMICR
2010/06
- 118 -
[AK4671]
Addr
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
Register Name
Digital Filter Select 2
Reserved
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
EQ Control 250Hz/100Hz
EQ Control 3.5kHz/1kHz
EQ Control 10kHz
PCM I/F Control 0
PCM I/F Control 1
PCM I/F Control 2
Digital Volume B Control
Digital Volume C Control
Side Tone Volume Control
Digital Mixing Control
SAR ADC Control
Note 67. PDN pin “L”
Note 68. “0”
1EH ∼ 2FH
Note 69.
D7
0
0
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
EQB3
EQD3
0
GPOM2
SDOAD
SDOBD
BVL7
CVL7
0
SDOR1
0
D6
0
0
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
EQB2
EQD2
0
GPOE2
BCKO2
PLLBT3
BVL6
CVL6
0
SDOR0
0
D5
0
0
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
EQB1
EQD1
0
PLLBT2
MSBSA
MSBSB
BVL5
CVL5
0
SDOL1
0
D4
EQ5
0
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
EQB0
EQD0
0
PLLBT1
BCKPA
BCKPB
BVL4
CVL4
0
SDOL0
GPOM1
D3
EQ4
0
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
EQA3
EQC3
EQE3
PLLBT0
LAWA1
LAWB1
BVL3
CVL3
SDOA
BVMX1
GPOE1
D2
EQ3
0
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
EQA2
EQC2
EQE2
PMPCM
LAWA0
LAWB0
BVL2
CVL2
SVB2
BVMX0
A1
D1
EQ2
0
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
EQA1
EQC1
EQE1
PMSRB
FMTA1
FMTB1
BVL1
CVL1
SVB1
SBMX1
A0
D0
EQ1
0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
EQA0
EQC0
EQE0
PMSRA
FMTA0
FMTB0
BVL0
CVL0
SVB0
SBMX0
PMSAD
“1”
32H ∼ 4FH
MS0666-J-02
2010/06
- 119 -
[AK4671]
■
Addr
00H
Register Name
AD/DA Power Management
R/W
Default
D7
PMDAR
R/W
0
D6
PMDAL
R/W
0
D5
PMADR
R/W
0
D4
PMADL
R/W
0
D3
D2
PMMICR
PMMICL
R/W
0
R/W
0
D1
PMMP
R/W
0
D0
PMVCM
R/W
0
PMVCM: VCOM
0: Power down (default)
1: Power up
PMVCM bit
“1”
PMVCM bit
“0”
“0”
PMMP: MPWR pin
0: Power down: Hi-Z (default)
1: Power up
PMMICL: MIC-Amp Lch
0: Power down (default)
1: Power up
PMMICR: MIC-Amp Rch
0: Power down (default)
1: Power up
PMADL: ADC Lch
0: Power down (default)
1: Power up
PMADL
PMADR bit
“0”
“1”
([email protected])
ADC
PMADR: ADC Rch
0: Power down (default)
1: Power up
PMDAL: DAC Lch
0: Power down (default)
1: Power up
PMDAR: DAC Rch
0: Power down (default)
1: Power up
ON/OFF (“1”/“0”)
PDN pin
“L”
“0”
20μA(typ)
(typ. 1μA)
ADC
PDN pin = “L”
DAC
ADC
MS0666-J-02
DAC
2010/06
- 120 -
[AK4671]
Addr
01H
Register Name
PLL Mode Select 0
R/W
Default
D7
FS3
R/W
1
D6
FS2
R/W
1
D5
FS1
R/W
1
D4
FS0
R/W
1
D3
PLL3
R/W
0
D2
PLL2
R/W
1
D1
PLL1
R/W
1
D0
PLL0
R/W
0
PLL3-0: PLL
(Table 4)
Default: “0110”(MCKI pin, 12MHz)
FS3-0:
(Table 5 and Table 6)
PLL mode
Addr
02H
Register Name
PLL Mode Select 1
R/W
Default
D7
BTCLK
R/W
0
D6
LP
R/W
0
MCKI
EXT mode
D5
BCKO
R/W
0
D4
PS1
R/W
0
(Table 11)
MCKI
D3
PS0
R/W
0
D2
MCKO
R/W
0
D1
M/S
R/W
0
D0
PMPLL
R/W
0
PMPLL: PLL
0: EXT Mode and Power Down (default)
1: PLL Mode and Power up
M/S: Master / Slave Mode
0: Slave Mode (default)
1: Master Mode
MCKO: MCKO
0: Disable: MCKO pin = “L” (default)
1: Enable: Output frequency is selected by PS1-0 bits.
PS1-0: MCKO
Default: “00”(256fs)
BCKO:
(Table 9)
BICK
(Table 10)
LP:
0: Normal Mode (default)
1: Low Power Mode: fs=22.05kHz
BTCLK: Audio CODEC
(default)
0: Audio I/F
1: PCM I/F
BTCLK bit PMPLL bit = “0”
Audio CODEC
BTCLK bit = “1”
PLLBT
Figure 57
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Addr
03H
Register Name
Format Select
R/W
Default
D7
0
RD
0
DIF1-0:
Default: “10” (
BCKP: DSP Mode
“0”: “↑” SDTO
“1”: “↓” SDTO
D6
0
RD
0
D5
0
RD
0
D4
SDOD
R/W
0
D3
MSBS
R/W
0
D2
BCKP
R/W
0
D1
DIF1
R/W
1
D0
DIF0
R/W
0
D2
INR0
R/W
0
D1
INL1
R/W
0
D0
INL0
R/W
0
(Table 16)
)
BICK
(Table 17)
, “↓” SDTI
(default)
, “↑” SDTI
MSBS: DSP Mode
LRCK
“0”: LRCK “↑”
“1”: LRCK “↑”
(Table 17)
BICK
BICK 1
(default)
SDOD: SDTO Disable (Table 47)
“0”: Enable (default)
“1”: Disable (“L”)
Addr
04H
Register Name
MIC Signal Select
R/W
Default
D7
MDIF4
R/W
0
D6
MDIF3
R/W
0
INL1-0: MIC-Amp Lch
Default: “00” (LIN1)
(Table 18)
INR1-0: MIC-Amp Rch
Default: “00” (RIN1)
(Table 18)
D5
MDIF2
R/W
0
D4
MDIF1
R/W
0
D3
INR1
R/W
0
MDIF1: Line1
(LIN1/RIN1 pins: Default)
0:
(IN1+/IN1− pins)
1:
MDIF2: Line2
(LIN2/RIN2 pins: Default)
0:
(IN2+/IN2− pins)
1:
MDIF3: Line3
(LIN3/RIN3 pins: Default)
0:
(IN3+/IN3− pins)
1:
MDIF4: Line4
0:
(LIN4/RIN4 pins: Default)
(IN4+/IN4− pins)
1:
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Addr
05H
Register Name
MIC Amp Gain
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
MGNR3
MGNR2
MGNR1
MGNR0
MGNL3
MGNL2
MGNL1
MGNL0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
0
R/W
1
R/W
0
R/W
1
D4
0
RD
0
D3
0
RD
0
D2
DTMIC
RD
0
MGNL3-0:
Lch
Default: “0101” (0dB)
(Table 19)
MGNR3-0:
Rch
Default: “0101” (0dB)
(Table 19)
Addr
06H
Register Name
Mixing Power Management 0
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D1
D0
PMLOOPR
PMLOOPL
R/W
0
R/W
0
PMLOOPL: MIC-Amp Lch
0: Power down (default)
1: Power up
PMLOOPR: MIC-Amp Rch
0: Power down (default)
1: Power up
DTMIC:
0:
1:
(Read Only: Table 21)
(default)
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Addr
07H
Register Name
Mixing Power Management 1
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
PMAINR4
PMAINL4
PMAINR3
PMAINL3
PMAINR2
PMAINL2
PMAINR1
PMAINL1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
D6
HPG2
R/W
0
D5
HPG1
R/W
1
D4
HPG0
R/W
1
D3
0
RD
0
PMAINL1: LIN1
0: Power down (default)
1: Power up
PMAINR1: RIN1
0: Power down (default)
1: Power up
PMAINL2: LIN2
0: Power down (default)
1: Power up
PMAINR2: RIN2
0: Power down (default)
1: Power up
PMAINL3: LIN3
0: Power down (default)
1: Power up
PMAINR3: RIN3
0: Power down (default)
1: Power up
PMAINL4: LIN4
0: Power down (default)
1: Power up
PMAINR4: RIN4
0: Power down (default)
1: Power up
Addr
08H
Register Name
Output Volume Control
R/W
Default
L1VL3-0: LOUT1/ROUT1
Default: “5H” (0dB)
HPG3-0: LOUT2/ROUT2
Default: “BH” (0dB)
D7
HPG3
R/W
1
D2
L1VL2
R/W
1
D1
L1VL1
R/W
0
D0
L1VL0
R/W
1
(Table 67)
(Table 70)
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Addr
09H
Register Name
LOUT1 Signal Select
R/W
Default
DACL: Stereo DAC Lch
0: OFF (default)
1: ON
PMLO1 bit = “1”
D7
L1G1
R/W
0
D6
L1G0
R/W
0
D5
LOOPL
R/W
0
D4
LINL4
R/W
0
D3
LINL3
R/W
0
D2
LINL2
R/W
0
D1
LINL1
R/W
0
D0
DACL
R/W
0
LOUT1
PMLO1 bit = “0”
LOUT1 pin
VSS1
LINL1: LIN1
LOUT1
0: OFF (default)
1: ON
LINL2: LIN2
LOUT1
0: OFF (default)
1: ON
LINL3: LIN3
LOUT1
0: OFF (default)
1: ON
LINL4: LIN4
LOUT1
0: OFF (default)
1: ON
LOOPL: MIC-Amp Lch
0: OFF (default)
1: ON
L1G1-0: LIN1/RIN1
Default: “00” (0dB)
LOUT1
(Table 60)
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[AK4671]
Addr
0AH
Register Name
ROUT1 Signal Select
R/W
Default
DACR: Stereo DAC Rch
0: OFF (default)
1: ON
PMRO1 bit = “1”
D7
L2G1
R/W
0
D6
L2G0
R/W
0
D5
LOOPR
R/W
0
D4
RINR4
R/W
0
D3
RINR3
R/W
0
D2
RINR2
R/W
0
D1
RINR1
R/W
0
D0
DACR
R/W
0
ROUT1
PMRO1 bit = “0”
ROUT1 pin
VSS1
RINR1: RIN1
ROUT1
0: OFF (default)
1: ON
RINR2: RIN2
ROUT1
0: OFF (default)
1: ON
RINR3: RIN3
ROUT1
0: OFF (default)
1: ON
RINR4: RIN4
ROUT1
0: OFF (default)
1: ON
LOOPR: MIC-Amp Rch
0: OFF (default)
1: ON
L2G1-0: LIN2/RIN2
Default: “00” (0dB)
ROUT1
(Table 61)
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Addr
0BH
Register Name
LOUT2 Signal Select
R/W
Default
DACHL: DAC Lch
0: OFF (default)
1: ON
D7
L3G1
R/W
0
D6
L3G0
R/W
0
D5
LOOPHL
R/W
0
D4
LINH4
R/W
0
D3
LINH3
R/W
0
D2
LINH2
R/W
0
D1
LINH1
R/W
0
D0
DACHL
R/W
0
LOUT2
LINH1: LIN1
LOUT2
0: OFF (default)
1: ON
LINH2: LIN2
LOUT2
0: OFF (default)
1: ON
LINH3: LIN3
LOUT2
0: OFF (default)
1: ON
LINH4: LIN4
LOUT2
0: OFF (default)
1: ON
LOOPHL: MIC-Amp Lch
0: OFF (default)
1: ON
L3G1-0: LIN3/RIN3
Default: “00” (0dB)
LOUT2
(Table 62)
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Addr
0CH
Register Name
ROUT2 Signal Select
R/W
Default
DACHR: DAC Rch
0: OFF (default)
1: ON
D7
L4G1
R/W
0
D6
L4G0
R/W
0
D5
LOOPHR
R/W
0
D4
RINH4
R/W
0
D3
RINH3
R/W
0
D2
RINH2
R/W
0
D1
RINH1
R/W
0
D0
DACHR
R/W
0
ROUT2
RINH1: RIN1
ROUT2
0: OFF (default)
1: ON
RINH2: RIN2
ROUT2
0: OFF (default)
1: ON
RINH3: RIN3
ROUT2
0: OFF (default)
1: ON
RINH4: RIN4
ROUT2
0: OFF (default)
1: ON
LOOPHR: MIC-Amp Rch
0: OFF (default)
1: ON
L4G1-0: LIN4/RIN4
Default: “00” (0dB)
ROUT2
(Table 63)
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Addr
0DH
Register Name
LOUT3 Signal Select
R/W
Default
DACSL: Stereo DAC Lch
0: OFF (default)
1: ON
PMLO3 bit = “1”
D7
LPG1
R/W
0
D6
LPG0
R/W
0
D5
LOOPSL
R/W
0
D4
LINS4
R/W
0
D3
LINS3
R/W
0
D2
LINS2
R/W
0
D1
LINS1
R/W
0
D0
DACSL
R/W
0
LOUT3 pin
PMLO3 bit = “0”
LOUT3 pin
VSS1
LINS1: LIN1
LOUT3
0: OFF (default)
1: ON
LINS2: LIN2
LOUT3
0: OFF (default)
1: ON
LINS3: LIN3
LOUT3
0: OFF (default)
1: ON
LINS4: LIN4
LOUT3
0: OFF (default)
1: ON
LOOPSL: MIC-Amp Lch
0: OFF (default)
1: ON
LPG1-0: MIC-Amp
Default: “00” (0dB)
LOUT3
(Table 64)
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Addr
0EH
Register Name
ROUT3 Signal Select
R/W
Default
DACSR: Stereo DAC Rch
0: OFF (default)
1: ON
PMRO3 bit = “1”
D7
0
RD
0
D6
0
RD
0
D5
LOOPSR
R/W
0
D4
RINS4
R/W
0
D3
RINS3
R/W
0
D2
RINS2
R/W
0
D1
RINS1
R/W
0
D0
DACSR
R/W
0
ROUT3 pin
PMRO3 bit = “0”
ROUT3 pin
VSS1
RINS1: RIN1
ROUT3
0: OFF (default)
1: ON
RINS2: RIN2
ROUT3
0: OFF (default)
1: ON
RINS3: RIN3
ROUT3
0: OFF (default)
1: ON
RINS4: RIN4
ROUT3
0: OFF (default)
1: ON
LOOPSR: MIC-Amp Rch
0: OFF (default)
1: ON
ROUT3
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Addr
0FH
Register Name
LOUT1 Power Management
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
RCV
R/W
0
D4
LOOPM
R/W
0
D3
LOM
R/W
0
D2
LOPS1
R/W
0
D1
PMRO1
R/W
0
D0
PMLO1
R/W
0
PMLO1: Lch
1
0: Power down (default)
1: Power up
PMRO1: Rch
1
0: Power down (default)
1: Power up
LOPS1:
1
0: Normal Operation (default)
1: Power Save Mode
LOM: DAC
1
0: Stereo Mixing (default)
1: Mono Mixing
LOOPM: MIC-Amp
0: Stereo Mixing (default)
1: Mono Mixing
RCV:
0:
1:
1
(LOUT1/ROUT1 pins) (default)
(RCP/RCN pins)
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Addr
10H
Register Name
LOUT2 Power Management
R/W
Default
D7
0
RD
0
D6
D5
D4
PMRO2S
PMLO2S
LOOPM2
R/W
0
R/W
0
R/W
0
D3
LOM2
R/W
0
D2
MUTEN
R/W
0
D1
PMRO2
R/W
0
D0
PMLO2
R/W
0
PMRO2: Rch
0: Power down (default)
1: Power up
PMLO2: Lch
0: Power down (default)
1: Power up
MUTEN: LOUT2/ROUT2
0: Mute (default)
1: Normal operation
LOM2: DAC
LOUT2/ROUT2
0: Stereo Mixing (default)
1: Mono Mixing
LOOPM2: MIC-Amp
LOUT2/ROUT2
0: Stereo Mixing (default)
1: Mono Mixing
PMRO2S: ROUT2 MIX-Amp
0: Power down (default)
1: Power up
PMLO2S: LOUT2 MIX-Amp
0: Power down (default)
1: Power up
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Addr
11H
Register Name
LOUT3 Power Management
R/W
Default
D7
L3VL1
R/W
1
D6
L3VL0
R/W
0
D5
D4
LODIF
LOOPM3
R/W
0
R/W
0
D3
LOM3
R/W
0
D2
LOPS3
R/W
0
D1
PMRO3
R/W
0
D0
PMLO3
R/W
0
PMLO3: Lch
3
0: Power down (default)
1: Power up
PMRO3: Rch
3
0: Power down (default)
1: Power up
LOPS3:
3
0: Normal Operation (default)
1: Power Save Mode
LOM3: DAC
3
0: Stereo Mixing (default)
1: Mono Mixing
LOOPM3: MIC-Amp
0: Stereo Mixing (default)
1: Mono Mixing
LODIF:
0:
1:
L3VL1-0: LOUT3/ROUT3
Default: “10” (0dB)
3
(LOUT3/ROUT3 pins) (default)
(LOP/LON pins)
(Table 73)
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Addr
12H
13H
Register Name
Lch Input Volume Control
Rch Input Volume Control
R/W
Default
D7
IVL7
IVR7
R/W
1
IVL7-0, IVR7-0:
Default: “91H” (0dB)
Addr
14H
D6
IVL6
IVR6
R/W
0
D4
IVL4
IVR4
R/W
1
Register Name
ALC Reference Select
R/W
Default
D7
REF7
R/W
1
D6
REF6
R/W
1
Register Name
Digital Mixing Control
R/W
Default
D5
REF5
R/W
1
D4
REF4
R/W
0
D2
IVL2
IVR2
R/W
0
D1
IVL1
IVR1
R/W
0
D0
IVL0
IVR0
R/W
1
D2
REF2
R/W
0
D1
REF1
R/W
0
D0
REF0
R/W
1
D7
D6
D5
D4
D3
D2
D1
D0
SRMXR1
SRMXR0
SRMXL1
SRMXL0
PFMXR1
PFMXR0
PFMXL1
PFMXL0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
D4
WTM2
R/W
0
D3
WTM1
R/W
0
D2
WTM0
R/W
0
D1
ZTM1
R/W
0
D0
ZTM0
R/W
0
1 (Table 49)
PFMX 1-0: 5-band EQ Rch
Default: “00” (SDTI)
1 (Table 50)
SRMXL1-0: 5-band EQ Lch
Default: “00” (SDTI)
2 (Table 51)
SRMX 1-0: 5-band EQ Rch
Default: “00” (SDTI)
2 (Table 52)
Register Name
ALC Timer Select
R/W
Default
D3
REF3
R/W
0
0.375dB step, 242 Level (Table 29)
PFMXL1-0: 5-band EQ Lch
Default: “00” (SDTI)
Addr
16H
D3
IVL3
IVR3
R/W
0
; 0.375dB step, 242 Level (Table 33)
REF7-0: ALC
Default: “E1H” (+30.0dB)
Addr
15H
D5
IVL5
IVR5
R/W
0
D7
0
RD
0
D6
RFST1
R/W
0
ZTM1-0: ALC
D5
RFST0
R/W
0
(Table 26)
ALC
“00” (128/fs)
WTM2-0: ALC
ALC
“000” (128/fs)
RFST1-0: ALC
Default: “00”(4
(Table 27)
(Table 30)
)
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Addr
17H
Register Name
ALC Mode Control
R/W
Default
D7
0
RD
0
LMTH1-0: ALC
Default: “00”
D6
ZELMN
R/W
0
D4
LMAT0
R/W
0
D3
RGAIN1
R/W
0
/
RGAIN1-0: ALC
Default: “00”
LMAT1-0: ALC
Default: “00”
D5
LMAT1
R/W
0
D2
RGAIN0
R/W
0
D1
LMTH1
R/W
0
D0
LMTH0
R/W
0
(Table 24)
(Table 28)
ATT
(Table 25)
ZELMN: ALC
0: Enable (default)
1: Disable
Addr
18H
Register Name
Mode Control 1
R/W
Default
D7
DAM
R/W
0
D6
MIXD
R/W
0
D5
SDIM1
R/W
0
D4
SDIM0
R/W
0
D3
EQ
R/W
0
D2
ADM
R/W
0
D1
IVOLC
R/W
1
D0
ALC
R/W
0
ALC:
ALC
0: ALC Disable (default)
1: ALC Enable
IVOLC: IVOL
0: Independent
1: Dependent (default)
IVOLC bit = “1”
ADM:
0: Stereo (default)
1: Mono: (L+R)/2
IVL7-0 bit
IVOL
IVR7-0 bit IVL7-0 bit
(Table 44)
EQ: 5-Band Equalizer
0: OFF (default)
1: ON
SDIM1-0: SDTI
(Table 48)
Default: “00” (Lch=L, Rch=R)
MIXD: DAC, SRC-A
0: L+R (default)
1: (L+R)/2
(Table 53 and Table 54)
DAM: DAC
(Table 53)
0: Stereo (default)
1: Mono: (L+R) or (L+R)/2 is selected by MIXD bit.
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Addr
19H
Register Name
Mode Control 2
R/W
Default
D7
SRA1
R/W
0
D6
SRA0
R/W
0
D5
BIV2
R/W
0
D4
BIV1
R/W
0
D3
BIV0
R/W
0
D2
SMUTE
R/W
0
D1
OVTM
R/W
0
D0
OVOLC
R/W
1
D4
OVL4
OVR4
R/W
1
D3
OVL3
OVR3
R/W
1
D2
OVL2
OVR2
R/W
0
D1
OVL1
OVR1
R/W
0
D0
OVL0
OVR0
R/W
0
D4
SVAR1
R/W
0
D3
SVAR0
R/W
0
D2
SVAL2
R/W
0
D1
SVAL1
R/W
0
D0
SVAL0
R/W
0
OVOLC:
0: Independent
1: Dependent (default)
OVOLC bit = “1”
OVL7-0 bits
OVR7-0 bits OVL7-0 bits
OVTM: Digital Volume
0: 1061/fs (default)
1: 256/fs
OVL7-0, OVR7-0 bits
00H
FFH
SMUTE:
0: Normal Operation (default)
1: DAC outputs soft-muted
BIV2-0: B/T
Default: “0H” (0dB)
SRA1-0: SRC-A
Default: “00” (Lch)
Addr
1AH
1BH
Register Name
Lch Output Volume Control
Rch Output Volume Control
R/W
Default
(Table 41)
(Table 54)
D7
OVL7
OVR7
R/W
0
OVL7-0, OVR7-0:
Default: “18H” (0dB)
Addr
1CH
Register Name
Side Tone A Control
R/W
Default
D6
OVL6
OVR6
R/W
0
D5
OVL5
OVR5
R/W
0
(Table 36)
D7
0
RD
0
D6
0
RD
0
D5
SVAR2
R/W
0
SVAL2-0, SVAR2-0: Side Tone Volume A (SVOLA) (Table 34)
Default: “000” (0dB)
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Addr
1DH
Register Name
Digital Filter Select
R/W
Default
D7
GN1
R/W
0
D6
GN0
R/W
0
D5
LPF
R/W
0
PFSEL: Programable Filter Block
0: ADC
1: SDTI
D2
FIL3
R/W
0
D1
HPFAD
R/W
1
D0
PFSEL
R/W
0
(Table 43)
F1A13-0, F1B13-0 bit
(0dB)
GN1-0: Gain
Default: “00” (0dB)
HPFAD bit = “0”
(Table 23)
FIL3
(default)
FIL3 bit = “1”
F3A13-0, F3B13-0 bit
OFF(MUTE)
EQ0:
0:
1:
D3
EQ0
R/W
0
(default)
HPFAD: ADC HPF
0: OFF
1: ON (default)
HPFAD bit = “1”
HPFAD
FIL3:
0:
1:
D4
HPF
R/W
0
FIL3 bit = “0”
FIL3
(default)
EQ0 bit = “1”
EQ0
E0A15-0, E0B13-0, E0C15-0 bit
(0dB)
HPF: HPF
0:
(default)
1:
HPF bit = “1”
F1A13-0, F1B13-0 bit
EQ0 bit = “0”
HPF bit = “0”
HPF
(0dB)
LPF: LPF
0:
(default)
1:
LPF bit = “1”
F2A13-0, F2B13-0 bit
LPF bit = “0”
LPF
(0dB)
MS0666-J-02
2010/06
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[AK4671]
Addr
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
Register Name
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
R/W
Default
D7
F3A7
F3AS
F3B7
0
E0A7
E0A15
E0B7
0
E0C7
E0C15
W
0
F3A13-0, F3B13-0:
Default: “0000H”
F3AS:
0: HPF (default)
1: LPF
D6
F3A6
0
F3B6
0
E0A6
E0A14
E0B6
0
E0C6
E0C14
W
0
FIL3
D5
F3A5
F3A13
F3B5
F3B13
E0A5
E0A13
E0B5
E0B13
E0C5
E0C13
W
0
D3
F3A3
F3A11
F3B3
F3B11
E0A3
E0A11
E0B3
E0B11
E0C3
E0C11
W
0
D2
F3A2
F3A10
F3B2
F3B10
E0A2
E0A10
E0B2
E0B10
E0C2
E0C10
W
0
D1
F3A1
F3A9
F3B1
F3B9
E0A1
E0A9
E0B1
E0B9
E0C1
E0C9
W
0
D0
F3A0
F3A8
F3B0
F3B8
E0A0
E0A8
E0B0
E0B8
E0C0
E0C8
W
0
D2
F1A2
F1A10
F1B2
F1B10
W
D1
F1A1
F1A9
F1B1
F1B9
W
D0
F1A0
F1A8
F1B0
F1B8
W
(14bit x 2)
FIL3
E0A15-0, E0B13-0, E0C15-C0:
Default: “0000H”
Addr
28H
29H
2AH
2BH
D4
F3A4
F3A12
F3B4
F3B12
E0A4
E0A12
E0B4
E0B12
E0C4
E0C12
W
0
Register Name
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
R/W
Default
(14bit x 2 + 16bit x 1)
D7
F1A7
0
F1B7
0
W
D6
F1A6
0
F1B6
0
W
D5
F1A5
F1A13
F1B5
F1B13
W
D4
F1A4
F1A12
F1B4
F1B12
W
D3
F1A3
F1A11
F1B3
F1B11
W
F1A13-0 bits = “1FA9H”, F1B13-0 bits = “20ADH”
F1A13-0, F1B13-B0:
FIL1
(14bit x 2)
Default: F1A13-0 bits = “1FA9H”, F1B13-0 bits = “20ADH” ([email protected]=44.1kHz)
Addr
2CH
2DH
2EH
2FH
Register Name
FIL2 Co-efficient 0
FIL2 Co-efficient 1
FIL2 Co-efficient 2
FIL2 Co-efficient 3
R/W
Default
F2A13-0, F3B13-0: LPF
Default: “0000H”
D7
F2A7
0
F2B7
0
W
0
FIL2
D6
F2A6
0
F2B6
0
W
0
D5
F2A5
F2A13
F2B5
F2B13
W
0
D4
F2A4
F2A12
F2B4
F2B12
W
0
D3
F2A3
F2A11
F2B3
F2B11
W
0
D2
F2A2
F2A10
F2B2
F2B10
W
0
D1
F2A1
F2A9
F2B1
F2B9
W
0
D0
F2A0
F2A8
F2B0
F2B8
W
0
(14bit x 2)
MS0666-J-02
2010/06
- 138 -
[AK4671]
Addr
30H
Register Name
Digital Filter Select 2
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
EQ5
R/W
0
D3
EQ4
R/W
0
D2
EQ3
R/W
0
D1
EQ2
R/W
0
EQ1: Equalizer 1
0: Disable (default)
1: Enable
EQ1 bit = “1”
EQ1
E1A15-0, E1B15-0, E1C15-0 bit
(0dB)
EQ1 bit = “0”
EQ2: Equalizer 2
0: Disable (default)
1: Enable
EQ2 bit = “1”
EQ2
E2A15-0, E2B15-0, E2C15-0 bit
(0dB)
EQ2 bit = “0”
EQ3: Equalizer 3
0: Disable (default)
1: Enable
EQ3 bit = “1”
EQ3
E3A15-0, E3B15-0, E3C15-0 bit
(0dB)
EQ3 bit = “0”
EQ4: Equalizer 4
0: Disable (default)
1: Enable
EQ4 bit = “1”
EQ4
E4A15-0, E4B15-0, E4C15-0 bit
(0dB)
EQ4 bit = “0”
EQ5: Equalizer 5
0: Disable (default)
1: Enable
EQ5 bit = “1”
EQ5
E5A15-0, E5B15-0, E5C15-0 bit
(0dB)
EQ5 bit = “0”
MS0666-J-02
D0
EQ1
R/W
0
2010/06
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[AK4671]
Addr
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
Register Name
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
R/W
Default
D7
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
W
0
D6
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
W
0
D5
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
W
0
E1A15-0, E1B15-0, E1C15-0: Equalizer 1
Default: “0000H”
(16bit x3)
E2A15-0, E2B15-0, E2C15-0: Equalizer 2
Default: “0000H”
(16bit x3)
E3A15-0, E3B15-0, E3C15-0: Equalizer 3
Default: “0000H”
(16bit x3)
E4A15-0, E4B15-0, E4C15-0: Equalizer 4
Default: “0000H”
(16bit x3)
E5A15-0, E5B15-0, E5C15-0: Equalizer 5
Default: “0000H”
(16bit x3)
MS0666-J-02
D4
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
W
0
D3
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
W
0
D2
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
W
0
D1
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
W
0
D0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
W
0
2010/06
- 140 -
[AK4671]
Addr
50H
51H
Register Name
EQ Control 250Hz/100Hz
EQ Control 3.5kHz/1kHz
R/W
Default
Addr
52H
Register Name
EQ Control 10kHz
R/W
Default
D7
EQB3
EQD3
R/W
1
D6
EQB2
EQD2
R/W
0
D5
EQB1
EQD1
R/W
0
D4
EQB0
EQD0
R/W
0
D3
EQA3
EQC3
R/W
1
D2
EQA2
EQC2
R/W
0
D1
EQA1
EQC1
R/W
0
D0
EQA0
EQC0
R/W
0
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
EQE3
R/W
1
D2
EQE2
R/W
0
D1
EQE1
R/W
0
D0
EQE0
R/W
0
D3
PLLBT0
R/W
0
D2
PMPCM
R/W
0
D1
PMSRB
R/W
0
D0
PMSRA
R/W
0
EQA3-0: Select the boost level of 100Hz
EQB3-0: Select the boost level of 250Hz
EQC3-0: Select the boost level of 1kHz
EQD3-0: Select the boost level of 3.5kHz
EQE3-0: Select the boost level of 10kHz
See Table 35.
Addr
53H
Register Name
PCM I/F Control 0
R/W
Default
D7
GPOM2
R/W
0
D6
GPOE2
R/W
0
D5
PLLBT2
R/W
0
D4
PLLBT1
R/W
0
PMSRA: SRC-A
0: Power down (default)
1: Power up
PMSRB: SRC-B
0: Power down (default)
1: Power up
PMPCM: PCM I/F
0: Power down (default)
1: Power up
PLLBT2-0: SRC PLLBT
PLLBT3 bit Addr=55H, D6
Default: “0000”: SYNCA
(Table 76)
GPOE2: General Purpose Output 2 Enable at GPOM2 bit = “1”
“0”: GPO2 pin = “L” (default)
“1”: GPO2 pin = “H”
GPOM2: General Purpose Output 2 Operation Mode (Table 92)
“0”: Controlled by GPOE2 bit (default)
“1”: MIC Detection Interrupt
MS0666-J-02
2010/06
- 141 -
[AK4671]
Addr
54H
Register Name
PCM I/F Control 2
R/W
Default
D7
SDOAD
R/W
0
D6
BCKO2
R/W
0
D5
MSBSA
R/W
0
D4
BCKPA
R/W
0
D3
LAWA1
R/W
0
D2
LAWA0
R/W
0
D1
FMTA1
R/W
0
D0
FMTA0
R/W
0
D4
BCKPB
R/W
0
D3
LAWB1
R/W
0
D2
LAWB0
R/W
0
D1
FMTB1
R/W
0
D0
FMTB0
R/W
0
FMTA1-0: PCM I/F A Format (Table 84)
Default: “00” (Mode 0)
LAWA1-0: PCM I/F A Mode (Table 82)
Default: “00” (Mode 0)
(Table 86)
BCKPA: PCM I/F A BICKA
, “↓” SDTIA
(default)
“0”: “↑” SDTOA
, “↑” SDTIA
“1”: “↓” SDTOA
MSBSA: PCM I/F A
“0”: SYNCA
“1”: SYNCA
SYNCA
MSB
BICKA
BCKO2: BICKA/B
0: 16fs2 (default)
1: 32fs2
(Table 86)
(default)
MSB
(Table 77)
SDOAD: SDTOA Disable (Table 56)
“0”: Enable (default)
“1”: Disable (“L”)
Addr
55H
Register Name
PCM I/F Control 3
R/W
Default
D7
SDOBD
R/W
0
D6
PLLBT3
R/W
0
D5
MSBSB
R/W
0
FMTB1-0: PCM I/F B Format (Table 85)
Default: “00” (Mode 0)
LAWB1-0: PCM I/F B Mode (Table 83)
Default: “00” (Mode 0)
(Table 87)
BCKPB: PCM I/F B BICKB
“0”: “↑” SDTOB
, “↓” SDTIB
(default)
, “↑” SDTIB
“1”: “↓” SDTOB
MSBSB: PCM I/F B SYNCB
MSB
“0”: SYNCB
BICKB
“1”: SYNCB
PLLBT3: SRC PLLBT
PLLBT2-0 bits Addr=53H, D5-3
Default: “0000”: SYNCA
(Table 87)
(default)
MSB
(Table 76)
SDOBD: SDTOB Disable (Table 58)
“0”: Enable (default)
“1”: Disable (“L”)
MS0666-J-02
2010/06
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[AK4671]
Addr
56H
Register Name
Digital Volume B Control
R/W
Default
BVL7-0:
Default: “18H” (0dB)
Addr
57H
Register Name
Digital Volume C Control
R/W
Default
CVL7-0:
Default: “18H” (0dB)
Addr
58H
Register Name
Side Tone Volume Control
R/W
Default
SVB2-0:
Default: “0H” (0dB)
SDOA: SDTOA
“0”: SRC-A (default)
“1”: SDTI-B
Addr
59H
Register Name
Digital Mixing Control
R/W
Default
D7
BVL7
R/W
0
D6
BVL6
R/W
0
D5
BVL5
R/W
0
D4
BVL4
R/W
1
D3
BVL3
R/W
1
D2
BVL2
R/W
0
D1
BVL1
R/W
0
D0
BVL0
R/W
0
D5
CVL5
R/W
0
D4
CVL4
R/W
1
D3
CVL3
R/W
1
D2
CVL2
R/W
0
D1
CVL1
R/W
0
D0
CVL0
R/W
0
D5
0
RD
0
D4
0
RD
0
D3
SDOA
R/W
0
D2
SVB2
R/W
0
D1
SVB1
R/W
0
D0
SVB0
R/W
0
D5
SDOL1
R/W
0
D4
SDOL0
R/W
0
D3
BVMX1
R/W
0
D2
BVMX0
R/W
0
D1
SBMX1
R/W
0
D0
SBMX0
R/W
0
B (Table 38)
D7
CVL7
R/W
0
D6
CVL6
R/W
0
C (Table 39)
D7
0
RD
0
D6
0
RD
0
B (Table 40)
(Table 55)
D7
SDOR1
R/W
0
D6
SDOR0
R/W
0
SBMX1-0: SDTOB
Default: “00” (SDTIA)
(Table 57)
BVMX1-0: SRC-B
Default: “00” (SDTIA)
(Table 59)
SDOL1-0: SDTO Lch
(Table 45)
Default: “00” (Lch Signal Selected by Table 44)
SDOR1-0: SDTO Rch
(Table 46)
Default: “00” (Rch Signal Selected by Table 44)
MS0666-J-02
2010/06
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[AK4671]
Addr
5AH
Register Name
SAR ADC Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
GPOM1
R/W
0
D3
GPOE1
R/W
0
D2
A1
R/W
0
D1
A0
R/W
0
D0
PMSAD
R/W
0
PMSAD: 10bit ADC Power Management
“0”: Power down (default)
“1”: Power up
A1-0: SAR ADC Measurement Mode (Table 94)
Default: “00” (SAIN1)
GPOE1: General Purpose Output 1 Enable at GPOM1 bit = “1”
“0”: GPO pin = “L” (default)
“1”: GPO pin = “H”
GPOM1: General Purpose Output 1 Operation Mode
“0”: Controlled by GPOE1 bit (default)
“1”: Controlled by A0 bit
MS0666-J-02
2010/06
- 144 -
[AK4671]
Figure 108
(AKD4671)
Headphone
Analog
Ground
Digital
Ground
Digital
(Base Band)
1.6 ∼ 3.6V
10u
0.1u
TEST
LOUT2
AVDD
VSS1
RCP
ROUT2
MUTET
C
VCOM VCOCBT
VCOC
PVDD
0.1u
0.1u
Base Band
R
0.1u
2.2u
1u
Rp
Cp
Analog
2.2 ∼ 3.6V
VSS2
TVDD2
SDTOA
BICKA
SYNCA
GPO2
CDTI
SDTIA
RCN
VSS4
DVDD
ROUT3
LOUT3
CCLK
CSN
RIN4
LIN4
I2C
BICK
LIN3
RIN3
MCKI
MCKO
Digital
(μP & CPU)
1.6 ∼ 3.6V
Receiver
Ext SPK-Amp
0.1u
μP
Stereo
Speaker
AK4671EG
Top View
Line In
CPU
NC
Internal MIC
IN1+
IN1−
SAIN2
SAVDD
TVDD3
SDTOB
MDT
MPWR
SAIN3
SAIN1
VSS3
SYNCB
PDN
LRCK
BICKB
SDTO
CDTO
SDTIB
SDTI
GPO1
Bluetooth
Module
0.1u
0.1u
1k
IN2−
1k
IN2+
2.2k
External MIC
Digital
(Bluetooth)
1.6 ∼ 3.6V
DC Measurement
:
- AK4671 VSS1, VSS2, VSS3, VSS4
VCOC pin
- EXT mode (PMPLL bit = “0”)
Cp Rp Table 4
- PLL mode (PMPLL bit = “1”)
M/S bit “1”
Hi-Z
AK4671 LRCK, BICK pins
AK4671
- VCOCBT pin C R Table 76
PMPCM bit = “1”
- PDN pin = “H”
PCM I/F
PCM I/F
LRCK, BICK pins
100kΩ
Hi-Z
100kΩ
Figure 108.
(
4
MS0666-J-02
)
2010/06
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[AK4671]
1.
AVDD, PVDD, SAVDD, DVDD, TVDD2, TVDD3
AVDD, PVDD, SAVDD, DVDD, TVDD2, TVDD3
PDN pin = “L”
PDN pin “H”
1)
PDN pin = “L”
PDN pin = “L”
150ns
PDN pin = “H”
DVDD
2)
PDN pin = “L”
DVDD
VSS1, VSS2, VSS3, VSS4
PC
2.
2.2μF
VCOM
0.1μF
VSS1
VCOM pin
VCOM pin
3.
(0.5 x AVDD)
0.6 x AVDD Vpp(typ) (MGNL=MGNR=0dB,
)
fc=1/(2πRC)
DC
AK4671
VSS1
AVDD
4.
DAC
8000H(@16bit)
0.5 x AVDD (typ)
pins
2’s
DC
7FFFH(@16bit)
0000H(@16bit)
VCOM
VCOM
LOUT1, ROUT1, LOUT2, ROUT2, LOUT3/LOP, ROUT3/LON
RCP, RCN pins
DC
MS0666-J-02
2010/06
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[AK4671]
(Audio)
„
ADC
DAC
Power-up
1. PLL
Example:
Power Supply
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
(3)
PMVCM bit
(Addr:00H, D0)
(4)
(1) Power Supply & PDN pin = “L” Æ “H”
MCKO bit
(Addr:02H, D2)
PMPLL bit
(2)Addr:02H, Data:22H
Addr:03H, Data:02H
Addr:01H, Data:F4H
(Addr:02H, D0)
(5)
MCKI pin
Input
M/S bit
(3)Addr:00H, Data:01H
(Addr:02H, D1)
40msec(max)
(6)
BICK pin
LRCK pin
Output
(4)Addr:02H, Data:27H
Output
MCKO, BICK and LRCK output
40msec(max)
(8)
MCKO pin
(7)
Figure 109. Clock Set Up Sequence (1)
<
>
PDN pin “L” Æ “H”
(1)
AK4671
150ns
“L”
(
)
(2)
(3) VCOM
DIF1-0, PLL3-0, FS3-0, BCKO, M/S bits
: PMVCM bit = “0” Æ “1”
VCOM
(4) MCKO
: MCKO bit = “1”
MCKO
: MCKO bit = “0”
(5) PMPLL bit “0” Æ “1”
MCKI pin
PLL
40ms(max.)
(6) PLL
BICK, LRCK
(7) MCKO bit = “1”
MCKO pin
(8) MCKO bit = “1”
PLL
MCKO pin
MS0666-J-02
PLL
2010/06
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[AK4671]
2. PLL
(MCKI pin)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(3)
(2)Addr:03H, Data:02H
Addr:01H, Data:F4H
PMVCM bit
(Addr:00H, D0)
(4)
MCKO bit
(Addr:02H, D2)
(3)Addr:00H, Data:01H
PMPLL bit
(Addr:02H, D0)
(5)
MCKI pin
(4)Addr:02H, Data:25H
Input
40msec(max)
(7)
MCKO pin
MCKO output start
Output
(6)
(8)
BICK pin
LRCK pin
BICK and LRCK input start
Input
Figure 110. Clock Set Up Sequence (2)
<
>
PDN pin “L” Æ “H”
(1)
AK4671
150ns
“L”
(
(2)
(3) VCOM
(4) MCKO
(5) PMPLL bit
PLL
(6)
(7) PLL
(8) MCKO
)
DIF1-0, PLL3-0, FS3-0 bits
PMVCM bit = “0” Æ “1”
VCOM
: MCKO bit = “1”
“0” Æ “1”
MCKI pin
40ms(max.)
MCKO pin
MCKO pin
BICK, LRCK
MS0666-J-02
PLL
2010/06
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[AK4671]
3. PLL
(LRCK or BICK pin)
Example:
Power Supply
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
(3)
PMVCM bit
(Addr:00H, D0)
PMPLL bit
(2) Addr:03H, Data:02H
Addr:01H, Data:83H
(Addr:02H, D0)
LRCK pin
BICK pin
Input
(3) Addr:00H, Data:01H
(4)
Internal Clock
(4) Addr:02H, Data:01H
(5)
Figure 111. Clock Set Up Sequence (3)
<
>
PDN pin “L” Æ “H”
(1)
AK4671
150ns
“L”
(
(2)
(3) VCOM
(4) PMPLL bit
)
DIF1-0, FS3-2, PLL3-0 bits
: PMVCM bit = “0” Æ “1”
VCOM
“0” Æ “1”
PLL
(LRCK or BICK pin)
PLL
LRCK PLL
2ms(max.)
PLL
160ms(max.), BICK
PLL
(5) PLL
MS0666-J-02
2010/06
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[AK4671]
4.
Example:
Audio I/F Format: MSB justified (ADC and DAC)
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(2) Addr:03H, Data:02H
Addr:01H, Data:00H
(3)
PMVCM bit
(Addr:00H, D0)
(4)
MCKI pin
Input
(3) Addr:00H, Data:01H
(4)
LRCK pin
BICK pin
Input
MCKI, BICK and LRCK input
Figure 112. Clock Set Up Sequence (4)
<
>
PDN pin “L” Æ “H”
(1)
AK4671
150ns
“L”
(
)
(2)
(3) VCOM
DIF1-0, FS2-0 bits
PMVCM bit = “0” Æ “1”
VCOM
(4) MCKI, LRCK, BICK
MS0666-J-02
2010/06
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[AK4671]
5.
Example:
Audio I/F Format: MSB justified (ADC and DAC)
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
(1) Power Supply & PDN pin = “L” Æ “H”
Power Supply
(1)
PDN pin
(2) MCKI input
(4)
PMVCM bit
(Addr:00H, D0)
(3) Addr:03H, Data:02H
Addr:01H, Data:00H
Addr:02H, Data:02H
(2)
MCKI pin
Input
(3)
M/S bit
BICK and LRCK output
(Addr:02H, D1)
LRCK pin
BICK pin
Output
(4) Addr:00H, Data:01H
Figure 113. Clock Set Up Sequence (5)
<
>
PDN pin “L” Æ “H”
(1)
AK4671
150ns
“L”
(
(2) MCKI
(3) DIF1-0, FS2-0 bits
(4) VCOM
)
M/S bit “1”
PMVCM bit = “0” Æ “1”
VCOM
MS0666-J-02
LRCK
BICK
2010/06
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[AK4671]
■
Example:
FS3-0 bits
0000
(Addr:01H, D7-4)
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Pre MIC AMP: +15dB
MIC Power: On
ALC setting: Refer to Table 62
ALC: Enable
1111
(1)
MIC Control
55H
(Addr:05H, D7-0)
AAH
(2)
ALC Control 1
(1) Addr:01H, Data:F4H
00H
(Addr:16H)
05H
(2) Addr:05H, Data: AAH
(3)
ALC Control 2
E1H
(Addr:14H)
E1H
(3) Addr:16H, Data:05H
(4)
ALC Control 3
15H
(Addr:17H)
01H
(4) Addr:14H, Data:E1H
(5)
ALC Control 4
02H
(Addr:18H)
03H
02H
ALC State
(5) Addr:17H, Data:01H
(9)
(6)
ALC Disable
ALC Enable
ALC Disable
(6) Addr:18H, Data:03H
(7) Addr:00H, Data:3FH
PMMP bit
(Addr:00H, D1)
Recording
PMMICL/R bits
PMADL/R bits
1059 / fs
(Addr:00H, D5-2)
(8)
(7)
ADC Internal
State
Power Down
(8) Addr:00H, Data:01H
Initialize Normal State Power Down
(9) Addr:18H, Data:02H
Figure 114. Stereo MIC Input Sequence
(MIC Recording: LIN1/RIN1 → MICL/R → ADCL/R → ALC → Audio I/F → SDTO)
<
>
fs=44.1kHz
ALC
ALC
“Figure 62”
(1)
(FS3-0 bits)
PLL mode
PLL
(7)
ADC
(2) MIC-Amp Gain (
05H)
(3) ALC Timer (
16H)
(4) ALC REF (
14H)
(5) LMTH1-0, RGAIN1-0, LMAT1-0 bits (
17H)
(6) ALC bit (
18H)
(7)
ADC
: PMMP = PMMICL = PMMICR = PMADL = PMADR bits = “0” → “1”
ADC
[email protected]=44.1kHz
ALC
(IVL/R7-0 bits)
(0dB)
HPF
“1”
(8)
ADC
PMMP bit = “1”
4
ADC
PMADR bits = “0”)
(IVL/R7-0 bits)
AC
PMVCM bit =
Input Resistance
ADC Power-up
: PMMP = PMMICL = PMMICR = PMADL = PMADR = “1” → “0”
ALC Disable
ALC
(ALC bit = “0”)
ADC
(PMADL =
PMADL = PMADR bits = “0”
(9) ALC Disable: ALC bit = “1” → “0”
MS0666-J-02
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[AK4671]
■
FS3-0 bits
(Addr:01H, D7-4)
0000
1111
E x a m p le :
(1)
HPG3-0 bits
(Addr:08H, D7-4)
1011
P L L M a s ter M o d e
A u d i o I/F F o r m a t: M S B ju s tif i e d ( A D C & D A C )
S a m p l in g F r e q u e n c y : 4 4 . 1 k H z
O V O L C b it = “ 1 ” ( d e f a u lt)
D ig i t a l V o l u m e L e v e l : − 8 d B
H P V o lu m e L e v e l: − 3 d B
5 b a n d E Q : E n a b le
1010
(2)
( 1 ) A d d r :0 1 H , D a t a :F 4 H
DACHL/R bits
(12)
(Addr:0B&0CH, D0)
EQ bit
(Addr:18H, D3)
0
1
0
(3)
( 2 ) A d d r :0 8 H , D a t a A 5 H
A d d r :0 B H & 0 C H , D a t a 0 1 H
( 3 ) A d d r :1 8 H , D a t a 0 A H
(11)
( 4 ) A d d r :1 A H & 1 B H , D a ta 2 8 H
OVL/R7-0 bits
(Addr:1AH&1BH, D7-0)
18H
28H
( 5 ) A d d r :0 0 H , D a t a C 1 H
(4)
PMDAL/R bits
(Addr:00H, D7-6)
( 6 ) A d d r :1 0 H , D a t a 6 3 H
(5)
(10)
( 7 ) A d d r :1 0 H , D a t a 6 7 H
PML/RO2S bits
P la y b a c k
(Addr:10H, D6-5)
(6)
(9)
PML/RO2 bits
(Addr:10H, D1-0)
MUTEN bit
( 8 ) A d d r :1 0 H , D a t a 6 3 H
( 9 ) A d d r :1 0 H , D a t a 0 0 H
(7)
(8)
( 1 0 ) A d d r : 0 0 H , D a ta 0 1 H
(Addr:10H, D2)
LOUT2 pin
ROUT2 pin
( 1 1 ) A d d r : 1 8 H , D a ta 0 2 H
Normal Output
( 1 2 ) A d d r : 0 B H & 0 C H , D a ta 0 0 H
Figure 115. Headphone-Amp Output Sequence
(Headphone Playback: SDTI → Audio I/F → EQ → DATT → DACL/R → LOUT2/ROUT2)
<
>
(1)
(FS3-0 bits)
PLL mode
PLL
(5) DAC
(6) HP-Amp
(2) SDTI Æ DAC Æ HP-Amp
: DACHL = DACHR bits = “0” → “1”
HP-Amp
(
08H, HPG3-0 bits)
(3) 5-band Equalizer ON: EQ bit = “0” Æ “1” (EQ Boost
50H-52H
)
(4)
(
1AH&1BH)
OVOLC bit = “1”(default)
OVL7-0bits(1AH) Lch
Rch
DAC
Default (0dB)
(5) DAC
: PMDAL = PMDAR bits = “0” → “1”
(6) HP-Amp
MIX-Amp
: PMLO2 = PMRO2 = PMLO2S = PMRO2S bits = “0” → “1”
VSS1
(7) HP-Amp
: MUTEN bit = “0” → “1”
MUTET pin
AVDD
MUTET pin
C = 1μF, AVDD=3.3V
τr = 250ms(max.)
(8) HP-Amp
: MUTEN bit = “1” → “0”
MUTET pin
AVDD
VSS1
HP-Amp
VSS1
MUTET pin
C = 1μF, AVDD=3.3V
250ms(max.)
(9) HP-Amp
MIX-Amp
: PMLO2 = PMRO2 = PMLO2S = PMRO2S bits = “1” → “0”
(10) DAC
: PMDAL =PMDAR bits = “1” → “0”
(11) 5-band Equalizer OFF: EQ bit = “1” Æ “0”
(12) DAC Æ HP-Amp
Disable: DACHL = DACHR bits = “1” → “0”
MS0666-J-02
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[AK4671]
■
Example:
FS3-0 bits
(Addr:01H, D7-4)
0000
PLL, Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
OVOLC bit = “1”(default)
Digital Volume Level: −8dB
LINEOUT Volume Level: −3dB
1111
(1)
L3VL1-0 bits
(Addr:11H, D7-D6)
10
01
(1) Addr:01H, Data:F4H
(2)
(2) Addr:11H, Data:40H
Addr:1DH, Data:01H
Addr:15H, Data:05H
Addr:0DH&0EH, Data:01H
PFSEL bis
(Addr:1DH, D0)
PFMXL/R1-0 bits 0000
0101
(Addr:15H, D3-0)
(3) Addr:1AH&1BH, Data:28H
DACSL/R bits
(9)
(Addr:0DH&0EH, D0)
OVL/R7-0 bits
(Addr:1AH&1BH, D7-0)
18H
(4) Addr:11H, Data:44H
(5) Addr:00H, Data:C1H
Addr:11H, Data:47H
28H
(3)
(6) Addr:11H, Data:43H
LOPS3 bit
(Addr:11H, D2)
(4)
(6)
(7)
(10)
PMDAL/R bits
(7) Addr:11H, Data:47H
(Addr:00H, D7-6)
(5)
(8)
(8) Addr:00H, Data:01H
Addr:11H, Data:44H
PML/RO3 bits
(Addr:11H, D1-0)
LOUT3 pin
ROUT3 pin
Playback
>300 ms
>300 ms
(9) Addr:0DH&0E, Data:00H
Normal Output
(10) Addr:11H, Data:40H
Figure 116. Stereo Lineout Sequence
(Speaker Playback: SDTI → Audio I/F → SVOLA → DATT → DACL/R → LOUT3/ROUT3 → External SPK-Amp)
<
>
(1)
(2)
(3)
(4)
(5)
(6)
(FS3-0 bits)
PLL mode
PLL
(6) DAC
SDTI Æ DAC Æ
: PFSEL = “0” Æ “1”, PFMXL1-0 = PFMXR1-0 bits =
“0000” Æ “0101”, DACSL = DACSR bits = “0” Æ “1”
(
11H, L3VL1-0 bits)
(
1AH&1BH)
OVOLC bit = “1”(default)
OVL7-0bits(1AH) Lch
Rch
DAC
Default (0dB)
: LOPS3 bit = “0” Æ “1”
DAC
: PMDAL = PMDAR = PMLO3 = PMRO3 bits = “0” → “1”
PMLO3 = PMRO3 bits = “1” LOUT3, ROUT3 pins
C = 1μF,
AVDD=3.3V
300ms(max.)
: LOPS3 bit = “1” Æ “0”
LOUT3, ROUT3 pins
LOUT3, ROUT3 pins
(7)
(8) DAC
LOUT3, ROUT3 pins
(9) DAC Æ
(10)
LOUT3, ROUT3 pins
: LOPS3 bit: “0” Æ “1”
: PMDAL = PMDAR = PMLO3 = PMRO3 bits = “1” → “0”
C = 1μF, AVDD=3.3V
300ms(max.)
Disable: DACSL = DACSR bits = “1” Æ “0”
: LOPS3 bit = “1” Æ “0”
MS0666-J-02
2010/06
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[AK4671]
■
ADC
DAC
1. PLL
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(Addr:02H, D0)
(1)
MCKO bit
"1" or "0"
(1) Addr:02H, Data:02H
(Addr:02H, D2)
(2)
External MCKI
Input
(2) Stop an external MCKI
Figure 117. Clock Stopping Sequence (1)
<
>
(1) PLL
MCKO
(2) MCKI
2. PLL
: PMPLL bit = “1” → “0”
: MCKO bit = “1” → “0”
(MCKI pin)
Example
(1)
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: MCKI
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
PMPLL bit
(Addr:02H, D0)
(1)
MCKO bit
(1) Addr:02H, Data:00H
(Addr:02H, D2)
(2)
External MCKI
Input
(2) Stop the external clocks
Figure 118. Clock Stopping Sequence (2)
<
>
(1) PLL
MCKO
(2)
3. PLL
: PMPLL bit = “1” → “0”
: MCKO bit = “1” → “0”
(LRCK, BICK pin)
Example
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(Addr:02H, D0)
(2)
External BICK
Input
(1) Addr:02H, Data:00H
(2)
External LRCK
Input
(2) Stop the external clocks
Figure 119. Clock Stopping Sequence (3)
<
>
(1) PLL
(2)
: PMPLL bit = “1” → “0”
MS0666-J-02
2010/06
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[AK4671]
4.
(1)
External MCKI
Input
Example
(1)
External BICK
Input
External LRCK
Input
Audio I/F Format:MSB justified(ADC & DAC)
Input MCKI frequency:1024fs
Sampling Frequency:44.1kHz
(1)
(1) Stop the external clocks
Figure 120. Clock Stopping Sequence (4)
<
>
(1)
5.
(1)
External MCKI
Input
Example
BICK
Output
"H" or "L"
LRCK
Output
"H" or "L"
Audio I/F Format:MSB justified(ADC & DAC)
Input MCKI frequency:1024fs
Sampling Frequency:44.1kHz
(1) Stop the external MCKI
Figure 121. Clock Stopping Sequence (5)
<
>
(1) MCKI
BICK
LRCK
“H”
“L”
■
VCOM
PMVCM bit = “0”
PDN pin = “L”
(typ. 20μA)
(typ. 1μA)
MS0666-J-02
2010/06
- 156 -
[AK4671]
(PCM)
■
ADC
DAC
Power-up
1. PCM I/F A
Example:
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
PLLBT Reference clock: SYNCA
SYNCA frequency: 1fs2
Sampling Frequency: 8kHz
Power Supply
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(3)
PMVCM bit
(2) Addr:02H, Data:C0H
Addr:03H, Data:12H
Addr:54H, Data:00H
Addr:53H, Data:00H
Addr:55H, Data:00H
(Addr:00H, D0)
PMPCM bit
(Addr:53H, D2)
SYNCA pin
BICKA pin
Input
(3) Addr:00H, Data:01H
(4)
Internal Clock
(4) Addr:53H, Data:04H
(5)
Figure 122. Clock Set Up Sequence (1)
<
>
PDN pin “L” Æ “H”
(1)
AK4671
150ns
“L”
(
(2)
)
BTCLK, LP, SDOD, FMTA1-0, LAWA1-0, BCKPA, MSBSA, PLLBT3-0 bits
: PMVCM bit = “0” Æ “1”
VCOM
(4) PMPCM bit “0” Æ “1”
PLLBT
PLLBT
260ms(max.), BICKA PLLBT
(5) PLLBT
(3) VCOM
MS0666-J-02
(SYNCA or BICKA pin)
SYNCA PLLBT
40ms(max.)
PLLBT
2010/06
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[AK4671]
2. PCM I/F A
Example:
Power Supply
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
PLLBT Reference clock: SYNCB
SYNCB frequency: 1fs2
Sampling Frequency: 8kHz
(1)
PDN pin
(2)
(3)
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
PMVCM bit
(Addr:00H, D0)
PMPCM bit
(2) Addr:02H, Data:C0H
Addr:03H, Data:12H
Addr:54H, Data:00H
Addr:53H, Data:00H
Addr:55H, Data:00H
(Addr:53H, D2)
SYNCB pin
BICKB pin
Input
(4)
Internal Clock
(5)
(3) Addr:00H, Data:01H
(6)
SYNCA pin
BICKA pin
Output
(4) Addr:53H, Data:04H
Figure 123. Clock Set Up Sequence (2)
<
>
PDN pin “L” Æ “H”
(1)
AK4671
150ns
“L”
(
(2)
)
BTCLK, LP, SDOD, FMTA1-0, LAWA1-0, BCKPA, MSBSA, PLLBT3-0 bits
: PMVCM bit = “0” Æ “1”
VCOM
(4) PMPCM bit “0” Æ “1”
PLLBT
PLLBT
260ms(max.), BICKB PLLBT
(5) PLLBT
(6) PLLBT
SYNCA, BICKA pins
(3) VCOM
MS0666-J-02
(SYNCB or BICKB pin)
SYNCB PLLBT
40ms(max.)
PLLBT
2010/06
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[AK4671]
■
MIC Control 1
(Addr:04H, D7-0)
14H
00H
Example:
PCM I/F A: Slave Mode
PCM I/F A Format: Linear, Short Frame (ADC & DAC)
Sampling Frequency: 8kHz
Pre MIC AMP: +15dB
MIC Power: On
Digital Volume Level: +17.25dB
ADC HPF: Enable
5 band EQ: Enable
(1)
MIC Control 2
(Addr:05H, D3-0)
HPFAD bit
(Addr:1DH, D1)
0101
1010
0
1
(2)
HPF bit
(Addr:1DH, D4)
(1) Addr:04H, Data:14H
Addr:05H, Data: AAH
(8)
0
1
(2) Addr:1DH, Data:12H
PFMXL1-0 bits
(Addr:15H, D1-0)
00
01
(3) Addr:15H, Data:01H
(3)
EQ bit
(Addr:18H, D3)
0
0
1
IVL7-0 bits
(Addr:12H, D7-0)
(4) Addr:18H, Data:0AH
(9)
(4)
91H
(5) Addr:12H, Data:BFH
BFH
(5)
(6) Addr:00H, Data:17H
Addr:53H, Data:05H
PMMP bit
(Addr:00H, D1)
Phone Call
PMMICL bit
PMADL bit
(Addr:00H, D4&D2)
(7) Addr:00H, Data:01H
Addr:53H, Data:04H
PMSRA bit
(Addr:53H, D0)
1059 / fs
(7)
(6)
ADC Internal
State
Power Down
Initialize Normal State
(8) Addr:1DH, Data:00H
Power Down
(9) Addr:18H, Data:02H
Figure 124. Mono MIC Input Sequence
(Phone Call Tx: IN1+/IN1- → MICL → ADCL → HPF→ IVL → EQ → SRC-A → PCM I/F A → SDTOA)
<
>
PLLBT
, ADC
(6)
SRC-A
(1)
(
04H)
MIC-Amp Gain (
05H)
(2) ADC High Pass Filter ON: HPFAD bit = “0” Æ “1”
High Pass Filter
: HPF bit = “0” Æ “1” (
28H- 2BH
)
fs2=8kHz
HPF
HPFAD = HPF bits = “0”
PMADL = PMADR = PMDAL
= PMDAR bits = “0”
(3) ADC Æ 5-band EQ
: PFMXL1-0 bits = “00” Æ “01”
(4) 5-band Equalizer ON: EQ bit = “0” Æ “1” (EQ Boost
50H-52H
)
(5)
(
12H)
PMADL = PMADR bits = “0”
IVL7-0 = IVR7-0 bits = “91H”(0dB)
(6)
, ADC
SRC-A
: PMMP = PMMICL = PMADL = PMSRA bits = “0” → “1”
ADC
[email protected]=8kHz
HPF
PMMP bit = “1”
ADC Power-up
(7)
, ADC
SRC-A
PMADL = PMADR bits = “0”
PMVCM bit = “1”
Input Resistance
AC
4
: PMMP = PMMICL = PMADL = PMSRA bits = “1” → “0”
(IVL/R7-0 bits)
(8) ADC High Pass Filter OFF: HPFAD bit = “1” Æ “0”
High Pass Filter
: HPF bit = “1” Æ “0”
(9) 5-band Equalizer OFF: EQ bit = “1” Æ “0”
MS0666-J-02
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- 159 -
[AK4671]
■
Example:
L1VL2-0 bits
(Addr:08H, D2-0)
101
PCM I/F A: Slave Mode
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
Sampling Frequency: 8kHz
Digital Volume Level: −8dB
RCV Volume Level: 0dB
5 band EQ: Enable
100
(1)
SRMXR1-0 bits
(Addr:15H, D7-6)
00
(1) Addr:08H, Data:B4H
Addr:15H, Data:40H
Addr:0AH, Data:01H
Addr:0FH, Data:20H
01
DACR bit
(10)
(Addr:0AH, D0)
(2) Addr:18H, Data:0AH
RCV bit
(Addr:0FH, D5)
EQ bit
(Addr:18H, D3)
OVR7-0 bits
(Addr:1BH, D7-0)
(3) Addr:1BH, Data:28H
0
1
0
(2)
(4) Addr:0FH, Data:24H
(9)
18H
(5) Addr:53H, Data:06H
Addr:00H, Data:81H
Addr:0FH, Data:27H
28H
(3)
(6) Addr:0FH, Data:23H
LOPS1 bit
(Addr:0FH, D2)
(6)
(4)
(7)
(11)
PMSRB bit
(7) Addr:0FH, Data:27H
(Addr:53H, D1)
(8) Addr:53H, Data:04H
Addr:00H, Data:01H
Addr:0FH, Data:24H
PMDAR bit
(Addr:00H, D7)
(5)
(8)
PML/RO1 bits
(Addr:0FH, D1-0)
Phone Call
(9) Addr:18H, Data:02H
>1 ms
(10) Addr:0AH, Data:00H
RCP pin
RCN pin
Normal Output
(11) Addr:0FH, Data:20H
Figure 125. Receiver-Amp Output Sequence
(Phone Call Rx: SDTIA → PCM I/F A → SRC-B → EQ → DATT → DACR → RCP/RCN)
<
>
PLLBT
(5)
SRC-B,
DAC
RCV-Amp
(1) SDTIA Æ DAC Æ RCV-Amp
: SRMXR1-0 bits = “00” Æ “01”, DACR bit = “0” Æ “1”, RCV bit =
“0” Æ “1”
RCV-Amp
(
08H, L1VL2-0 bits)
(2) 5-band Equalizer ON: EQ bit = “0” Æ “1” (EQ Boost
50H-52H
)
(3)
(
1BH)
OVOLC bit = “1”(default)
OVL7-0bits(1AH) Lch
Rch
DAC
Default (0dB)
(4)
: LOPS1 bit = “0” Æ “1”
(5) SRC-B , DAC
RCV-Amp
: PMSRB bit = PMDAR = PMLO1 = PMRO1 bits = “0” → “1”
PMLO1 = PMRO1 bits = “1” RCN pin
(6)
: LOPS1 bit = “1” Æ “0”
RCP, RCN pins
RCN pin
(7)
(8) SRC-B , DAC
RCV-Amp
: LOPS1 bit: “0” Æ “1”
: PMSRB bit = PMDAR = PMLO1 = PMRO1 bits = “1” → “0”
(9) 5-band Equalizer OFF: EQ bit = “1” Æ “0”
(10) DAC Æ RCV-Amp
Disable: DACR bit = “1” Æ “0”
(11)
: LOPS1 bit = “1” Æ “0”
RCV-Amp
MS0666-J-02
2010/06
- 160 -
[AK4671]
■
Example:
L3VL1-0 bits
(Addr:11H, D7-D6)
10
PCM I/F A: Slave Mode
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
Sampling Frequency: 8kHz
Digital Volume Level: −8dB
LINEOUT Volume Level: −3dB
5 band EQ: Enable
01
(1) Addr:11H, Data:40H
Addr:15H, Data:40H
Addr:0EH, Data:01H
(1)
SRMXR1-0 bits
(Addr:15H, D7-6)
00
01
(2) Addr:18H, Data:0AH
DACSR bit
(10)
(Addr:0EH, D0)
EQ bit
(Addr:18H, D3)
OVR7-0 bits
(Addr:1BH, D7-0)
(3) Addr:1BH, Data:28H
0
1
0
(2)
(4) Addr:11H, Data:44H
(9)
18H
(5) Addr:53H, Data:06H
Addr:00H, Data:81H
Addr:11H, Data:46H
28H
(3)
(6) Addr:11H, Data:42H
LOPS3 bit
(Addr:11H, D2)
(4)
(6)
(7)
(11)
PMSRB bit
(7) Addr:11H, Data:46H
(Addr:53H, D1)
PMDAR bit
(Addr:00H, D7)
(8)
(5)
PMRO3 bit
(Addr:11H, D1)
(8) Addr:53H, Data:04H
Addr:00H, Data:01H
Addr:11H, Data:44H
(9) Addr:18H, Data:02H
>300 ms
>300 ms
ROUT3 pin
Playback
(10) Addr:0EH, Data:00H
Normal Output
(11) Addr:11H, Data:40H
Figure 126. Mono Lineout Sequence
(Speaker Playback: SDTIA → PCM I/F A → SRC-B → EQ → DATT → DACR → ROUT3 → External SPK-Amp)
<
>
PLLBT
(5)
SRC-B,
DAC
(1) SDTIA Æ DAC Æ
(2)
(3)
(4)
(5)
(6)
: SRMXR1-0 bits = “00” Æ “01”, DACSR bit = “0” Æ “1”
(
11H, L3VL1-0 bits)
5-band Equalizer ON: EQ bit = “0” Æ “1” (EQ Boost
50H-52H
)
(
1BH)
OVOLC bit = “1”(default)
OVL7-0bits(1AH) Lch
Rch
DAC
Default (0dB)
: LOPS3 bit = “0” Æ “1”
SRC-B , DAC
: PMSRB bit = PMDAR = PMRO3 bits = “0” → “1”
PMRO3 bit = “1” ROUT3 pin
C = 1μF, AVDD=3.3V
300ms(max.)
: LOPS3 bit = “1” Æ “0”
ROUT3 pin
ROUT3 pin
(7)
(8) SRC-B , DAC
ROUT3 pin
(9) 5-band Equalizer
(10) DAC Æ
(11)
ROUT3 pin
: LOPS3 bit: “0” Æ “1”
: PMSRB bit = PMDAR = PMRO3 bits = “1” → “0”
C = 1μF, AVDD=3.3V
300ms(max.)
OFF: EQ bit = “1” Æ “0”
Disable: DACSR bit = “1” Æ “0”
: LOPS3 bit = “1” Æ “0”
MS0666-J-02
2010/06
- 161 -
[AK4671]
■
ADC
DAC
1. PCM I/F A
Example
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
PLLBT Reference clock: SYNCA
SYNCA frequency: 1fs2
Sampling Frequency: 8kHz
(1)
PMPCM bit
(Addr:53H, D2)
(2)
External SYNCA
Input
(1) Addr:53H, Data:00H
(2)
External BICKA
Input
(2) Stop the external clocks
Figure 127. Clock Stopping Sequence (1)
<
>
(1) PLLBT
(2)
: PMPCM bit = “1” → “0”
2. PCM I/F A
(1 )
PMPCM bit
(Ad d r:5 3 H , D 2 )
Example
(2 )
External SYNCB
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
PLLBT Reference clock: SYNCB
SYNCB frequency: 1fs2
Sampling Frequency: 8kHz
Input
(2 )
External BICKB
Input
SYNCA
Output
"H" or "L"
BICKA
Output
"H" or "L"
(1) Addr:53H, Data:00H
(2) Stop the external clocks
Figure 128. Clock Stopping Sequence (2)
<
>
(1) PLLBT
(2)
: PMPCM bit = “1” → “0”
SYNCA
BICKA
“H”
“L”
■
VCOM
PMVCM bit = “0”
PDN pin = “L”
(typ. 20μA)
(typ. 1μA)
MS0666-J-02
2010/06
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[AK4671]
5.0 ± 0.1
φ 0.05
A
57 - φ 0.3 ± 0.05
M S AB
9 8 7 65
4 3 2 1
4.0
5.0 ± 0.1
A
B
C
D
E
B
F
G
H
J
0.5
0.5
1.0MAX
0.25 ± 0.05
S
0.08 S
■
:
: BT
: SnAgCu
MS0666-J-02
2010/06
- 163 -
[AK4671]
4671
XXXX
1
A
XXXX: Date code (4 digit)
Pin #A1 indication
Date (YY/MM/DD)
07/10/15
08/12/04
10/06/04
Revision
00
01
02
Reason
Page
163
6
104
Contents
:
BICKA, SYNCA, BICKB, SYNCB:
[VSS4
]
Î[
VSS4
PMPCM bit
“0”
PCM
I/F A(BICKA/SYNCA)
PCM I/F B
(BICKB/SYNCB)
100kΩ
/
]
Table 86:
MSBSA, BCKPA=“00”
[SDTOA MSB
SYNCA “↓”
]
Î[SDTOA MSB
SYNCA “↑”
BICKA “↓”
“↑”
]
MSBSA, BCKPA=“01”
[SDTOA MSB
SYNCA “↓”
]
Î[SDTOA MSB
SYNCA “↑”
BICKA “↑”
“↓”
]
MSBSA, BCKPA=“10”
[SDTOA MSB
SYNCA “↑”
1
BICKA “↑”
]
Î[ SDTOA MSB
SYNCA “↑”
BICKA 2
“↑”
]
MS0666-J-02
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[AK4671]
Date (YY/MM/DD)
10/06/04
Revision
02
Reason
Page
104
Contents
Table 86:
MSBSA, BCKPA=“11”
[SDTOA MSB
BICKA“↓”
Î[ SDTOA MSB
BICKA 2
“↓”
]
Table 87:
MSBSB, BCKPB=“00”
[SDTOB MSB
SYNCA “↑”
1
~
]
SYNCA “↑”
SYNCB “↓”
]
105
~107
Î[SDTOB MSB
SYNCB “↑”
BICKB “↓”
“↑”
]
MSBSB, BCKPB=“01”
[SDTOB MSB
SYNCB “↓”
]
Î[SDTOB MSB
SYNCB “↑”
BICKB “↑”
“↓”
]
MSBSB, BCKPB=“10”
[SDTOB MSB
SYNCB “↑”
1
BICKB “↑”
]
Î[ SDTOB MSB
SYNCB “↑”
BICKB 2
“↑”
]
MSBSB, BCKPB=“11”
[SDTOB MSB
SYNCB “↑”
1
BICKB“↓”
~
]
Î[ SDTOB MSB
SYNCB “↑”
BICKB 2
“↓”
]
Figure 84-91: BICKA SYNCA
MS0666-J-02
2010/06
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[AK4671]
z
z
z
z
z
z
MS0666-J-02
2010/06
- 166 -