データシート

[AK4358]
AK4358
192kHz 24-Bit 8ch DAC with DSD Input
AK4358
8
192kHz
(SCF)
PCM
24
ΔΣ
DAC
DSD
DVD-A, SACD
†
: 8kHz 192kHz
† 24
8
Slow roll-off
† THD+N: -94dB
† DR, S/N: 112dB
†
SCF
† DSD
†
32, 44.1, 48kHz
†
†
†
µP I/F: 3
, I2C
† I/F
:
,
(16bit, 20bit, 24bit), I2S, TDM, DSD
†
: 256fs, 384fs, 512fs or 768fs PCM
128fs, 192fs, 256fs or 384fs PCM 2
128fs or 192fs PCM 4
512fs or 768fs DSD
†
: 4.75 5.25V
† 48pin LQFP
DZF
LOUT1+
LOUT1-
SCF
DAC
DATT
ROUT1+
ROUT1-
SCF
DAC
DATT
LOUT2+
LOUT2-
SCF
DAC
DATT
ROUT2+
ROUT2-
SCF
DAC
DATT
LOUT3+
LOUT3-
SCF
DAC
DATT
ROUT3+
ROUT3-
SCF
DAC
DATT
LOUT4+
LOUT4-
SCF
DAC
DATT
ROUT4+
ROUT4-
SCF
DAC
DATT
Audio
I/F
MCLK
LRCK
BICK
SDTI1
SDTI2
SDTI3
SDTI4
PCM
Control
Register
DSD
3-wire
or I2C
DCLK
DSDL1
DSDR1
DSDL2
DSDR2
DSDL3
DSDR3
DSDL4
DSDR4
AK4358
MS0203-J-02
2009/05
-1-
[AK4358]
■
AK4358VQ
AKD4358
-40∼+85°C
48pin LQFP
ROUT2+
LOUT3+
LOUT3-
ROUT3+
ROUT3-
LOUT4+
LOUT4-
42
41
40
39
38
37
LOUT245
ROUT2-
LOUT2+
46
43
ROUT147
44
ROUT1+
48
■
1
36
LOUT1+
2
35
AVDD
DZF3
3
34
VREFH
DZF2
4
33
ROUT4+
32
ROUT4-
31
DIF0
LOUT1-
AK4358VQ
AVSS
DZF1
5
CAD0
6
ACKSN
7
30
DSDR3
PDN
8
29
DSDL3
BICK
9
28
DSDR2
Top View
17
18
19
20
21
22
23
24
LRCK
I2C
CCLK/SCL
CDTI/SDA
CSN/CAD1
DCLK
DSDL4
DSDR4
DSDL1
16
25
SDTI3
12
15
DVSS
SDTI2
DSDR1
14
DSDL2
26
13
27
SDTI1
10
11
SDTI4
MCLK
DVDD
MS0203-J-02
2009/05
-2-
[AK4358]
■ Compatibility with AK4357
1. Function & Performance
Functions
# of channels
DR
48kHz/96kHz TDM
I2C
DSDM control
Input channel of DZF pin
AK4357
6
106dB
Not available
Not available
Pin/Register
Fixed
AK4358
8
112dB
Available
Available
Register
Programmable
2. Pin Configuration
Pin #
3
4
5
7
12
13
18
19
20
21
22
23
24
32
33
37
38
AK4357
DZFL1
DZFR1
DZF23
CAD1
NC
DVSS
SMUTE
CCLK
CDTI
CSN
DSDM
DCLK
NC
DIF1
DIF2
AVSS
AVSS
AK4358
DZF3
DZF2
DZF1
ACKSN
DVSS
SDTI4
I2C
CCLK/SCL
CDTI/SDA
CSN/CAD1
DCLK
DSDL4
DSDR4
ROUT4ROUT4+
LOUT4LOUT4-
Bit
D5
D6
D7
D7
D7
D7
D7
D7
D7, D6
AK4357
DZFM
0
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
0, 0
Not available
Not available
Not available
Not available
Not available
3. Register
Addr
00H
02H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
AK4358
0
PW4
ATTE
ATTE
ATTE
ATTE
ATTE
ATTE
TDM1, TDM0
LOUT4 ATT Control
ROUT4 ATT Control
DZF1 control
DZF2 control
DZF3 control
MS0203-J-02
2009/05
-3-
[AK4358]
PIN/FUNCTION
No.
1
2
3
4
5
6
7
Pin Name
LOUT1LOUT1+
DZF3
DZF2
DZF1
CAD0
ACKSN
I/O
O
O
O
O
O
I
I
8
PDN
I
9
10
BICK
MCLK
I
I
11
12
13
14
15
16
17
18
DVDD
DVSS
SDTI4
SDTI1
SDTI2
SDTI3
LRCK
I2C
I
I
I
I
I
I
19
CCLK/SCL
I
20
CDTI/SDA
I/O
21
CSN/CAD1
I
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
DCLK
DSDL4
DSDR4
DSDL1
DSDR1
DSDL2
DSDR2
DSDL3
DSDR3
DIF0
ROUT4ROUT4+
VREFH
AVDD
AVSS
LOUT4LOUT4+
ROUT3ROUT3+
LOUT3LOUT3+
ROUT2ROUT2+
LOUT2-
I
I
I
I
I
I
I
I
I
I
O
O
I
O
O
O
O
O
O
O
O
O
Function
DAC1 Lch Negative Analog Output Pin
DAC1 Lch Positive Analog Output Pin
Zero Input Detect 3 Pin
Zero Input Detect 2 Pin
Zero Input Detect 1 Pin
Chip Address 0 Pin
Auto Setting Mode Disable Pin (Pull-down Pin)
“L”: Auto Setting Mode, “H”: Manual Setting Mode
Power-Down Mode Pin
When at “L”, the AK4358 is in the power-down mode and is held in reset.
The AK4358 should always be reset upon power-up.
Audio Serial Data Clock Pin
Master Clock Input Pin
An external TTL clock should be input on this pin.
Digital Power Supply Pin, +4.75∼+5.25V
Digital Ground Pin
DAC4 Audio Serial Data Input Pin
DAC1 Audio Serial Data Input Pin
DAC2 Audio Serial Data Input Pin
DAC3 Audio Serial Data Input Pin
L/R Clock Pin
Control Mode Select Pin
“L”: 3-wire Serial, “H”: I2C Bus
Control Data Clock Pin
I2C = “L”: CCLK (3-wire Serial), I2C = “H”: SCL (I2C Bus)
Control Data Input Pin
I2C = “L”: CDTI (3-wire Serial), I2C = “H”: SDA (I2C Bus)
Chip Select Pin
I2C = “L”: CSN (3-wire Serial), I2C = “H”: CAD1 (I2C Bus)
DSD Clock Pin
DAC4 DSD Lch Data Input Pin
DAC4 DSD Rch Data Input Pin
DAC1 DSD Lch Data Input Pin
DAC1 DSD Rch Data Input Pin
DAC2DSD Lch Data Input Pin
DAC2 DSD Rch Data Input Pin
DAC3 DSD Lch Data Input Pin
DAC3 DSD Rch Data Input Pin
Audio Data Interface Format 0 Pin
DAC4 Rch Negative Analog Output Pin
DAC4 Rch Positive Analog Output Pin
Positive Voltage Reference Input Pin
Analog Power Supply Pin, +4.75∼+5.25V
Analog Ground Pin
DAC4 Lch Negative Analog Output Pin
DAC4 Lch Positive Analog Output Pin
DAC3 Rch Negative Analog Output Pin
DAC3 Rch Positive Analog Output Pin
DAC3 Lch Negative Analog Output Pin
DAC3 Lch Positive Analog Output Pin
DAC2 Rch Negative Analog Output Pin
DAC2 Rch Positive Analog Output Pin
DAC2 Lch Negative Analog Output Pin
MS0203-J-02
2009/05
-4-
[AK4358]
46
LOUT2+
O
DAC2 Lch Positive Analog Output Pin
47
ROUT1O
DAC1 Rch Negative Analog Output Pin
48
ROUT1+
O
DAC1 Rch Positive Analog Output Pin
Note: All input pins except pull-down pin should not be left floating.
(AVSS=DVSS=0V; Note 1)
Parameter
Power Supplies
Analog
Digital
|AVSS-DVSS|
(Note 2)
Input Current (any pins except for supplies)
Digital Input Voltage
Ambient Operating Temperature
Storage Temperature
Symbol
AVDD
DVDD
ΔGND
IIN
VIND
Ta
Tstg
Min
-0.3
-0.3
-0.3
-40
-65
Symbol
AVDD
DVDD
VREF
Min
4.75
4.75
AVDD-0.5
Max
6.0
6.0
0.3
±10
DVDD+0.3
85
150
Units
V
V
V
mA
V
°C
°C
Note 1.
Note 2. AVSS DVSS
:
(AVSS=DVSS=0V; Note 1)
Parameter
Analog
Power Supplies
Digital
(Note 3)
Voltage Reference
Typ
5.0
5.0
-
Max
5.25
5.25
AVDD
Units
V
V
V
Note 3. AVDD DVDD
:
MS0203-J-02
2009/05
-5-
[AK4358]
(
Ta = 25°C; AVDD=DVDD=5.0V;VREFH=AVDD; fs = 44.1kHz; BICK = 64fs;
Signal Frequency = 1kHz; 24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥2kΩ)
Parameter
Min
Typ
Max
Resolution
24
Dynamic Characteristics
(Note 4)
THD+N
fs=44.1kHz
0dBFS
-94
-86
BW=20kHz
-60dBFS
-48
fs=96kHz
0dBFS
-92
-84
BW=40kHz
-60dBFS
-45
fs=192kHz
0dBFS
-92
BW=40kHz
-60dBFS
-45
Dynamic Range (-60dBFS with A-weighted)
(Note 5)
102
112
S/N
(A-weighted)
(Note 6)
102
112
Interchannel Isolation (1kHz)
90
100
Interchannel Gain Mismatch
0.2
0.5
DC Accuracy
Gain Drift
100
Output Voltage
(Note 7)
±2.35
±2.5
±2.65
Load Resistance
(Note 8)
2
Power Supplies
Power Supply Current (AVDD+DVDD)
56
70
Normal Operation (PDN = “H”, fs≤96kHz)
(Note 9)
62
85
Normal Operation (PDN = “H”, fs=192kHz)
(Note 10)
10
100
Power-Down Mode (PDN = “L”)
(Note 11)
Units
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
ppm/°C
Vpp
kΩ
mA
mA
µA
Note 4. Audio Precision (System Two)
Note 5. 100dB at 16bit data.
Note 6. S/N
Note 7.
(0dB)
(AOUT-) = ±2.5Vpp×VREFH/5
Note 8. AC
DC
VREFH
AOUT ([email protected]) = (AOUT+) -
4kΩ
Note 9. AVDD=40mA(Typ), DVDD=12mA(Typ)@44.1kHz&5V, 16mA(Typ)@96kHz&5V
Note 10. AVDD=40mA(Typ), DVDD=22mA(Typ)@192kHz&5V
Note 11.
(MCLK, BICK, LRCK)
DVDD
MS0203-J-02
DVSS
2009/05
-6-
[AK4358]
(Ta = 25°C; AVDD=DVDD = 4.75 ∼ 5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “0”; PCM Mode)
Parameter
Symbol
Min
Typ
Max
Digital filter
PB
0
20.0
Passband
±0.05dB (Note 12)
22.05
-6.0dB
Stopband
(Note 12)
SB
24.1
Passband Ripple
PR
± 0.02
Stopband Attenuation
SA
54
Group Delay
(Note 13)
GD
19.1
Digital Filter + SCF
Frequency Response 20.0kHz Fs=44.1kHz
FR
± 0.2
40.0kHz Fs=96kHz
FR
± 0.3
80.0kHz Fs=192kHz
FR
+0/-0.6
Note 12.
fs (
)
Units
kHz
kHz
kHz
dB
dB
1/fs
dB
dB
dB
PB=0.4535×fs(@±0.05dB)
SB=0.546×fs
Note 13.
16/24
(Ta = 25°C; AVDD=DVDD = 4.75~5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “1”; PCM Mode)
Parameter
Symbol
Min
(Note 14)
PB
(Note 14)
SB
PR
SA
GD
0
39.2
Typ
Max
Units
18.2
8.1
-
Digital Filter
Passband
±0.04dB
-3.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 13)
72
-
19.1
-
kHz
kHz
kHz
dB
dB
1/fs
-
+0/-5
+0/-4
+0/-5
-
dB
dB
dB
± 0.005
Digital Filter + SCF
Frequency Response
Note 14.
20.0kHz
40.0kHz
80.0kHz
fs=44.kHz
fs=96kHz
fs=192kHz
FR
FR
FR
fs (
)
PB = 0.185×fs (@±0.04dB), SB =
0.888×fs.
DC
(Ta = 25°C; AVDD=DVDD = 4.75 ∼ 5.25V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout = -80µA)
Low-Level Output Voltage
(Iout = 80µA)
Input Leakage Current
(Note 15)
Symbol
VIH
VIL
VOH
VOL
Iin
Min
2.2
DVDD-0.4
-
Typ
-
Max
0.8
0.4
± 10
Units
V
V
V
V
µA
Note 15. ACKSN pin has internal pull-down devices, nominally 100kΩ.
MS0203-J-02
2009/05
-7-
[AK4358]
(Ta = 25°C; AVDD=DVDD = 4.75 ∼ 5.25V; CL = 20pF)
Parameter
Master Clock Frequency
Duty Cycle
LRCK Frequency
Normal Mode (TDM0= “L”, TDM1= “L”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
TDM256 mode (TDM0= “H”, TDM1= “L”)
Normal Speed Mode
High time
Low time
TDM128 mode (TDM0= “H”, TDM1= “H”)
Normal Speed Mode
Double Speed Mode
High time
Low time
PCM Audio Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge
(Note 16)
LRCK Edge to BICK “↑”
(Note 16)
SDTI Hold Time
SDTI Setup Time
DSD Audio Interface Timing
DCLK Period
DCLK Pulse Width Low
Pulse Width High
DCLK Edge to DSDL/R
(Note 17)
Control Interface Timing (3-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 18)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
MS0203-J-02
Symbol
fCLK
dCLK
Min
2.048
40
fsn
fsd
fsq
Duty
Typ
11.2896
Max
36.864
60
Units
MHz
%
8
60
120
45
48
96
192
55
kHz
kHz
kHz
%
fsn
tLRH
tLRL
32
3/256fs
3/256fs
48
kHz
ns
ns
fsn
fsd
tLRH
tLRL
32
60
3/128fs
3/128fs
48
96
kHz
kHz
ns
ns
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
81
30
30
20
20
10
10
ns
ns
ns
ns
ns
ns
ns
tDCK
tDCKL
tDCKH
tDDD
1/64fs
160
160
-20
ns
ns
ns
ns
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
4.7
4.0
4.7
4.0
4.7
0
0.25
4.0
0
20
ns
ns
ns
ns
ns
ns
ns
ns
100
1.0
0.3
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
2009/05
-8-
[AK4358]
Parameter
Reset Timing
PDN Pulse Width
Note 16.
(Note 19)
LRCK
BICK
Symbol
Min
tPD
150
Typ
Max
Units
ns
“↑”
Note 17.
Note 18.
300ns(SCL
Note 19.
PDN
2
Note 20. I C
)
“L”
Philips Semiconductors
MS0203-J-02
2009/05
-9-
[AK4358]
■
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDS
tSDH
VIH
SDTI
VIL
Audio Serial Interface Timing (PCM Mode)
MS0203-J-02
2009/05
- 10 -
[AK4358]
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Normal Mode, DCKB = “0”)
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB = “0”)
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
A4
VIH
VIL
WRITE Command Input Timing
MS0203-J-02
2009/05
- 11 -
[AK4358]
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
CDTI
D3
D2
D1
VIH
D0
VIL
WRITE Data Input Timing
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
I2C Bus mode Timing
tPD
PDN
VIL
Power-down Timing
MS0203-J-02
2009/05
- 12 -
[AK4358]
■ D/A
AK4358 PCM
DSD
DSDR1-4
DSD
D/P
(PW1=PW2=PW3=PW4= “0”)
D/A
PCM
D/P
PDN
D/P bit
0
1
DSD
BICK, SDTI1-4, LRCK
PCM/DSD
2~3/fs
DCLK, DSDL1-4,
PCM
RSTN
PW
DAC Output
PCM
DSD
Table 1. DSD/PCM
■
1) PCM
MCLK, LRCK, BICK
(LRCK)
MCLK
ΔΣ
MCLK
(Manual Setting Mode)
(Auto Setting Mode)
Manual Setting Mode (ACKS = “0”: Register 00H)
DFS0/1
(Table 2)
MCLK
(Table 3~Table 5)
Auto Setting Mode (ACKS = “1”: Default)
MCLK
(Table 6)
(Table 7)
DFS0/1
ACKSN
“H”
ACKS
Manual Setting Mode
ACKSN
“L”
ACKS
(PDN= “H”)
(MCLK)
(MCLK, BICK, LRCK)
(PDN= “L”)
DSD
ON
(PDN = “↑”)
DCLK,DSDL1-4,DSDR1-4
“H”
MCLK
“L”
DFS1
DFS0
Sampling Rate (fs)
0
0
Normal Speed Mode
8kHz~48kHz
0
1
Double Speed Mode
60kHz~96kHz
1
0
Quad Speed Mode
Table 2.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
Table 3.
Default
120kHz~192kHz
(Manual Setting Mode)
MCLK
384fs
512fs
12.2880MHz 16.3840MHz
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
(Normal Speed Mode
MS0203-J-02
768fs
24.5760MHz
33.8688MHz
36.8640MHz
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
Manual Setting Mode)
2009/05
- 13 -
[AK4358]
LRCK
fs
88.2kHz
96.0kHz
MCLK
192fs
256fs
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
128fs
11.2896MHz
12.2880MHz
Table 4.
(Double Speed Mode
LRCK
fs
176.4kHz
192.0kHz
(Quad Speed Mode
MCLK
512fs
768fs
256fs
384fs
128fs
192fs
Manual Setting Mode)
(Auto Setting Mode)
MCLK (MHz)
256fs
384fs
22.5792
33.8688
24.5760
36.8640
-
192fs
33.8688
36.8640
BICK
64fs
11.2896MHz
12.2880MHz
Sampling Speed
Normal
Double
Quad
Table 6.
128fs
22.5792
24.5760
BICK
64fs
5.6448MHz
6.1440MHz
Manual Setting Mode)
MCLK
128fs
192fs
22.5792MHz 33.8688MHz
24.5760MHz 36.8640MHz
Table 5.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
384fs
33.8688MHz
36.8640MHz
Table 7.
ACKSN pin
0
0
1
1
512fs
16.3840
22.5792
24.5760
-
768fs
24.5760
33.8688
36.8640
-
Sampling Speed
Normal
Double
Quad
(Auto Setting Mode)
ACKS bit
0
1
0
1
Table 8. ACKSN
Clock Mode
Manual Setting Mode
Auto Setting Mode
Manual Setting Mode
Manual Setting Mode
(Default)
ACKS
2) DSD
MCLK, DCLK
MCLK
(PDN= “H”)
(MCLK)
DCKS
DSD
(DCLK)
(MCLK, DCLK)
(PDN= “L”)
PCM
ON
(PDN = “↑”)
BICK, LRCK, SDTI
“H”
MS0203-J-02
MCLK
“L”
2009/05
- 14 -
[AK4358]
DCKS
MCLK
DCLK
0
512fs
64fs
Table 9.
1
768fs
64fs
(fs=44.1kHz)
■
1) PCM
PCM
(Table 10) DIF0
OR
TDM0
BICK LRCK
DIF0-2
MSB
Mode 2 16/20
SDTI1-4
DIF0-2
2’s
5
“010” DIF0
DIF0
BICK
LSB
“0”
“1”
TDM256
I/F TDM
TDM1
“0”
(Table 11)
SDTI1
DAC(8ch)
SDTI2-4
BICK 256fs
LRCK “H”
“L”
3/256fs(min)
MSB
2’s
SDTI1 BICK
TDM128
(TDM1 = “1”, Table 12)
SDT1
DAC (L1,R1,L2,R2) SDT2
DAC (L3,R3,L4,R4)
4ch
SDTI3-4
BICK 128fs
Mode
0
1
2
3
4
TDM1
0
0
0
0
0
TDM0
0
0
0
0
0
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
SDTI Format
16bit
20bit
24bit
24bit I2S
24bit
Table 10.
LRCK
H/L
H/L
H/L
L/H
H/L
BICK
≥32fs
≥40fs
≥48fs
≥48fs
≥48fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
Default
(Normal mode)
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDTI
Mode 0
15
0
14
1
6
5
14
4
15
3
16
2
17
1
0
31
15
0
14
1
6
5
14
4
15
3
16
2
17
1
0
31
15
0
14
1
BICK
(64fs)
SDTI
Mode 0
Don’t care
15
14
0
Don’t care
15
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
MS0203-J-02
2009/05
- 15 -
[AK4358]
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
0
1
BICK
(64fs)
SDTI
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDTI
Mode 4
Don’t care
23
22
21
20
23
22
20
21
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1,4 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDTI
23
22
1
0
Don’t care
23
22
0
1
Don’t care
23
22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
23 22
1
0
Don’t care
23 22
1
0
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
MS0203-J-02
2009/05
- 16 -
[AK4358]
Mode
5
6
7
TDM1
0
0
0
0
0
TDM0
1
1
1
1
1
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
SDTI Format
N/A
N/A
24bit
24bit I2S
24bit
Table 11.
LRCK
BICK
Figure
↑
↓
↑
256fs
256fs
256fs
Figure 5
Figure 6
Figure 7
(TDM256 mode)
3/256fs (min)
3/256fs (min)
256 BICK
LRCK
BICK(256fs)
SDTI1(i)
23 22
0
23 22
0
23 22
L1
R1
32 BICK
32 BICK
0
23 22
0
23 22
L2
R2
32 BICK
32 BICK
0
23 22
0
23 22
0
23 22
0
23 22
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
Figure 5. Mode 5 Timing
3/256fs (min)
256 BICK
3/256fs (min)
LRCK
BICK(256fs)
SDTI1(i)
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
Figure 6. Mode 6 Timing
3/256fs (min)
256 BICK
3/256fs (min)
LRCK
BICK(256fs)
SDTI1(i)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0
23
Figure 7. Mode 7 Timing
MS0203-J-02
2009/05
- 17 -
[AK4358]
Mode
8
9
10
TDM1
1
1
1
1
1
TDM0
1
1
1
1
1
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
SDTI Format
N/A
N/A
24bit
24bit I2S
24bit
Table 12.
LRCK
BICK
Figure
↑
↓
↑
128fs
128fs
128fs
Figure 8
Figure 9
Figure 10
(TDM128 mode)
3/128fs (min)
128 BICK
3/128fs (min)
LRCK
BICK(128fs)
SDTI1(i)
SDTI2(i)
23 22
23 22
0
0
23 22
L1
R1
32 BICK
32 BICK
32 BICK
23 22
23 22
0
0
23 22
0
L2
23 22
R2
32 BICK
23 22
0
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
0
23 22
0
23 22
0
23
0
23
Figure 8. Mode 8 Timing
3/128fs (min)
128 BICK
3/128fs (min)
LRCK
BICK(128fs)
SDTI1(i)
SDTI2(i)
23 22
0
23 22
0
0
23 22
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
0
23 22
23 22
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
Figure 9. Mode 9 Timing
3/128fs (min)
128 BICK
3/128fs (min)
LRCK
BICK(128fs)
SDTI1(i)
SDTI2(i)
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
0
19
0
19
Figure 10. Mode 10 Timing
MS0203-J-02
2009/05
- 18 -
[AK4358]
2) DSD
DSD
DIF0-2
DCLK
64fs
DCLK
DCKB
DCLK (64fs)
DCKB=1
DCLK (64fs)
DCKB=0
DSDL,DSDR
Normal
D0
D1
DSDL,DSDR
Phase Modulation
D1
D0
D2
D2
D1
D3
D3
D2
Figure 11. DSD Mode Timing
■ D/A
RSTN bit
≥4/fs
D/A Mode
PCM Mode
DSD Mode
≥0
D/A Data
PCM Data
DSD Data
Figure 12. D/A
(PCM to DSD)
RSTN bit
D/A Mode
DSD Mode
PCM Mode
≥4/fs
D/A Data
DSD Data
PCM Data
Figure 13. D/A
DSD
DSD
25%
(DSD to PCM)
75%
SACD
MS0203-J-02
Scarlet Book
2009/05
- 19 -
[AK4358]
■
IIR
3
(32kHz, 44.1kHz, 48kHz)
Double Speed Mode, Quad Speed Mode
OFF
DEM1
DEM0
Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF
48kHz
32kHz
Table 13.
(50/15μs
DSD
)
DEM0-1
Default
(Normal Speed Mode)
■
AK4358 SMUTE
DAC
ATS1-0
DAC
ATTE
0.5dB
128
0dB
-63dB
(Table 15) Mode0 Mode1
ATTE
“0”
ATT
ATT6-0
DAC
“0”
“1”
ATTE
1
0
ATT6-0
7FH
7EH
7DH
:
02H
01H
00H
Don’t care
Attenuation Level
0dB
-0.5dB
-1.0dB
:
-62.5dB
-63.0dB
SMUTE (-∞)
OFF ( “0” )
Default
Table 14.
Mode
0
1
2
3
ATS1
0
0
1
1
ATS0
0
1
0
1
ATT speed
1792/fs
896/fs
256/fs
N/A
Default
Table 15.
Mode0
7FH(0dB)
896/fs
ATT7-0 7FH
PCM
00H(SMUTE)
1792/fs
Mode1
7FH(0dB)
00H(MUTE)
Mode2,3
7FH(0dB)
00H(MUTE)
256/fs
PDN
“L”
ATT6-0 RSTN
“0”
7FH
RSTN
“1”
DSD
MS0203-J-02
2009/05
- 20 -
[AK4358]
■
8192/fs
“0”
AK4358 Table 16
“0”
DZF
“H”
DZF
“L”
“H”
RSTN
DZFE
“0”
“0”
DZFB
DZF
DZF1
DZF2
DZF3
“1”
PW1-4
“0”
“1”
“1”
“1”
DAC
DAC
DAC
0DH
0EH
0FH
DZF
“L”
“0”
RSTN
“0”
DZF
4~5LRCK
DZF
“L”
PW1-4
PW
“0”
DAC
DZF
“L”
DZF
AND
AND
AND
Table 16. DZF
■
×ATT
(Table 15)
-∞
ATT
×ATT
SMUTE
-∞ (“0”)
ATT
“1”
ATT
SMUTE
ATT
“0”
-∞
-∞
ATT
SMUTE bit
(1)
(1)
ATT Level
(3)
Attenuation
-∞
GD
GD
(2)
AOUT
(4)
8192/fs
DZF pin
:
(1) ATT
(2)
(3)
×ATT
(Table 15)
Mode 0
ATT
“128”
1792/fs
(GD)
-∞
0dB
(4)
“0”
DZF
8192/fs
“L”
“0”
DZF
“H”
Figure 14.
MS0203-J-02
2009/05
- 21 -
[AK4358]
■
ON
PDN
“L”
MCLK
MCLK 4/fs
■
AK4358 PDN
“L”
DAC
PDN
DAC
(PW1-4)
“0”
Hi-Z
PDN
Internal
State
Normal Operation
Power-down
D/A In
(Digital)
Normal Operation
“0” data
GD
(1)
D/A Out
(Analog)
GD
(2)
(3)
(3)
(1)
(4)
Clock In
Don’t care
MCLK, LRCK, BICK
DZF
(6)
External
MUTE
(5)
(1)
(2)
(3) PDN
(4)
(5)
(6)
Mute ON
(GD)
Hi-Z
(“↑ ↓”)
“0”
(PDN = “L”)
(MCLK, BICK, LRCK)
(3)
(PDN
= “L”)
Figure 15.
DZF
“L”
/
MS0203-J-02
2009/05
- 22 -
[AK4358]
■
RSTN
VCOM
“0”
DZF
DAC
“H”
Figure 16 RSTN
RSTN bit
3~4/fs (6)
2~3/fs (6)
Internal
RSTN bit
Internal
State
Normal Operation
Normal Operation
Digital Block Power-down
D/A In
(Digital)
“0” data
(1)
GD
GD
(2)
(3)
D/A Out
(Analog)
(3)
(1)
(4)
Clock In
Don’t care
MCLK,LRCK,BICK
2/fs(5)
DZF
(1)
(2) RSTN = “0”
(3)
RSTN
(4)
(5) DZF
“L”
(6) RSTN
(GD)
VCOM
(“↓ ↑”)
(RSTN = “0”)
RSTN
“0”
(MCLK, BICK, LRCK)
"H"
LSI
RSTN
LSI
RSTN
2/fs
3 ~4/fs
2 ~ 3/fs
Figure 16.
MS0203-J-02
2009/05
- 23 -
[AK4358]
■
2
CAD1
C1
“1”
I2C
(3
3
I2C
)
CAD0,
C0
PDN
CAD0
“L”
RSTN
“0”
* AK4358
* PDN = “L”
Function
Manual Setting Mode
De-emphasis
DZFE
SMUTE
Audio data format
DSD mode
Attenuator
Slow roll-off response
O
X
X
X
DIF0
X
X
X
Table 17.
(1) 3
(O:
O
O
O
O
O
O
O
O
, X:
)
(I2C = “L”)
3
I/F
: CSN, CCLK, CDTI
I/F
Chip address
(2bit, C1= “1”
C0=CAD0), Read/Write (1bit, “1”
, Write only), Register address (MSB first, 5bit) Control
data (MSB first, 8bit)
CCLK “↑”
CSN “↑”
CCLK
5MHz (max)
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1= “1”, C0=CAD0)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 17. Control I/F Timing
MS0203-J-02
2009/05
- 24 -
[AK4358]
(2) I2C
AK4358
(I2C= “H”)
I 2C
(max:100kHz)
I2C
(Start Condition)
SCL
(Figure 22)
(R/W)
(Figure 19)
CAD1-0
(Acknowledge)
Write
(Not Acknowledge)
(Figure 23)
2
(
(Figure 20)
3
(Figure 21) AK4358
(Stop Condition)
(Figure 22)
Figure 18
“H”
SDA
5
(max:400kHz)
IC
“L”
“H”
7
2
“00100”
R/W
R/W
8
IC
AK4358
“0”
AK4358
“1”
SDA
)
8
SCL
MSB first
8
“H”
3
SDA
AK4358
“0”
MSB first
“L”
“H”
1
“0FH”
“00H”
“H”
SCL
SDA
“L”
S
T
A
R
T
SDA
S
“H” “L”
“H”
SDA
(Figure 24) SCL
S
T
O
P
R/W
Slave
Address
Sub
Address(n)
A
C
K
Data(n)
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 18. I2C
0
0
1
0
0
(CAD1, CAD0
Figure 19.
0
0
0
D6
D5
Figure 21.
CAD0
R/W
)
1
A4
Figure 20.
D7
CAD1
A3
A2
A1
A0
D3
D2
D1
D0
2
D4
3
MS0203-J-02
2009/05
- 25 -
[AK4358]
SDA
SCL
S
P
start condition
stop condition
Figure 22.
DATA
OUTPUT BY
MASTER
not acknowledge
DATA
OUTPUT BY
SLAVE(AK4529)
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 23. I2C
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 24. I2C
MS0203-J-02
2009/05
- 26 -
[AK4358]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
Register Name
Control 1
Control 2
Speed & Power Down Control
De-emphasis Control
LOUT1 ATT Control
ROUT1 ATT Control
LOUT2 ATT Control
ROUT2 ATT Control
LOUT3 ATT Control
ROUT3 ATT Control
Control 3
LOUT4 ATT Control
ROUT4 ATT Control
DZF1 Control
DZF2 Control
DZF3 Control
D7
ACKS
0
0
0
ATTE
ATTE
ATTE
ATTE
ATTE
ATTE
TDM1
ATTE
ATTE
L1
L1
L1
D6
SLOW
0
PW4
0
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
TDM0
ATT6
ATT6
R1
R1
R1
D5
0
0
DFS1
D4
DZFE
0
DFS0
D3
DIF2
0
PW3
D2
DIF1
0
PW2
D1
DIF0
0
0
0
0
DEM1
DEM0
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
DCKS
ATT5
ATT5
L2
L2
L2
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
D/P
ATT4
ATT4
R2
R2
R2
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
DCKB
ATT3
ATT3
L3
L3
L3
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
DZFB
ATT2
ATT2
R3
R3
R3
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATS1
ATT1
ATT1
L4
L4
L4
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATS0
ATT0
ATT0
R4
R4
R4
SMUTE
PW1
D0
RSTN
RSTN
RSTN
Note: For addresses from 10H to 1FH, data must not be written.
When PDN goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the only internal timing is reset, and the registers are not initialized to their default
values. All data can be written to the registers even if PW1-4 or RSTN bit is “0”.
ACKS bit is ANDed with the ACKSN pin.
DIF0 bit is ORed with the DIF pin.
MS0203-J-02
2009/05
- 27 -
[AK4358]
■ Register Definitions
Addr
00H
Register Name
Control 1
Default
D7
ACKS
1
D6
SLOW
0
D5
0
0
D4
DZFE
1
D3
DIF2
0
D2
DIF1
1
D1
DIF0
0
D0
RSTN
1
RSTN: Internal timing reset
0: Reset. All DZF pins go to “H” and any registers are not initialized.
1: Normal operation
When MCLK frequency or DFS changes, the AK4358 should be reset by PDN pin or RSTN bit.
DIF2-0: Audio data interface modes (See Table 10, Table 11, Table 12, PCM Only)
Initial: “010”,
Register bit of DIF0 is ORed with the DIF0 pin.
DZFE: Data Zero Detect Enable
0: Disable
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins are “L” at DZFB bit “0”
and are “H” at DZFB bit “1”.
SLOW: Slow Roll-off Filter Enable (PCM Only)
0: Sharp Roll-off Filter
1: Slow Roll-off Filter
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0 is
ignored. When this bit is “0”, DFS1-0 set the sampling speed mode.
Register bit of ACKS is ANDed with the inverted of the ACKSN pin.
Addr
01H
Register Name
Control 2
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
SMUTE
0
D0
RSTN
1
RSTN: Internal timing reset
0: Reset. All DZF pins of go to “H” and any registers are not initialized.
1: Normal operation
When MCLK frequency or DFS changes, the AK4358 should be reset by PDN pin or RSTN bit.
SMUTE: Soft Mute Enable
0: Normal operation
1: All DAC outputs soft-muted
MS0203-J-02
2009/05
- 28 -
[AK4358]
Addr
02H
Register Name
Speed & Power Down Control
Default
D7
0
0
D6
PW4
1
D5
DFS1
0
D4
DFS0
0
D3
PW3
1
D2
PW2
1
D1
PW1
1
D0
RSTN
1
RSTN: Internal timing reset
0: Reset. All DZF pins go to “H” and any registers are not initialized.
1: Normal operation
When MCLK frequency or DFS changes, the AK4358 should be reset by PDN pin or RSTN bit.
PW4-1: Power-down control (0: Power-down, 1: Power-up)
PW1: Power down control of DAC1
PW2: Power down control of DAC2
PW3: Power down control of DAC3
PW4: Power down control of DAC4
All sections are powered-down by PW1=PW2=PW3=PW4=0.
DFS1-0: Sampling speed control (See Table 2, PCM Only)
00: Normal speed
01: Double speed
10: Quad speed
When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs.
Addr
03H
Register Name
De-emphasis Control
Default
D7
0
0
D6
0
0
D5
D4
D3
D2
D1
D0
0
0
0
0
DEM1
DEM0
0
0
0
0
0
1
DEM1-0: De-emphasis response control for DAC1/2/3/4 data on SDTI1/2/3/4 (See Table 13, PCM only)
Initial: “01”, OFF
Addr
04H
05H
06H
07H
08H
09H
0BH
0CH
Register Name
LOUT1 ATT Control
ROUT1 ATT Control
LOUT2 ATT Control
ROUT2 ATT Control
LOUT3 ATT Control
ROUT3 ATT Control
LOUT4 ATT Control
ROUT4 ATT Control
Default
D7
ATTE
ATTE
ATTE
ATTE
ATTE
ATTE
ATTE
ATTE
1
D6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
1
D5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
1
D4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
1
D3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
1
D2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
1
D1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
1
D0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
1
ATT6-0: Attenuation Level
128 levels, 0.5dB step (See Table 14)
ATTE: Attenuation Output Enable
0: Disable
1: Enable
MS0203-J-02
2009/05
- 29 -
[AK4358]
Addr
0AH
Register Name
Control 3
Default
D7
TDM1
0
D6
TDM0
0
D5
DCKS
0
D4
D/P
0
D3
DCKB
0
D2
DZFB
0
D1
ATS1
0
D0
ATS0
0
ATS1-0: DATT Speed Setting (See Table 15)
Initial: “00”, mode 0
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge
1: DSD data is output from DCLK rising edge
D/P: DSD/PCM Mode Select
0: PCM Mode. SCLK, SDTI1-4, LRCK
1: DSD Mode. DCLK, DSDL1-4, DSDR1-4
When D/P changes form “1” to “0”, the AK4358 should be reset by PDN pin, PW bit or RSTN bit.
When D/P changes form “0” to “1”, the AK4358 should be reset by PW bit or RSTN bit.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs
1: 768fs
TDM0-1: TDM Mode Select (PCM only)
Mode
Normal
TDM256
TDM128
Addr
0DH
Register Name
DZF1 Control
Default
TDM1
0
0
1
TDM0
0
1
1
D7
L1
1
BICK
32fs∼
256fs fixed
128fs fixed
D6
R1
1
SDTI
1-4
1
1-2
D5
L2
1
Sampling Speed
Normal, Double, Quad Speed
Normal Speed
Normal, Double Speed
D4
R2
1
D3
L3
1
D2
R3
1
D1
L4
1
D0
R4
1
D4
R2
R2
0
D3
L3
L3
0
D2
R3
R3
0
D1
L4
L4
0
D0
R4
R4
0
L1-4, R1-4: Zero Detect Flag Enable Bit for DZF1 pin
0: Disable
1: Enable
Addr
0EH
0FH
Register Name
DZF2 Control
DZF3 Control
Default
D7
L1
L1
0
D6
R1
R1
0
D5
L2
L2
0
L1-4, R1-4: Zero Detect Flag Enable Bit for DZF2,3 pins
0: Disable
1: Enable
MS0203-J-02
2009/05
- 30 -
[AK4358]
Figure 25
(AKD4358)
+
10u
Digital 5V
0.1u
Reset
4
3
2
DZF2
DZF3
LOUT1+
1
5
DZF1
LOUT1-
6
CAD0
7
8
PDN
9
BICK
ROUT1- 47
15 SDTI2
LOUT2+ 46
16 SDTI3
LOUT2- 45
AK4358
ROUT2- 43
19 CCLK/SCL
LOUT3- 41
35 AVDD
34 VREFH
33 ROUT4+
32 ROUT4-
25
31 DIF0
DSDL1
Data
30 DSDR3
LOUT4+ 38
29 DSDL3
23 DSDL4
28 DSDR2
ROUT3- 39
26 DSDR1
ROUT3+ 40
22 DCLK
27 DSDL2
21 CSN/CAD1
DSD
LPF
MUTE
R1ch
OUT
LPF
MUTE
L2ch
OUT
LPF
MUTE
R2ch
OUT
LPF
MUTE
L3ch
OUT
LPF
MUTE
R3ch
OUT
LPF
MUTE
L4ch
OUT
LOUT3+ 42
Top View
20 CDTI/SDA
DSDR4
L1ch
OUT
ROUT2+ 44
18 I2C
24
MUTE
48
14 SDTI1
17 LRCK
uP
ROUT1+
LPF
LOUT4- 37
36 AVSS
DSP
CAD1
13 SDTI4
MCLK 10
DVSS 12
Gen
DVDD 11
Clock
Controller
Analog 5V
+
0.1u
10u
Mode
Control
LPF
System Ground
MUTE
R4ch
OUT
Analog Ground
Figure 25. Typical Connection Diagram
Notes:
- LRCK = fs, BICK=64fs.
- AOUT
-
MS0203-J-02
2009/05
- 31 -
[AK4358]
3
2
DZF3
LOUT1+
ROUT1+ 48
14 SDTI1
ROUT1-
47
15 SDTI2
LOUT2+
46
16 SDTI3
LOUT2-
45
17 LRCK
ROUT2+ 44
AK4358
18 I2C
ROUT2-
43
19 CCLK/SCL
LOUT3+
42
20 CDTI/SDA
LOUT3-
41
21 CSN/CAD1
ROUT3+ 40
36 AVSS
35 AVDD
34 VREFH
33 ROUT4+
32 ROUT4-
31 DIF0
30 DSDR3
37
28 DSDR2
38
LOUT4-
24 DSDR4
27 DSDL2
39
LOUT4+
26 DSDR1
ROUT3-
23 DSDL4
25 DSDL1
22 DCLK
29 DSDL3
Controller
1
4
DZF2
13 SDTI4
System
LOUT1-
6
5
7
CAD1
DZF1
8
PDN
CAD0
9
BICK
MCLK 10
DVSS 12
Analog Ground
DVDD 11
Digital Ground
Figure 26.
: AVSS DVSS
1.
AVDD DVDD
AVDD DVDD
AVSS DVSS
PC
(0.1μF)
2.
VREF
0.1μF
VREF
VREF
AVDD
AVSS
3.
DAC
1
800000H(@24bit)
AVDD/2
0.5xVREF Vpp (typ)
AOUT+ AOUTVAOUT=(AOUT+)-(AOUT-)
5.0Vpp (typ @VREF=5V)
2’s
7FFFFFH(@24bit)
000000H(@24bit)
AOUT
0V
(SCF)
LPF
AOUT+/-
MS0203-J-02
DC
2009/05
- 32 -
[AK4358]
4.
SACD
-30dB/oct
Scarlet Book
SACD
AK4358
50kHz
(Table 18)
Frequency
20kHz
50kHz
100kHz
(Figure 27)
Gain
-0.4dB
-2.8dB
-15.5dB
Table 18. Internal Filter Response at DSD mode
2.0k
AOUT-
1.8k
4.3k
1.0k
2.5Vpp
2200p
270p
+Vop
3300p
2.0k
1.8k
1.0k
AOUT+
-
Analog
Out
+
4.3k
2.5Vpp
270p
5.65Vpp
-Vop
Figure 27. External 3rd order LPF Circuit Example for DSD
Frequency
Gain
20kHz
-0.05dB
50kHz
-0.51dB
100kHz
-16.8dB
DC gain = 1.07dB
Table 19. 3rd order LPF (Figure 27) Response
3.9k
AOUT-
4.7k
R1
2.5Vpp
470p
+Vop
3900p
3.9k
AOUT+
2.5Vpp
Analog
Out
R1
4.7k
470p
6.05Vpp
-Vop
When R1=180Ω
fc=90.1kHz, Q=0.735, g=-0.04dB at 40kHz
When R1=150Ω
fc=99.0kHz, Q=0.680, g=-0.23dB at 40kHz
Figure 28. External 2nd order LPF Circuit Example for PCM
MS0203-J-02
2009/05
- 33 -
[AK4358]
48pin LQFP(Unit:mm)
1.70Max
9.0 ± 0.2
0.13 ± 0.13
7.0
36
25
24
48
13
7.0
37
1
9.0 ± 0.2
1.40 ± 0.05
12
0.16 ± 0.07
0.22 ± 0.08
0.5
0.10 M
0° ∼ 10°
0.5 ± 0.2
0.10
■
:
:
:
(
)
MS0203-J-02
2009/05
- 34 -
[AK4358]
AKM
AK4358VQ
XXXXXXX
1
1) Asahi Kasei Logo
2) Marking Code: AK4358VQ
3) Date Code: XXXXXXX(7 digits)
4) Pin #1 indication
Date (YY/MM/DD)
02/02/10
06/02/23
Revision
00
01
Reason
Page
Contents
8
TDM256 mode (TDM0= “H”, TDM1= “L”)
tLRH (min): 1/256fs → 3/256fs
tLRL (min): 1/256fs → 3/256fs
TDM128 mode (TDM0= “H”, TDM1= “H”)
tLRH (min): 1/256fs → 3/256fs
tLRL (min): 1/256fs → 3/256fs
15
17
18
09/05/25
02
22
MS0203-J-02
1) PCM
LRCK “H”
LRCK “H”
Figure 5,6,7
“H”
“L”
Figure 8,9,10
“H”
“L”
■
“
→“
“L”
“L”
1/256fs(min)
3/256fs(min)
→
3/256fs(min)
3/256fs(min)
(PW1-3)”
(PW1-4)”
2009/05
- 35 -
[AK4358]
•
•
•
•
•
•
MS0203-J-02
2009/05
- 36 -