データシート

[AK4648]
AK4648
Stereo CODEC with MIC/HP/SPK-AMP
AK4648
AK4648
CODEC
PLL
PMP(
)
CSP
1.
2.
•4
•
(
or
)
•
•
(+32dB/+26dB/+20dB or 0dB)
• Digital ALC (Automatic Level Control)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
• ADC
: S/(N+D): 83dB, DR, S/N: 86dB (MIC-Amp=+20dB)
S/(N+D): 88dB, DR, S/N: 95dB (MIC-Amp=0dB)
•
•
• Programmable EQ
•
(tc=50/15μs, fs=32kHz, 44.1kHz, 48kHz)
•
•
(+12dB ∼ −115.0dB, 0.5dB Step, Mute)
• Digital ALC (Automatic Level Control)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
•
• Programmable EQ
• 5-Band Equalizer
•
: S/(N+D): 88dB, S/N: 92dB
•
- Single-ended / Pseudo Cap-less
: + 3dB ~ - 33dB, 3dB Step
- HP-AMP
: S/(N+D): [email protected], S/N: 90dB
: 40mW @16Ω (HVDD=3.6V)
62.5mW@16Ω (HVDD=4.5V)
ON/OFF
•
- SPK-AMP
: S/(N+D): 60dB@240mW, S/N: 90dB
- BTL
: 820mW @ 8Ω, HVDD=3.6V, High Power Mono SPK Mode
1.6W @ 8Ω, HVDD=5.0V, High Power Mono SPK Mode
640mW @ 8Ω, HVDD=3.6V, Stereo SPK & Mono SPK Mode
1.0W @ 8Ω, HVDD=4.5V, Stereo SPK Mode
1.3W @ 8Ω, HVDD=5V, Mono SPK Mode
ON/OFF
•
:4
3.
MS0625-J-01
2007/06
-1-
[AK4648]
4.
:
(1) PLL
•
(2)
5.
6.
7.
8.
9.
10.
11.
12.
13.
: 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz,
26MHz, 27MHz (MCKI pin)
1fs (LRCK pin)
32fs or 64fs (BICK pin)
•
: 256fs, 512fs or 1024fs (MCKI pin)
: 32fs/64fs/128fs/256fs
:
• PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• EXT Master/Slave Mode:
7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs)
(Ver 1.0, 400kHz Fast-Mode)
μP
: I2C
: MSB First, 2’s complement
• ADC : 16bit
, I2S, DSP Mode
• DAC : 16bit
, 16bit
, 16-24bit I2S, DSP Mode
Ta = −30 ∼ 85°C
:
• AVDD, DVDD: 2.6 ∼ 3.6V (typ. 3.3V)
• HVDD: 2.6 ∼ 5.0V (typ. 3.6V)
• TVDD (Digital I/O): 1.6 ∼ 3.6V (typ. 3.3V)
: CSP (3.7mm x 3.8mm, 0.5mm pitch)
AK4643/4/5
MS0625-J-01
2007/06
-2-
[AK4648]
■
AVDD VSS1
VCOM
DVDD
VSS3
TVDD
PMMP
MPWR
MIC Power
Supply
PMADL
or PMMICL
LIN1
Internal
MIC
CAD0
Control
Register
External
MIC
Wind-Noise Stereo
HPF Reduction Separation
A/D
MIC-Amp
LIN2
SDA
PDN
PMADL or PMADR
RIN1
SCL
ALC
PMADR
or PMMICR
BICK
RIN2
LRCK
SDTO
PMAINR2
LIN3/MIN
Line In
RIN3/VCOC
Line In
RIN4
Audio
I/F
PMAINL2
SDTI
LIN4
PMAINR3
PMAINR4
PMAINL3
PMAINL4
PMMIN
PMLO
PMDAC
LOUT
Stereo Line Out
or
Mono Diff Out
D/A
Stereo
DATT 5-Band
ALC
Separation
SMUTE EQ
HPF
ROUT
MCKO
PMPLL
PMHPL
PLL
VCOC
HPL
Headphone
MCKI
PMHPR
HPR
MUTET
PMHPC
Common Output
for HP-Amp
Common
HVCM
SPLP
Speaker
SPLN
PMSPL
SPRP
Speaker
SPRN
PMSPR
HVDD VSS2
(VCOC pin RIN3 pin
Figure 1.
MS0625-J-01
)
2007/06
-3-
[AK4648]
■ AK4643/45
1. Function
Function
Digital I/O of μP I/F
Analog Mixing for Playback
Input Selector for Recording
HP-Amp Hi-Z Setting for wired OR
PLL
Speaker-Amp
Headphone-Amp
Receiver-Amp
Bass Boost
5-band EQ
up I/F
Package
AK4643
2.6 to 3.6V
3 Stereo
3 Stereo
No
11.2896/12/12.288/
13.5/24/27MHz
Yes (Mono)
Yes
(Po=62mW @ 3.3V)
AK4645
1.6 to 3.6V
4 Stereo
4 Stereo
Yes
11.2896/12/12.288/13/
13.5/19.2/24/26/27MHz
No
←
Yes
Yes
No
3-wire/I2C
32QFN (5mm x 5mm)
No
←
←
←
←
MS0625-J-01
AK4648
←
←
←
←
←
Yes (Stereo)
Yes
(Po=40mW @ 3.6V)
Support Pseudo cap-less
←
No
Yes
I2C
CSP (3.7x 3.8mm)
2007/06
-4-
[AK4648]
2.
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
(AK4643/5
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Lch Input Volume Control
Lch Digital Volume Control
ALC Mode Control 3
Rch Input Volume Control
Rch Digital Volume Control
Mode Control 3
Mode Control 4
Power Management 3
Digital Filter Select
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
Power Management 4
Mode Control 5
Lineout Mixing Select
HP Mixing Select
SPK Mixing Select
EQ Control 250Hz/100Hz
EQ Control 3.5kHz/1kHz
EQ Control 10kHz
)
D7
PMSPR
HPZ
SPPSN
LOVL
PLL3
PS1
DVTM
0
REF7
IVL7
DVL7
RGAIN1
IVR7
DVR7
0
HPG3
INR1
GN1
F3A7
F3AS
F3B7
0
EQA7
EQA15
EQB7
0
EQC7
EQC15
F1A7
F1AS
F1B7
0
D6
PLL1
FS3
ZTM1
ALC
REF5
IVL5
DVL5
0
IVR5
DVR5
SMUTE
HPG1
0
0
F3A5
F3A13
F3B5
F3B13
EQA5
EQA13
EQB5
EQB13
EQC5
EQC13
F1A5
F1A13
F1B5
F1B13
D4
PMSPL
PMHPR
DACL
SPKG1
PLL0
MSBS
ZTM0
ZELMN
REF4
IVL4
DVL4
0
IVR4
DVR4
DVOLC
HPG0
MDIF2
FIL1
F3A4
F3A12
F3B4
F3B12
EQA4
EQA12
EQB4
EQB12
EQC4
EQC12
F1A4
F1A12
F1B4
F1B12
D3
PMLO
M/S
0
SPKG0
BCKO
BCKP
WTM1
LMAT1
REF3
IVL3
DVL3
0
IVR3
DVR3
0
IVOLC
MDIF1
EQ
F3A3
F3A11
F3B3
F3B11
EQA3
EQA11
EQB3
EQB11
EQC3
EQC11
F1A3
F1A11
F1B3
F1B11
D2
PMDAC
PMHPC
PMMP
MINL
0
FS2
WTM0
LMAT0
REF2
IVL2
DVL2
0
IVR2
DVR2
FBEQ
HPM
INR0
FIL3
F3A2
F3A10
F3B2
F3B10
EQA2
EQA10
EQB2
EQB10
EQC2
EQC10
F1A2
F1A10
F1B2
F1B10
D1
0
MCKO
0
SPKG2
DIF1
FS1
RFST1
RGAIN0
REF1
IVL1
DVL1
VBAT
IVR1
DVR1
DEM1
MINH
INL0
0
F3A1
F3A9
F3B1
F3B9
EQA1
EQA9
EQB1
EQB9
EQC1
EQC9
F1A1
F1A9
F1B1
F1B9
HPMTN
MINS
LOPS
PLL2
PS0
WTM2
0
REF6
IVL6
DVL6
LMTH1
IVR6
DVR6
LOOP
HPG2
INL1
GN0
F3A6
0
F3B6
0
EQA6
EQA14
EQB6
0
EQC6
EQC14
F1A6
0
F1B6
0
0
DIF0
FS0
RFST0
LMTH0
REF0
IVL0
DVL0
0
IVR0
DVR0
DEM0
DACH
PMADR
0
F3A0
F3A8
F3B0
F3B8
EQA0
EQA8
EQB0
EQB8
EQC0
EQC8
F1A0
F1A8
F1B0
F1B8
PMAINR4
PMAINL4
0
LOM
0
0
FBEQB3
FBEQD3
0
XXX
XXX
XXX
PMAINR3
PMAINL3
PMAINR2
PMAINL2
PMMICR
PMMICL
SPKMN
MICR3
MICL3
LOM3
RINR4
LINL4
HPM3
RINH4
LINH4
0
RINS4
LINS4
FBEQB2 FBEQB1 FBEQB0
FBEQD2 FBEQD1 FBEQD0
0
0
0
AK4645
AK4648
AK4643
AK4648
AK4643/5
AK4648
L4DIF
RINR3
RINH3
RINS3
FBEQA3
FBEQC3
FBEQE3
MIX
LINL3
LINH3
LINS3
FBEQA2
FBEQC2
FBEQE2
AIN3
RINR2
RINH2
RINS2
FBEQA1
FBEQC1
FBEQE1
LODIF
LINL2
LINH2
LINS2
FBEQA0
FBEQC0
FBEQE0
PMVCM
D5
PMMIN
PMHPL
DACS
MGAIN1
MS0625-J-01
D0
PMADL
PMPLL
MGAIN0
2007/06
-5-
[AK4648]
■
−30 ∼ +85°C
AK4648
AK4648EC
AKD4648
CSP (3.7mm x 3.8mm, 0.5mm pitch)
■
Top View
7
6
5
4
3
2
1
A
B
C
D
E
F
G
Top View
7
6
5
4
3
2
1
TEST
LIN4/IN4+
ROUT/LON
SPRP
HVDD
NC
A
VCOM
RIN2/IN2LOUT/LOP
SPRN
VSS2
SPLP
SPLN
B
AVDD
MIN/LIN3
LIN2/IN2+
RIN4/IN4HVCM
VSS2
C
LIN1/IN1VSS1
NC
NC
HPL
HPR
MUTET
D
MS0625-J-01
MPWR
VCOC/RIN3
NC
NC
DVDD
PDN
VSS3
E
CAD0
SCL
RIN1/IN1+
SDA
SDTO
TVDD
MCKI
F
NC
SDTI
LRCK
BICK
MCKO
TVDD
NC
G
2007/06
-6-
[AK4648]
No.
A1, D4,
D5, E4,
E5, G1,
G7
A2
A4
Pin Name
I/O
NC
-
HVDD
SPRP
ROUT
LON
LIN4
IN4+
O
O
O
I
I
A7
TEST
O
B1
B2
B3, C1
B4
SPLN
SPLP
VSS2
SPRN
LOUT
LOP
RIN2
IN2−
O
O
O
O
O
I
I
B7
VCOM
O
C2
C7
HVCM
RIN4
IN4−
LIN2
IN2+
MIN
LIN3
AVDD
O
I
I
I
I
I
I
-
D1
MUTET
O
D2
D3
D6
E1
HPR
HPL
VSS1
LIN1
IN1−
VSS3
O
O
I
I
-
E2
PDN
I
E3
DVDD
-
A5
A6
B5
B6
C4
C5
C6
D7
E6
E7
F1
F2, G2
F3
F4
F5
VCOC
O
RIN3
MPWR
MCKI
TVDD
SDTO
SDA
RIN1
IN1+
I
O
I
O
I/O
I
I
Function
No Connection Pin
(VSS1, VSS2 or VSS3)
, 2.6 ∼ 5.0V
Rch
Rch
(LODIF bit = “0”:
(LODIF bit = “1”:
4
(L4DIF bit = “0”:
4
(L4DIF bit = “1”:
Lch
)
)
)
)
Test Pin
Lch
Lch
2
Rch
Lch
(LODIF bit = “0”:
(LODIF bit = “1”:
2
(MDIF2 bit = “0”:
2
(MDIF2 bit = “1”:
, 0.45 x AVDD
DAC
Rch
ADC
Rch
)
)
)
)
4
4
Lch
Lch
VSS2 pin
Rch
Lch
1
Lch
(L4DIF bit = “0”:
(L4DIF bit = “1”:
)
2
(MDIF2 bit = “0”:
2
(MDIF2 bit = “1”:
)
(AIN3 bit = “0”: PLL
3
(AIN3 bit = “1”: PLL
)
, 2.6 ∼ 3.6V
1
1
(MDIF1 bit = “0”:
(MDIF1 bit = “1”:
)
)
)
)
)
3
“H”:
“L”:
, 2.6 ∼ 3.6V
PLL
VSS1
Rch
(AIN3 bit = “0”: PLL
3
)
, 1.6 ∼ 3.6V
I/O
Rch
(AIN3 bit = “1”: PLL
)
1
1
MS0625-J-01
(MDIF1 bit = “0”:
(MDIF1 bit = “1”:
)
)
2007/06
-7-
[AK4648]
No.
F6
F7
G3
G4
G5
G6
Pin Name
SCL
CAD0
MCKO
BICK
LRCK
SDTI
I/O
I
I
O
I/O
I/O
I
Function
Note 1.
(MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3, LIN4, RIN4)
Note 2.
(MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3, LIN4, RIN4 pins)
Note 3.
(SPLP, SPLN, SPRP, SPRN pins )
Pseudo Cap-less Mode
(LOUT, ROUT
HPL, HPR (Signle-ended Mode
DC
))
DC
■
Analog
Digital
MPWR, VCOC/RIN3, HPR, HPL, MUTET,
RIN4/IN4−, LIN4/IN4+, ROUT/LON, LOUT/LOP,
MIN/LIN3, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−,
RIN1/IN1+, SPRP, SPRN, HVCM, SPLP, SPLN,
TEST
MCKI, SDTI
MCKO, SDTO
MS0625-J-01
VSS3
2007/06
-8-
[AK4648]
(VSS1, VSS2, VSS3=0V; Note 4, Note 5)
Parameter
Power Supplies:
Analog
Digital
Digital I/O
Headphone-Amp
Input Current, Any Pin Except Supplies
Analog Input Voltage (Note 6)
Digital Input Voltage (Note 7)
Ambient Temperature (powered applied)
Storage Temperature
Maximum Power Disspation Ta = 85°C (Note 9)
(Note 8)
Ta = 70°C (Note 10)
Symbol
AVDD
DVDD
TVDD
HVDD
IIN
VINA
VIND
Ta
Tstg
Pd1
Pd2
Min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−30
−65
-
max
6.0
6.0
6.0
6.0
±10
AVDD+0.3
TVDD+0.3
85
150
1.2
1.46
Units
V
V
V
V
mA
V
V
°C
°C
W
W
Note 4.
Note 5. VSS1, VSS2, VSS3
Note 6. RIN4/IN4−, LIN4/IN4+, MIN/LIN3, RIN3, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ pins
Note 7. PDN, SCL, SDA, SDTI, LRCK, BICK, MCKI, CAD0 pins
SDA, SCL pins
(TVDD+0.3)V
Note 8.
300%
AK4648
Note 9. Stereo SPK Mode
Note 10.Stereo SPK Mode
Ta (max) = 70°C
HVDD = 2.6V ∼ 4.6V
:
MS0625-J-01
2007/06
-9-
[AK4648]
(VSS1, VSS2, VSS3=0V; Note 4)
Parameter
Power Supplies Analog
(Note 11) Digital
Digital I/O
HP/SPK-Amp
Difference
Note 4.
Note 11.AVDD, DVDD, TVDD, HVDD
= “L”
Symbol
AVDD
DVDD
TVDD
HVDD
AVDD−DVDD
min
2.6
2.6
1.6
2.6
−0.3
max
3.6
3.6
DVDD
5.0
+0.3
PDN pin
(
AK4648
2
“L”
1. TVDD=HVDD=ON
2. TVDD=ON
:
OFF
ON
PDN pin “L”
"H"
typ
3.3
3.3
3.3
3.6
0
Units
V
V
V
V
V
PDN pin
“H”
)
ON/OFF
AVDD=DVDD ON/OFF
AVDD=DVDD=HVDD ON/OFF
TVDD,AVDD,DVDD,HVDD
AK4648
150ns
PDN pin
“L”
:
MS0625-J-01
2007/06
- 10 -
[AK4648]
(Ta=25°C; AVDD, DVDD, TVDD=3.3V, HVDD=3.6V; VSS1=VSS2=VSS3=0V; fs=44.1kHz, BICK=64fs; Signal
Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified)
min
typ
max
Units
Parameter
MIC Amplifier: LIN1/RIN1/LIN2/RIN2/LIN4/RIN4 pins & LIN3/RIN3 pins (AIN3 bit = “1”);
PMAINL2=PMAINR2=PMAINL3=PMAINR3=PMAINL4=PMAINR4 bits = “0”;
MDIF1=MDIF2 bits = “0” (Single-ended inputs)
Input
MGAIN1-0 bits = “00”
40
60
80
kΩ
Resistance MGAIN1-0 bits = “01”, “10”or “11”
20
30
40
kΩ
MGAIN1-0 bits = “00”
0
dB
MGAIN1-0 bits = “01”
+20
dB
Gain
MGAIN1-0 bits = “10”
+26
dB
MGAIN1-0 bits = “11”
+32
dB
MIC Amplifier: IN1+/IN1−/IN2+/IN2− pins; MDIF1 = MDIF2 bits = “1” (Full-differential input)
Input Voltage (Note 12)
MGAIN1-0 bits = “00”
1.155
Vpp
MGAIN1-0 bits = “01”
0.228
Vpp
MGAIN1-0 bits = “10”
0.114
Vpp
MGAIN1-0 bits = “11”
0.057
Vpp
MIC Power Supply: MPWR pin
Output Voltage (Note 13)
2.22
2.47
2.72
V
Load Resistance
0.5
kΩ
Load Capacitance
30
pF
ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2/LIN4/RIN4 pins & LIN3/RIN3 pins (AIN3 bit = “1”)
→ ADC → IVOL, IVOL=0dB, ALC=OFF
Resolution
16
Bits
(Note 15)
0.168
0.198
0.228
Vpp
Input Voltage (Note 14)
1.68
1.98
2.28
Vpp
(Note 16)
(Note 15, LIN1/RIN1/LIN2/RIN2)
71
83
dBFS
S/(N+D)
(Note 15, LIN3/RIN3/LIN4/RIN4)
83
dBFS
(−1dBFS)
(Note 16, except for LIN3/RIN3)
88
dBFS
(Note 16, LIN3/RIN3)
72
dBFS
(Note 15)
76
86
dB
D-Range (−60dBFS, A-weighted)
95
dB
(Note 16)
(Note 15)
76
86
dB
S/N (A-weighted)
95
dB
(Note 16)
(Note 15)
75
90
dB
Interchannel Isolation
100
dB
(Note 16)
(Note 15)
0.1
0.8
dB
Interchannel Gain Mismatch
0.1
0.8
dB
(Note 16)
Note 12.
AC
IN1+, IN1-, IN2+, IN2- pin
AVDD
Vin =
|(IN+) − (IN−)| = 0.35 x AVDD (max) @ MGAIN1-0 bits = “00”, 0.069 x AVDD (max.) @ MGAIN1-0 bits =
“01”, 0.035 x AVDD (max.) @ MGAIN1-0 bits = “10”, 0.017 x AVDD (max.) @ MGAIN1-0 bits = “11”.
MGAIN1-0 bits = “00”
ADC
-6dB (@ IVL/R = 0dB)
ADC
Note 13.
AVDD
Vout = 0.75 x AVDD (typ.)
Note 14.
AVDD
Vin = 0.06 x AVDD (typ.) @ MGAIN1-0 bits = “01” (+20dB), Vin = 0.6 x
AVDD (typ.) @ MGAIN1-0 bits = “00” (0dB)
Note 15. MGAIN1-0 bits = “01” (+20dB)
Note 16. MGAIN1-0 bits = “00” (0dB)
MS0625-J-01
2007/06
- 11 -
[AK4648]
min
typ
max
Units
Parameter
DAC Characteristics:
Resolution
16
Bits
Stereo Line Output Characteristics: DAC → LOUT/ROUT pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit =
“0”, LODIF bit = “0”, RL=10kΩ (Single-ended); unless otherwise specified.
Output Voltage (Note 17)
LOVL bit = “0”
1.78
1.98
2.18
Vpp
LOVL bit = “1”
2.25
2.50
2.75
Vpp
78
88
dBFS
S/(N+D) (−3dBFS)
S/N (A-weighted)
82
92
dB
Interchannel Isolation
80
100
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Load Resistance
10
kΩ
Load Capacitance
30
pF
Mono Line Output Characteristics: DAC → LOP/LON pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit = “0”,
LODIF bit = “1”, RL=10kΩ for each pin (Full-differential)
Output Voltage (Note 18)
LOVL bit = “0”
3.52
3.96
4.36
Vpp
LOVL bit = “1”
5.00
Vpp
78
88
dBFS
S/(N+D) (−3dBFS)
S/N (A-weighted)
85
95
dB
Load Resistance (LOP/LON pins, respectively)
10
kΩ
Load Capacitance (LOP/LON pins, respectively)
30
pF
Note 17.
Note 18.
AVDD
AVDD
Vout = 0.6 x AVDD (typ.)@LOVL bit = “0”.
Vout = (LOP) − (LON) = 0.59 x AVDD (typ.)@LOVL bit = “0”, −6dBFS.
MS0625-J-01
2007/06
- 12 -
[AK4648]
min
typ
max
Units
Parameter
Headphone-Amp Characteristics in Single-ended mode:
DAC → HPL/HPR pins, ALC=OFF, IVOL=0dB, DVOL=0dB; VBAT bit = “0”; PMHPC bit = “0”; unless otherwise
specified.
Headphone Volume (HPG3-0 bits)
Volume Range
-33
+3
dB
Gain Step: +3dB to –33dB
1.5
3
4.5
dB
Output Voltage (Note 19)
1.58
1.98
2.38
Vpp
HPG = 0dB, 0dBFS, HVDD=3.6V, RL=22.8Ω
2.24
2.8
3.36
Vpp
HPG = +3dB, 0dBFS, HVDD=4.5V, RL=100Ω
HPG = +3dB, -2dBFS, HVDD=3.6V, RL=16Ω (Po=40mW)
0.8
Vrms
HPG = +3dB, 0dBFS, HVDD=4.5V, RL=16Ω (Po=62.5mW)
1.0
Vrms
S/(N+D)
60
70
dBFS
HPG = 0dB, −3dBFS, HVDD=3.6V, RL=22.8Ω
75
dBFS
HPG = +3dB, −3dBFS, HVDD=4.5V, RL=100Ω
HPG = +3dB, -2dBFS, HVDD=3.6V, RL=16Ω (Po=40mW)
60
dBFS
HPG = +3dB, 0dBFS, HVDD=4.5V, RL=16Ω (Po=62.5mW)
60
dBFS
(Note 20)
80
90
dB
S/N (A-weighted)
90
dB
(Note 21)
(Note 20)
65
75
dB
Interchannel Isolation
80
dB
(Note 21)
(Note 20)
0.1
0.8
dB
Interchannel Gain Mismatch
0.1
0.8
dB
(Note 21)
Load Resistance
16
Ω
30
pF
Figure 2 C1
Load Capacitance
300
pF
Figure 2 C2
Note 19.
AVDD
Vout = 0.6 x AVDD(typ.) @ HPG = 0dB, 0.848 x AVDD(typ.) @ HPG = +3dB
Note 20. HPG = 0dB, HVDD=3.6V, RL=22.8Ω.
Note 21. HPG = +3dB, HVDD=4.5V, RL=100Ω.
HP-Amp
HPL/HPR pin
Measurement Point
47μF
6.8Ω
C1
0.22μF
C2
16Ω
10Ω
Figure 2. HP-Amp Output Circuit in single-ended mode
MS0625-J-01
2007/06
- 13 -
[AK4648]
min
typ
max
Units
Parameter
Headphone-Amp Characteristics in Pseudo Cap-less mode:
DAC → HPL/HPR pins, ALC=OFF, IVOL=0dB, DVOL=0dB; VBAT bit = “0”; PMHPC bit = “1”; unless otherwise
specified.
Headphone Volume (HPG3-0 bits)
Volume Range
-33
+3
dB
Gain Step: +3dB to –33dB
1.5
3
4.5
dB
Output Voltage (Note 22)
1.58
1.98
2.38
Vpp
HPG = 0dB, 0dBFS, HVDD=3.6V, RL=22.8Ω
2.24
2.8
3.36
Vpp
HPG = +3dB, 0dBFS, HVDD=4.5V, RL=100Ω
HPG = +3dB, -2dBFS, HVDD=3.6V, RL=16Ω (Po=40mW)
0.8
Vrms
HPG = +3dB, 0dBFS, HVDD=4.5V, RL=16Ω (Po=62.5mW)
1.0
Vrms
S/(N+D)
30
50
dBFS
HPG = 0dB, −3dBFS, HVDD=3.6V, RL=22.8Ω
60
dBFS
HPG = +3dB, −3dBFS, HVDD=4.5V, RL=100Ω
HPG = +3dB, -2dBFS, HVDD=3.6V, RL=16Ω (Po=40mW)
45
dBFS
HPG = +3dB, 0dBFS, HVDD=4.5V, RL=16Ω (Po=62.5mW)
40
dBFS
(Note 23)
80
90
dB
S/N (A-weighted)
90
dB
(Note 24)
(Note 23)
40
50
dB
Interchannel Isolation
60
dB
(Note 24)
(Note 23)
0.1
0.8
dB
Interchannel Gain Mismatch
0.1
0.8
dB
(Note 24)
Load Resistance (Note 25)
16
Ω
30
pF
Figure 3 C1
Load Capacitance
300
pF
Figure 3 C2
Note 22.
AVDD
Vout = 0.6 x AVDD(typ.) @ HPG = 0dB, 0.848 x AVDD(typ.) @ HPG = +3dB
Note 23. HPG = 0dB, HVDD=3.6V, RL=22.8Ω
Note 24. HPG = +3dB, HVDD=4.5V, RL=100Ω
Note 25. HPL pin – HVCM pin or HPR pin – HVCM pin
HP-Amp
HPL/HPR pin
Measurement Point
6.8Ω
C1
0.22μF
C2
10Ω
16Ω
VCOM Amp for
HP-Amp
HVCM pin
C2
Note: HVCM pin
Figure 3. HP-Amp Output Circuit in Pseudo Cap-less Mode
MS0625-J-01
2007/06
- 14 -
[AK4648]
min
typ
max
Units
Parameter
Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, IVOL=0dB, DVOL=0dB, RL=8Ω, BTL,
HVDD=3.6V; unless otherwise specified.
Output Voltage (Note 26)
3.11
Vpp
SPKG2-0 bits = “000”, −0.5dBFS (Po=150mW)
3.13
3.92
4.71
Vpp
SPKG2-0 bits = “001”, −0.5dBFS (Po=240mW)
HVDD=3.6V, SPKG2-0 bits = “011”, Mono/Stereo SPK Mode; -1.5dBFS
(Po=0.6W)
HVDD=3.6V, SPKG2-0 bits = “011”, High Power Mono SPK Mode,
0dBFS (Po=0.8W)
HVDD=4.5V, SPKG2-0 bits = “011”, 0dBFS (Po=1W)
Line Input Æ SPLP/SPLN or SPRP/SPRN pins, HVDD=4.5V, SPKG2-0
bits = “011”, −2.3dBV Input (Po=1W)
S/(N+D)
SPKG2-0 bits = “000”, −0.5dBFS (Po=150mW)
SPKG2-0 bits = “001”, −0.5dBFS (Po=240mW)
HVDD=3.6V, SPKG2-0 bits = “011”, Mono/Stereo SPK Mode, -1.5dBFS
(Po=0.6W)
HVDD=3.6V, SPKG2-0 bits = “011”, High Power Mono SPK Mode,
0dBFS (Po=0.8W)
HVDD=4.5V, SPKG2-0 bits = “011”, 0dBFS (Po=1W)
Line Input Æ SPLP/SPLN or SPRP/SPRN pins, HVDD=4.5V, SPKG2-0
bits = “011”, Mono/Stereo SPK Mode ,−2.3dBV Input (Po=1W)
Line Input Æ SPLP/SPLN or SPRP/SPRN pins, HVDD=5V, SPKG2-0 bits
= “011”, Mono SPK Mode, −1.3dBV Input (Po=1.3W)
Line Input Æ SPLP/SPLN or SPRP/SPRN pins, HVDD=5V, SPKG2-0 bits
= “011”, High Power Mono SPK Mode, −0.3dBV Input (Po=1.6W)
S/N (A-weighted)
Interchannel GainMismatch (SPKMN bit = “1”)
Interchannel Isolation (SPKMN bit = “1”)
Load Resistance
Load Capacitance
-
2.27
-
Vrms
-
2.56
-
Vrms
-
2.83
-
Vrms
-
2.83
-
Vrms
20
60
60
-
dB
dB
-
20
-
dB
-
20
-
dB
-
20
-
dB
-
20
-
dB
-
20
-
dB
-
20
-
dB
80
8
-
90
0.5
90
-
30
dB
dB
dB
Ω
pF
Note 26.
AVDD
Vout = 0.94 x AVDD (typ.)@SPKG2-0 bits = “000”, 1.19 x AVDD(typ.)@SPKG2-0 bits = “001”, 2.05 x
AVDD(typ.)@SPKG2-0 bits = “010”, 2.58 x AVDD(typ.) @ SPKG2-0 bits = “011”, 0.6 x AVDD (typ.) @
SPKG2-0 bits = “100”, 0.3 x AVDD (typ.) @ SPKG2-0 bits = “101” at Full-differential output.
Note 27.
SPLP/SPLN pins or SPRP/SPRN pins
MS0625-J-01
2007/06
- 15 -
[AK4648]
min
Parameter
Mono Input: MIN pin (AIN3 bit = “0”; External Input Resistance=20kΩ)
Maximum Input Voltage (Note 28)
Gain (Note 29)
MIN Æ LOUT/ROUT
LOVL bit = “0”
−4.5
LOVL bit = “1”
MIN Æ HPL/HPR
HPG = 0dB
−24.5
MIN Æ SPLP/SPLN or SPRP/SPRN
ALC bit = “0”, SPKG2-0 bits = “000”
−0.07
ALC bit = “0”, SPKG2-0 bits = “001”
ALC bit = “0”, SPKG2-0 bits = “010”
ALC bit = “0”, SPKG2-0 bits = “011”
ALC bit = “0”, SPKG2-0 bits = “100”
ALC bit = “0”, SPKG2-0 bits = “101”
ALC bit = “1”, SPKG2-0 bits = “000”
ALC bit = “1”, SPKG2-0 bits = “001”
ALC bit = “1”, SPKG2-0 bits = “010”
ALC bit = “1”, SPKG2-0 bits = “011”
ALC bit = “1”, SPKG2-0 bits = “100”
ALC bit = “1”, SPKG2-0 bits = “101”
Note 28.
Note 29.
AVDD
(Rin)
typ
max
Units
1.98
-
Vpp
0
+2
−20
+4.5
−15.5
dB
dB
dB
+4.43
+6.43
+10.65
+12.65
0
-6
+6.43
+8.43
+12.65
+14.65
+2
-4
+8.93
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Vin = 0.6 x AVDD x Rin / 20kΩ (typ.).
MS0625-J-01
2007/06
- 16 -
[AK4648]
min
Parameter
Stereo Input: LIN2/RIN2/LIN4/RIN4 pins; LIN3/RIN3 pins (AIN3 bit = “1”)
Maximum Input Voltage (Note 30)
Gain
LIN/RIN Æ LOUT/ROUT
LOVL bit = “0”
−4.5
LOVL bit = “1”
LIN/RIN Æ HPL/HPR
HPG = 0dB
−4.5
LIN/RIN Æ SPLP/SPLN or SPRP/SPRN (Note 33)
ALC bit = “0”, SPKG2-0 bits = “000”
−0.07
ALC bit = “0”, SPKG2-0 bits = “001”
ALC bit = “0”, SPKG2-0 bits = “010”
ALC bit = “0”, SPKG2-0 bits = “011”
ALC bit = “0”, SPKG2-0 bits = “100”
ALC bit = “0”, SPKG2-0 bits = “101”
ALC bit = “1”, SPKG2-0 bits = “000”
ALC bit = “1”, SPKG2-0 bits = “001”
ALC bit = “1”, SPKG2-0 bits = “010”
ALC bit = “1”, SPKG2-0 bits = “011”
ALC bit = “1”, SPKG2-0 bits = “100”
ALC bit = “1”, SPKG2-0 bits = “101”
Full-differential Mono Input: IN4+/− pins (L4DIF bit = “1”)
Maximum Input Voltage (Note 31)
Gain
LOVL bit = “0”
IN4+/− Æ LOUT/ROUT
−10.5
(LODIF bit = “0”)
LOVL bit = “1”
LOVL bit = “0”
IN4+/− Æ LOP/LON
−4.5
(LODIF bit = “1”, Note 32)
LOVL bit = “1”
HPG = 0dB
IN4+/− Æ HPL/HPR
−10.5
IN4+/− Æ SPLP/SPLN or SPRP/SPRN
ALC bit = “0”, SPKG2-0 bits = “000”
-6.09
ALC bit = “0”, SPKG2-0 bits = “001”
ALC bit = “0”, SPKG2-0 bits = “010”
ALC bit = “0”, SPKG2-0 bits = “011”
ALC bit = “0”, SPKG2-0 bits = “100”
ALC bit = “0”, SPKG2-0 bits = “101”
ALC bit = “1”, SPKG2-0 bits = “000”
ALC bit = “1”, SPKG2-0 bits = “001”
ALC bit = “1”, SPKG2-0 bits = “010”
ALC bit = “1”, SPKG2-0 bits = “011”
ALC bit = “1”, SPKG2-0 bits = “100”
ALC bit = “1”, SPKG2-0 bits = “101”
-
typ
max
Units
1.98
-
Vpp
0
+2
0
+4.5
+4.5
dB
dB
dB
+4.43
+6.43
+10.65
+12.65
0
-6
+6.43
+8.43
+12.65
+14.65
+2
-4
+8.93
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
3.96
-
Vpp
−6
−4
0
+2
−6
−1.5
+4.5
−1.5
dB
dB
dB
dB
dB
-1.59
+0.41
+4.63
+6.63
-6
-12
+0.41
+2.41
+6.63
+8.63
-4
-10
+2.91
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Note 30.
Note 31.
AVDD
Vin = 0.6 x AVDD (typ.).
AVDD
Vin = (IN4+) − (IN4−) = 1.2 x AVDD (typ.).
IN4+, IN4− pins
Note 32. Vout = (LOP) − (LON) at LODIF bit = “1”.
Note 33. SPKMN bit = “0”
LIN/RIN
-6.02dB
MS0625-J-01
2007/06
- 17 -
[AK4648]
Parameter
Power Supplies:
Power Up (PDN pin = “H”)
All Circuit Power-up:
AVDD+DVDD+TVDD (Note 34)
HVDD: HP-Amp Normal Operation, No Output (Note 35)
Single-ended Mode (PMHPC bit = “0”)
Pseudo Cap-less Mode (PMHPC bit = “1”)
HVDD: SPK-Amp Normal Operation, No Output
Stereo & High Power Mono SPK Mode (Note 36)
Mono SPK Mode (Note 37)
Power Down (PDN pin = “L”) (Note 38)
AVDD+DVDD+TVDD+HVDD
min
typ
max
Units
-
16.7
25
mA
-
3.3
5.2
8
mA
mA
-
14.5
7.5
43
-
mA
mA
-
1
100
μA
Note 34. PLL Master Mode (MCKI=12.288MHz)
PMADL = PMADR = PMDAC = PMSPL=PMSPR=PMLO =
PMHPL = PMHPR = PMHPC = PMVCM = PMPLL = MCKO = PMMIN = PMMP = M/S bits = “1”
MPWR pin
0mA
AVDD=12mA(typ.), DVDD=3mA(typ.), TVDD=1.7mA(typ.).
EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”)
: AVDD=11mA(typ.), DVDD=2.5mA(typ.),
TVDD=0.03mA(typ.).
Note 35. PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = PMMIN = HPMTN bits
= “1”
Note 36. PMADL = PMADR = PMDAC = PMSPL = PMSPR = PMLO = PMVCM = PMPLL = PMMIN = SPPSN bits =
“1”
Note 37. PMADL = PMADR = PMDAC = PMVCM = PMPLL = PMMIN = SPPSN bits = “1”
PMSPL bit
PMSPR bit = “1”
Note 38.
TVDD
VSS3
MS0625-J-01
2007/06
- 18 -
[AK4648]
■
: Ta=25°C; AVDD=DVDD=TVDD=3.3V; HVDD=3.6V, VSS1=VSS2=VSS3=0V; fs=44.1kHz, External Slave
Mode, BICK=64fs
PMVCM
PMMIN
PMSPL
PMSPR
PMLO
PMDAC
PMADL
PMHPL
PMHPR
PMHPC
PMADR
PMMICL
PMMICR
PMAINL2
PMAINR2
PMAINL3
PMAINR3
AVDD [mA]
DVDD [mA]
TVDD [mA]
HVDD [mA]
Total Power [mW]
Power Management Bit
01H
10H
All Power-down
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DAC Æ Lineout
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
5.3
1.9
0.03
0.3
24.9
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
4.7
1.9
0.03
3.3
33.8
1
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
4.7
1.9
0.03
5.2
40.6
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
4.7
1.9
0.03
7.5
48.9
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
5.1
1.9
0.03
14.5
75.4
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
2.5
0
0
3.3
20.1
1
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
2.5
0
0
5.2
27.0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
2.5
0
0
7.5
35.3
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
2.9
0
0
14.5
61.8
MIN Æ Lineout
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
2.6
0
0
0.3
9.7
LIN2/RIN2 Æ ADC
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
6.4
1.6
0.03
0.3
27.6
LIN1 (Mono) Æ ADC
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
4.2
1.4
0.03
0.3
19.7
1
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
0
9.4
3.1
0.03
3.3
53.2
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
9.4
3.1
0.03
5.2
60.1
00H
Mode
DAC Æ HP
(Note 39)
DAC Æ HP
(Note 40)
DAC Æ SPK
(Note 41)
DAC Æ SPK
(Note 42)
LIN2/RIN2 Æ HP
(Note 39)
LIN2/RIN2 Æ HP
(Note 40)
LIN2/RIN2 Æ SPK
(Note 41)
LIN2/RIN2 Æ SPK
(Note 42)
LIN2/RIN2 Æ ADC
&DACÆHP(Note 39)
LIN2/RIN2 Æ ADC
&DACÆHP(Note 40)
20H
Note 39. Single-ended Mode
Note 40. Pseudo Cap-less Mode
Note 41. Mono SPK (In case of using Lch SPK-Amp. When Rch SPK-Amp is used, PMSPL bit is “0” and PMSPR bit is
“1”.)
Note 42. Stereo SPK Mode or High Power Mono SPK Mode
Table 1. Power Consumption for each operation mode (typ.)
MS0625-J-01
2007/06
- 19 -
[AK4648]
(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; TVDD=1.6 ∼ 3.6V; HVDD=2.6 ∼ 5.0V; fs = 44.1kHz; DEM=OFF;
FIL1=FIL3=EQ=FBEQ=OFF)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
Passband (Note 43)
PB
0
17.3
kHz
±0.16dB
19.4
kHz
−0.66dB
19.9
kHz
−1.1dB
22.1
kHz
−6.9dB
Stopband
SB
26.1
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
73
dB
Group Delay (Note 44)
GD
19
1/fs
Group Delay Distortion
0
ΔGD
μs
ADC Digital Filter (HPF): (Note 45)
Frequency Response (Note 43) −3.0dB
FR
0.9
Hz
2.7
Hz
−0.5dB
6.0
Hz
−0.1dB
DAC Digital Filter (LPF):
Passband (Note 43)
PB
0
19.6
kHz
±0.1dB
20.0
kHz
−0.7dB
22.05
kHz
−6.0dB
Stopband
SB
25.2
kHz
Passband Ripple
PR
dB
±0.01
Stopband Attenuation
SA
59
dB
Group Delay (Note 44)
GD
26
1/fs
DAC Digital Filter (LPF) + SCF:
FR
dB
Frequency Response: 0 ∼ 20.0kHz
±1.0
DAC Digital Filter (HPF): (Note 45)
Frequency Response (Note 43) −3.0dB
FR
0.9
Hz
2.7
Hz
−0.5dB
6.0
Hz
−0.1dB
Note 43.
Note 44.
fs (
PB=20.0kHz(@−0.7dB)
)
0.454 x fs
(DAC)
ADC
1kHz
16
PMADL=PMADR bits = “0”
DAC
Group Delay 25/fs(typ.)
Note 45. PMADL bit = “1” or PMADR bit = “1”
ADC HPF ON DAC HPF OFF
PMADL=PMADR bits = “0”, PMDAC bit = “1”
DAC HPF ON ADC HPF
16
DAC
MS0625-J-01
OFF
2007/06
- 20 -
[AK4648]
DC
(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; TVDD=1.6 ∼ 3.6V; HVDD=2.6 ∼ 5.0V)
Parameter
Symbol
Min
High-Level Input Voltage
2.2V≤TVDD≤3.6V
VIH
70%TVDD
1.6V≤TVDD<2.2V
VIH
80%TVDD
Low-Level Input Voltage
2.2V≤TVDD≤3.6V
VIL
1.6V≤TVDD<2.2V
VIL
High-Level Output Voltage
VOH
(Iout=−200μA)
TVDD−0.2
Low-Level Output Voltage
VOL
(Except SDA pin: Iout=200μA)
(SDA pin, 2.0V≤TVDD≤3.6V: Iout=3mA)
VOL
VOL
(SDA pin, 1.6V≤TVDD<2.0V: Iout=3mA)
Input Leakage Current
Iin
-
typ
-
max
30%TVDD
20%TVDD
-
Units
V
V
V
V
V
-
0.2
0.4
20%TVDD
±10
V
V
V
μA
(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; TVDD=1.6 ∼ 3.6V; HVDD=2.6 ∼ 5.0V; CL=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
MHz
Pulse Width Low
tCLKL
0.4/fCLK
ns
Pulse Width High
tCLKH
0.4/fCLK
ns
MCKO Output Timing
Frequency
fMCK
0.2352
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
%
256fs at fs=32kHz, 29.4kHz
dMCK
33
%
LRCK Output Timing
Frequency
fs
7.35
48
kHz
DSP Mode: Pulse Width High
tLRCKH
tBCK
ns
Except DSP Mode: Duty Cycle
Duty
50
%
BICK Output Timing
Period
BCKO bit = “0”
tBCK
1/(32fs)
ns
BCKO bit = “1”
tBCK
1/(64fs)
ns
Duty Cycle
dBCK
50
%
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
MHz
Pulse Width Low
tCLKL
0.4/fCLK
ns
Pulse Width High
tCLKH
0.4/fCLK
ns
MCKO Output Timing
Frequency
fMCK
0.2352
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
%
256fs at fs=32kHz, 29.4kHz
dMCK
33
%
LRCK Input Timing
Frequency
fs
7.35
48
kHz
DSP Mode: Pulse Width High
tLRCKH
tBCK−60
1/fs − tBCK
ns
Except DSP Mode: Duty Cycle
Duty
45
55
%
BICK Input Timing
Period
tBCK
1/(64fs)
1/(32fs)
ns
Pulse Width Low
tBCKL
0.4 x tBCK
ns
Pulse Width High
tBCKH
0.4 x tBCK
ns
MS0625-J-01
2007/06
- 21 -
[AK4648]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
PLL3-0 bits = “0011”
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Slave Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Input Timing
Frequency
256fs
fs
512fs
fs
1024fs
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Master Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Output Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Output Timing
Period
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
MS0625-J-01
min
typ
max
Units
7.35
tBCK−60
45
-
48
1/fs − tBCK
55
kHz
ns
%
1/(64fs)
130
130
-
1/(32fs)
-
ns
ns
ns
7.35
tBCK−60
45
-
48
1/fs − tBCK
55
kHz
ns
%
0.4 x tBCK
0.4 x tBCK
1/(32fs)
1/(64fs)
-
-
ns
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
7.35
7.35
tBCK−60
45
-
48
26
13
1/fs − tBCK
55
kHz
kHz
kHz
ns
%
312.5
130
130
-
-
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
-
tBCK
50
48
-
kHz
ns
%
-
1/(32fs)
1/(64fs)
50
-
ns
ns
%
2007/06
- 22 -
[AK4648]
Parameter
Symbol
Audio Interface Timing (DSP Mode)
Master Mode
tDBF
LRCK “↑” to BICK “↑” (Note 46)
tDBF
LRCK “↑” to BICK “↓” (Note 47)
tBSD
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
BICK “↓” to SDTO (BCKP bit = “1”)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
tLRB
LRCK “↑” to BICK “↑” (Note 46)
tLRB
LRCK “↑” to BICK “↓” (Note 47)
tBLR
BICK “↑” to LRCK “↑” (Note 46)
tBLR
BICK “↓” to LRCK “↑” (Note 47)
tBSD
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
BICK “↓” to SDTO (BCKP bit = “1”)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Audio Interface Timing (Right/Left justified & I2S)
Master Mode
tMBLR
BICK “↓” to LRCK Edge (Note 48)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
tLRB
LRCK Edge to BICK “↑” (Note 48)
tBLR
BICK “↑” to LRCK Edge (Note 48)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Note 46. MSBS, BCKP bits = “00” or “11”.
Note 47. MSBS, BCKP bits = “01” or “10”.
Note 48.
LRCK
BICK
min
typ
max
Units
0.5 x tBCK − 40
0.5 x tBCK − 40
−70
−70
50
50
0.5 x tBCK
0.5 x tBCK
-
0.5 x tBCK + 40
0.5 x tBCK + 40
70
70
-
ns
ns
ns
ns
ns
ns
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
50
50
-
80
80
-
ns
ns
ns
ns
ns
ns
ns
ns
−40
−70
-
40
70
ns
ns
−70
50
50
-
70
-
ns
ns
ns
50
50
-
-
80
ns
ns
ns
50
50
-
80
-
ns
ns
ns
“↑”
MS0625-J-01
2007/06
- 23 -
[AK4648]
Parameter
Control Interface Timing (I2C Bus):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 50)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width (Note 51)
PMADL or PMADR “↑” to SDTO valid (Note 52)
Note 49. I2C Philips Semiconductors
Note 50.
300ns (SCL
)
Note 51. AK4648 PDN pin = “L”
Note 52. PMADL bit
PMADR bit
Symbol
min
typ
max
Units
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
tSP
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
tPD
tPDV
150
-
1059
-
ns
1/fs
LRCK
MS0625-J-01
“↑”
2007/06
- 24 -
[AK4648]
■
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
50%TVDD
LRCK
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
50%TVDD
BICK
tBCKH
tBCKL
dBCK = tBCKH / tBCK x 100
tBCKL / tBCK x 100
1/fMCK
50%TVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Note 53. MCKO is not available at EXT Master mode.
Figure 4. Clock Timing (PLL/EXT Master mode)
tLRCKH
LRCK
50%TVDD
tDBF
BICK
(BCKP = "0")
50%TVDD
BICK
(BCKP = "1")
50%TVDD
tBSD
SDTO
MSB
tSDS
50%TVDD
tSDH
VIH
SDTI
VIL
Figure 5. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS bit = “0”)
MS0625-J-01
2007/06
- 25 -
[AK4648]
tLRCKH
LRCK
50%TVDD
tDBF
BICK
(BCKP = "1")
50%TVDD
BICK
(BCKP = "0")
50%TVDD
tBSD
SDTO
50%TVDD
MSB
tSDS
tSDH
VIH
SDTI
VIL
Figure 6. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS bit = “1”)
50%TVDD
LRCK
tMBLR
BICK
50%TVDD
tLRD
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 7. Audio Interface Timing (PLL/EXT Master mode, Except DSP mode)
MS0625-J-01
2007/06
- 26 -
[AK4648]
1/fs
VIH
LRCK
VIL
tLRCKH
tBLR
tBCK
VIH
BICK
(BCKP = "0")
VIL
tBCKH
tBCKL
VIH
BICK
(BCKP = "1")
VIL
Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS bit = “0”)
1/fs
VIH
LRCK
VIL
tLRCKH
tBLR
tBCK
VIH
BICK
(BCKP = "1")
VIL
tBCKH
tBCKL
VIH
BICK
(BCKP = "0")
VIL
Figure 9. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS bit = “1”)
MS0625-J-01
2007/06
- 27 -
[AK4648]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
VIH
BICK
VIL
tBCKH
tBCKL
fMCK
50%TVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 10. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin, Except DSP mode)
tLRCKH
VIH
LRCK
VIL
tLRB
VIH
BICK
VIL
(BCKP = "0")
VIH
BICK
(BCKP = "1")
VIL
tBSD
SDTO
MSB
tSDS
50%TVDD
tSDH
VIH
SDTI
MSB
VIL
Figure 11. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS bit = “0”)
MS0625-J-01
2007/06
- 28 -
[AK4648]
tLRCKH
VIH
LRCK
VIL
tLRB
VIH
BICK
VIL
(BCKP = "1")
VIH
BICK
(BCKP = "0")
VIL
tBSD
SDTO
50%TVDD
MSB
tSDS
tSDH
VIH
SDTI
MSB
VIL
Figure 12. Audio Interface Timing (PLL Slave mode, DSP mode, MSBS bit = “1”)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 13. Clock Timing (EXT Slave mode)
MS0625-J-01
2007/06
- 29 -
[AK4648]
VIH
LRCK
VIL
tLRB
tBLR
VIH
BICK
VIL
tBSD
tLRD
SDTO
50%TVDD
MSB
tSDH
tSDS
VIH
SDTI
VIL
Figure 14. Audio Interface Timing (PLL/EXT Slave mode, Except DSP mode)
VIH
SDA
VIL
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
2
Figure 15. I C
PMADL bit
or
PMADR bit
tPDV
SDTO
50%TVDD
Figure 16. Power Down & Reset Timing 1
tPD
PDN
VIL
Figure 17. Power Down & Reset Timing 2
MS0625-J-01
2007/06
- 30 -
[AK4648]
■
I/F
5
(Table 2 and Table 3.)
Mode
PLL Master Mode (Note 54)
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: LRCK or BICK pin)
EXT Slave Mode
EXT Master Mode
Note 54. PLL Master Mode
PMPLL bit
1
M/S bit
1
PLL3-0 bits
Table 5
Figure
Figure 18
1
0
Table 5
Figure 19
1
0
Table 5
0
0
x
0
1
x
M/S bit = “1”, PMPLL bit = “0”, MCKO bit = “1”
Figure 20
Figure 21
Figure 22
Figure 23
MCKO pin
Table 2. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
0
PLL Master Mode
1
0
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
1
MCKO pin
“L”
PS1-0 bits
MCKI pin
PLL3-0 bits
“L”
PS1-0 bits
PLL3-0 bits
GND
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
0
“L”
EXT Slave Mode
0
“L”
EXT Master Mode
0
“L”
FS1-0 bits
FS1-0 bits
BICK pin
Output
(BCKO bit
)
LRCK pin
Input
(≥ 32fs)
Input
(1fs)
Input
(PLL3-0
bits
)
Input
(≥ 32fs)
Output
(BCKO bit
)
Output
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
Table 3. Clock pins state in Clock Mode
■
AK4648
M/S bit
M/S bit
(PDN pin = “L”)
“1”
“0”
“1”
M/S bit “1”
AK4648 LRCK, BICK pin
AK4648
LRCK, BICK pin
100kΩ
M/S bit
Mode
0
Slave Mode
(default)
1
Master Mode
Table 4. Select Master/Slave Mode
MS0625-J-01
2007/06
- 31 -
[AK4648]
■ PLL
(AIN3 bit = “0”, PMPLL bit = “1”)
PMPLL bit = “1”
PLL
PLL FS3-0 bits, PLL3-0 bits
PMPLL bit
“0” Æ “1”
Table 5
AIN3 bit = “1”
PLL
1) PLL Mode
PLL
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
0
1
0
0
0
0
0
0
0
1
LRCK pin
N/A
1fs
-
2
0
0
1
0
BICK pin
32fs
3
0
0
1
1
BICK pin
64fs
4
5
6
7
8
12
13
14
15
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
0
0
1
0
1
Others
Others
VCOC pin
R,C
R[Ω] C[F]
6.8k
220n
10k
4.7n
10k
10n
10k
4.7n
10k
10n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
10n
10k
10n
10k
220n
10k
220n
MCKI pin
11.2896MHz
MCKI pin
12.288MHz
MCKI pin
12MHz
MCKI pin
24MHz
MCKI pin
19.2MHz
MCKI pin
13.5MHz
MCKI pin
27MHz
MCKI pin
13MHz
MCKI pin
26MHz
N/A
Table 5. Setting of PLL Mode (*fs: Sampling Frequency)
PLL
(max.)
160ms
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
40ms
40ms
40ms
60ms
60ms
(default)
2) PLL Mode
MCKI
Table 6
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
0
0
8kHz
(default)
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
4
0
1
0
0
7.35kHz
5
0
1
0
1
11.025kHz
6
0
1
1
0
14.7kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
14
1
1
1
0
29.4kHz
15
1
1
1
1
44.1kHz
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = MCKI pin)
MS0625-J-01
2007/06
- 32 -
[AK4648]
LRCK or BICK
FS3, FS1-0 bits
(Table 7) FS2b bit
“Don’t care”
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency Range
0
x
0
0
0
(default)
7.35kHz ≤ fs ≤ 8kHz
0
x
1
1
0
8kHz < fs ≤ 12kHz
0
x
0
2
1
12kHz < fs ≤ 16kHz
0
x
1
3
1
16kHz < fs ≤ 24kHz
1
x
0
6
1
24kHz < fs ≤ 32kHz
1
x
1
7
1
32kHz < fs ≤ 48kHz
Others
Others
N/A
(x: Don’t care)
Table 7. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin)
■ PLL
1) PLL Master Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “1”)
bit = “1”
MCKO pin
PLL
PMPLL bit = “0” Æ “1”
MCKO pin
“L”
(Table 8)
BICK
LRCK
PLL
BICK
“L”
LRCK “L”
MCKO bit = “0”
1
MCKO
LRCK, BICK
1fs
PMPLL bit = “0”
LRCK
BICK,
“L”
MCKO pin
BICK pin
LRCK pin
MCKO bit = “0”
MCKO bit = “1”
“L” Output
“L” Output
“L” Output
PMPLL bit “0” Æ “1”
“L” Output
PLL Unlock (
)
“L” Output
1fs Output
Table 10
Table 11
PLL Lock
Table 8. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PLL State
2) PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”)
DAC
PMPLL bit = “0” Æ “1”
PLL
PLL
DACL, DACH bits “0”
PLL
MCKO pin
ADC
DAC
MCKO
Table 10
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
PMPLL bit “0” Æ “1”
“L” Output
PLL Unlock (
)
“L” Output
Output
PLL Lock
Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PLL State
MS0625-J-01
2007/06
- 33 -
[AK4648]
■ PLL Master Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “1”)
11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz
PLL
MCKO, BICK, LRCK
(MCKO)
PS1-0 bits (Table 10)
MCKO bit ON/OFF
BICK
BCKO bit
32fs or 64fs
(Table 11)
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
DSP or μP
AK4648
MCKI
256fs/128fs/64fs/32fs
MCKO
32fs, 64fs
BICK
1fs
LRCK
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 18. PLL Master Mode
Mode
PS1 bit
0
0
1
0
2
1
3
1
Table 10. MCKO
PS0 bit
0
1
0
1
(PLL
MCKO pin
256fs
(default)
128fs
64fs
32fs
, MCKO bit = “1”)
BCKO bit
BICK
0
32fs
(default)
1
64fs
Table 11. BICK Output Frequency at Master Mode
MS0625-J-01
2007/06
- 34 -
[AK4648]
■ PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”)
MCKI, BICK or LRCK pin
PLL
PLL
AK4648
(Table 5)
PLL3-0 bits
a) PLL
: MCKI pin
MCKO
BICK, LRCK
MCKO LRCK
(MCKO pin) PS1-0 bits (Table 10)
FS3-0 bits
bit ON/OFF
MCKO
(Table 6)
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
AK4648
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 19. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
MS0625-J-01
2007/06
- 35 -
[AK4648]
b) PLL
FS3-0 bits
Table 7.)
: BICK or LRCK pin
7.35kHz ∼ 48kHz
((x: Don’t care)
AK4648
DSP or μP
MCKO
MCKI
BICK
LRCK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 20. PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
AK4648
DSP or μP
MCKO
MCKI
BICK
LRCK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 21. PLL Slave Mode 2 (PLL Reference Clock: LRCK pin)
ADC or DAC
LRCK)
(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”)
(MCKI, BICK,
(PMADL=PMADR=PMDAC bits = “0”)
MS0625-J-01
2007/06
- 36 -
[AK4648]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PMPLL bit “0”
ADC, DAC
(EXT Mode)
MCKI pin
PLL
CODEC
I/F
MCKI (256fs, 512fs or 1024fs), BICK (≥32fs), LRCK(fs)
MCKI
MCKI
FS1-0 bit
LRCK
(Table 12)
MCKI Input
Sampling Frequency
Frequency
Range
x
0
0
0
256fs
(default)
7.35kHz ∼ 48kHz
x
1
0
1
1024fs
7.35kHz ∼ 13kHz
x
2
1
0
256fs
7.35kHz ∼ 48kHz
x
3
1
1
512fs
7.35kHz ∼ 26kHz
Table 12. EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
MCKI
(x: Don’t care)
Mode
FS3-2 bits
FS1 bit
FS0 bit
DAC
S/N
S/N
Table 13 DAC
MCKI
LOUT/ROUT pins
S/N
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
93dB
1024fs
93dB
Table 13. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI
ADC or DAC
LRCK)
(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”)
(MCKI, BICK,
(PMADL=PMADR=PMDAC bits = “0”)
AK4648
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BICK
LRCK
MCLK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 22. EXT Slave Mode
MS0625-J-01
2007/06
- 37 -
[AK4648]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
PMPLL bit = “0”
M/S bit = “1”
MCKI pin
PLL
(256fs, 512fs or 1024fs)
MCKI
(EXT Master Mode)
ADC,DAC
MCKI
FS1-0 bits
(Table 14)
MCKI Input
Sampling Frequency
Frequency
Range
x
0
0
0
256fs
(default)
7.35kHz ∼ 48kHz
x
1
0
1
1024fs
7.35kHz ∼ 13kHz
x
2
1
0
256fs
7.35kHz ∼ 48kHz
x
3
1
1
512fs
7.35kHz ∼ 26kHz
Table 14. EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
MCKI
(x: Don’t care)
Mode
FS3-2 bits
FS1 bit
FS0 bit
DAC
S/N
S/N
Table 15 DAC
MCKI
LOUT/ROUT pins
S/N
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
93dB
1024fs
93dB
Table 15. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI
ADC
DAC
MCKI
(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”)
MCKI
MCKI
(PMADL=PMADR=PMDAC bits =
“0”)
AK4648
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BICK
LRCK
MCLK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 23. EXT Master Mode
BCKO bit
BICK
0
32fs
(default)
1
64fs
Table 16. BICK Output Frequency at Master Mode
MS0625-J-01
2007/06
- 38 -
[AK4648]
■
PDN pin
“L”
AK4648
PMADR bit “0” → “1”
1059/fs=24ms@fs=44.1kHz
“0”
ADC
PMDAC bit = “1”
ADC
PMDAC bit = “0”
PMADL bit
2’s
PMADL=PMADR bits = “0” PMDAC bit = “0” Æ “1”
1059/fs=24ms@fs=44.1kHz
“0”
DAC
DAC
ADC
ADC
DAC
DAC
DAC
PMADL bit
2’s
(25/fs=0.6ms@fs=44.1kHz)
PMADR bit “1”
■
4
(Table 17)
LRCK
Mode
0
1
2
3
DIF1 bit
0
0
1
1
Mode 1, 2, 3
SDTO
Mode 0 (DSP
(Table 18)
)
DIF1
DIF0
0
SDTO (ADC)
DSP Mode
SDTI (DAC)
DSP Mode
I2S
I2S
Table 17. Audio Interface Format
“↓”
SDTI
BICK
BCKP, MSBS bits
MSBS
BCKP
0
0
SDTO
“↑”
0
1
SDTO
“↓”
1
0
1
1
0
ADC
MSB
16bit
“−1” 8bit
“–256”
MSB
MSB
BICK
≥ 32fs
≥ 32fs
≥ 32fs
≥ 32fs
Figure
Table 18
Figure 28
Figure 29
Figure 30
(default)
“↑”
I/F
Audio Interface Format
LRCK “↑”
1
BICK
BICK “↓” SDTI MSB
Figure 24
LRCK “↑”
1
BICK
BICK “↑” SDTI MSB
Figure 25
SDTO MSB
LRCK “↑”
1
“↓”
BICK “↑”
“↓” SDTI MSB
SDTO MSB
LRCK “↑”
1
“↑”
BICK “↓”
“↑” SDTI MSB
Table 18. Audio Interface Format in Mode 0
8bit
“−1”
2’s
BICK
DIF0 bit
0
1
0
1
BICK
DIF1-0 bits
8bit
8bit
Figure
BICK
BICK
Figure 26
BICK
BICK
Figure 27
16bit
“−1” DAC
(default)
16bit
16bit
16bit
(128)
MS0625-J-01
2007/06
- 39 -
[AK4648]
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
46
34
47
48
49
50
27
26
62
63
30
31
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
2
1
0
15 14
1
0
2
1
0
Rch
Lch
SDTI(i)
2
15 14
15 14
1/fs
15:MSB, 0:LSB
Figure 24. Mode 0 Timing (BCKP bit = “0”, MSBS bit = “0”)
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
29
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
34
46
47
48
49
50
62
63
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
2
1
0
2
1
0
2
1
0
Rch
Lch
SDTI(i)
15 14
15 14
15 14
1/fs
15:MSB, 0:LSB
Figure 25. Mode 0 Timing (BCKP bit = “1”, MSBS bit = “0”)
MS0625-J-01
2007/06
- 40 -
[AK4648]
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
46
34
48
47
49
50
27
26
62
63
30
31
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
15 14
Lch
SDTI(i)
2
1
0
2
1
0
Rch
15 14
2
1
0
15 14
1/fs
15:MSB, 0:LSB
Figure 26. Mode 0 Timing (BCKP bit = “0”, MSBS bit = “1”)
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
29
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
34
46
47
48
49
50
62
63
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
Lch
SDTI(i)
15 14
2
1
0
2
1
0
Rch
15 14
2
1
0
15 14
1/fs
15:MSB, 0:LSB
Figure 27. Mode 0 Timing (BCKP bit = “1”, MSBS bit = “1”)
MS0625-J-01
2007/06
- 41 -
[AK4648]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
SDTI(i)
1 0
15 14 13
15 14 13
15 14
Don't Care
1 0
1 0
Don't Care
15
15 14
2 1 0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 28. Mode 1 Timing
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14 13
1 0
SDTI(i)
15 14 13
1 0
Don't Care
15 14 13
1 0
15 14 13
1 0
15
Don't Care
15
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 29. Mode 2 Timing
MS0625-J-01
2007/06
- 42 -
[AK4648]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
0 15 14
8 7 6 5 4 3 2 1 0 15 14
8 7 6 5 4 3 2 1 0
SDTI(i)
0 15 14
8 7 6 5 4 3 2 1 0 15 14
8 7 6 5 4 3 2 1 0
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14
2 1 0
SDTI(i)
15 14
2 1 0
Don't Care
15 14
2 1 0
15 14
2 1 0
Don't Care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 30. Mode 3 Timing
■
PMADL, PMADR, MIX bits
ADC
bit = “1”
EQ=FIL3 bits = “0”
(ALC bit = “0”)
PMADL bit
0
0
1
PMADR bit
0
1
0
1
1
Table 19.
■
MIX bit
x
x
x
0
1
MIX
ALC
(ALC bit = “1”)
ADC Lch data
ADC Rch data
All “0”
All “0”
Rch Input Signal
Rch Input Signal
Lch Input Signal
Lch Input Signal
Lch Input Signal
Rch Input Signal
(L+R)/2
(L+R)/2
(x: Don’t care)
(default)
HPF
AK4648 DC
44.1kHz)
ADC HPF ON DAC HPF
ON ADC HPF OFF
OFF
HPF
HPF
0.9Hz (@fs=
(fs)
PMADL bit = “1” or PMADR bit = “1”
PMADL=PMADR bits = “0”, PMDAC bit = “1”
DAC HPF
MS0625-J-01
2007/06
- 43 -
[AK4648]
■
AK4648
bits
LIN1/LIN2/LIN3/LIN4, RIN1/RIN2/RIN3/RIN4
MDIF2 bits = “1”
LIN1, RIN1, LIN2, RIN2 pins
(Figure 32)
MDIF1 bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Others
MDIF2 bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
INL1 bit
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
INL0 bit
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
INR1 bit
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
MDIF1, MDIF2 bits = “0”
IN1−, IN1+, IN2+, IN2− pins
Lch
LIN1
LIN1
LIN1
LIN1
LIN2
LIN2
LIN2
LIN2
LIN3
LIN3
LIN3
LIN3
LIN4
LIN4
LIN4
LIN4
LIN1
LIN3
LIN4
IN1+/−
IN1+/−
IN1+/−
IN1+/−
N/A
Table 20. MIC/Line In Path Select (N/A: Not available)
MS0625-J-01
INL1-0, INR1-0
MDIF1,
INR0 bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
Rch
RIN1
RIN2
RIN3
RIN4
RIN1
RIN2
RIN3
RIN4
RIN1
RIN2
RIN3
RIN4
RIN1
RIN2
RIN3
RIN4
IN2+/−
IN2+/−
IN2+/−
RIN2
RIN3
RIN4
IN2+/−
N/A
(default)
2007/06
- 44 -
[AK4648]
AK4648
INL1-0 bits
LIN1/IN1− pin
ADC Lch
RIN1/IN1+ pin
MDIF1 bit
MIC-Amp
INR1-0 bits
RIN2/IN2− pin
ADC Rch
LIN2/IN2+ pin
MDIF2 bit
AIN3 bit
LIN3
AIN3 bit
RIN3
MIC-Amp
MIN/LIN3 pin
PMMIN
PMAINR2 bit
PMAINL2 bit
PMAINR4 bit
PMAINL4 bit
MICR3 bit
RIN4/IN4− pin
PMAINR3 bit
VCOC
LIN4/IN4+ pin
PMAINL3 bit
MICL3 bit
VCOC/RIN3 pin
Lineout, HP-Amp, SPK-Amp
Figure 31.
AK4648
MPWR pin
1k
IN1− pin
MIC-Amp
IN1+ pin
A/D
SDTO pin
1k
Figure 32.
IN1+/− pins
MDIF1 bit
1
0
(MDIF1/2 bits = “1”)
LIN2/RIN2 pins
MDIF2 bit
0
0
2
INL1 bit
INL0 bit
INR1 bit
INR0 bit
0
0
0
1
0
1
0
1
Table 21. MIC/Line In Path Select Example
MS0625-J-01
Lch
IN1+/−
LIN2
Rch
RIN2
RIN2
2007/06
- 45 -
[AK4648]
■
MGAIN1-0 bit
MGAIN1-0 bits = “00”
typ. 60kΩ MGAIN1-0 bits = “01”, “10”, “11”
AK4648
(Table 22)
typ. 30kΩ
MGAIN1 bit
0
0
1
1
MGAIN0 bit
0
1
0
1
Table 22.
Input Gain
0dB
+20dB
+26dB
+32dB
(default)
■
PMMP bit = “1”
(typ.)
MPWR pin
min. 0.5kΩ
min. 2kΩ
2
(0.75 x AVDD)V
MPWR pin
(Figure 33)
PMMP bit
MPWR pin
0
Hi-Z
1
Output
Table 23.
(default)
MIC Power
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
MPWR pin
Microphone
LIN1 pin
Microphone
RIN1 pin
Microphone
LIN2 pin
Microphone
RIN2 pin
Figure 33. MIC Block Circuit
MS0625-J-01
2007/06
- 46 -
[AK4648]
■ Digital EQ/HPF/LPF
A/D
AK4648
ALC
ALC
(Figure 34) FIL1, FIL3, EQ
“ALC
”
1
IIR
Digital EQ/HPF/LPF
DAC
ADC
ADC DAC
Digital EQ/HPF/LPF
FIL3, EQ, FIL1, GN1-0 bits
“0”
PMADL bit, PMADR bit
00
PMDAC bit
0
1
0
01, 10 or 11
Digital EQ/HPF/LPF
LOOP bit
x
x
x
0
1
1
(default)
,
Note 55.
Table 24. Digital EQ/HPF/LPF
(x: Don’t care)
ATT FIL3
GN1-0 bits (Table 25) EQ
F1AS, F3AS bits
FIL1, FIL3
FIL3 OFF(MUTE)
“0”
HPF
F1AS, F3AS bits
EQ, FIL1 0dB
“1”
FIL3, EQ, FIL1 bits
LPF
“0”
(FIL3 MUTE)
MIX bit = “1”
FIL1
EQ=FIL3 bits = “0”
FIL1
F1A13-0
F1B13-0
F1AS
FIL3
F3A13-0
F3B13-0
F3AS
0dB ∼ -10dB
MUTE
(FIL3
EQ
)
EQA15-0
EQB13-0
EQC15-0
+12dB ∼ 0dB
Gain
ALC
GN1-0
+24/+12/0dB
Figure 34. Digital EQ/HPF/LPF
GN1
GN0
0
0
0
1
1
x
Table 25. Gain
Gain
0dB
(default)
+12dB
+24dB
(x: Don’t care)
MS0625-J-01
2007/06
- 47 -
[AK4648]
[
]
1) FIL1, FIL3 HPF
fs:
fc:
f:
K:
[dB] (FIL1
0dB
)
FIL1: F1AS bit = “0”, F1A[13:0] bits =A, F1B[13:0] bits =B
FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A = 10K/20 x
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
1 − z −1
H(z) = A
2 − 2cos (2πf/fs)
M(f) = A
1 + Bz −1
θ(f) = tan −1
1 + B2 + 2Bcos (2πf/fs)
(B+1)sin (2πf/fs)
1 - B + (B−1)cos (2πf/fs)
2) FIL1, FIL3 LPF
fs:
fc:
f:
K:
[dB] (FIL1
0dB
)
FIL1: F1AS bit = “1”, F1A[13:0] bits =A, F1B[13:0] bits =B
FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1
A = 10K/20 x
,
1 + 1 / tan (πfc/fs)
1 + z −1
H(z) = A
1 + Bz −1
B=
1 + 1 / tan (πfc/fs)
2 + 2cos (2πf/fs)
M(f) = A
1 + B2 + 2Bcos (2πf/fs)
MS0625-J-01
θ(f) = tan −1
(B−1)sin (2πf/fs)
1 + B + (B+1)cos (2πf/fs)
2007/06
- 48 -
[AK4648]
3) EQ
fs:
fc1:
fc2:
f:
K:
[dB] (
+12dB
)
EQA[15:0] bits =A, EQB[13:0] bits =B, EQC[15:0] bits =C
(MSB=EQA15, EQB13, EQC15; LSB=EQA0, EQB0, EQC0)
A = 10K/20 x
1 − 1 / tan (πfc1/fs)
1 + 1 / tan (πfc2/fs)
,
B=
1 + 1 / tan (πfc1/fs)
A + Cz −1
H(z) =
,
1 + 1 / tan (πfc1/fs)
A2 + C2 + 2ACcos (2πf/fs)
1 + B2 + 2Bcos (2πf/fs)
2
[
(2
) x 213
X=(
X
2
1 − 1 / tan (πfc2/fs)
1 + 1 / tan (πfc1/fs)
(AB−C)sin (2πf/fs)
θ(f) = tan −1
M(f) =
1 + Bz −1
C =10K/20 x
A + BC + (AB+C)cos (2πf/fs)
)
(2
]
)
MSB
]
[
1) FIL1
: fs=44.1kHz, fc=100Hz HPF
F1AS bit = “0”
F1A[13:0] bits = 01 1111 1100 0110
F1B[13:0] bits = 10 0000 0111 0100
2) EQ
: fs=44.1kHz, fc1=300Hz, fc2=3000Hz, Gain=+8dB
Gain[dB]
+8dB
fc1
fc2
Frequency
EQA[15:0] bits = 0000 1001 0110 1110
EQB[13:0] bits = 10 0001 0101 1001
EQC[15:0] bits = 1111 1001 1110 1111
MS0625-J-01
2007/06
- 49 -
[AK4648]
■ ALC
ALC
ALC bit = “1”
ALC
PMADL bit, PMADR bit
00
ALC
ALC
PMDAC bit
0
1
0
01, 10 or 11
1.
DAC
ALC
LOOP bit
x
x
x
0
1
Table 26. ALC
1
(default)
,
(x: Don’t care)
ALC
ALC
Lch, Rch
LMAT1-0 bits
)
(Table 27)
)
ALC
IVL, IVR
)
ALC
LMAT1-0 bits
IVL, IVR
1 step
ZELMN bit = “0”(
ZTM1-0 bits
ALC
IVL, IVR (L/R
(Table 28)
L/R
(Table 29)
ZELMN bit = “1”(
ALC bit
LMTH1
0
0
1
1
“0”
0
1
LMAT1
0
0
1
1
x
Table 28. ALC
ZTM1
ZTM0
0
0
1
1
0
1
0
1
: 1/fs)
ALC
LMTH0 ALC
0
ALC Output ≥ −2.5dBFS
1
ALC Output ≥ −4.1dBFS
0
ALC Output ≥ −6.0dBFS
1
ALC Output ≥ −8.5dBFS
Table 27. ALC
ZELMN
(
ALC
−2.5dBFS > ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
LMAT0 ALC
0
1 step
1
2 step
0
4 step
1
8 step
x
1step
ATT
128/fs
256/fs
512/fs
1024/fs
Table 29. ALC
8kHz
16ms
32ms
64ms
128ms
MS0625-J-01
(default)
ATT
0.375dB
(default)
0.750dB
1.500dB
3.000dB
0.375dB
(x: Don’t care)
16kHz
8ms
16ms
32ms
64ms
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
(default)
2007/06
- 50 -
[AK4648]
2.
ALC
WTM2-0
(Table 30)
(Table 27)
ALC
(Table 32)
ZTM1-0 bits
(Table 29)
RGAIN1-0 bits
(Table 31)
IVL, IVR (L/R
)
WTM2-0 bits
WTM2-0 bits
ZTM1-0 bits
ALC
IVL, IVR
30H
IVL, IVR
32H
IVL, IVR
bits)
RGAIN1-0 bits = “01”(2 steps)
0.75dB(0.375dB x 2)
ALC
ALC
ALC
ZTM1-0 bits
ALC
ALC
IVL, IVR
(REF7-0
ALC
(
) ≤ Output Signal < (
(
) > Output Signal
ALC
)
ALC
(
)
RFST1-0 bits
WTM2
WTM1
WTM0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RGAIN1
0
0
1
1
128/fs
256/fs
512/fs
1024/fs
2048/fs
4096/fs
8192/fs
16384/fs
Table 30. ALC
RGAIN0
0
1
0
1
Table 31. ALC
(Table 33)
ALC
8kHz
16ms
32ms
64ms
128ms
256ms
512ms
1024ms
2048ms
16kHz
8ms
16ms
32ms
64ms
128ms
256ms
512ms
1024ms
GAIN STEP
1 step
0.375dB
2 step
0.750dB
3 step
1.125dB
4 step
1.500dB
MS0625-J-01
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
46.4ms
92.9ms
185.8ms
371.5ms
(default)
(default)
2007/06
- 51 -
[AK4648]
REF7-0
GAIN(dB)
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
E2H
+30.375
E1H
+30.0
E0H
+29.625
:
:
03H
−53.25
02H
−53.625
01H
−54.0
00H
MUTE
Table 32. ALC
RFST1 bit
0
0
1
1
RFST0 bit
0
1
0
1
Step
0.375dB
4
8
16
N/A
(default)
(default)
Table 33.
MS0625-J-01
2007/06
- 52 -
[AK4648]
3.
ALC
Table 34
ALC
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same or
longer data as ZTM1-0 bits.
Maximum gain at recovery operation
WTM2-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
RFST1-0
ALC
Gain of IVOL
Limiter ATT step
Recovery GAIN step
Fast Recovery Speed
ALC enable
Data
01
0
01
fs=8kHz
Operation
−4.1dBFS
Enable
32ms
Data
01
0
11
fs=44.1kHz
Operation
−4.1dBFS
Enable
23.2ms
001
32ms
011
23.2ms
E1H
+30dB
E1H
+30dB
E1H
+30dB
E1H
+30dB
1 step
1 step
4 times
Enable
00
00
00
1
1 step
1 step
4 times
Enable
00
00
00
1
Table 34. ALC
ALC
ALC
bit = “0”
(ALC
PMADL = PMADR bits = “0”)
LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 32ms@8kHz
Zero Crossing Timeout Period = 32ms@8kHz
Limiter and Recovery Step = 1
Fast Recovery Speed = 4 step
Gain of IVOL = +30dB
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC bit = “1”
Manual Mode
WR (ZTM1-0, WTM2-0, RFST1-0)
(1) Addr=06H, Data=14H
WR (REF7-0)
(2) Addr=08H, Data=E1H
WR (IVL/R7-0)
* The value of IVOL should be
(3) Addr=09H&0CH, Data=E1H
the same or smaller than REF’s
WR (RGAIN1, LMTH1)
(4) Addr=0BH, Data=00H
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”)
(5) Addr=07H, Data=21H
ALC Operation
Note : WR : Write
Figure 35. ALC
MS0625-J-01
2007/06
- 53 -
[AK4648]
■
(
)
ALC bit = “0”
1.
2.
ALC
(ZTM1-0, LMTH1-0 bits
ALC
)
3.
IVL7-0, IVR7-0 bits
PMADL = PMADR bits = “0”
“1”
ADC
(Table 35)
ZTM1-0 bits
IVL7-0, IVR7-0 bits
L/R
PMADL bit = “1” or PMADR bit =
IVOL
IVL7-0 = IVR7-0 bits = “91H” (0dB)
IVL7-0
IVR7-0
F1H
F0H
EFH
:
E2H
E1H
E0H
:
03H
02H
01H
00H
Table 35.
GAIN (dB)
+36.0
+35.625
+35.25
:
+30.375
+30.0
+29.625
:
−53.25
−53.625
−54
MUTE
MS0625-J-01
Step
0.375dB
(default)
2007/06
- 54 -
[AK4648]
IVL7-0, IVR7-0 bits
ALC bit
ALC Status
Disable
Enable
IVL7-0 bits
E1H(+30dB)
IVR7-0 bits
C6H(+20dB)
Internal IVL
E1H(+30dB)
Internal IVR
C6H(+20dB)
E1(+30dB) --> F1(+36dB)
(1)
IVL IVR
IVL, IVR
E1(+30dB)
(2)
E1(+30dB) --> F1(+36dB)
Figure 36. ALC
(1) ALC
(2) ALC
Disable
C6H(+20dB)
IVOL
IVL
(09H, 0CH)
ALC Disable
ALC Enable
ALC bit = “1”
ALC bit = “0”
MS0625-J-01
2007/06
- 55 -
[AK4648]
■
3
IIR
(tc=50/15μs
(32kHz, 44.1kHz, 48kHz)
DEM1-0 bits
)
(Table 36)
DEM1
DEM0
0
0
0
1
1
0
1
1
Table 36.
Mode
44.1kHz
OFF
48kHz
32kHz
(default)
■ 5-Band Equalizer
AK4648 DAC
FBEQx3-0 bits
5
Table 37
• Center frequency: 100Hz, 250Hz, 1kHz, 3.5kHz, 10kHz (Note 56, Note 57)
• Cut/Boost amount: Minimum –10.5dB, Maximum +12dB, Step 1.5dB
44.1kHz
Note 56:
Note 57: 100Hz
Note 58: 10kHz
100Hz
10 Hz
ON/OF
5
FBEQA3-0:
FBEQB3-0:
FBEQC3-0:
FBEQD3-0:
FBEQE3-0:
FBEQ bit
Select the boost level of 100Hz
Select the boost level of 250Hz
Select the boost level of 1kHz
Select the boost level of 3.5kHz
Select the boost level of 10kHz
FBEQx3-0
Boost
0H
+12.0dB
1H
+10.5dB
2H
+9.0dB
3H
+7.5dB
:
:
8H
0dB
(default)
:
:
DH
−7.5dB
EH
−9.0dB
FH
−10.5dB
Table 37. Boost amount of 5 Band Equalizer
MS0625-J-01
2007/06
- 56 -
[AK4648]
■
AK4648 MUTE
0.5dB
DAC
DVOLC bit “1”
“0”
Lch, Rch
256/fs
00H(+12dB)
FFH(MUTE)
256
(DATT)
+12dB
−115dB
DVL7-0 bits Lch, Rch
DVOLC
ATT
1061
DVTM bit = “0”
bit
DVTM bit
1061/fs(24ms@fs=44.1kHz)
DVL/R7-0
00H
01H
02H
:
18H
:
FDH
FEH
FFH
DVTM bit
0
1
Gain
Step
+12.0dB
+11.5dB
+11.0dB
:
0.5dB
0dB
(default)
:
−114.5dB
−115.0dB
MUTE (−∞)
Table 38. Digital Volume Code Table
FFH
DVL/R7-0 bits = 00H
fs=8kHz
1061/fs
133ms
256/fs
32ms
Table 39.
MS0625-J-01
fs=44.1kHz
24ms
6ms
(default)
2007/06
- 57 -
[AK4648]
■
DAC
SMUTE bit “1”
SMUTE bit “0”
SMUTE bit
−∞(“0”)
DVTM bit
−∞
−∞
bits
DVTM bit
DVTM bit
DVL/R7-0 bits
DVL/R7-0
(Figure 37)
S M U T E bit
D VTM bit
D VL/R 7-0 bits
D VTM bit
(1)
(3)
A ttenuation
-∞
GD
(2)
GD
A nalog O utput
Figure 37.
(1) DVTM bit
(2)
(3)
−∞(“0”)
(GD)
DVTM bit
DVL/R7-0 bits
MS0625-J-01
2007/06
- 58 -
[AK4648]
■
:
(LIN2/RIN2/LIN4/RIN4 pins, AIN3 bit = “1”: LIN3/RIN3 pins)
PMAINL2=PMAINR2 bits = “1”
LINS2 bit
RINS2 bit
LIN2/RIN2 pins
“1”
LINL2 bit
PMAINL4=PMAINR4 bits = “1”
LINS4 bit
RINS4 bit
RINR2 bit
RINR4 bit
PMADL bit
0
1
“1”
LINH4 bit
RINH4 bit
“1”
LIN4/RIN4 pins
“1”
PMADR bit “1”
MGAIN1-0 bits = “00”
LIN2/RIN2/LIN4/RIN4 pins
bits = “01”, “10”, “11”
typ. 20kΩ
PMAINL2 bit
PMAINR2 bit
PMAINL4 bit
PMAINR4 bit
RINH2 bit
“1”
“1”
LINL4 bit
Pin
LIN2
RIN2
LIN4
RIN4
LINH2 bit
bit
PMMICL or PMADL bit
PMMICR or PMADR bit
PMMICL or PMADL bit
PMMICR or PMADR bit
A/D
typ. 30kΩ MGAIN1-0
Input Impedance
(typ.)
MGAIN1-0 bits
00
01, 10 or 11
00
0
01, 10 or 11
00
1
01, 10 or 11
Table 40. Input Impedance of LIN2/RIN2/LIN4/RIN4 pins
60k
30k
60k
30k
30k
20k
1
MIN/VCOC pins
LIN3/RIN3 pins
AIN3 bit = “1”
PMAINL3=PMAINR3 bits = “1”
LIN3/RIN3 pins
PMMICL=PMMICR=MICL3=MICR3 bits = “1”
MIC-Amp
LINS3 bit
RINS3 bit
LINH3 bit
RINH3 bit “1”
PLL
LIN3/RIN3 pins
“1”
LINL3 bit
RINR3 bit
“1”
PMADL bit
PMADR bit “1”
A/D
LIN3/RIN3 pins
MICL3=MICR3 bits = “0”
MGAIN1-0 bits = “00”
typ. 30kΩ MGAIN1-0 bits = “01”, “10”, “11”
typ. 20kΩ
MICL3=MICR3 bits = “1”
MGAIN1-0 bits = “00”
typ. 60kΩ MGAIN1-0 bits = “01”, “10”, “11”
typ. 30kΩ
Pin
LIN3
RIN3
PMAINL3 bit
PMAINR3 bit
bit
PMMICL or PMADL bit
PMMICR or PMADR bit
MICL3 bit
MICR3 bit
MGAIN1-0 bits
Input Impedance
(typ.)
00
01, 10 or 11
00
1
0
0
01, 10 or 11
00
0
01, 10 or 11
1
1
00
1
01, 10 or 11
Table 41. Input Impedance of LIN3/RIN3 pins (AIN3 bit = “1”; x: Don’t care)
0
1
x
60k
30k
60k
30k
30k
20k
60k
30k
(typ.) Table 42, Table 43, Table 44, Table 45
MS0625-J-01
2007/06
- 59 -
[AK4648]
AK4648
INL1-0 bits
LIN1/IN1− pin
ADC Lch
RIN1/IN1+ pin
MDIF1 bit
MIC-Amp
INR1-0 bits
RIN2/IN2− pin
ADC Rch
LIN2/IN2+ pin
MDIF2 bit
MIC-Amp
MIN/LIN3 pin
MICR3 bit
PMAINR3 bit
PMAINR2 bit
PMAINL2 bit
PMAINR4 bit
PMAINL4 bit
RIN4/IN4− pin
MICL3 bit
LIN4/IN4+ pin
PMAINL3 bit
VCOC/RIN3 pin
Lineout, HP-Amp, SPK-Amp
Figure 38.
PMAINL2 bit
PMAINR2 bit
LIN2 pin
RIN2 pin
(
)
LINL2 bit
RINR2 bit
LINH2 bit
RINH2 bit
LOUT/LOP pin,
ROUT/LON pin
HPL, HPR pin
LINS2 bit
RINS2 bit
SPLP/SPLN pin,
SPRP/SPRN pin
Figure 39.
(LIN2/RIN2)
MS0625-J-01
2007/06
- 60 -
[AK4648]
PMAINL4 bit
PMAINR4 bit
LIN4 pin
RIN4 pin
LINL4 bit
RINR4 bit
LINH4 bit
RINH4 bit
LOUT/LOP pin,
ROUT/LON pin
HPL, HPR pin
LINS4 bit
RINS4 bit
SPLP/SPLN pin,
SPRP/SPRN pin
Figure 40.
PMAINL3 bit
PMAINR3 bit
LIN3 pin
RIN3 pin
(LIN4/RIN4)
LINL3 bit
RINR3 bit
LINH3 bit
RINH3 bit
LOUT/LOP pin,
ROUT/LON pin
HPL, HPR pin
LINS3 bit
RINS3 bit
SPLP/SPLN pin,
SPRP/SPRN pin
Figure 41.
(LIN3/RIN3: PLL
)
LOVL bit
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4
Æ LOUT/ROUT
0
0dB
(default)
1
+2dB
Table 42. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ LOUT/ROUT Output Gain (typ.)
LOVL bit
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4
Æ LOP/LON
0
0dB
(default)
1
+2dB
Table 43. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ LOP/LON Output Gain (typ.)
HPG bit Setting
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4
Æ HPL/HPR
0dB
0dB
(default)
Table 44. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ Headphone-Amp Output Gain (typ.)
MS0625-J-01
2007/06
- 61 -
[AK4648]
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Æ SPLP/SPLN or SPRP/SPRN
ALC bit = “0”
ALC bit = “1”
SPKMN bit = “1” SPKMN bit = “0” SPKMN bit = “1”
SPKMN bit = “0”
+4.41dB
+0.41dB
+6.41dB
(default)
000
−1.59dB
001
+0.41dB
+6.41dB
+2.41dB
+8.41dB
010
+4.63dB
+10.63dB
+6.63dB
+12.63dB
011
+6.63dB
+12.63dB
+8.63dB
+14.63dB
100
-6dB
0dB
-4dB
+2dB
101
-12dB
-6dB
-10dB
-4dB
110
N/A
N/A
N/A
N/A
111
N/A
N/A
N/A
N/A
Table 45. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ Speaker-Amp Output Gain (typ.), N/A: Not available
SPKG2-0
bits
■
:
L4DIF bit = “1”
LIN4, RIN4 pins
(L4DIF bit = “1”: IN4+/IN4− pins)
IN4+, IN4− pins
IN4+, IN4− pins
PMAINL4 bit = “1”
LINS4 bit
RINS4 bit “1”
LINL4 bit
LINH4 bit
RINR4 bit
RINH4 bit
“1”
“1”
(IN4+) − (IN4−)
(typ.) Table 46, Table 47, Table 48, Table 49
AK4648
MIC-Amp Lch
LIN4/IN4+ pin
L4DIF bit PMAINL4 bit
MIC-Amp Rch
RIN4/IN4− pin
PMAINR4 bit
Lineout, HP-Amp, Speaker-Amp
Figure 42. Full-differential Mono Analog Mixing Circuit
LOVL bit
IN4+/IN4− Æ LOUT/ROUT
(default)
0
−6dB
1
−4dB
Table 46. IN4+/IN4− Input Æ LOUT/ROUT Output Gain (typ.)
LOVL bit
IN4+/IN4− Æ LOP/LON
0
0dB
(default)
1
+2dB
Table 47. IN4+/IN4− Input Æ LOP/LON Output Gain (typ.)
MS0625-J-01
2007/06
- 62 -
[AK4648]
HPG bit Setting
IN4+/IN4− Æ HPL/HPR
(default)
0dB
−6dB
Table 48. IN4+/IN4− Input Æ Headphone-Amp Output Gain (typ.)
IN4+/IN4- Æ SPLP/SPLN or SPRP/SPRN
ALC bit = “0”
ALC bit = “1”
+0.41dB
(default)
000
−1.59dB
001
+0.41dB
+2.41dB
010
+4.63dB
+6.63dB
011
+6.63dB
+8.63dB
100
-6dB
-4dB
101
-12dB
-10dB
110
N/A
N/A
111
N/A
N/A
Table 49. IN4+/IN4- Input Æ Speaker-Amp Output Gain (typ.), N/A: Not avaiable
SPKG2-0 bits
■
:
(AIN3 bit = “0”: MIN pin)
MIN pin
AIN3 bit = “0”
MINS bit “1”
MINL bit “1”
Ri = 20kΩ
Ri
PMMIN bit = “1”
MINH bit
“1”
Ri
(typ.) Table 50, Table 51, Table 52, Table 53
Ri
MINL bit
Analog Input
LOUT/LOP pin,
ROUT/LON pin
MIN pin
MINH bit
HPL, HPR pin
MINS bit
SPLP/SPLN pin,
SPRP/SPRN pin
Figure 43. Block Diagram of MIN pin
LOVL bit
0
1
Table 50. Ri = 20kΩ
LOVL bit
0
1
Table 51. Ri = 20kΩ
MIN Æ LOUT/ROUT
0dB
+2dB
MIN
Æ LOUT/ROUT
MIN Æ LOP/LON
+6dB
+8dB
MIN
Æ LOP/LON
MS0625-J-01
(default)
(typ.)
(default)
(typ.)
2007/06
- 63 -
[AK4648]
HPG bit Setting
0dB
Table 52. Ri = 20kΩ
MIN Æ HPL/HPR
−20dB
MIN
Æ
MIN Æ SPLP/SPLN or SPRP/SPRN
ALC bit = “0”
ALC bit = “1”
000
+4.43dB
+6.43dB
001
+6.43dB
+8.43dB
010
+10.65dB
+12.65dB
011
+12.65dB
+14.65dB
100
0dB
+2dB
101
-6dB
-4dB
110
N/A
N/A
111
N/A
N/A
Table 53. Ri = 20kΩ
MIN
Æ
(typ.)
SPKG2-0 bits
■
(default)
(typ.)
(LOUT/ROUT pins)
“0”
DACL bit “1”
DAC Lch, Rch
LOUT, ROUT pins
DACL bit “0”
OFF
LOUT, ROUT pins VCOM
min. 10kΩ
PMLO=LOPS bits = “0”
VSS1 100kΩ(typ.)
LOPS bit
= “1”
LOPS bit = “1”
PMLO bit
ON/OFF
ON/OFF
Figure 45
C
20kΩ
C=1μF, AVDD=3.3V
300ms
PMLO bit = “1”
LOPS bit = “0”
LODIF bit
LOVL bit
DAC
[(L+R)/2]
MICL3, MICR3 bits
LOUT, ROUT pins
LOM bit = “1”
LOM3 bit = “1”
LOUT, ROUT pins
(LIN3/RIN3
MIC-Amp
DACL bit
) [(L+R)/2]
LOVL bit
LOUT pin
DAC
ROUT pin
Figure 44.
LOPS
0
1
PMLO
0
1
0
1
Table 54.
Mode
LOUT/ROUT pin
Pull-down to VSS1
(default)
Fall down to VSS1
Rise up to VCOM
MS0625-J-01
2007/06
- 64 -
[AK4648]
LOVL
Gain
0
0dB
1
+2dB
Table 55.
(typ.)
0.6 x AVDD
0.757 x AVDD
LOUT pin
ROUT pin
1μF
(default)
220Ω
20kΩ
Figure 45.
(
)
(
)
(2 )
(5 )
P M L O b it
(1 )
(3 )
(4 )
(6 )
L O P S b it
L O U T , R O U T p in s
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
(
Figure 46.
(1)
(2)
ON
LOPS bit = “1”
PMLO bit = “1”
C=1μF, AVDD=3.3V
LOUT, ROUT pins
300ms)
(3) LOUT, ROUT pins
(4)
(5)
)
200ms (max.
LOPS bit = “0”
ON
LOPS bit = “1”
PMLO bit = “0”
C=1μF, AVDD=3.3V
LOUT, ROUT pins
300ms)
(6) LOUT, ROUT pins
200ms (max.
LOPS bit = “0”
MS0625-J-01
2007/06
- 65 -
[AK4648]
ON/OFF
DACL, MINL, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, MICL3, MICR3 bits
AIN3 bit = “0”
MIN
20kΩ
0dB(typ.)@LOVL bit = “0”
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4/DAC
0dB(typ.)@LOVL bit = “0”
LINL2 bit
LIN2 pin
0dB
LIN4 pin
0dB
LINL4 bit
MINL bit
MIN
0dB
AIN3 bit
LIN3/MIN pin
MICL3 bit
LIN3
M
I
LINL3 bit
LOUT pin
X
0dB
LIN1 pin
MIC-Amp Lch
DACL bit
0dB
DAC Lch
RINR2 bit
RIN2 pin
0dB
RIN4 pin
0dB
RINR4 bit
AIN3 bit
MICR3 bit
RIN3
RIN3/VCOM pin
RINR3 bit
I
ROUT pin
0dB
VCOC
RIN1 pin
M
MINL bit
X
0dB
MIC-Amp Rch
DACL bit
0dB
DAC Rch
Note: MICL3 bit = “1”
Figure 47.
MIN
( LOVL bit = “0”)
MS0625-J-01
2007/06
- 66 -
[AK4648]
■
(LOP/LON pins)
LOUT/ROUT pins
LOP/LON pins
LODIF bit = “1”
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4
[(L+R)/2]
min. 10kΩ
PMLO bit = “0”
LOP/LON pins Hi-Z
PMLO bit = “1”, LOPS bit = “1”
PMLO bit = “1”, LOPS bit = “0”
DAC
LOP/LON pins
LOVL bit
(LOP) − (LON) = (IN4+) − (IN4−)
L4DIF=LODIF bits = “1”
DACL bit
LOVL bit
LOP pin
DAC
LON pin
Figure 48. Mono Line Output
PMLO
0
1
LOPS
Mode
LOP
LON
x
Power-down
Hi-Z
Hi-Z
1
Power-save
Hi-Z
VCOM
0
Normal Operation
Normal Operation Normal Operation
Table 56. Mono Line Output Mode Setting (x: Don’t care)
LOVL
0
1
(default)
Gain
Output Voltage (typ.)
+6dB
1.2 x AVDD
(default)
+8dB
1.5 x AVDD
Table 57. Mono Line Output Volume Setting
PMLO bit
LOPS bit
LOP pin
LON pin
Hi-Z
Hi-Z
Hi-Z
VCOM
VCOM
Hi-Z
Figure 49. Power-up/Power-down Timing for Mono Line Output
MS0625-J-01
2007/06
- 67 -
[AK4648]
ON/OFF
DACL, MINL, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, MICL3, MICR3 bits
AIN3 bit = “0”
MIN
20kΩ
+6dB(typ.)@LOVL bit = “0”
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4/DAC
0dB(typ.)@LOVL bit = “0”
LINL2 bit
LIN2 pin
0dB
LIN4 pin
0dB
LINL4 bit
MINL bit
MIN
AIN3 bit
LIN3/MIN pin
+6dB
MICL3 bit
LIN3
LINL3 bit
0dB
LIN1 pin
MIC-Amp Lch
RINR2 bit
RIN2 pin
0dB
RIN4 pin
0dB
M
RINR4 bit
AIN3 bit
MICR3 bit
RIN3
RIN3/VCOM pin
I
LOP/N pin
X
RINR3 bit
0dB
VCOC
RIN1 pin
MIC-Amp Rch
DACL bit
DAC Lch
0dB
DACL bit
0dB
DAC Rch
Note: MICL3 bit = “1”
Figure 50.
MIN
( LOVL bit = “0”)
MS0625-J-01
2007/06
- 68 -
[AK4648]
■
(HPL/HPR pins)
HVDD
HVDD/2@VBAT bit = “0”
HPG3-0 bits
16Ω (min.)
(Table 58)
HPM bit = “1”
HPM3 bit = “1”
DAC
[(L+R)/2]
MICL3, MICR3 bits
HPL, HPR pins
(LIN3/RIN3
HPG3-0 bits
FH-DH
CH
BH
AH
9H
8H
7H
6H
5H
4H
3H
2H
1H
0H
HPL, HPR pins
MIC-Amp
) [(L+R)/2]
Volume [dB]
N/A
+3dB
0dB
(default)
-3dB
-6dB
-9dB
-12dB
-15dB
-18dB
-21dB
-24dB
-27dB
-30dB
-33dB
(N/A: Not available)
Table 58.
AK4648
1.
(Single-ended Mode)
HP-Amp
HPL pin
Headphone
C
R
0.22μF
10Ω
VCOM Amp for
HP-Amp
16Ω
HVCM pin
HP-Amp
16Ω
HPR pin
C
R
0.22μF
10Ω
Figure 51.
(Single-ended Mode)
MS0625-J-01
2007/06
- 69 -
[AK4648]
R 12Ω
(0.22μF±20%
10Ω±20%
)
(fc)
Table 59
5-band Equalizer
RL 16Ω
(fs)
typ. (0.6 x AVDD)Vpp @ HPG = 0dB
R [Ω]
C [μF]
fc [Hz]
fc [Hz]
5-band EQ =
OFF
5-band EQ = ON
(+6dB/100Hz @
fs=44.1kHz)
Output Power [mW]@0dBFS
HVDD=3.0V
AVDD=3.0V
HVDD=3.3V
AVDD=3.3V
220
45
17
25.3
30.6
100
100
43
100
70
28
6.8
12.5
15.1
47
149
73
100
50
19
16
6.3
7.7
47
106
46
10
137
66
Note 59. Output power at 16Ω load.
Table 59. External Circuit Example (HPG = 0dB)
0
HPMTN bit
“0”
VSS2
HVDD/2@VBAT bit = “0”
HVDD
HVDD
MUTET pin
3.6V
1μF±30%
4.2V
5.0V
3.6V
2.2μF±30%
4.2V
5.0V
Note 60.
Note 61.
Table 60. MUTET pin
HPMTN bit= “0” Æ “1”
(Note 60)
typ.
max
120ms
210ms
230ms
260ms
260ms
460ms
500ms
550ms
0.8 x HVDD/2
MUTE ON/OFF
MS0625-J-01
HVDD=5V
AVDD=3.3V
30.6
15.1
7.7
HPMTN bit “1”
MUTET pin
MUTET pin
HPMTN bit = “1” Æ “0”
(Note 61)
typ.
max.
140ms
260ms
270ms
290ms
310ms
560ms
570ms
590ms
(VBAT bit = “0”)
2007/06
- 70 -
[AK4648]
PMHPL, PMHPR bits “0”
HPL, HPR pins “L” (VSS2)
PMHPL bit,
PMHPR bit
HPMTN bit
HPL pin,
HPR pin
(1) (2)
(3)
(4)
Figure 52.
(Single-ended Mode)
(PMHPL, PMHPR bits = “1”)
(HPMTN bit = “1”)
(HPMTN bit = “0”)
(PMHPL, PMHPR bits = “0”)
(1)
(2)
(3)
(4)
2.
VSS2
VSS2
(Pseudo Cap-less Mode)
HP-Amp
HPL pin
Headphone
R
0.22μF
10Ω
VCOM Amp for
HP-Amp
16Ω
HVCM pin
HP-Amp
16Ω
HPR pin
R
0.22μF
10Ω
Figure 53.
R 12Ω
(0.22μF±20%
10Ω±20%
(Pseudo Cap-less Mode)
)
MS0625-J-01
2007/06
- 71 -
[AK4648]
HPMTN bit “0”
HPMTN bit “1”
MUTET pin
MUTET pin
VSS2
HVDD/2@VBAT bit = “0”
HVDD
HPMTN bit= “0” Æ “1”
(Note 62)
typ.
max
120ms
210ms
230ms
260ms
260ms
460ms
500ms
550ms
0.8 x HVDD/2
MUTET pin
HVDD
3.6V
1μF±30%
4.2V
5.0V
3.6V
2.2μF±30%
4.2V
5.0V
Note 62.
Note 63.
Table 61. MUTET pin
PMHPL, PMHPR, PMHPC bits “0”
HPL, HPR, HVCM pins
HPMTN bit = “1” Æ “0”
(Note 63)
typ.
max.
140ms
260ms
270ms
290ms
310ms
560ms
570ms
590ms
MUTE ON/OFF
(VBAT bit = “0”)
“L” (VSS2)
PMHPL bit,
PMHPR bit
PMHPC bit
HPMTN bit
HPL pin,
HPR pin,
HVCM pin
(1) (2)
(3)
(4)
Figure 54.
(Pseudo Cap-less Mode)
(PMHPL, PMHPR, PMHPC bits = “1”)
(HPMTN bit = “1”)
(HPMTN bit = “0”)
(PMHPL, PMHPR, PMHPC bits = “0”)
(1)
(2)
(3)
(4)
VSS2
VSS2
PSRR
HVDD
VBAT bit = “1”
AVDD(typ.)
PSRR
AVDD=3.3V
VBAT bit
Common Voltage [V]
Table 62.
RF
HVDD
0.64 x
2.1V
0
0.5 x HVDD
MS0625-J-01
HVDD
4.2V
1
0.64 x AVDD
2007/06
- 72 -
[AK4648]
Wired OR
PMVCM=PMHPL=PMHPR
200kΩ(typ.) VSS2
OR
PMVCM
x
0
1
1
PMHPL/R
0
0
1
1
PMHPC bits = “0”, HPZ bit = “1”
HP-Amp
AK4648 HP-Amp
HP-Amp
-0.3V
20μA(typ.)
Pseudo Cap-less Mode
HPMTN
HPZ
Mode
x
0
Power-down & Mute
x
1
Power-down
0
x
Mute
1
x
Normal Operation
Table 63. HP-Amp Mode Setting (x: Don’t care)
HPL, HPR pins
HP-Amp Wired
“HVDD+0.3V”
Wired OR
HPL/R pins
VSS2
(default)
Pull-down by 200kΩ
VSS2
Normal Operation
HPL pin
AK4648
Headphone
HPR pin
Another
HP-Amp
Figure 55.
Wired OR
MS0625-J-01
2007/06
- 73 -
[AK4648]
HP-Amp Power Management bit HPZ bit
Rch
GND
Single-ended Mode Pseudo Cap-less Mode
1.
2.
Rch
Signle ended-Mode
(1)
: PMHPL=PMHPR=HPZ bits = “0”
HPL/HPR pins VSS2
(2) Lch HP-Amp
: PMHPL = “1”
Lch HP-Amp
Power-up
HPL pin
VSS2
(3) Rch HP-Amp
: HPZ bit = “1”
HPR pin
VSS2
typ. 200kΩ
(4)
: HPMTN bit: “0” Æ 1
HPL pin
HPR pin
typ. 200kΩ VSS2
Hi-z
VSS2
Pseudo Cap-less Mode
(1)
: PMHPL=PMHPR=PMHPC=HPZ bits = “0”
HPL/HPR/HVCM pins VSS2
(2) Lch HP-Amp
: PMHPL = PMHPC bits = “1”
Lch HP-Amp
HPL/HVCM pins
VSS2
(3) Rch HP-Amp
: HPZ bit = “1”
HPR pin
typ. 200kΩ VSS2
(4)
: HPMTN bit: “0” Æ 1
HPL pin
HPR pin
typ. 200kΩ VSS2
HVCM
MS0625-J-01
2007/06
- 74 -
[AK4648]
ON/OFF
DACH, MINH, LINH2, RINH2, LINH4, RINH4, MICL3, MICR3 bits
AIN3 bit = “0”
MIN
20kΩ
−20dB(typ.)@HPG = 0dB
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4/DAC
0dB(typ.)@HPG = 0dB
LINH2 bit
LIN2 pin
0dB
LINH4 bit
LIN4 pin
0dB
MINH bit
MIN
-20dB
AIN3 bit
LIN3/MIN pin
MICL3 bit
LIN3
M
I
LINH3 bit
HPL pin
X
0dB
LIN1 pin
MIC-Amp Lch
DACH bit
DAC Lch
0dB
RINH2 bit
RIN2 pin
0dB
RIN4 pin
0dB
RINH4 bit
AIN3 bit
MICR3 bit
RIN3
RIN3/VCOM pin
RINH3 bit
I
HPR pin
0dB
VCOC
RIN1 pin
M
MINH bit
X
-20dB
MIC-Amp Rch
DACH bit
0dB
DAC Rch
Note: MICL3 bit = “1”
Figure 56.
MIN
(HPG = 0dB)
MS0625-J-01
2007/06
- 75 -
[AK4648]
■
(SPP/SPN pins)
PMSPL, PMSPR bits
Power ON/OFF
Stereo SPK Mode (SPKMN bit = “1”, PMSPL=PMSPR bits = “1”) Mono SPK Mode (SPKMN bit =
“0”, PMSPL bit = “1” or PMSPR bit = “1”)
HVDD=3.6V 640mW
High Power Mono SPK Mode
(SPKMN bit = “0”, PMSPL=PMSPR bit = “1”)
HVDD=3.6V
820mW
High
Power Mono SPK Mode
SPLP pin SPRP pin, SPRP pin SPRN pin
SPKMN bit
PMSPL =PMSPR bit = “0”
ON/OFF
SPPSN bit
SPKMN bit
Mode
Mono SPK
SPKMN bit
0
0
0
High Power Mono SPK
0
Stereo SPK
1
1
1
1
*1:
Mixing [(L+R)/2]
*2:
PMSPL bit
0
1
0
1
0
0
1
1
PMSPR bit SPLP/SPLN pin SPRP/SPRN pin
0
PD
PD
0
PU (*1)
PD
1
PD
PU (*1)
1
PU (*2)
0
PD
PD
1
PD
PU: Rch
0
PU: Lch
PD
1
PU: Lch
PU: Rch
HVDD=3.6V
640mW
Mixing [(L+R)/2]
HVDD=3.6V
820mW
Table 64. Speaker Output Mode Setting (PD: Power-Down, PU: Power-Up)
HVDD
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4
[(L+R)/2]
BTL
2.6V ∼ 5.0V
SPKMN bit
or
AVDD
SPKG2-0 bits
000
001
010
011
100
101
110
111
DAC
SPKG2-0 bits
SPKG2-0 bits
ALC bit = “0”
+4.43dB
+6.43dB
+10.65dB
+12.65dB
0dB
-6dB
N/A
N/A
Table 65. SPK-Amp
ALC bit = “1”
+6.43dB
+8.43dB
+12.65dB
+14.65dB
+2dB
-4dB
N/A
N/A
(default)
N/A: Not available
MS0625-J-01
2007/06
- 76 -
[AK4648]
AVDD
HVDD
3.6V
3.3V
4.5V
SPK-Amp
ALC bit = “0”
SPKG2-0 bits
000
001
010
011
000
001
010
011
3.30Vpp
4.15Vpp
5.2Vpp (Note 64)
5.2Vpp (Note 64)
3.30Vpp
4.15Vpp
6.75Vpp
7.0Vpp (Note 64)
Note 64.
SPK-Amp
5.2Vpp (@ HVDD=3.6V)
(DAC
=0dBFS)
ALC bit = “1”
(LMTH1-0 bits = “00”; -2.5dBFS)
3.11Vpp
3.92Vpp
5.2Vpp (Note 64)
5.2Vpp (Note 64)
3.11Vpp
3.92Vpp
6.37Vpp
7.0Vpp (Note 64)
DAC
0dBFS
DVOL
DAC
7.0Vpp (@ HVDD=4.5V)
Table 66. SPK-Amp
ALC
fs=44.1kHz
Data
Operation
00
−2.5dBFS
0
Enable
10
11.6ms
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same data
as ZTM1-0 bits
Maximum gain at recovery operation
011
23.2ms
C1H
+18dB
Gain of IVOL
91H
0dB
00
00
1
1 step
1 step
Enable
WTM2-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
ALC
Limiter ATT step
Recovery GAIN step
ALC enable
Table 67.
ALC
MS0625-J-01
2007/06
- 77 -
[AK4648]
PMSPL bit SPLP/SPLN pin
Power-up/down
PMSPR bit
SPRP/SPRN pin
SPPSN bit Lch/Rch
PMSPL bit (PMSPR bit) “0”
SPLP(SPRP), SPLN(SPRN) pin
PMSPL bit (PMSPR bit)
“1”
SPPSN bit “0”
SPLP (SPRP) pin Hi-Z SPLN (SPRN) pin HVDD/2
Hi-Z
SPK-Amp Power-down
PMSPL=PMSPR bits = “0”
PMSPL bit
PMSPR bit
0
SPPSN bit
Mode
x
0
1
Table 68.
1
SPLP pin
SPRP pin
Hi-Z
Hi-Z
SPLN pin
SPRN pin
Hi-Z
HVDD/2
(default)
(x: Don’t care)
PMSPL bit
PMSPR bit
SPPSN bit
SPLP pin,
SPRP pin
SPLN pin,
SPRN pin
Hi-Z
Hi-Z
Hi-Z
HVDD/2
HVDD/2
Hi-Z
Figure 57. Power-up/Power-down Timing for Speaker-Amp
MS0625-J-01
2007/06
- 78 -
[AK4648]
1. Stereo SPK Mode
(SPKMN bit = “1”)
ON/OFF
DACS, MINS, LINS2, RINS2, LINS3, RINS3, LINS4, RINS4, MICL3, MICR3 bits
AIN3 bit = “0”
MIN
20kΩ
+4.43dB(typ.)@SPKG2-0 bits =
“000”, ALC bit = “0”
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4/DAC
+4.43dB(typ.)@SPKG2-0 bits =
“000”, ALC bit = “0”
LINS2 bit
LIN2 pin
+4.43dB
LINS4 bit
LIN4 pin
+4.43dB
MINS bit
MIN
+4.43dB
AIN3 bit
LIN3/MIN pin
LIN3
MICL3 bit
M
I
LINS3 bit
SPLP/N pin
X
+4.43dB
LIN1 pin
MIC-Amp Lch
DACS bit
DAC Lch
+4.43dB
RINS2 bit
+4.43dB
RIN2 pin
RINS4 bit
RIN4 pin
+4.43dB
AIN3 bit
RIN3
MICR3 bit
RINS3 bit
I
SPRP/N pin
+4.43dB
RIN3/VCOM pin
VCOC
RIN1 pin
M
MINS bit
X
+4.43dB
MIC-Amp Rch
DACS bit
DAC Rch
Figure 58.
+4.43dB
Note: MICL3 bit = “1”
MIN
(SPKMN bit = “1”, SPKG2-0 bits = “000”, ALC bit = “0”)
MS0625-J-01
2007/06
- 79 -
[AK4648]
2. Mono SPK Mode & High Power Mono SPK Mode
(SPKMN bit = “0”)
ON/OFF
DACS, MINS, LINS2, RINS2, LINS3, RINS3, LIN4S, RIN4S, MICL3, MICR3 bits
AIN3 bit = “0”
MIN
20kΩ
+4.43dB(typ.)@SPKG2-0 bits =
“000”, ALC bit = “0”
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4/DAC
-1.59dB(typ.)@SPKG2-0 bits =
“000”, ALC bit = “0”
LINS2 bit
LIN2 pin
-1.59dB
LIN4 pin
-1.59dB
LINS4 bit
MINS bit
MIN
+4.43dB
AIN3 bit
LIN3/MIN pin
LIN3
MICL3 bit
LINS3 bit
-1.59dB
LIN1 pin
MIC-Amp Lch
DACS bit
DAC Lch
-1.59dB
M
I
RINS2 bit
RIN2 pin
-1.59dB
RIN4 pin
-1.59dB
SPLP/N pin
or
SPRP/N pin
X
RINS4 bit
AIN3 bit
MICR3 bit
RIN3
RIN3/VCOM pin
RINS3 bit
-1.59dB
VCOC
RIN1 pin
MIC-Amp Rch
DACS bit
DAC Rch
Note: MICL3 bit = “1”
Figure 59.
-1.59dB
MIN
(SPKMN bit = “0”, SPKG2-0 bits = “000”, ALC bit = “0”)
MS0625-J-01
2007/06
- 80 -
[AK4648]
■
AK4648 I2C
Fast-Mode (max.:400kHz)
SDA, SCL pins
(TVDD+0.3)V
1. WRITE
I2C
(Start Condition)
(Figure 66)
8
IC
AK4648
SDA
R/W bit “1”
2
Figure 60
“H”
SCL
SDA
“L”
“L”
7
(R/W)
6
“001001”
(Figure 61)
CAD0 pin
1
(Acknowledge)
(Figure 67) R/W bit
(
)
(Figure 62)
3
(Figure 63) AK4648
“0”
MSB first
IC
“H”
SDA
8
MSB first
2
8
(Stop Condition)
(Figure 66)
“H”
“0”
SCL
“H”
1
AK4648
“27H”
“00H”
“H”
SDA
SCL
“H”
(Figure 68) SCL
“L”
“L”
“H”
SDA
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
A
C
K
Data(n)
Data(n+1)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 60. I2C
0
0
0
1
Figure 61.
1
0
A5
0
0
D6
D5
Figure 63.
CAD0
(CAD0
A4
Figure 62.
D7
1
R/W
)
A3
A2
A1
A0
D3
D2
D1
D0
2
D4
3
MS0625-J-01
2007/06
- 81 -
[AK4648]
2. READ
R/W bit “1”
AK4648 READ
“27H”
“00H”
2
AK4648
READ
2-1.
AK4648
(READ
WRITE
“n+1”
(R/W bit = “1”)
AK4648 READ
)
“n”
1
READ
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
Data(n+1)
Data(n+2)
MA
AC
SK
T
E
R
A
C
K
MA
AC
SK
T
E
R
Data(n+x)
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
P
MN
AA
SC
T
EK
R
Figure 64.
2-2.
READ
(R/W bit = “1”)
WRITE
WRITE
= “0”)
AK4648
(R/W bit= “1”)
READ
(R/W bit
AK4648
1
READ
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
MA
AC
S K
T
E
R
Data(n+x)
MA
AC
S
T K
E
R
MA
AC
S
T K
E
R
P
MN
A A
S
T C
E K
R
Figure 65.
MS0625-J-01
2007/06
- 82 -
[AK4648]
SDA
SCL
S
P
start condition
stop condition
Figure 66.
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 67. I2C
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 68. I2C
MS0625-J-01
2007/06
- 83 -
[AK4648]
■
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Lch Input Volume Control
Lch Digital Volume Control
ALC Mode Control 3
Rch Input Volume Control
Rch Digital Volume Control
Mode Control 3
Mode Control 4
Power Management 3
Digital Filter Select
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
Power Management 4
Mode Control 5
Lineout Mixing Select
HP Mixing Select
SPK Mixing Select
EQ Control 250Hz/100Hz
EQ Control 3.5kHz/1kHz
EQ Control 10kHz
Note 65. PDN pin
Note 66. “0”
D7
D6
PMSPR
PMVCM
HPZ
SPPSN
LOVL
PLL3
PS1
DVTM
0
REF7
IVL7
DVL7
RGAIN1
IVR7
DVR7
0
HPG3
INR1
GN1
F3A7
F3AS
F3B7
0
EQA7
EQA15
EQB7
0
EQC7
EQC15
F1A7
F1AS
F1B7
0
HPMTN
MINS
LOPS
PLL2
PS0
WTM2
0
REF6
IVL6
DVL6
LMTH1
IVR6
DVR6
LOOP
HPG2
INL1
GN0
F3A6
0
F3B6
0
EQA6
EQA14
EQB6
0
EQC6
EQC14
F1A6
0
F1B6
0
PMAINR4
0
LOM
0
0
FBEQB3
FBEQD3
0
D5
PMMIN
PMHPL
DACS
PLL1
FS3
ZTM1
ALC
REF5
IVL5
DVL5
0
IVR5
DVR5
SMUTE
HPG1
0
0
F3A5
F3A13
F3B5
F3B13
EQA5
EQA13
EQB5
EQB13
EQC5
EQC13
F1A5
F1A13
F1B5
F1B13
PMHPR
DACL
SPKG1
PLL0
MSBS
ZTM0
ZELMN
REF4
IVL4
DVL4
0
IVR4
DVR4
DVOLC
HPG0
MDIF2
FIL1
F3A4
F3A12
F3B4
F3B12
EQA4
EQA12
EQB4
EQB12
EQC4
EQC12
F1A4
F1A12
F1B4
F1B12
D3
PMLO
M/S
0
SPKG0
BCKO
BCKP
WTM1
LMAT1
REF3
IVL3
DVL3
0
IVR3
DVR3
0
IVOLC
MDIF1
EQ
F3A3
F3A11
F3B3
F3B11
EQA3
EQA11
EQB3
EQB11
EQC3
EQC11
F1A3
F1A11
F1B3
F1B11
D2
PMDAC
PMHPC
PMMP
MINL
0
FS2
WTM0
LMAT0
REF2
IVL2
DVL2
0
IVR2
DVR2
FBEQ
HPM
INR0
FIL3
F3A2
F3A10
F3B2
F3B10
EQA2
EQA10
EQB2
EQB10
EQC2
EQC10
F1A2
F1A10
F1B2
F1B10
D1
0
MCKO
0
SPKG2
DIF1
FS1
RFST1
RGAIN0
REF1
IVL1
DVL1
VBAT
IVR1
DVR1
DEM1
MINH
INL0
0
F3A1
F3A9
F3B1
F3B9
EQA1
EQA9
EQB1
EQB9
EQC1
EQC9
F1A1
F1A9
F1B1
F1B9
0
DIF0
FS0
RFST0
LMTH0
REF0
IVL0
DVL0
0
IVR0
DVR0
DEM0
DACH
PMADR
0
F3A0
F3A8
F3B0
F3B8
EQA0
EQA8
EQB0
EQB8
EQC0
EQC8
F1A0
F1A8
F1B0
F1B8
PMAINL4
PMAINR3
PMAINL3
PMAINR2
PMAINL2
PMMICR
PMMICL
SPKMN
LOM3
HPM3
0
FBEQB2
FBEQD2
0
MICR3
RINR4
RINH4
RINS4
FBEQB1
FBEQD1
0
MICL3
LINL4
LINH4
LINS4
FBEQB0
FBEQD0
0
L4DIF
RINR3
RINH3
RINS3
FBEQA3
FBEQC3
FBEQE3
MIX
LINL3
LINH3
LINS3
FBEQA2
FBEQC2
FBEQE2
AIN3
RINR2
RINH2
RINS2
FBEQA1
FBEQC1
FBEQE1
LODIF
LINL2
LINH2
LINS2
FBEQA0
FBEQC0
FBEQE0
MGAIN1
D4
PMSPL
D0
PMADL
PMPLL
MGAIN0
“L”
“1”
MS0625-J-01
2007/06
- 84 -
[AK4648]
■
Addr
00H
Register Name
Power Management 1
R/W
Default
D7
PMSPR
R/W
0
PMADL: MIC-Amp Lch, ADC Lch
0: Power down (default)
1: Power up
PMADR bit
PMADL
D6
PMVCM
R/W
0
“0”
D5
PMMIN
R/W
0
D4
PMSPL
R/W
0
D3
PMLO
R/W
0
D2
PMDAC
R/W
0
“1”
D1
0
RD
0
D0
PMADL
R/W
0
(1059/[email protected])
ADC
PMDAC: DAC
0: Power down (default)
1: Power up
PMLO:
0: Power down (default)
1: Power up
PMSPL: Lch
0: Power down (default)
1: Power up
PMMIN:
0: Power down (default)
1: Power up
PMMIN or PMAINL3 bit = “1”
PMVCM: VCOM
0: Power down (default)
1: Power up
PMVCM bit “1”
00H, 01H, 02H, 10H, 20H
“0”
PMVCM bit
MCKO bit “0”
PMSPR: Rch
0: Power down (default)
1: Power up
ON/OFF (“1”/“0”)
PDN pin “L”
00H, 01H, 02H, 10H, 20H
MCKO bit “0”
ADC DAC
ADC
MS0625-J-01
DAC
2007/06
- 85 -
[AK4648]
Addr
01H
Register Name
Power Management 2
R/W
Default
D7
HPZ
R/W
0
D6
HPMTN
R/W
0
D5
PMHPL
R/W
0
D4
PMHPR
R/W
0
D3
M/S
R/W
0
D2
PMHPC
R/W
0
D1
MCKO
R/W
0
D0
PMPLL
R/W
0
PMPLL: PLL
0: EXT Mode and Power Down (default)
1: PLL Mode and Power up
MCKO: MCKO
0: Disable: MCKO pin = “L” (default)
1: Enable: Output frequency is selected by PS1-0 bits.
PMHPC:
0: Power down (default)
1: Power up
M/S: Master / Slave Mode
0: Slave Mode (default)
1: Master Mode
PMHPR: Rch
0: Power down (default)
1: Power up
PMHPL: Lch
0: Power down (default)
1: Power up
HPMTN:
0: Mute (default)
1: Normal operation
HPZ: HP-Amp
0:
(default)
1: 200kΩ(typ.)
Lch or Rch HP-Amp
MS0625-J-01
2007/06
- 86 -
[AK4648]
Addr
02H
Register Name
Signal Select 1
R/W
Default
MGAIN1-0:
MGAIN1 bit 03H D5 bit
D7
SPPSN
R/W
0
D6
MINS
R/W
0
D5
DACS
R/W
0
D4
DACL
R/W
0
D3
0
RD
0
D2
PMMP
R/W
0
D1
0
RD
0
D0
MGAIN0
R/W
1
(Table 22)
PMMP: MPWR pin
0: Power down: Hi-Z (default)
1: Power up
DACL: DAC
0: OFF (default)
1: ON
PMLO bit = “1”
PMLO bit = “0”
LOUT, ROUT pins VSS1
DACS: DAC
0: OFF (default)
1: ON
“1” DAC
MINS: MIN pin
0: OFF (default)
1: ON
“1” MIN pin
SPPSN:
0: Power Save Mode (default)
1: Normal Operation
“0”
pin HVDD/2
SPLP/SPRP pin Hi-Z SPLN/SPRN
PMSPLor PMSPR bit =“1”
MS0625-J-01
2007/06
- 87 -
[AK4648]
Addr
03H
Register Name
Signal Select 2
R/W
Default
D7
LOVL
R/W
0
D6
LOPS
R/W
0
D5
MGAIN1
R/W
0
D4
SPKG1
R/W
0
D3
SPKG
R/W
0
D2
MINL
R/W
0
D1
SPKG2
R/W
0
D0
0
RD
0
MIN
MINL:
0: OFF (default)
1: ON
PMLO bit = “1”
PMLO bit = “0”
LOUT, ROUT pins VSS1
(Table 65)
SPKG2-0:
(Table 22)
MGAIN1:
LOPS:
0: Normal Operation (default)
1: Power Save Mode
/
LOVL:
0: 0dB/+6dB (default)
1: +2dB/+8dB
Addr
04H
Register Name
Mode Control 1
R/W
Default
DIF1-0:
Default: “10” (
BCKO:
(Table 55, Table 57)
D7
PLL3
R/W
0
D6
PLL2
R/W
0
D5
PLL1
R/W
0
D4
PLL0
R/W
0
D3
BCKO
R/W
0
D2
0
RD
0
D1
DIF1
R/W
1
D0
DIF0
R/W
0
(Table 17)
)
BICK
PLL3-0: PLL
Default: “0000” (LRCK pin)
(Table 11)
(Table 5)
MS0625-J-01
2007/06
- 88 -
[AK4648]
Addr
05H
Register Name
Mode Control 2
R/W
Default
D7
PS1
R/W
0
D6
PS0
R/W
0
D5
FS3
R/W
0
(Table 6 and Table 7)
FS3-0:
MCKI
PLL
BCKP: DSP Mode
“0”: “↑” SDTO
“1”: “↓” SDTO
EXT
D3
BCKP
R/W
0
D2
FS2
R/W
0
D1
FS1
R/W
0
D0
FS0
R/W
0
D1
RFST1
R/W
0
D0
RFST0
R/W
0
(Table 12)
MCKI
BICK
(Table 18)
, “↓” SDTI
(default)
, “↑” SDTI
LRCK
MSBS: DSP Mode
“0”: LRCK “↑”
“1”: LRCK “↑”
PS1-0: MCKO
Default: “00” (256fs)
Addr
06H
D4
MSBS
R/W
0
Register Name
Timer Select
R/W
Default
(Table 18)
BICK
BICK 1
(default)
(Table 10)
D7
DVTM
R/W
0
D6
WTM2
R/W
0
D5
ZTM1
R/W
0
D4
ZTM0
R/W
0
D3
WTM1
R/W
0
D2
WTM0
R/W
0
(Table 33)
RFST1-0: ALC
Default: “00”(4 )
(Table 30)
WTM2-0: ALC
ALC
“000” (128/fs)
(Table 29)
ZTM1-0: ALC
ALC
“00” (128/fs)
DVTM: Digital Volume
0: 1061/fs (default)
1: 256/fs
DVL7-0, DVR7-0 bits
00H
MS0625-J-01
FFH
2007/06
- 89 -
[AK4648]
Addr
07H
Register Name
ALC Mode Control 1
R/W
Default
D7
0
RD
0
LMTH1-0: ALC
Default: “00”
LMTH1 bit 0BH D6 bit
RGAIN1-0: ALC
Default: “00”
RGAIN1 bit 0BH D7 bit
LMAT1-0: ALC
Default: “00”
ATT
D6
0
RD
0
D5
ALC
R/W
0
D4
ZELMN
R/W
0
D3
LMAT1
R/W
0
/
D2
LMAT0
R/W
0
D1
R/W
0
D0
LMTH0
R/W
0
D2
REF2
R/W
0
D1
REF1
R/W
0
D0
REF0
R/W
1
D2
IVL2
IVR2
R/W
0
D1
IVL1
IVR1
R/W
0
D0
IVL0
IVR0
R/W
1
D2
DVL2
DVR2
R/W
0
D1
DVL1
DVR1
R/W
0
D0
DVL0
DVR0
R/W
0
RGAIN0
(Table 27)
(Table 31)
(Table 28)
ZELMN: ALC
0: Enable (default)
1: Disable
ALC: ALC
0: ALC Disable (default)
1: ALC Enable
Addr
08H
Register Name
ALC Mode Control 2
R/W
Default
D7
REF7
R/W
1
D6
REF6
R/W
1
Register Name
Lch Input Volume Control
Rch Input Volume Control
R/W
Default
D7
IVL7
IVR7
R/W
1
Register Name
Lch Digital Volume Control
Rch Digital Volume Control
R/W
Default
DVL7-0, DVR7-0:
Default: “18H” (0dB)
D3
REF3
R/W
0
D6
IVL6
IVR6
R/W
1
D5
IVL5
IVR5
R/W
1
D4
IVL4
IVR4
R/W
0
D3
IVL3
IVR3
R/W
0
; 0.375dB step, 242 Level (Table 35)
IVL7-0, IVR7-0:
Default: “E1H” (+30.0dB)
Addr
0AH
0DH
D4
REF4
R/W
0
0.375dB step, 242 Level (Table 32)
REF7-0: ALC
Default: “E1H” (+30.0dB)
Addr
09H
0CH
D5
REF5
R/W
1
D7
DVL7
DVR7
R/W
0
D6
DVL6
DVR6
R/W
0
D5
DVL5
DVR5
R/W
0
D4
DVL4
DVR4
R/W
1
D3
DVL3
DVR3
R/W
1
(Table 38)
MS0625-J-01
2007/06
- 90 -
[AK4648]
Addr
0BH
Register Name
ALC Mode Control 3
R/W
Default
D7
RGAIN1
R/W
0
D6
LMTH1
R/W
0
VBAT:
0: 0.5 x HVDD (default)
1: 0.64 x AVDD
DEM1-0:
Default: “01” (OFF)
D3
0
RD
0
/
D2
0
RD
0
D1
VBAT
R/W
0
D0
0
RD
0
D1
DEM1
R/W
0
D0
DEM0
R/W
1
(Table 27)
(Table 31)
RGAIN1: ALC
Register Name
Mode Control 3
R/W
Default
D4
0
RD
0
(Table 62)
LMTH1: ALC
Addr
0EH
D5
0
RD
0
D7
0
RD
0
D6
LOOP
R/W
0
D5
SMUTE
R/W
0
D4
DVOLC
R/W
1
D3
0
RD
0
D2
FBEQ
R/W
0
(Table 36)
FBEQ: 5-Band Equalizer
0: Disable (default)
1: Enable
DVOLC:
0: Independent
1: Dependent (default)
DVOLC bit = “1”
DVR7-0 bit DVL7-0 bit
DVL7-0 bit
SMUTE:
0: Normal Operation (default)
1: DAC outputs soft-muted
LOOP:
0: SDTI → DAC (default)
1: SDTO → DAC
MS0625-J-01
2007/06
- 91 -
[AK4648]
Addr
0FH
Register Name
Mode Control 4
R/W
Default
D7
HPG3
R/W
1
D6
D5
D4
HPG2
HPG1
HPG0
R/W
0
R/W
1
R/W
1
D3
IVOLC
R/W
1
D2
HPM
R/W
0
D1
MINH
R/W
0
D0
DACH
R/W
0
DACH: DAC
0: OFF (default)
1: ON
MINH: MIN pin
0: OFF (default)
1: ON
HPM:
0:
1:
(default)
HPM bit = “1”
DAC
IVOLC: IVOL
0: Independent
1: Dependent (default)
IVOLC bit = “1”
(L+R)/2
IVL7-0 bit
IVOL
IVR7-0 bit IVL7-0 bit
HPG3-0:
Default: 0dB (Table 58)
Addr
10H
Register Name
Power Management 3
R/W
Default
D7
INR1
R/W
0
D6
INL1
R/W
0
D5
0
RD
0
D4
MDIF2
R/W
0
D3
MDIF1
R/W
0
D2
INR0
R/W
0
D1
INL0
R/W
0
D0
PMADR
R/W
0
PMADR: MIC-Amp Rch, ADC Rch
0: Power down (default)
1: Power up
INL1-0: ADC Lch
Default: 00 (LIN1 pin)
(Table 20)
INR1-0: ADC Rch
Default: 00 (RIN1 pin)
(Table 20)
MDIF1:
0:
1:
MDIF2:
0:
1:
/
1
(LIN1/RIN1 pin: Default)
(IN1+/IN1− pin)
Pin # D7 #F5
/
2
(LIN2/RIN2 pin: Default)
(IN2+/IN2− pin)
Pin#C5 #B6
MS0625-J-01
2007/06
- 92 -
[AK4648]
Addr
11H
Register Name
Digital Filter Select
R/W
Default
GN1-0: Gain
Default: “00” (0dB)
FIL3:
0:
1:
D7
GN1
R/W
0
D6
GN0
R/W
0
D5
0
RD
0
D2
FIL3
R/W
0
D1
0
RD
0
D0
0
RD
0
FIL3
(Default)
FIL3 bit = “0”
FIL3
(default)
EQ bit = “1”
EQ
FIL1:
0:
1:
D3
EQ
R/W
0
(Table 25)
FIL3 bit = “1”
F3A13-0, F3B13-0 bit
OFF(MUTE)
EQ:
0:
1:
D4
FIL1
R/W
0
EQA15-0, EQB13-0, EQC15-0 bit
(0dB)
EQ bit = “0”
FIL1
(default)
FIL1 bit = “1”
F1A13-0, F1B13-0 bit
FIL1 bit = “0”
FIL1
(0dB)
MS0625-J-01
2007/06
- 93 -
[AK4648]
Addr
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Register Name
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
R/W
Default
D7
F3A7
F3AS
F3B7
0
EQA7
EQA15
EQB7
0
EQC7
EQC15
F1A7
F1AS
F1B7
0
R/W
0
F3A13-0, F3B13-0:
Default: “0000H”
F3AS:
0: HPF (default)
1: LPF
D6
F3A6
0
F3B6
0
EQA6
EQA14
EQB6
0
EQC6
EQC14
F1A6
0
F1B6
0
R/W
0
FIL3
D5
F3A5
F3A13
F3B5
F3B13
EQA5
EQA13
EQB5
EQB13
EQC5
EQC13
F1A5
F1A13
F1B5
F1B13
R/W
0
D3
F3A3
F3A11
F3B3
F3B11
EQA3
EQA11
EQB3
EQB11
EQC3
EQC11
F1A3
F1A11
F1B3
F1B11
R/W
0
D2
F3A2
F3A10
F3B2
F3B10
EQA2
EQA10
EQB2
EQB10
EQC2
EQC10
F1A2
F1A10
F1B2
F1B10
R/W
0
D1
F3A1
F3A9
F3B1
F3B9
EQA1
EQA9
EQB1
EQB9
EQC1
EQC9
F1A1
F1A9
F1B1
F1B9
R/W
0
D0
F3A0
F3A8
F3B0
F3B8
EQA0
EQA8
EQB0
EQB8
EQC0
EQC8
F1A0
F1A8
F1B0
F1B8
R/W
0
(14bit x 2)
FIL3
EQA15-0, EQB13-0, EQC15-C0:
Default: “0000H”
F1A13-0, F1B13-B0:
Default: “0000H”
F1AS:
0: HPF (default)
1: LPF
D4
F3A4
F3A12
F3B4
F3B12
EQA4
EQA12
EQB4
EQB12
EQC4
EQC12
F1A4
F1A12
F1B4
F1B12
R/W
0
(14bit x 2 + 16bit x 1)
FIL1
(14bit x 2)
FIL1
MS0625-J-01
2007/06
- 94 -
[AK4648]
Addr
20H
Register Name
Power Management 4
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
PMAINR4
PMAINL4
PMAINR3
PMAINL3
PMAINR2
PMAINL2
PMMICR
PMMICL
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PMMICL: MIC-Amp Lch
0: Power down (default)
1: Power up
PMMICR: MIC-Amp Rch
0: Power down (default)
1: Power up
PMAINL2: LIN2
0: Power down (default)
1: Power up
PMAINR2: RIN2
0: Power down (default)
1: Power up
PMAINL3: LIN3
0: Power down (default)
1: Power up
PMMIN or PMAINL3 bit = “1”
PMAINR3: RIN3
0: Power down (default)
1: Power up
PMAINL4: LIN4
0: Power down (default)
1: Power up
PMAINR4: RIN4
0: Power down (default)
1: Power up
MS0625-J-01
2007/06
- 95 -
[AK4648]
Addr
21H
Register Name
Mode Control 5
R/W
Default
D7
0
RD
0
LODIF:
0:
1:
AIN3:
0:
1:
MIX:
0:
1:
L4DIF:
0:
1:
D6
D5
SPKMN MICR3
R/W
R/W
0
0
D4
D3
D2
D1
D0
MICL3
R/W
0
L4DIF
R/W
0
MIX
R/W
0
AIN3
R/W
0
LODIF
R/W
0
(LOUT/ROUT pins) (default)
(LOP/LON pins)
(MIN pin) (default)
(LIN3/RIN3 pins): PLL
(default)
: (L+R)/2
: LIN4/RIN4 pins (default)
: IN4+/− pins
MICL3:
0: LIN3 pin
(default)
1: MIC-Amp Lch
MICR3:
0: RIN3 pin
(default)
1: MIC-Amp Rch
(Table 68)
SPKMN:
0: Mono SPK Mode or High Power Mono SPK Mode (default)
1: Stereo SPK Mode
MS0625-J-01
2007/06
- 96 -
[AK4648]
Addr
22H
Register Name
Lineout Mixing Select
R/W
Default
D7
LOM
R/W
0
D6
LOM3
R/W
0
D5
RINR4
R/W
0
D4
LINL4
R/W
0
D3
RINR3
R/W
0
D2
LINL3
R/W
0
D1
RINR2
R/W
0
LINL2: LIN2
0: OFF (default)
1: ON
(MIC-Amp
)
RINR2: RIN2
0: OFF (default)
1: ON
(MIC-Amp
)
LINL4: LIN4
0: OFF (default)
1: ON
(MIC-Amp
)
RINR4: RIN4
0: OFF (default)
1: ON
(MIC-Amp
)
D0
LINL2
R/W
0
LINL3: LIN3 (or MIC-Amp Lch)
0: OFF (default)
1: ON
RINR3: RIN3 (or MIC-Amp Rch)
0: OFF (default)
1: ON
LOM3: MIC-Amp (or LIN3/RIN3)
0: Stereo Mixing (default)
1: Mono Mixing
LOM: DAC
0: Stereo Mixing (default)
1: Mono Mixing
MS0625-J-01
2007/06
- 97 -
[AK4648]
Addr
23H
Register Name
HP Mixing Select
R/W
Default
D7
0
RD
0
D6
HPM3
R/W
0
D5
RINH4
R/W
0
D4
LINH4
R/W
0
D3
RINH3
R/W
0
D2
LINH3
R/W
0
D1
RINH2
R/W
0
LINH2: LIN2
0: OFF (default)
1: ON
(MIC-Amp
)
RINH2: RIN2
0: OFF (default)
1: ON
(MIC-Amp
)
LINH4: LIN4
0: OFF (default)
1: ON
(MIC-Amp
)
RINH4: RIN4
0: OFF (default)
1: ON
(MIC-Amp
)
D0
LINH2
R/W
0
LINH3: LIN3 (or MIC-Amp Lch)
0: OFF (default)
1: ON
RINH3: RIN3 (or MIC-Amp Rch)
0: OFF (default)
1: ON
HPM3: MIC-Amp (or LIN3/RIN3)
0: Stereo Mixing (default)
1: Mono Mixing
MS0625-J-01
2007/06
- 98 -
[AK4648]
Addr
24H
Register Name
SPK Mixing Select
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
RINS4
R/W
0
D4
LINS4
R/W
0
D3
RINS3
R/W
0
D2
LINS3
R/W
0
D1
RINS2
R/W
0
D0
LINS2
R/W
0
LINS2: LIN2 pin
0: OFF (default)
1: ON
RINS2: RIN2 pin
0: OFF (default)
1: ON
LINS3: LIN3 pin
0: OFF (default)
1: ON
RINS3: RIN3 pin
0: OFF (default)
1: ON
LINS4: LIN4 pin
0: OFF (default)
1: ON
RINS4: RIN4 pin
0: OFF (default)
1: ON
Addr
25H
26H
Register Name
D7
D6
D5
EQ Control of 250Hz/100Hz FBEQB3 FBEQB2 FBEQB1
EQ Control of 3.5kHz/1kHz FBEQD3 FBEQD2 FBEQD1
R/W
R/W
R/W
R/W
Default
1
0
0
Addr
27H
Register Name
EQ Control of 10kHz
D4
FBEQB0
FBEQD0
R/W
0
D3
D2
D1
FBEQA3 FBEQA2 FBEQA1
FBEQC3 FBEQC2 FBEQC1
R/W
R/W
R/W
1
0
0
D0
FBEQA0
FBEQC0
R/W
0
D0
FBEQE0
D7
0
D6
0
D5
0
D4
0
D3
FBEQE3
R/W
RD
RD
RD
RD
R/W
R/W
R/W
R/W
Default
0
0
0
0
1
0
0
0
5-Band Equalizer Boost
* FBEQ bit = “1”
FBEQA3-0: Select the boost level of 100Hz (Default: 0dB)
FBEQB3-0: Select the boost level of 250Hz (Default: 0dB)
FBEQC3-0: Select the boost level of 1kHz (Default: 0dB)
FBEQD3-0: Select the boost level of 3.5kHz (Default: 0dB)
FBEQE3-0: Select the boost level of 10kHz (Default: 0dB)
MS0625-J-01
D2
D1
FBEQE2 FBEQE1
(Table 37)
2007/06
- 99 -
[AK4648]
Figure 69
Figure 70
Analog Supply
2.6 ∼ 3.6V
(AKD4648)
10u
Analog
Ground
Digital
Ground
2.2k
2.2k
2.2k
2.2k
10
C
Internal MIC
R
2.2u
External MIC
0.1u
0.1u
Line In
CAD0
NC
VCOC
SCL
SDTI
NC
NC
RIN1
LRCK
NC
NC
SDA
BICK
TEST
VCOM
AVDD
LIN4
RIN2
MIN
VSS1
ROUT
LOUT
LIN2
SPRP
SPRN
RIN4
LIN1
MPWR
μP
Mono In
220
1u
220
VSS2
0.1u
Analog Supply
2.6 ∼ 5.0V
1u
20k
20k
Line out
10u
HPL
DVDD
SDTO
MCKO
CPU
HVDD
SPLP
HVCM
HPR
PDN
TVDD
TVDD
NC
SPLN
VSS2
MUTET
VSS3
MCKI
NC
Stereo Speaker
1u
0.1u
0.1u
Digital
1.6 ∼ 3.6V
Top View
Headphone
(See Figure 51 and Figure 53)
:
- AK4648 VSS1, VSS2, VSS3
- EXT
(PMPLL bit = “0”)
- PLL
(PMPLL bit = “1”)
-
- AVDD
10Ω
Figure 69.
VCOC/RIN3 pin
Cp Rp Table 5
M/S bit “1”
AK4648 LRCK, BICK pin
AK4648 LRCK, BICK pin 100kΩ
0.1μF
DVDD
(AIN3 bit = “0”, CAD0 = “0”, MIC Input, Stereo SPK Mode)
MS0625-J-01
2007/06
- 100 -
[AK4648]
Analog Supply
2.6 ∼ 3.6V
10u
Analog
Ground
10
Digital
Ground
2.2u
Line In
0.1u
TEST
VCOM
0.1u
AVDD
LIN1
MPWR
CAD0
NC
μP
220
1u
LIN4
RIN2
LIN3
VSS1
RIN3
SCL
SDTI
ROUT
LOUT
LIN2
NC
NC
RIN1
LRCK
SPRP
SPRN
RIN4
NC
NC
SDA
BICK
220
1u
VSS2
0.1u
Analog Supply
2.6 ∼ 5.0V
20k
20k
Line out
10u
HPL
DVDD
SDTO
MCKO
CPU
HVDD
SPLP
HVCM
HPR
PDN
TVDD
TVDD
NC
SPLN
VSS2
MUTET
VSS3
MCKI
NC
0.1u
1u
Mono Speaker
0.1u
Digital
1.6 ∼ 3.6V
Top View
Headphone
(See Figure 51 and Figure 53)
:
- AK4648 VSS1, VSS2, VSS3
- AIN3 bit = “1”
PLL
-
- AVDD
10Ω
(AIN3 bit = “1”: PLL
M/S bit
“1”
AK4648 LRCK, BICK pin
AK4648 LRCK, BICK pin 100kΩ
0.1μF
DVDD
Figure 70.
, CAD0 = “0”,
MS0625-J-01
, High Power Mono SPK Mode)
2007/06
- 101 -
[AK4648]
1.
AVDD, DVDD, TVDD, HVDD
AVDD, DVDD, TVDD, HVDD
PDN pin = “L”
PDN pin “H”
1)
PDN pin = “L”
PDN pin = “L”
150ns
PDN pin = “H”
HVDD
TVDD
DVDD
TVDD
DVDD
DVDD
2)
PDN pin = “L”
HVDD
DVDD
VSS1, VSS2, VSS3
PC
2.
2.2μF
VCOM
0.1μF
VSS1
VCOM pin
VCOM pin
3.
MIN
(0.45 x AVDD)
0.06 x AVDD Vpp(typ.)@MGAIN1-0 bits = “01”, 0.03 x AVDD
Vpp(typ.)@MGAIN1-0 bits = “10”, 0.015 x AVDD Vpp(typ.)@MGAIN1-0 bits = “11”
0.6 x AVDD
Vpp(typ.)@MGAIN1-0 bits = “00”
MIN
(0.45 x AVDD)
0.6 x AVDD Vpp(typ.)
DC
fc=1/(2πRC)
AK4648 VSS1
AVDD
4.
DAC
8000H(@16bit)
2’s
0000H(@16bit)
7FFFH(@16bit)
VCOM
VCOM
0.45 x AVDD (typ.)
HVDD/2
MS0625-J-01
2007/06
- 102 -
[AK4648]
■
DAC Power-up
ADC
1. PLL
Example:
Power Supply
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
(3)
PMVCM bit
(Addr:00H, D6)
(4)
(1) Power Supply & PDN pin = “L” Æ “H”
MCKO bit
(Addr:01H, D1)
PMPLL bit
(2)Addr:01H, Data:08H
Addr:04H, Data:4AH
Addr:05H, Data:27H
(Addr:01H, D0)
(5)
MCKI pin
Input
M/S bit
(3)Addr:00H, Data:40H
(Addr:01H, D3)
40msec(max)
(6)
BICK pin
LRCK pin
Output
(4)Addr:01H, Data:0BH
Output
MCKO, BICK and LRCK output
40msec(max)
(8)
MCKO pin
(7)
Figure 71. Clock Set Up Sequence (1)
<
>
PDN pin “L” Æ “H”
(1)
AK4648
150ns
“L”
(
)
(2)
(3) VCOM
DIF1-0, PLL3-0, FS3-0, BCKO, M/S bits
: PMVCM bit = “0” Æ “1”
VCOM
(4) MCKO
: MCKO bit = “1”
MCKO
: MCKO bit = “0”
(5) PMPLL bit “0” Æ “1”
MCKI pin
40ms(max.)
(6) PLL
BICK, LRCK
(7) MCKO bit = “1”
MCKO pin
(8) MCKO bit = “1”
PLL
MCKO pin
MS0625-J-01
PLL
PLL
2007/06
- 103 -
[AK4648]
2. PLL
(LRCK or BICK pin)
Example:
Power Supply
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
(3)
PMVCM bit
(Addr:00H, D6)
PMPLL bit
(2) Addr:04H, Data:32H
Addr:05H, Data:27H
(Addr:01H, D0)
LRCK pin
BICK pin
Input
(3) Addr:00H, Data:40H
(4)
Internal Clock
(4) Addr:01H, Data:01H
(5)
Figure 72. Clock Set Up Sequence (2)
<
>
PDN pin “L” Æ “H”
(1)
AK4648
150ns
“L”
(
(2)
(3) VCOM
(4) PMPLL bit
)
DIF1-0, FS3-0, PLL3-0 bits
: PMVCM bit = “0” Æ “1”
VCOM
“0” Æ “1”
PLL
(LRCK or BICK pin)
PLL
LRCK PLL
2ms(max.)
PLL
160ms(max.), BICK PLL
(5) PLL
MS0625-J-01
2007/06
- 104 -
[AK4648]
3. PLL
(MCKI pin)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(3)
(2)Addr:04H, Data:4AH
Addr:05H, Data:27H
PMVCM bit
(Addr:00H, D6)
(4)
MCKO bit
(Addr:01H, D1)
(3)Addr:00H, Data:40H
PMPLL bit
(Addr:01H, D0)
(5)
MCKI pin
(4)Addr:01H, Data:03H
Input
40msec(max)
(6)
MCKO pin
MCKO output start
Output
(7)
(8)
BICK pin
LRCK pin
BICK and LRCK input start
Input
Figure 73. Clock Set Up Sequence (3)
<
>
PDN pin “L” Æ “H”
(1)
AK4648
150ns
“L”
(
(2)
(3) VCOM
(4) MCKO
(5) PMPLL bit
PLL
(6) PLL
(7)
(8) MCKO
)
DIF1-0, PLL3-0, FS3-0 bits
PMVCM bit = “0” Æ “1”
VCOM
: MCKO bit = “1”
“0” Æ “1”
MCKI pin
40ms(max.)
MCKO pin
MCKO pin
BICK, LRCK
MS0625-J-01
PLL
2007/06
- 105 -
[AK4648]
4.
(
)
Example:
Audio I/F Format: MSB justified (ADC and DAC)
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(2) Addr:04H, Data:02H
Addr:05H, Data:00H
(3)
PMVCM bit
(Addr:00H, D6)
(4)
MCKI pin
Input
(3) Addr:00H, Data:40H
(4)
LRCK pin
BICK pin
Input
MCKI, BICK and LRCK input
Figure 74. Clock Set Up Sequence (4)
<
>
PDN pin “L” Æ “H”
(1)
AK4648
150ns
“L”
(
)
DIF1-0, FS1-0 bits
PMVCM bit = “0” Æ “1”
VCOM
(4) MCKI, LRCK, BICK
(2)
(3) VCOM
MS0625-J-01
2007/06
- 106 -
[AK4648]
5.
(
)
Example:
Audio I/F Format: MSB justified (ADC and DAC)
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
(1) Power Supply & PDN pin = “L” Æ “H”
Power Supply
(1)
PDN pin
(2) MCKI input
(4)
PMVCM bit
(Addr:00H, D6)
(3) Addr:04H, Data:02H
Addr:05H, Data:00H
Addr:01H, Data:08H
(2)
MCKI pin
Input
(3)
M/S bit
BICK and LRCK output
(Addr:01H, D3)
LRCK pin
BICK pin
Output
(4) Addr:00H, Data:40H
Figure 75. Clock Set Up Sequence (5)
<
>
PDN pin “L” Æ “H”
(1)
AK4648
150ns
“L”
(
(2) MCKI
(3) DIF1-0, FS1-0 bits
(4) VCOM
)
M/S bit “1”
PMVCM bit = “0” Æ “1”
VCOM
MS0625-J-01
LRCK
BICK
2007/06
- 107 -
[AK4648]
■
Example:
FS3-0 bits
(Addr:05H, D5&D2-0)
0,000
PLL Master Mode
Audio I/F Format:MSB justified (ADC & DAC)
Sampling Frequency:44.1kHz
Pre MIC AMP:+20dB
MIC Power On
ALC setting:Refer to Table 34
ALC bit=“1”
1,111
(1)
MIC Control
(1) Addr:05H, Data:27H
001
(Addr:02H, D2-0)
101
(2) Addr:02H, Data:05H
(2)
ALC Control 1
00H
(Addr:06H)
3CH
(3) Addr:06H, Data:3CH
E1H
(4) Addr:08H, Data:E1H
(3)
ALC Control 2
E1H
(Addr:08H)
(4)
(5) Addr:0BH, Data:00H
ALC Control 3
00H
(Addr:0BH)
00H
(6) Addr:07H, Data:21H
(5)
ALC Control 4
07H
(Addr:07H)
21H
01H
(6)
ALC State
(9)
ALC Disable
ALC Enable
(7) Addr:00H, Data:41H
Addr:10H, Data:01H
ALC Disable
Recording
PMADL/R bits
(Addr:00H&10H, D0)
1059 / fs
(8)
(7)
ADC Internal
State
Power Down
(8) Addr:00H, Data:40H
Addr:10H, Data:00H
Initialize Normal State Power Down
(9) Addr:07H, Data:01H
Figure 76. MIC Input Recording Sequence
<
>
fs=44.1kHz
ALC
ALC
“Figure 35. ”
(1)
(FS3-0 bits)
PLL
PLL
(7)
ADC
(2)
(
02H)
(3) ALC Timer (
06H)
(4) ALC REF (
08H)
(5) LMTH1, RGAIN1 bits
(
0BH)
(6) LMTH0, RGAIN0, LMAT1-0, ALC bits
(
07H)
(7)
ADC
: PMADL = PMADR bits = “0” → “1”
ADC
1059/fs=24ms@fs=44.1kHz
ALC
(IVL/R7-0 bits)
(+30dB)
HPF
“1”
(8)
PMVCM bit =
60k(typ.)
PMMP bit = “1”
AC
4
ADC Power-up
ADC
: PMADL = PMADR bits = “1” → “0”
ADC
ALC Disable
ALC
(ALC bit = “0”)
ADC
(PMADL = PMADR bits = “0”)
PMADL = PMADR bits = “0”
(IVL/R7-0 bits)
(9) ALC Disable: ALC bit = “1” → “0”
MS0625-J-01
2007/06
- 108 -
[AK4648]
■
FS3-0 bits
(Addr:05H, D5&D2-0)
X,XXX
1,111
(1)
(14)
DACS bit
(Addr:02H, D5)
(2)
SPKG2-0 bits
(Addr:03H, D4-3, D1)
ALC Control 1
(Addr:06H)
ALC Control 2
(Addr:08H)
ALC Control 3
(Addr:0BH)
000
Example:
001
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: 0dB
ALC: Enable, Stereo SPKMode
(3)
XXH
3CH
(4)
(1) Addr:05H, Data:27H
XXH
C1H
(2) Addr:02H, Data:20H
(5)
XXH
00H
(3) Addr:03H, Data:08H
(6)
ALC bit
(Addr:07H, D5)
0
(4) Addr:06H, Data:3CH
X
(7)
(5) Addr:08H, Data:E1H
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
E1H
91H
(6) Addr:0BH, Data:00H
(8)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
18H
XXH
(7) Addr:07H, Data:20H
(9)
SPKMN bit
(Addr:21H, D6)
0
X
(8) Addr:09H & 0CH, Data:91H
(10)
(15)
PMDAC bit
(9) Addr:0AH & 0DH, Data:28H
(Addr:00H, D2)
(10) Addr:21H, Data:40H
PMMIN bit
(Addr:00H, D5)
(11)
(11) Addr:00H, Data:F4H
PMSPL/R bits
(Addr:00H, D7,D4)
(12) Addr:02H, Data:A0H
(12)
SPPSN bit
(Addr:02H, D7)
Playback
(13)
SPLP pin
SPRP pin
SPLN pin
SPRN pin
Hi-Z
Hi-Z
Normal Output
Hi-Z
HVDD/2 Normal Output HVDD/2
(13) Addr:02H, Data:20H
Hi-Z
(14) Addr:02H, Data:00H
(15) Addr:00H, Data:40H
Figure 77. Speaker-Amp Output Sequence
<
>
(1)
(FS3-0 bits)
PLL
PLL
(5) DAC
(2) DAC Æ SPK-Amp
: DACS bit = “0” Æ “1”
(3) SPK-Amp
: SPKG2-0 bits = “000” “001”
(4) ALC Timer (
06H)
(5) ALC REF (
08H)
(6) LMTH1, RGAIN1 bits
(
0BH)
(7) LMTH0, RGAIN0, LMAT1-0, ALC bits
(
07H)
PMADL bit = “1”
PMADR bit = “1”
DAC ALC
(8)
(
09H&0CH)
PMADL = PMADR bits = “0”
IVL7-0 = IVR7-0 bits = “91H”(0dB)
(9)
(
0AH&0DH)
DVOLC bit = “1”(default)
DVL7-0bits(0AH) Lch
Rch
DAC
Default (0dB)
(10)
: SPKMN bit: “0” Æ “1” (Stereo SPK Mode)
Mono SPK Mode & High Power Mono SPK Mode
SPKMN bit
MS0625-J-01
“0”
2007/06
- 109 -
[AK4648]
:
(11) DAC, MIN-Amp
a. Mono SPK Mode (SPLP/SPLN pin
)
: PMDAC = PMMIN = PMSPL bits = “0” → “1”
b. Stereo SPK Mode & High Power Mono SPK Mode
: PMDAC = PMMIN = PMSPL = PMSPR bits
= “0” → “1”
(1059/fs=24ms@fs=44.1kHz) DAC
2’s
“0”
DAC
(23/fs=0.5ms@fs=44.1kHz)
DAC
PMADL bit
PMADR bit “1”
DAC
ALC bit = “1”
(1059/fs = 24ms
@fs=44.1kHz) ALC
(ALC
IVL/R7-0 bits
)
ALC IVL/R7-0 bits
(12)
: SPPSN bit = “0” → “1”
Mono SPK Mode
Hi-Z
(13)
: SPPSN bit = “1” → “0”
(14) DAC Æ SPK-Amp
Disable: DACS bit = “1” Æ “0”
(15) DAC, MIN-Amp
: PMDAC = PMMIN = PMSPL = PMSPR bits = “1” → “0”
MS0625-J-01
2007/06
- 110 -
[AK4648]
■
Mono
Example:
Clocks can be stopped.
CLOCK
Stereo SPK Mode
SPKMN bit
0
(Addr:21H, D6)
X
(1) Addr:21H, Data:40H
(1)
PMMIN bit
(Addr:00H, D5)
(2)
(2) Addr:00H, Data:E0H
(6)
PMSPL/R bits
(Addr:00H, D7&D4)
(3) Addr:02H, Data:60H
DACS bit
(Addr:02H, D5)
X
0
(3)
(7)
MINS bit
(Addr:02H, D6)
(4) Addr:02H, Data:E0H
(4)
Mono Signal Output
SPPSN bit
(Addr:02H, D7)
(5)
SPLP pin
SPRP pin
SPLN pin
SPRN pin
Hi-Z
Hi-Z
Normal Output
HVDD/2
Normal Output
(5) Addr:02H, Data:60H
Hi-Z
HVDD/2
Hi-Z
(6) Addr:00H, Data:40H
(7) Addr:02H, Data:00H
Figure 78. “MIN-Amp Æ Speaker-Amp” Output Sequence
<
>
“MIN-Amp Æ SPK-Amp”
(1)
(2)
(3)
(4)
(5)
(6)
(7)
a. Mono SPK Mode & High Power Stereo SPK Mode
: SPKMN bit = “0”
b. Stereo SPK Mode: SPKMN bit = “1”
MIN-Amp
:
a. Mono SPK Mode (SPLP/SPLN pin
)
: PMMIN = PMSPL bits = “0” → “1”
b. Stereo SPK Mode & High Power Mono SPK Mode
: PMMIN = PMSPL = PMSPR bits = “0” →
“1”
DAC Æ SPK-Amp
Disable: DACS bit = “0”
MIN Æ SPK-Amp
Enable: MINS bit = “0” → “1”
: SPPSN bit = “0” → “1”
: SPPSN bit = “1” → “0”
MIN-Amp
: PMMIN = PMSPK bits = “1” → “0”
MIN Æ SPK-Amp
Disable: MINS bit = “1” → “0”
MS0625-J-01
2007/06
- 111 -
[AK4648]
■
FS3-0 bits
(Addr:05H, D5&D2-0)
HPG3-0 bits
(Addr:0FH, D7-4)
0,000
1,111
(1)
E x a m p le :
1011
P L L M a s te r M o d e
S a m p lin g F r e q u e n c y : 4 4 .1 k H z
D V O L C b it = “ 1 ” ( d e fa u lt)
D ig ita l V o lu m e L e v e l: − 8 d B , H P V o lu m e L e v e l: - 3 d B
5 b a n d E Q : E n a b le
D e -e m p h a s e s re s p o n s e : O F F
S o f t M u te T im e : 2 5 6 /fs , P s e u d o C a p -le s s M o d e
1010
(2)
DACH bit
(13)
(Addr:0FH, D0)
FBEQ bit
(Addr:0EH, D2)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
( 1 ) A d d r :0 5 H , D a t a :2 7 H
( 2 ) A d d r :0 F H , D a ta A 9 H
0
1
0
(3)
(12)
E1H
91H
( 3 ) A d d r :0 E H , D a t a 1 5 H
( 4 ) A d d r :0 9 H & 0 C H , D a ta 9 1 H
(4)
( 5 ) A d d r :0 A H & 0 D H , D a ta 2 8 H
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
18H
28H
( 6 ) A d d r :0 0 H , D a t a 6 4 H
(5)
PMDAC bit
( 7 ) A d d r :0 1 H , D a t a 3 D H
(Addr:00H, D2)
(6)
(11)
( 8 ) A d d r :0 1 H , D a t a 7 9 H
PMMIN bit
(Addr:00H, D5)
PMHPL/R/C bits
P la y b a c k
(7)
(10)
( 9 ) A d d r :0 1 H , D a t a 3 9 H
(Addr:01H, D5-4&D2)
( 1 0 ) A d d r :0 1 H , D a ta 0 9 H
HPMTN bit
(8)
(9)
(Addr:01H, D6)
HPL/R pins,
HVCM pin
( 1 1 ) A d d r :0 0 H , D a ta 4 0 H
Normal Output
( 1 2 ) A d d r :0 E H , D a ta 1 1 H
( 1 3 ) A d d r :0 F H , D a ta A 8 H
Figure 79. Headphone-Amp Output Sequence
<
>
(1)
(FS3-0 bits)
PLL
PLL
(5) DAC
(2) DAC Æ HP-Amp
: DACH bit = “0” → “1”
HP-Amp
(
: 0F, HPG3-0 bits)
(3) 5-band Equalizer ON (EQ Boost
Addr=25H-27H
): FBEQ bit = “0” Æ “1”
(4)
(
09H&0CH)
PMADL = PMADR bits = “0”
IVL7-0 = IVR7-0 bits = “91H”(0dB)
(5)
(
0AH&0DH)
DVOLC bit = “1”(default)
DVL7-0bits(0AH) Lch
Rch
DAC
Default (0dB)
(6) DAC
MIN-Amp
: PMDAC = PMMIN bits = “0” → “1”
(1059/fs=24ms@fs=44.1kHz) DAC
2’s
“0”
DAC
(25/fs =0.5ms@fs=44.1kHz)
DAC
PMADL bit
PMADR bit “1”
DAC
ALC bit = “1”
(1059/fs = 24ms
@fs=44.1kHz) ALC
(ALC
IVL/R7-0 bits
)
ALC IVL/R7-0 bits
(7)
a. Pseudo Cap-less Mode
: PMHPL = PMHPR = PMHPC bits = “0” → “1”
b. Single-ende Mode
: PMHPL=PMHPR bits = “0” Æ “1”
VSS2
(8)
: HPMTN bit = “0” → “1”
MUTET pin
HVDD
MUTET pin
C
= 1μF±30%, HVDD=3.6V
(0.8 x HVDD/2) τr =120ms(typ.), 210ms(max.)
Single-ended Mode
HVCM pin
VSS2
MS0625-J-01
2007/06
- 112 -
[AK4648]
(9)
MUTET pin
HVDD=3.6V
: HPMTN bit = “1” → “0”
HVDD
VSS2
260ms(max.)
MUTET pin
VSS2
C = 1μF±30%,
(10)
: PMHPL = PMHPR = PMHPC bits = “1” → “0”
(11) DAC
MIN-Amp
: PMDAC = PMMIN bits = “1” → “0”
(12) 5-band Equalizer OFF: FBEQ bit = “1” Æ “0”
(13) DAC Æ HP-Amp
Disable: DACH bit = “1” → “0”
MS0625-J-01
2007/06
- 113 -
[AK4648]
■
Example:
FS3-0 bits
(Addr:05H, D5&D2-0)
0,000
PLL, Master Mode
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: −8dB
LOVL=MINL bits = “0”
1,111
(1)
(1) Addr:05H, Data:27H
(10)
DACL bit
(2)
(2) Addr:02H, Data:10H
(Addr:02H, D4)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
E1H
(3) Addr:09H&0CH, Data:91H
91H
(3)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
(4) Addr:0AH&0DH, Data:28H
18H
28H
(5) Addr:03H, Data:40H
(4)
LOPS bit
(6) Addr:00H, Data:6CH
(Addr:03H, D6)
(7)
(5)
(8)
(11)
PMDAC bit
(Addr:00H, D2)
(7) Addr:03H, Data:00H
Playback
PMMIN bit
(8) Addr:03H, Data:40H
(Addr:00H, D5)
(6)
(9)
(9) Addr:00H, Data:40H
PMLO bit
(Addr:00H, D3)
>300 ms
(10) Addr:02H, Data:00H
LOUT pin
ROUT pin
>300 ms
Normal Output
(11) Addr:03H, Data:00H
Figure 80. Stereo Lineout Sequence
<
>
(1)
(FS3-0 bits)
PLL
(5) DAC
DAC Æ
: DACL bit = “0” Æ “1”
(
09H&0CH)
PMADL = PMADR bits = “0”
IVL7-0 = IVR7-0 bits = “91H”(0dB)
(
0AH&0DH)
DVOLC bit = “1”(default)
DVL7-0bits(0AH) Lch
Rch
DAC
Default (0dB)
: LOPS bit = “0” Æ “1”
DAC, MIN-Amp
: PMDAC = PMMIN = PMLO bits = “0” → “1”
(1059/fs=24ms@fs=44.1kHz) DAC
2’s
“0”
DAC
(25/fs=0.5ms@fs=44.1kHz)
DAC
PMADL bit
PMADR bit “1”
DAC
ALC bit = “1”
(1059/fs = 24ms
@fs=44.1kHz) ALC
(ALC
IVL/R7-0 bits
)
ALC IVL/R7-0 bits
PMLO bit = “1” LOUT, ROUT pins
C = 1μF, AVDD=3.3V
max. 300ms
: LOPS bit = “1” Æ “0”
LOUT, ROUT pins
LOUT, ROUT pins
PLL
(2)
(3)
(4)
(5)
(6)
(7)
: LOPS bit: “0” Æ “1”
: PMDAC = PMMIN = PMLO bits = “1” → “0”
C = 1μF, AVDD=3.3V
max. 300ms
(8)
(9) DAC, MIN-Amp
LOUT, ROUT pins
(10) DAC Æ
(11)
LOUT, ROUT pins
Disable: DACL bit = “1” Æ “0”
: LOPS bit = “1” Æ “0”
MS0625-J-01
2007/06
- 114 -
[AK4648]
■
DAC
ADC
1. PLL
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 8kHz
(1)
PMPLL bit
(Addr:01H, D0)
(2)
MCKO bit
"1" or "0"
(1) (2) Addr:01H, Data:08H
(Addr:01H, D1)
(3)
External MCKI
Input
(3) Stop an external MCKI
Figure 81. Clock Stopping Sequence (1)
<
>
(1) PLL
(2) MCKO
(3)
: PMPLL bit = “1” → “0”
: MCKO bit = “1” → “0”
PLL
2. PLL
(LRCK, BICK pin)
Example
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 8kHz
(1)
PMPLL bit
(Addr:01H, D0)
(2)
External BICK
Input
(1) Addr:01H, Data:00H
(2)
External LRCK
Input
(2) Stop the external clocks
Figure 82. Clock Stopping Sequence (2)
<
>
(1) PLL
(2)
3. PLL
: PMPLL bit = “1” → “0”
(MCKI pin)
Example
(1)
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: MCKI
BICK frequency: 64fs
Sampling Frequency: 8kHz
PMPLL bit
(Addr:01H, D0)
(1)
MCKO bit
(1) Addr:01H, Data:00H
(Addr:01H, D1)
(2)
External MCKI
Input
(2) Stop the external clocks
Figure 83. Clock Stopping Sequence (3)
<
>
(1) PLL
MCKO
(2)
: PMPLL bit = “1” → “0”
: MCKO bit = “1” → “0”
MS0625-J-01
2007/06
- 115 -
[AK4648]
4.
(1)
External MCKI
Input
Example
(1)
External BICK
Input
External LRCK
Input
Audio I/F Format :MSB justified(ADC & DAC)
Input MCKI frequency:1024fs
Sampling Frequency:8kHz
(1)
(1) Stop the external clocks
Figure 84. Clock Stopping Sequence (4)
<
>
(1)
5.
(1)
External MCKI
Input
Example
BICK
Output
"H" or "L"
LRCK
Output
"H" or "L"
Audio I/F Format :MSB justified(ADC & DAC)
Input MCKI frequency:1024fs
Sampling Frequency:8kHz
(1) Stop the external MCKI
Figure 85. Clock Stopping Sequence (5)
<
>
(1) MCKI
BICK
LRCK
“H”
“L”
■
VCOM
(typ. 1uA)
PMVCM bit = “0”
PDN pin = “L”
(typ.
1μA)
MS0625-J-01
2007/06
- 116 -
(0.38)
3.76 ± 0.05
0.50
7
6
6
0.50
7
XXXX
5
5
4
4
3
3
2
(0.33)
4648
3.66 ± 0.05
B
[AK4648]
2
1
B
C
Top View
D
E
F
G
G
F
E
D
C
B
φ 0.30 ± 0.05
0.25 ± 0.05
0.60 ± 0.02
1
A
A
A
φ 0.05 M S AB
Bottom View
S
0.08 S
MS0625-J-01
2007/06
- 117 -
[AK4648]
4648
XXXX
1
A
XXXX: Date code (4 digits)
Pin #A1 indication
Date (YY/MM/DD)
07/05/25
07/06/07
Revision
00
01
Reason
Page
1
15
MS0625-J-01
Contents
:
1.3W @ 8Ω, HVDD=5V, Stereo SPK &
Mono SPK Mode
Î 1.3W @ 8Ω, HVDD=5V, Mono SPK
Mode
1.0W @ 8Ω, HVDD=4.5V, Mono SPK
Mode
Speaker-Amp Characteristics:
S/(N+D), Po=1.3W: “Stereo SPK Mode”
2007/06
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[AK4648]
•
•
•
•
•
•
MS0625-J-01
2007/06
- 119 -