Real-Time Analog Computational Unit (ACU) AD538 FEATURES FUNCTIONAL BLOCK DIAGRAM IX VX D 25kΩ 100Ω LOG RATIO VZ 25kΩ 100Ω IZ A INTERNAL VOLTAGE REFERENCE +10V +2V VY IY 25kΩ AD538 LOG C ANTILOG I OUTPUT APPLICATIONS One- or two-quadrant multiply/divide Log ratio computation Squaring/square rooting Trigonometric function approximations Linearization via curve fitting Precision AGC Power functions B VO 00959-001 VO = VY(VZ/VX)m transfer function Wide dynamic range (denominator) −1000:1 Simultaneous multiplication and division Resistor-programmable powers and roots No external trims required Low input offsets <100 μV Low error ±0.25% of reading (100:1 range) Monolithic construction Real-time analog multiplication, division and exponentiation High accuracy analog division with a wide input dynamic range On board +2 V or +10 V scaling reference Voltage and current (summing) input modes Monolithic construction with lower cost and higher reliability than hybrid and modular circuits Figure 1. GENERAL DESCRIPTION The AD538 is a monolithic real-time computational circuit that provides precision analog multiplication, division, and exponentiation. The combination of low input and output offset voltages and excellent linearity results in accurate computation over an unusually wide input dynamic range. Laser wafer trimming makes multiplication and division with errors as low as 0.25% of reading possible, while typical output offsets of 100 μV or less add to the overall off-the-shelf performance level. Real-time analog signal processing is further enhanced by the 400 kHz bandwidth of the device. multiplication and division can be set using the on-chip +2 V or +10 V references, or controlled externally to provide simultaneous multiplication and division. Exponentiation with an m value from 0.2 to 5 can be implemented with the addition of one or two external resistors. The overall transfer function of the AD538 is VO = VY(VZ/VX)m. Programming a particular function is via pin strapping. No external components are required for one-quadrant (positive input) multiplication and division. Two-quadrant (bipolar numerator) division is possible with the use of external level shifting and scaling resistors. The desired scale factor for both The AD538 is available in two accuracy grades (A and B) over the industrial (−25°C to +85°C) temperature range and one grade (S) over the military (−55°C to +125°C) temperature range. The device is packaged in an 18-lead TO-118 hermetic side-brazed ceramic DIP. A-grade chips are also available. Direct log ratio computation is possible by using only the log ratio and output sections of the chip. Access to the multiple summing junctions adds further to the flexibility of the AD538. Finally, a wide power supply range of ±4.5 V to ±18 V allows operation from standard ±5 V, ±12 V and ±15 V supplies. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. 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AD538 TABLE OF CONTENTS Features .............................................................................................. 1 Stability Precautions ................................................................... 10 Applications ....................................................................................... 1 Using The Voltage References .................................................. 10 Functional Block Diagram .............................................................. 1 One-Quadrant Multiplication/Division .................................. 11 General Description ......................................................................... 1 Two-Quadrant Division ............................................................ 12 Revision History ............................................................................... 2 Log Ratio Operation .................................................................. 12 Specifications..................................................................................... 3 Analog Computation Of Powers And Roots .......................... 13 Absolute Maximum Ratings ............................................................ 5 Square Root Operation .............................................................. 13 ESD Caution .................................................................................. 5 Applications Information .............................................................. 15 Pin Configuration and Function Descriptions ............................. 6 Transducer Linearization .......................................................... 15 Typical Performance Characteristics ............................................. 7 ARC-Tangent Approximation .................................................. 15 Theory of Operation ........................................................................ 9 Outline Dimensions ....................................................................... 16 Re-Examination of Multiplier/Divider Accuracy .................... 9 Ordering Guide .......................................................................... 16 Functional Description .............................................................. 10 REVISION HISTORY 6/11—Rev. D to Rev. E Updated Format .................................................................. Universal Added Table 3.................................................................................... 6 Changes to Ordering Guide .......................................................... 11 5/10—Rev. C to Rev. D Updated Outline Dimensions ....................................................... 11 Changes to Ordering Guide .......................................................... 11 Rev. E | Page 2 of 16 AD538 SPECIFICATIONS VS = ±15 V, TA = 25°C, unless otherwise noted. Table 1. Parameter MULTIPLIER DIVIDER PERFORMANCE Nominal Transfer Function Test Conditions/ Comments 10 V ≥ VX, VY, VZ ≥ 0 400 µA ≥ IX, IY, IZ ≥ 0 Total Error Terms 100:1 Input Range 1 Min AD538AD Typ Max Min VO = VY(VZ/VX)m VO = 25 kΩ × IY(IZ/IX)m 100 mV ≤ VX ≤ 10 V 100 mV ≤ VY ≤ 10 V AD538BD Typ Max Min VO = VY(VZ/VX)m VO = 25 kΩ × IY(IZ/IX)m AD538SD Typ Max Unit VO = VY(VZ/VX)m VO = 25 kΩ × IY(IZ/IX)m ±0.5 ±200 ±1 ±500 ±0.25 ±100 ±0.5 ±250 ±0.5 ±200 ±1 ±500 % of Reading + µV ±1 ±450 ±1 ±2 ±750 ±2 ±0.5 ±350 ±0.5 ±1 ±500 ±1 ±1.25 ±750 ±1 ±2.5 ±1000 ±2 % of Reading + µV % of Reading + ±200 ±100 ±500 ±250 ±100 ±750 ±250 ±150 ±200 ±200 ±500 ±250 µV µV × (VY + VZ)/VX ±1 ±450 ±450 ±3 ±750 ±750 ±1 ±350 ±350 ±2 ±500 ±500 ±2 ±750 ±750 ±4 ±1000 ±1000 % of Reading + µV + µV × (VY + VZ)/VX 100 mV ≤ VZ ≤ 10 V VZ ≤ 10 VX, m = 1.0 TA = TMIN to TMAX Wide Dynamic Range 2 100 mV ≤ VX ≤ 10 V 100 mV ≤ VY ≤ 10 V 100 mV ≤ VZ ≤ 10 V VZ ≤ 10 VX, m = 1.0 TA = TMIN to TMAX Exponent (m) Range OUTPUT CHARACTERISTICS Offset Voltage Output Voltage Swing Output Current FREQUENCY RESPONSE Slew Rate Small Signal Bandwidth VOLTAGE REFERENCE Accuracy Additional Error Output Current Power Supply Rejection +2 V = VREF +10 V = VREF POWER SUPPLY Rated Operating Range 3 PSRR Quiescent Current TA = TMIN to TMAX VY = 0, VC = −600 mV TA = TMIN to TMAX RL = 2 kΩ 0.2 ±500 ±450 ±750 +11 10 1 ±4.5 V ≤ VS ≤ ±18 V ±13 V ≤ VS ≤ ±18 V RL = 2 kΩ 5 ±100 ±250 ±350 ±500 +11 10 0.2 ±50 ±30 5 300 200 600 500 1 ±15 ±15 ±20 2.5 ±25 ±30 300 200 600 500 1 ±15 0.5 ±18 0.1 4.5 7 ±4.5 ±200 ±500 µV ±750 ±1000 +11 µV V 10 mA 1.4 400 V/µs kHz ±25 ±30 2.5 ±50 ±50 mV mV mA 300 200 600 500 µV/V µV/V 0.5 ±18 0.1 V V %/V 4.5 7 mA ±15 0.5 ±18 0.1 4.5 7 Rev. E | Page 3 of 16 5 −11 1.4 400 ±25 ±20 2.5 ±4.5 5 −11 1.4 400 100 mV ≤ 10 VY, VZ, VX ≤ 10 V ±4.5 V<, VS < ±18 V VX = VY = VZ = 1 V VO = 1 V 0.2 ±200 −11 5 VREF = 10 V or 2 V TA = TMIN or TMAX VREF = 10 V to 2 V 5 ±4.5 AD538 Parameter TEMPERATURE RANGE Rated Storage Test Conditions/ Comments Min AD538AD Typ Max Min −25 −65 +85 +150 −25 −65 AD538BD Typ 1 Max Min AD538SD Typ Max +85 +150 −55 −65 +125 +150 Unit °C °C Over the 100 mV to 10 V operating range total error is the sum of a percent of reading term and an output offset. With this input dynamic range the input offset contribution to total error is negligible compared to the percent of reading error. Thus, it is specified indirectly as a part of the percent of reading error. 2 The most accurate representation of total error with low level inputs is the summation of a percent of reading term, an output offset and an input offset multiplied by the incremental gain (VY + VZ) VX. 3 When using supplies below ±13 V, the 10 V reference pin must be connected to the 2 V pin in order for the AD538 to operate correctly. Rev. E | Page 4 of 16 AD538 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Internal Power Dissipation Output Short Circuit-to-Ground Input Voltages VX, VY, VZ Input Currents IX, IY, IZ, IO Operating Temperature Range Storage Temperature Range Lead Temperature, Storage Thermal Resistance θJC θJA Rating ±18 V 250 mW Indefinite (+VS − 1 V), −1 V 1 mA −25°C to +85°C −65°C to +150°C 60 sec, +300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 35°C/W 120°C/W Rev. E | Page 5 of 16 AD538 IZ 1 18 A VZ 2 17 D 16 IX 15 VX +VS 6 TOP VIEW (Not to Scale) 14 SIGNAL GND 13 PWR GND –VS 7 12 C VO 8 11 IY I 9 10 VY B 3 +10V 4 +2V 5 AD538 00959-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 3. Pin No. 1 2 3 Mnemonic IZ VZ B 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 +10V +2V +VS –VS VO I VY IY C PWR GND SIGNAL GND VX IX D A Description Current Input for the Z Multiplicand. Voltage Input for the Z Multiplicand. Output of the Log Ratio Differential Amplifier. This amplifier subtracts the log of the Z input from the log of the X input, or performs the equivalent logarithmic equivalent of long division. +10 V Reference Voltage Output. +2 V Reference Voltage Output. Positive Supply Rail. Negative Rail. Output Voltage. Current Input to the Output Amplifier. Voltage Input to the Y Multiplicand. Current Input to the Y Multiplicand. Current Input to the Base of the Antilog Log-to-Linear Converter. High level Power Return of the Chip. Low Level Ground Return of the Device. Voltage Input of the X Multiplicand. Current Input of the X Input Multiplicand. Use for Log Ratio Function. Use for Log Ratio Function. Rev. E | Page 6 of 16 AD538 TYPICAL PERFORMANCE CHARACTERISTICS 5 1000 1M 400 OFFSET 1 200 0 –55 –40 % OF READING –20 0 20 40 60 TEMPERATURE (°C) 80 100 0 125 4 800 3 600 2 400 OFFSET 200 TOTAL % OF READING ERROR 1000 1 10k 0.01 0.1 1 DENOMINATOR VOLTAGE, VX – V dc 6 1200 5 1000 4 800 3 600 2 200 1 0 20 40 60 TEMPERATURE (°C) 80 100 OFFSET 0 125 0 –55 –40 00959-004 –20 400 % OF READING % OF READING 0 –55 –40 10 Figure 6. Small Signal Bandwidth vs. Denominator Voltage (One-Quadrant Mult/Div) OUTPUT STAGE OFFSET (µV) 5 Figure 4. Divider Error vs. Temperature (100 mV < VX, VY, VZ ≤ 10 V) –20 0 20 40 60 TEMPERATURE (°C) 80 100 0 125 Figure 7. Multiplier Error vs. Temperature (10 mV < VX, VY, VZ ≤ 100 mV) 1000 5 1000 4 800 3 600 100 10 2 400 % OF READING 1 200 OUTPUT STAGE OFFSET (µV) TOTAL % OF READING ERROR VX = 10V VY = 0V VZ = 5V +5V SIN ωt VOLTS VO (mV p-p) 1 100 1k 10k 100k INPUT FREQUENCY (Hz) 1M 0 –55 –40 Figure 5. VZ Feedthrough vs. Frequency –20 0 20 40 60 TEMPERATURE (°C) 80 100 0 125 Figure 8. Divider Error vs. Temperature (10 mV < VX, VY, VZ ≤ 100 mV) Rev. E | Page 7 of 16 00959-008 OFFSET 00959-005 TOTAL % OF READING ERROR Figure 3. Multiplier Error vs. Temperature (100 mV < VX, VY, VZ ≤ 10 V) 40k 00959-007 2 100k 00959-006 600 400k OUTPUT STAGE OFFSET (µV) 3 SMALL SIGNAL BANDWIDTH (Hz) 800 OUTPUT STAGE OFFSET (µV) 4 00959-003 TOTAL % OF READING ERROR VY = 10V dc VZ = VX +0.05 VX SIN ωt AD538 150 5 VX = 10V VY = 5V +5V SIN ωt VOLTS VZ = 0V 1 0.1 100 1k 10k 100k INPUT FREQUENCY (Hz) Figure 9. VY Feedthrough vs. Frequency 1M 4 3 VX = 0.01V 2 VX = 10V 1 0 0.01 0.1 1 DC OUTPUT VOLTAGE (V) 10 00959-010 VOLTAGE NOISE (en – µV/ Hz) 10 00959-009 VO (mV p-p) 100 FOR THE FREQUENCY RANGE OF 10Hz TO 100kHz THE TOTAL rms OUTPUT NOISE, eo, FOR A GIVEN BANDWIDTH Bw, IS CALCULATED eo = en Bw. Figure 10. 1 kHz Output Noise Spectral Density vs. DC Output Voltage Rev. E | Page 8 of 16 AD538 THEORY OF OPERATION RE-EXAMINATION OF MULTIPLIER/DIVIDER ACCURACY Traditionally, the accuracy (actually the errors) of analog multipliers and dividers has been specified in terms of percent of full scale. Thus specified, a 1% multiplier error with a 10 V full-scale output would mean a worst-case error of +100 mV at any level within its designated output range. While this type of error specification is easy to test evaluate, and interpret, it can leave the user guessing as to how useful the multiplier actually is at low output levels, those approaching the specified error limit (in this case) 100 mV. The error sources of the AD538 do not follow the percent of full-scale approach to specification, thus it more optimally fits the needs of the very wide dynamic range applications for which it is best suited. Rather than as a percent of full scale, the AD538’s error as a multiplier or divider for a 100:1 (100 mV to 10 V) input range is specified as the sum of two error components: a percent of reading (ideal output) term plus a fixed output offset. Following this format, the AD538AD, operating as a multiplier or divider with inputs down to 100 mV, has a maximum error of ±1% of reading ±500 μV. Some sample total error calculations for both grades over the 100:1 input range are illustrated in Table 4. This error specification format is a familiar one to designers and users of digital voltmeters where error is specified as a percent of reading ± a certain number of digits on the meter readout. For operation as a multiplier or divider over a wider dynamic range (>100:1), the AD538 has a more detailed error specification that is the sum of three components: a percent of reading term, an output offset term, and an input offset term for the VY/VX log ratio section. A sample application of this specification, taken from Table 4, for the AD538AD with VY = 1 V, VZ = 100 mV and VX = 10 mV would yield a maximum error of ±2.0% of reading ±500 μV ± (1 V + 100 mV)/10 mV × 250 μV or ±2.0% of reading ±500 μV ± 27.5 mV. This example illustrates that with very low level inputs the AD538’s incremental gain (VY + VZ)/VX has increased to make the input offset contribution to error substantial. Table 4. Sample Error Calculation Chart (Worst Case) 100:1 INPUT RANGE Total Error = ±% rdg ±Output VOS WIDE DYNAMIC RANGE Total Error = ±% rdg ± Output VOS ± Input VOS × (VY + VZ)/VX Total Offset Error Term (mV) 0.5 (AD) 0.25 (BD) % of Reading Error Term (mV) 100 (AD) 50 (BD) Total Error Summation (mV) 100.5 (AD) 50.25 (BD) Total Error Summation as a % of the Ideal Output 1.0 (AD) 0.5 (BD) 10 0.5 0.25 (AD) (BD) 100 50 (AD) (BD) 100.5 50.25 (AD) (BD) 1.0 0.5 (AD) (BD) 1 1 0.1 0.1 0.1 1 0.10 0.01 10 0.5 0.25 0.5 0.25 28 16.75 (AD) (BD) (AD) (BD) (AD) (BD) 10 ) 5 1 0.5 200 100 (AD (BD) (AD) (BD) (AD) (BD) 10.5 5.25 1.5 0.75 228 116.75 (AD) (BD) (AD) (BD) (AD) (BD) 1.05 0.5 1.5 0.75 2.28 1.17 (AD) (BD) (AD) (BD) (AD) (BD) 10 0.05 2 0.25 1.76 1 (AD) (BD) 5 2.5 (AD) (BD) 6.76 3.5 (AD) (BD) 2.7 1.4 (AD) (BD) 5 0.01 0.01 5 10 0.01 0.1 1 125.75 75.4 25.53 15.27 (AD) (BD) (AD) (BD) 100 50 20 10 (AD) (BD) (AD) (BD) 225.75 125.4 45.53 25.27 (AD) (BD) (AD) (BD) 4.52 2.51 4.55 2.53 (AD) (BD) (AD) (BD) VY Input (V) 10 VZ Input (V) 10 VX Input (V) 10 Ideal Output (V) 10 10 0.1 0.1 1 1 0.1 Rev. E | Page 9 of 16 AD538 FUNCTIONAL DESCRIPTION STABILITY PRECAUTIONS As shown in Figure 1 and Figure 11, the VZ and VX inputs connect directly to the input log ratio amplifiers of the AD538. This subsection provides an output voltage proportional to the natural log of input voltage, VZ, minus the natural log of input voltage, VX. The output of the log ratio subsection at B can be expressed by the transfer function At higher frequencies, the multistaged signal path of the AD538 can result in large phase shifts (as illustrated in Figure 11). If a condition of high incremental gain exists along that path (for example, VO = VY × VZ/VX = 10 V × 10 mV/10 mV = 10 V so that ΔVO/ΔVX = 1000), then small amounts of capacitive feedback from VO to the current inputs IZ or IX can result in instability. Appropriate care should be exercised in board layout to prevent capacitive feedback mechanisms under these conditions. kT VZ ln q VX LOGe ;V + Σ ANTILOGe VZ Ln Z LOGe VY BUFFER + VO = VY Ln Y B USING THE VOLTAGE REFERENCES A stable band gap voltage reference for scaling is included in the AD538. It is laser-trimmed to provide a selectable voltage output of +10 V buffered (Pin 4), +2 V unbuffered (Pin 5) or any voltages between +2 V and +10.2 V buffered as shown in Figure 12. The output impedance at Pin 5 is approximately 5 kΩ. Note that any loading of this pin produces an error in the +10 V reference voltage. External loads on the +2 V output should be greater than 500 kΩ to maintain errors less than 1%. +2V TO +10.2V BUFFERED VZ 2 LOG RATIO 25kΩ B 3 REF OUT 4 100Ω Finally, by increasing the gain, or attenuating the output of the log ratio subsection via resistor programming, it is possible to raise the quantity VZ/VX to the mth power. Without external programming, m is unity. Thus, the overall AD538 transfer function equals: M Figure 11. Model Circuit IZ 1 = VC VZ VX 50kΩ 11.5kΩ +2V 100Ω +VS 6 –VS 7 INTERNAL VOLTAGE REFERENCE 18 A 17 D 16 IX 15 VX 14 SIGNAL GND 13 PWR GND 12 C 11 IY 10 VY 25kΩ 5 AD538 OUTPUT 25kΩ VO 8 m I 9 ANTILOG LOG 25kΩ Figure 12. +2 V to +10.2 V Adjustable Reference where 0.2 < m < 5. When the AD538 is used as an analog divider, the VY input can be used to multiply the ratio VZ/VX by a convenient scale factor. The actual multiplication by the VY input signal is accomplished by adding the log of the VY input signal to the signal at C, which is already in the log domain. 00959-012 0.2≤M≤5 IY LOGe which reduces to: V VO = VY Z VX Σ IZ As with the log-ratio circuit included in the AD538, the user may use the antilog subsection by itself. When both subsections are combined, the output at B is tied to C, the transfer function of the AD538 computational unit is: V VO = VY Z VX M(Ln Z – Ln X) +Ln Y + q VO = VY e VC kT VO = V M(Ln Z – Ln X) – Under normal operation, the log-ratio output will be directly connected to a second functional block at Input C, the antilog subsection. This section performs the antilog according to the transfer function: kT q VZ ln Q kT VX Ln X VX The log ratio configuration may be used alone, if correctly temperature compensated and scaled to the desired output level (see the Applications Information section). e Y Ln Z – Ln X IX where: k is 1.3806 × 10−23 J/K. q is 1.60219 × 10−19 C. T is in Kelvins. In situations not requiring both reference levels, the +2 V output can be converted to a buffered output by tying Pin 4 and Pin 5 together. If both references are required simultaneously, the +10 V output should be used directly and the +2 V output should be externally buffered. Rev. E | Page 10 of 16 00959-013 VB = AD538 ONE-QUADRANT MULTIPLICATION/DIVISION When the input VX is tied to the +10 V reference terminal, the multiplier transfer function becomes: Figure 13 shows how the AD538 may be easily configured as a precision one-quadrant multiplier/divider. The transfer function VO = VY (VZ/VX) allows three independent input variables, a calculation not available with a conventional multiplier. In addition, the 1000:1 (that is, 10 mV to 10 V) input dynamic range of the AD538 greatly exceeds that of analog multipliers computing one-quadrant multiplication and division. VZ VX IZ 1 VZ VZ INPUT B +10V LOG RATIO 25kΩ 2 3 6 –15V 7 VO 17 D 16 IX 25kΩ 14 INTERNAL VOLTAGE REFERENCE 13 AD538 12 OUTPUT 25kΩ 8 OUTPUT I 100Ω 5 +15V A 15 4 100Ω +2V 18 9 11 ANTILOG LOG 10 By using the 10 V reference as the VY input, the circuit of Figure 13 is configured as a one-quadrant divider with a fixed scale factor. As with the one-quadrant multiplier, the inputs accept only single (positive) polarity signals. The output of the one-quadrant divider with a +10 V scale factor is: VX V VO = 10 V Z VX VX INPUT SIGNAL GND C IN4148 VY 25kΩ The typical bandwidth of this circuit is 370 kHz with 1 V to 10 V denominator input levels. At lower amplitudes, the bandwidth gradually decreases to approximately 200 kHz at the 2 mV input level. PWR GND IY As a multiplier, this circuit provides a typical bandwidth of 400 kHz with values of VX, VY, or VZ varying over a 100:1 range (that is, 100 mV to 10 V). The maximum error with a 100 mV to 10 V range for the two input variables will typically be +0.5% of reading. Using the optional Z offset trim scheme, as shown in Figure 14, this error can be reduced to +0.25% of reading. VY INPUT 00959-014 VO = VY V VO = VY Z 10 V Figure 13. One-Quadrant Combination Multiplier/Divider By simply connecting the input, VX (Pin 15) to the 10 V reference (Pin 4), and tying the log-ratio output at B to the antilog input at C, the AD538 can be configured as a onequadrant analog multiplier with 10 V scaling. If 2 V scaling is desired, VX can be tied to the 2 V reference. Rev. E | Page 11 of 16 AD538 TWO-QUADRANT DIVISION LOG RATIO OPERATION The two-quadrant linear divider circuit illustrated in Figure 14 uses the same basic connections as the one-quadrant version. However, in this circuit the numerator has been offset in the positive direction by adding the denominator input voltage to it. The offsetting scheme changes the divider’s transfer function from Figure 15 shows the AD538 configured for computing the log of the ratio of two input voltages (or currents). The output signal from B is connected to the summing junction of the output amplifier via two series resistors. The 90.9 Ω metal film resistor effectively degrades the temperature coefficient of the ±3500 ppm/°C resistor to produce a 1.09 kΩ +3300 ppm/°C equivalent value. In this configuration, the VY input must be tied to some voltage less than zero (−1.2 V in this case) removing this input from the transfer function. V VO = 10 V Z VX VO = 10 V The 5 kΩ potentiometer controls the circuit’s scale factor adjustment providing a +1 V per decade adjustment. The output offset potentiometer should be set to provide a zero output with VX = VZ = 1 V. The input VZ adjustment should be set for an output of 3 V with VZ = l mV and VX = 1 V. (VZ + AVX ) =10 V 1 A + VZ VX V = 10 A + 10 V Z VX V X –VS where: 35 kΩ A= 25 kΩ OPTIONAL Z OFFSET TRIM 10MΩ NUMERATOR VZ DENOMINATOR VX OPTIONAL INPUT VOS ADJUSTMENT B VZ VX 1 18 +2V 17 16 3 15 4 100Ω 100Ω 25kΩ 5 +15V 6 –15V 7 14 INTERNAL VOLTAGE REFERENCE 5kΩ 2kΩ 1% VO SCALE FACTOR ADJUST 13 AD538 I 12 OUTPUT 25kΩ 8 11 ANTILOG 9 A 48.7Ω LOG RATIO 25kΩ 2 OUTPUT D IX VX VX INPUT SIGNAL GND PWR GND C IY IN4148 LOG 10 VY 25kΩ +VS 10MΩ VZ VO = 10 FOR VX ≥ VZ VX 35kΩ Figure 15. Log Ratio Circuit IZ 10MΩ 1 VZ 3.9MΩ B +10V 18 25kΩ 17 D IX 16 3 15 4 100Ω +2V The log ratio circuit shown achieves ±0.5% accuracy in the log domain for input voltages within three decades of input range: 10 mV to 10 V. This error is not defined as a percent of fullscale output, but as a percent of input. For example, using a 1 V/decade scale factor, a 1% error in the positive direction at the input of the log ratio amplifier translates into a 4.3 mV deviation from the ideal OUTPUT (that is, 1 V × log10 (1.01) = 4.3214 mV). An input error 1% in the negative direction is slightly different, giving an output deviation of 4.3648 mV. A 35kΩ LOG RATIO 2 100Ω 25kΩ 5 +15V 6 –15V 7 14 INTERNAL VOLTAGE REFERENCE 13 AD538 VX SIGNAL GND PWR GND IN4148 R1 12.4kΩ I 12 OUTPUT 25kΩ 8 9 11 ANTILOG LOG 10 C IY VY 25kΩ ZERO ADJUST 00959-015 VO OUTPUT OPTIONAL 10kΩ OUTPUT VOS ADJUSTMENT –VS –1.2V R2 10kΩ +10V 1k +3500 ppm/°C AD589 1MΩ ADJ IZ VZ 90.9Ω 1% –VS 68kΩ VO = 1V LOG10 –1.2V 1MΩ As long as the magnitude of the denominator input is equal to or greater than the magnitude of the numerator input, the circuit accepts bipolar numerator voltages. However, under the conditions of a 0 V numerator input, the output would incorrectly equal +14 V. The offset can be removed by connecting the 10 V reference through Resistors R1 and R2 to the output section’s summing Node I at Pin 9 thus providing a gain of 1.4 at the center of the trimming potentiometer. The potentiometer, R2, adjusts out or corrects this offset, leaving the desired transfer function of 10 V (VZ/VX). VOS 68kΩ 5% AD589 Figure 14. Two-Quadrant Division with 10 V Scaling Rev. E | Page 12 of 16 00959-016 to AD538 ANALOG COMPUTATION OF POWERS AND ROOTS SQUARE ROOT OPERATION It is often necessary to raise the quotient of two input signals to a power or take a root. This could be squaring, cubing, square rooting or exponentiation to some noninteger power. Examples include power series generation. With the AD538, only one or two external resistors are required to set any desired power, over the range of 0.2 to 5. Raising the basic quantity VZ/VX to a power greater than one requires that the gain of the AD538’s log ratio subtractor be increased, via an external resistor between the A and D pins. Similarly, a voltage divider that attenuates the log ratio output between Point B and Point C will program the power to a value less than one. The explicit square root circuit of Figure 17 illustrates a precise method for performing a real-time square root computation. For added flexibility and accuracy, this circuit has a scale factor adjustment. RA B VZ VY C 3 2 A 12 D 18 VZ m ) VY ( VREF POWERS 17 8 m RA 2 3 4 5 196Ω 97.6Ω 64.9Ω 48.7Ω VO 10 15 VX VREF 196Ω M–1 RB = RC ≤ 200Ω RA = B VZ RC C 3 2 VY ( VY 10 VREF VZ m ) VREF 15 VX 8 VO m RB RC 1/2 1/3 1/4 1/5 100Ω 100Ω 150Ω 162Ω 100Ω 49.9Ω 49.9Ω 40.2Ω RB 1 = –1 RC M Figure 16. Basic Configurations and Transfer Functions for the AD538 1 V scaling is achieved by dividing-down the 2 V reference and applying approximately 1 V to both the VY and VX inputs. In this circuit, the VX input is intentionally set low, to about 0.95 V, so that the VY input can be adjusted high, permitting a ±5% scale factor trim. Using this trim scheme, the output voltage will be within ±3 mV ± 0.2% of the ideal value over a 10 V to 1 mV input range (80 dB). For a decreased input dynamic range of 10 mV to 10 V (60 dB) the error is even less; here the output will be within ±2 mV ± 0.2% of the ideal value. The bandwidth of the AD538 square root circuit is approximately 280 kHz with a 1 V p-p sine wave with a +2 V dc offset. This basic circuit may also be used to compute the cube, fourth or fifth roots of an input waveform. All that is required for a given root is that the correct ratio of resistors, RC and RB, be selected such that their sum is between 150 Ω and 200 Ω. ROOTS 12 00959-017 RB The actual square rooting operation is performed in this circuit by raising the quantity VZ/VX to the one-half power via the resistor divider network consisting of resistors RB and RC. For maximum linearity, the two resistors should be 1% (or better) ratio-matched metal film types. The optional absolute value circuit shown preceding the AD538 allows the use of bipolar input voltages. Only one op amp is required for the absolute value function because the IZ input of the AD538 functions as a summing junction. If it is necessary to preserve the sign of the input voltage, the polarity of the op amp output may be sensed and used after the computation to switch the sign bit of a DVM chip. Rev. E | Page 13 of 16 AD538 VO = 1V OPTIONAL ABSOLUTE VALUE SECTION VIN 1V 5kΩ IZ 10kΩ 20kΩ VZ IN4148 +VS VIN 20kΩ 7 2 1 3 B 20kΩ 3 A 17 D 16 IX VOS +10V 8 LOG RATIO 25kΩ 2 18 15 4 6 100Ω +2V 4 AD OP-07 OR AD811 –VS (VOS TAP TO –VS) +2V 6 –15V 7 I 25kΩ 5 +15V VO VO 100Ω 14 INTERNAL VOLTAGE REFERENCE 13 AD538 12 OUTPUT 25kΩ 8 11 ANTILOG 9 LOG 1kΩ 10 RB 100Ω * VX SIGNAL GND PWR GND C IY D1 VY IN4148 25kΩ 100Ω SCALE FACTOR TRIM 1kΩ * RATIO MATCH 1% METAL FILM RESISTORS FOR BEST ACCURACY Figure 17. Square Root Circuit Rev. E | Page 14 of 16 RC 100Ω * 00959-018 IN4148 1 AD538 APPLICATIONS INFORMATION Many electronic transducers used in scientific, commercial or industrial equipment monitor the physical properties of a device and/or its environment. Sensing (and perhaps compensating for) changes in pressure, temperature, moisture or other physical phenomenon can be an expensive undertaking, particularly where high accuracy and very low nonlinearity are important. In conventional analog systems accuracy may be easily increased by offset and scale factor trims; however, nonlinearity is usually the absolute limitation of the sensing device. With the ability to easily program a complex analog function, the AD538 can effectively compensate for the nonlinearities of an inexpensive transducer. The AD538 can be connected between the transducer preamplifier output and the next stage of monitoring or transmitting circuitry. The recommended procedure for linearizing a particular transducer is first to find the closest function which best approximates the nonlinearity of the device and then, to select the appropriate exponent resistor value(s). The (VθREF − Vθ) function is implemented in this circuit by adding together the output, Vθ, and an externally applied reference voltage, VθREF, via an external AD547 op amp. The 1 μF capacitor connected around the AD547’s 100 k Ω feedback resistor frequency compensates the loop (formed by the amplifier between Vθ and VY). Vθ = (VθREF where: Z θ = Tan −1 X 1.21 Z θ = TAN–1 X VZ VZ 18 LOG RATIO 25kΩ 2 B +10V 17 15 4 100Ω +2V +VS +15V –VS 14 INTERNAL VOLTAGE REFERENCE 6 7 1µF Vθ VO 25kΩ 100Ω 5 1µF –15V A D RA 931Ω, 1% 16 IX 3 13 AD538 12 OUTPUT 25kΩ 8 11 ANTILOG I 9 The circuit of Figure 18 is typical of those AD538 applications where the quantity VZ/VX is raised to powers greater than one. In an approximate arc-tangent function, the AD538 will accurately compute the angle that is defined by X and Y displacements represented by input voltages VX and VZ. With accuracy to within one degree (for input voltages between 100 μV and 10 V), the AD538 arc-tangent circuit is more precise than conventional analog circuits and is faster than most digital techniques. The circuit shown is set up for the transfer function: 1.21 IZ 1 ARC-TANGENT APPROXIMATION (V ) − Vθ ) Z (V X ) VZ VX Vθ = [VθREF –Vθ] × 10 LOG VX VX SIGNAL GND PWR GND C IY IN4148 VY 25kΩ 0.1µF +15V R1* 100kΩ 2 10kΩ FULL-SCALE ADJUST R2* 100kΩ 7 AD547JH 6 118kΩ 3 1µF 4 100kΩ –15V * RATIO MATCH 1% METAL FILM RESISTORS FOR BEST ACCURACY 00959-019 TRANSDUCER LINEARIZATION Figure 18. The Arc-Tangent Function The VB/VA quantity is calculated in the same manner as in the one-quadrant divider circuit, except that the resulting quotient is raised to the 1.21 power. Resistor RA (nominally 931 Ω) sets the power or m factor. For the highest arc-tangent accuracy the R1 and R2 external resistors should be ratio matched; however, the offset trim scheme shown in other circuits is not required since nonlinearity effects are the predominant source of error. Also note that instability will occur as the output approaches 90° because, by definition, the arc-tangent function is infinite and therefore, the gain of the AD538 will be extremely high. Rev. E | Page 15 of 16 AD538 OUTLINE DIMENSIONS 0.005 (0.13) MIN 0.098 (2.49) MAX 18 10 1 9 PIN 1 0.960 (24.38) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.310 (7.87) 0.220 (5.59) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING 0.100 0.070 (1.78) (2.54) 0.030 (0.76) PLANE BSC 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 19. 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] (D-18) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model 1 AD538ACHIPS AD538AD AD538ADZ AD538BD AD538BDZ AD538SD AD538SD/883B 1 Temperature Range −25°C to +85°C −25°C to +85°C −25°C to +85°C −25°C to +85°C −25°C to +85°C −55°C to +125°C −55°C to +125°C Package Description Chips 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00959-0-6/11(E) Rev. E | Page 16 of 16 Package Option D-18 D-18 D-18 D-18 D-18 D-18

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