データシート

[AK4213]
AK4213
Mono Class-D SPK-Amp with Stereo Cap-less HP-Amp
AK4213
D
/
ALC
AK4213
29pin CSP (3.0 x 3.0mm)
† Single-ended / Differential Input
† Analog Mixing Circuit
† Analog Input Volume: +10dB to –20dB, 2dB step
† µP Interface: I2C Bus (Ver1.0, 400kHz Fast Mode)
† Thermal Shutdown / Short Protection circuit
† Mono Class-D Speaker Amplifier:
- BTL output
- Output Power: 1.6W @ 8Ω, SVDD=5V
0.8W @ 8Ω, SVDD=3.6V
- THD+N: -65dB @ 8Ω, Po=0.25W, SVDD=3.6V
- Output Noise Level: 85μVrms
- ALC (Automatic Level Control) Circuit
- Bypass Mode
- Pop Noise Free at Power-ON/OFF and Mute
- External filter-less
† Stereo Cap-less Headphone Amplifier:
- Mono / Stereo Mode
- Output Power: 64mW 2ch @ 16 , SVDD=3.3V, THD+N=-40dB
- THD+N: -58dB @ 16Ω, Po=30mW, SVDD=3.3V
- Output Noise Level: 24μVrms
- Output Volume: +12dB to –50dB, 2dB step
- Pop Noise Free at Power-ON/OFF and Mute
† Power Supply:
- Analog: 2.6 ∼ 3.6V
- Headphone Amplifier: 2.6 ∼ 3.6V
- Speaker Amplifier: 3.0 ∼ 5.5V
- Digital Interface: 1.6 ∼ 3.6V
† Ta: −40 ∼ 85°C
† Package: 29pin CSP (3.0 x 3.0mm, 0.5mm pitch)
MS0949-J-01
-1-
2008/07
[AK4213]
■
AVDD
VSS1
MIXO SPIN
TEST
PMV1
LIN1/IN1−
Vol
RVINP
Mixing
Selector
RIN1/IN1+
Vol
PMMSP
SPN
LIN2/IN2−
Vol
RIN2/IN2+
Vol
PMSPK
PMVCM
Regulator
PMV3
LIN3/IN3−
SPP
ALC
PMV2
RVINN
SVDD
PMMHL
Vol
VSS2
Mixing
RIN3/IN3+
Selector
Vol
PMHPL
Mixing
VOL
HPL
VOL
HPR
Selector
PMMHR
VCOM
VCOM
PMVCM
PMHPR
Internal Oscillator
PMOSC
TVDD
SCL
SDA
PMCP
CP
Serial I/F
Charge Pump
CN
PVDD
PDN
VSS3 PVEE
Figure 1. AK4213 Block Diagram
MS0949-J-01
-2-
2008/07
[AK4213]
■
AK4213ECB
AKD4213
−40 ∼ +85°C
AK4213
29pin CSP (3.0 x 3.0mm, 0.5mm pitch)
■
5
4
Top View
3
2
1
A
B
C
5
HPR
LIN3/IN3-
4
HPL
RIN3/IN3+ RIN2/IN2+
3
PVEE
VCOM
E
F
RIN1/IN1+
SVDD
LIN1/IN1-
SPN
VSS2
SPP
VSS3
PDN
LIN2/IN2-
TEST
SPIN
PVDD
SDA
TVDD
RVINN
RVINP
CP
CN
SCL
VSS1
AVDD
MIXO
A
B
C
D
E
F
2
1
D
Top View
MS0949-J-01
-3-
2008/07
[AK4213]
No.
E1
D1
Pin Name
AVDD
VSS1
E3
TEST
I
D2
C1
C2
TVDD
SCL
SDA
I
I/O
C3
PDN
I
A1
B1
B2
B3
A3
A4
A5
F2
E2
B4
B5
C5
C4
D3
D5
F5
E5
E4
F4
D4
F1
F3
CP
CN
PVDD
VSS3
PVEE
HPL
HPR
RVINP
RVINN
RIN3/IN3+
LIN3/IN3VCOM
RIN2/IN2+
LIN2/IN2RIN1/IN1+
LIN1/IN1SVDD
VSS2
SPP
SPN
MIXO
SPIN
I
I
O
O
O
I
I
I
I
O
I
I
I
I
O
O
O
I
Note 1.
I/O
-
Function
Analog Power Supply Pin
Ground 1 Pin
Test Pin
This pin should be open.
Digital Interface Power Supply Pin
Control Data Clock Pin
Control Data Input/Output Pin
Power-Down Mode Pin
“H”: Power-up, “L”: Power-down, resets and initialization of the control register.
The AK4213 should be reset once upon power-up.
Positive Charge Pump Capacitor Terminal Pin
Negative Charge Pump Capacitor Terminal Pin
Charge Pump Circuit Positive Power Supply Pin
Ground 3 Pin
Charge Pump Circuit Negative Voltage Output Pin
Lch Headphone-Amp Output Pin
Rch Headphone-Amp Output Pin
Receiver Positive Input Pin
Receiver Negative Input Pin
Analog Input Pin
Analog Input Pin
Analog Common Voltage Output Pin
Analog Input Pin
Analog Input Pin
Analog Input Pin
Analog Input Pin
Speaker-Amp Power Supply Pin
Ground 2 Pin
Positive Speaker-Amp Output Pin
Negative Speaker-Amp Output Pin
MIX-Amp Output Pin
Speaker-Amp Input Pin
(LIN1/IN1-, RIN1/IN1+, LIN2/IN2-, RIN2/IN2+, LIN3/IN3-, RIN3/IN3+, SPIN, RVINP,
RVINN )
■
Analog
MS0949-J-01
HPL, HPR, MIXO, SPIN, SPP, SPN, LIN1/IN-,
RIN1/IN+, LIN2/IN2-, RIN2/IN2+, LIN3/IN3-,
RIN3/IN3+, RVINP, RVINN, TEST
-4-
2008/07
[AK4213]
(VSS1=VSS2=VSS3 =0V; Note 2)
Parameter
Symbol
min
max
Power Supplies: Analog
AVDD
6.0
−0.3
(Note 3)
Digital I/F
TVDD
6.0
−0.3
Speaker-Amp & Headphone-Amp
SVDD
6.0
−0.3
Charge Pump
PVDD
4.0
−0.3
Input Current, Any Pin Except Supplies
IIN
±10
Analog Input Voltage (Note 4)
VINA1
(AVDD + 0.3) or 6.0
−0.3
(Note 5)
VINA2
(
SVDD + 0.3) or 6.0
−0.3
Digital Input Voltage (Note 6)
VIND
(TVDD + 0.3) or 6.0
−0.3
Ambient Temperature (powered applied)
Ta
85
−40
Storage Temperature
Tstg
150
−65
Pd1
0.65
Maximum Power Dissipation Ta=85 (Note 8)
(Note 7) Ta=70 (Note 9)
Pd2
0.8
Note 2.
Note 3. VSS1,VSS2, VSS3
Note 4. LIN1/IN1-, RIN1/IN1+, LIN2/IN2-, RIN2/IN2+, LIN3/IN3-, RIN3/IN3+, SPIN pin
max
(AVDD+0.3)V
6.0V
Note 5. RVINP, RVINN pins
max
(SVDD+0.3)V
6.0V
Note 6. SDA, SCL, PDN pins
max
(TVDD+0.3)V
6.0V
SCL, SDA pin
(TVDD + 0.3)V
Note 7.
300%
AK4213
Note 8. Ta = 85°C
Note 9. Ta = 70°C
HP-Amp SPK-Amp
ON
SPK-Amp Po
1.3W @ 8Ω
HP-Amp SPK-Amp
ON
HP-Amp Po 30mW @ 16Ω
SPK-Amp
SPK-Amp
Po
Units
V
V
V
V
mA
V
V
V
°C
°C
W
W
HP-Amp
HP-Amp SPK-Amp
1.2W @ 8Ω
:
MS0949-J-01
-5-
2008/07
[AK4213]
(VSS1=VSS2=VSS3 =0V; Note 2)
Parameter
Power
Analog
Supplies
Digital I/F
(Note 10) Speaker-Amp & Headphone-Amp
Charge Pump
Difference
Symbol
AVDD
TVDD
SVDD
PVDD
PVDD – AVDD
SVDD – AVDD
min
2.6
1.6
3.0
2.6
-0.3
-0.3
typ
3.3
1.8
3.6
3.3
0
-
Note 10. AVDD, TVDD, SVDD, PVDD
Units
V
V
V
V
V
V
PDN pin = “L”
PDN pin
* AK4213
2
"L"
1. TVDD=SVDD=ON
2. TVDD=ON
:
OFF
ON
PDN pin
max
3.6
3.6
5.5
3.6
0.3
-
ON/OFF
: AVDD=PVDD ON/OFF
AVDD=PVDD=SVDD ON/OFF
TVDD,AVDD,PVDD,SVDD
"H"
“H”
PDN pin
150ns
:
MS0949-J-01
-6-
2008/07
[AK4213]
(Ta=25°C; AVDD=PVDD=3.3V, SVDD=3.6V, TVDD=1.8V, VSS1=VSS2=VSS3=0V; Input Signal Frequency
=1kHz; Measurement band width=10Hz ∼ 20kHz; Headphone-Amp: RL =16Ω; Speaker-Amp: RL =8Ω + 10μH; Charge
Pump Circuit External Capacitance: C1=C2= 2.2μF (Figure 4); unless otherwise specified)
Parameter
min
typ
max
Units
LIN1, RIN1, LIN2, RIN2, LIN3, RIN3 pins
Input Resistance
25
50
110
kΩ
Input Analog Volume: L1V3-0, R1V3-0, L2V3-0, R2V3-0, L3V3-0, R3V3-0 bits
Step Size
1
2
3
dB
Gain Control Range
-20
+10
dB
MIX-Amp: MIXO pins
Load Resistance
10
kΩ
Load Capacitance
30
pF
Headphone-Amp: (LIN/RIN Æ HPL/HPR pins), Input Volume=HPGA = 0dB
Output Power (THD+N=1%)
SVDD=3.3V
64
mW
THD+N:
0.7Vrms Single-ended Input, Po = 30mW
-58
-40
dB
Output Noise Level (A-weighted) (Note 11)
24
40
μVrms
Interchannel Gain Mismatch
0.2
0.8
dB
Load Resistance
16
Ω
Load Capacitance
300
pF
Output Voltage: 0.7Vrms Single-ended Input
0.62
0.69
0.76
Vrms
PSRR
217Hz (Note 12)
70
dB
1kHz (Note 12)
70
dB
217Hz (Note 13)
100
dB
1kHz (Note 13)
80
dB
Interchannel Isolation
60
80
dB
Headphone Analog Volume (HPGA4-0 bits)
Step Size
0.5
2
3.5
dB
Gain Control Range
-50
+12
dB
Class-D Speaker-Amp: LIN or RIN Æ SPP/SPN; ALC = OFF, Input Volume=SPGA=0dB, BTL
Output Power (THD+N=10%)
SVDD=5.0V
1.6
W
SVDD=3.6V
0.8
W
Output Level
SVDD = 5.0V, Input Level = 0.85Vrms (Note 14)
2.7
Vrms
SVDD = 3.6V, Input Level = 0.64Vrms (Note 15)
2.0
Vrms
SVDD = 3.6V, Input Level = 0.46Vrms (Note 16)
1.33
1.48
1.63
Vrms
THD+N
-65
-40
dB
Po=0.25W, Input Level = 0.46Vrms (Note 16)
Output Noise (A-weighted) (Note 17)
85
150
μVrms
Load Resistance
8
Ω
Load Capacitance (Note 21)
300
pF
PSRR
217Hz (Note 18)
60
dB
1kHz (Note 18)
50
dB
217Hz (Note 19)
50
dB
1kHz (Note 19)
50
dB
Switching Frequency
150
250
400
kHz
40
120
mA
(Note 20)
Start-Up Time
18
30
48
ms
MS0949-J-01
-7-
2008/07
[AK4213]
Parameter
min
typ
max
Units
SPIN pins
Input Resistance
15
26
36
Speaker Analog Volume: SPGA5-0 bits
Step Size
0.1
0.5
0.9
Gain Control Range
-12
+19.5
Bypass Mode: Figure 2, Input Level = 1.13Vrms, Common Voltage = 1.8V, Measured by SPP/SPN pins
THD+N
1.13Vrms, 3.2Vpp
-50
0.71Vrms, 2.0Vpp
-60
-50
Output Level
0.46
Switch ON Resistance ( BYPE bit = “1”)
2.8
Switch Off Isolation ; 3.6VDC Input, Figure 3
90
(SPP/SPN pins– RVINP/RVINN pins)
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
AVDD+TVDD:
ALL ON
(Note 22)
4.0
6.5
HP-Amp ON
(Note 23)
2.0
SPK-Amp ON
(Note 24)
2.8
PVDD (No Output): HP-Amp ON
1.3
3.2
SVDD (No Output): HP-Amp ON
2.0
4.0
SPK-Amp ON
1.0
4.0
Power-Down Mode (PDN pin = “L”)
(Note 25)
AVDD+PVDD+SVDD+TVDD
1
30
Note 11. Single-ended
29μVrms
Note 12. AVDD, PVDD
100mVpp
Note 13. SVDD 0.89Vpp
Note 14. Single-ended
Differential
0.425Vrms
Note 15. Single-ended
Differential
Note 16. Single-ended
Mixer
ON
Differential
Differential
kΩ
dB
dB
dB
dB
Vrms
Ω
dB
mA
mA
mA
mA
mA
mA
μA
typ.
,
0.32Vrms
,
0.23Vrms
Note 17. Single-ended
Mixer
ON
Differential
typ.90μVrms
Note 18. AVDD
100mVpp
Note 19. SVDD
100mVpp
Note 20. Single-ended Mode
Hz, 0.85Vrms
SPP pin SPN pin
SVDD-VSS2
Note 21.
VSS1 Load Capacitance
2
2
Note 22.
(PMVCM = PMOSC = PMCP = PMHPL = PMHPR = PMMHL = PMMHR = PMSPK = PMMSP = PMV1 =
PMV2 = PMV3 bits= “1”)
Note 23. Headphone-Amp
(PMVCM = PMOSC = PMCP = PMHPL = PMHPR = PMMHL = PMMHR = PMV1 bits= “1”,
PMSPK = PMMSP = PMV2 = PMV3 bits= “0”)
Note 24. Speaker-Amp
(PMVCM = PMOSC = PMCP = PMSPK = PMMSP = PMV1 bits= “1”,
PMHPL = PMHPR = PMMHL = PMMHR = PMV2 = PMV3 bits= “0”)
Note 25. All digital input pins are held at VSS1.
MS0949-J-01
-8-
2008/07
[AK4213]
Input Voltage: 1.13Vrms, Comm on Voltage=1.8V
Receiver-AMP
3.9Ω
3.9Ω
RVINN pin
RVINP pin
AK4213
SW 1
SPK-AMP
SPP pin
ALC
8Ω
Measurem ent point of
THD+N and Output Voltage
SPN pin
SW 2
Figure 2. Connection with external RCV-Amp
Measurement point of
AK4213
RVINP pin
Switch OFF Isolation
SW1
DC Input Voltage: 3.6V
SPK-AMP
SPP pin
ALC
50Ω
SPN pin
50Ω
RVINN pin
DC Input Voltage: 3.6V
SW2
AK4213
RVINP pin
SW1
50Ω
SPK-AMP
SPP pin
DC Input Voltage: 3.6V
ALC
Measurement point of
SPN pin
Switch OFF Isolation
DC Input Voltage: 3.6V
RVINN pin
50Ω
SW2
Figure 3. Measurement Circuit of Switch OFF Isolation
Headphone-amp negative voltage
PVEE pin
C1
CN pin
VSS3
CP pin
C2
Charge Pump Circuit
Figure 4. Charge Pump Circuit External Capacitor
MS0949-J-01
-9-
2008/07
[AK4213]
DC
(Ta= -40 85°C; AVDD=PVDD=2.6 ∼ 3.6V; SVDD=2.6 ∼ 5.5V, TVDD=1.6 ∼ 3.6V)
Parameter
Symbol
min
typ
High-Level Input Voltage (2.2V ≤ TVDD ≤ 3.6V)
VIH
70%TVDD
VIH
80%TVDD
(1.6V ≤ TVDD < 2.2V)
Low-Level Input Voltage (2.2V ≤ TVDD ≤ 3.6V)
VIL
VIL
(1.6V ≤ TVDD < 2.2V)
Low-Level Output Voltage
VOL
(2.0V ≤ TVDD ≤ 3.6V Iout = 3mA)
VOL
(1.6V ≤ TVDD < 2.0V Iout = 3mA)
Input Leakage Current
Iin
-
(Ta= -40 ∼ 85°C; AVDD=PVDD =2.6 ∼ 3.6V; SVDD=2.6 ∼ 5.5V TVDD=1.6 ∼ 3.6V)
Parameter
Symbol
min
Control Interface Timing: (Note 26)
SCL Clock Frequency
FSCL
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 27)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Capacitive load on bus
Cb
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
Power-down & Reset Timing
PDN Pulse Width (Note 28)
tPD
150
2
Note 26. I C Philips Semiconductors
Note 27.
300ns (SCL
)
Note 28.
PDN pin “L”
PDN pin “H”
MS0949-J-01
- 10 -
max
30%TVDD
20%TVDD
Units
V
V
V
V
0.4
20%TVDD
±2
V
V
μA
Typ
max
Units
-
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
-
-
ns
-
2008/07
[AK4213]
■
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Figure 5. I2C Bus Mode Timing
tPD
PDN
VIL
Figure 6. Power-down & Reset Timing
MS0949-J-01
- 11 -
2008/07
[AK4213]
■
&
AK4213
SD3-1 bits
Lch
Rch
Headphone-Amp Lch/Rch
VCOM
2dB step
/RIN
Power-Up
1 3 pins
+10dB
PMV3-1 bits
L/R
typ.16.4ms, max. 26.3ms
0.22μF
LIN
L1V3-0 bit
R1V3-0 bit
L2V3-0 bit
GAIN (dB)
R2V3-0 bit
L3V3-0 bit
R3V3-0 bit
FH
+10
EH
+8
:
CH
+4
BH
+2
AH
0
9H
−2
8H
−4
:
:
2H
−16
1H
−18
0H
−20
Table 1. Input Volume Setting
SD3 bit
SD2 bit
Input Mode
SD1 bit
0
Single-ended Mode
1
Differential Mode
Table 2. Input Mode Setting
MS0949-J-01
OFF
-20dB
- 12 -
Step
2dB
(default)
(default)
2008/07
[AK4213]
SPKL1 bit
LIN1/IN1−
VOL(L1V3-0 bits)
RIN1/IN1+
VOL(R1V3-0 bits)
PREL
SPKR1 bit
Mixing
SPKL2 bit
LIN2/IN2-
&
VOL(L2V3-0 bits)
SPKR2 bit
RIN2/IN2+
VOL(R2V3-0 bits)
Selector
To MIXO pin
SPKL3 bit
LIN3/IN3-
VOL(L3V3-0 bits)
RIN3/IN3+
VOL(R3V3-0 bits)
SPKR3 bit
HPLL1 bit
PREL
HPLR1 bit
Mixing
HPLL2 bit
&
HPLR2 bit
Selector
HPLL3 bit
To Lch Headphone-Amp
HPLR3 bit
HPRL1 bit
PREL
HPRR1 bit
Mixing
HPRL2 bit
&
HPRR2 bit
HPRL3 bit
Selector
To Rch Headphone-Amp
HPRR3 bit
Figure 7. Input Selector & Volume in Single-ended Mode (SD3-1 bits = “000”)
MS0949-J-01
- 13 -
2008/07
[AK4213]
SPKL1 bit
IN1−
PREL
VOL(L1V3-0 bits)
Mixing
IN1+
SPKL2 bit
IN2−
VOL(L2V3-0 bits)
&
Selector
IN2+
To MIXO pin
SPKL3 bit
IN3−
VOL(L3V3-0 bits)
IN3+
HPLL1 bit
PREL
Mixing
HPLL2 bit
&
To Lch Headphone-Amp
Selector
HPLL3 bit
HPRL1 bit
PREL
Mixing
HPRL2 bit
&
To Rch Headphone-Amp
Selector
HPRL3 bit
Figure 8. Input Selector and Volume in Differential Mode (SD3-1 bits = “111”)
MS0949-J-01
- 14 -
2008/07
[AK4213]
■ Class-D
ALC
PWM
SPP / SPN pin
MIXO pin SPIN pin
BPF
SPIN pin 0.1μF
SPIN pin
(Band Pass Filter)
MIXO pin
MIXO pin
BTL
ALC
BPF
&
DC
SPIN pin
SPGA5-0bits
0.015μF
1kΩ
typ.26kΩ
-
Mixing & Selector
0.033μF
+
ALC
AK4213
Figure 9. Example of Band-Pass-Filter for Speaker (BPF = typ. 442Hz to 4.83kHz @ -3dB)
MIXO pin
SPIN pin
SPGA5-0bits
0.1μF
typ.26kΩ
-
Mixing & Selector
+
ALC
AK4213
Figure 10. Example of normal connection for Speaker (fc = typ. 66Hz @ -3dB)
0.7Vrms
0.6W(/1ch)
Lch/R
ALC = OFF (SPGA=0dB)
Lch/Rch Input Volume -6dB
[(Lch + Rch) /2]
ON
+9.82dB
−7.5dBV ∼ −9.5dBV
LMTH bit = “1”
REF5-0 bits
“0”
Input
ALC = ON (ALC bit = “1”)
−11.5dBV ∼ −13.5dBV
Class-D
ALC
LMTH bit =
+11.76dB
Input Volume
Mixing & Selector
ALC OFF: SPGA5-0 bits
Class-D
(-1.94dB @ Vol=0dB)
(0dB)
ALC ON: REF5-0 bits
(+11.76dB)
Figure 11. Speaker-Amp Path Level Diagram
MS0949-J-01
- 15 -
2008/07
[AK4213]
PMSPK bit
“0”
ALC + SPK-Amp
30ms(typ.), 48ms(max).
PMSPK bit = “0” → “1”
1.6ms
SPGA5-0 bits
PMSPK bits
Speaker-Amp
0
Power-down
1
Power-up & Output
Table 3. Speaker-Amp
(default)
■ Bypass Mode
BYPE bit = “1” SW1=SW2=ON
SPP/SPN pin
Bypass Mode
RVINP pin, RVINN pin
SPP pin, SPN pin
SPK-Amp Hi-Z
BYPE bit = “0” (SW1=SW2=OFF)
PMSPK bit = “1”
BYPE bit
(Addr=00H 01H, 02H) “0”
Bypass Mode
OFF
Bypass
PMVCM bit = “1”
VCOM
Mode
PMSPK bit
BYPE bit
Mode
0
0
Power-down (SPP/SPN pins are Hi-Z)
0
1
Bypass Mode
1
x
Speaker Mode
Table 4. Speaker and Receiver Modes (x: Don’t care)
Receiver-AMP
3.9Ω
3.9Ω
RVINN pin
RVINP pin
AK4213
SW1
SPK-AMP
SPP pin
ALC
Speaker
SPN pin
SW2
Figure 12. Bypass Mode
1. Speaker Mode Î Bypass Mode
a. Spkeaer Amp
: PMSPK bit = “1” Æ “0”
b. Wait more than 500μs
c. Bypass Mode
( SW1=SW2=ON): BYPE bit = “0” Æ “1”
Figure 18
2. Bypass Mode Î Speaker Mode
a. Bypass Mode
(SW1=SW2=OFF): BYPE bit = “1” Æ “0”
b. Speaker-Amp
:
Figure 18
MS0949-J-01
- 16 -
2008/07
[AK4213]
■ ALC
ALC bit = “1”
SPGA5-0 bit
ALC
ALC
ALC bit = “0”
(1) ALC
ALC
(LMAT1-0 bits)
ALC
(LMTH bit)
ALC
ATT
SPGA
ZELMN bit=“0”(
)
ALC
SPGA
ALC
ZELMN bit=“1”(
200μs)
)
ZTM1-0 bits
ALC
SPGA
(
:typ. 125μs, max
1 step
LMAT1-0 bit
ALC bit
LMTH bit
0
1
Note: ALC
“0”
ALC
ALC
ALC Output ≥ −7.5dBV
ALC Output ≥ −11.5dBV
ALC
ALC
−7.5dBV > ALC Output ≥ −9.5dBV
−11.5dBV > ALC Output ≥ −13.5dBV
(default)
Table 5. ALC
ZELMN bit LMAT1 bit LMAT0 bit ALC
ATT
0
0
1 step
0.5dB
0
1
2 step
1.0dB
0
1
0
4 step
2.0dB
1
1
8 step
4.0dB
1
x
x
1step
0.5dB
Table 6. ALC
ATT
(x: Don’t’ care)
ZTM1 bit
0
0
1
1
ZTM0 bit
0
1
0
1
Table 7. ALC
Zero Crossing Timeout
typ.
max
16.4ms
26.3ms
32.8ms
51.5ms
65.6ms
105.0ms
131.2ms
210.0ms
(default)
(default)
(2) ALC
MS0949-J-01
- 17 -
2008/07
[AK4213]
ALC
WTM2-0 bits
(LMTH bit)
(REF5-0 bits)
RGAIN1-0 bit
ALC
WTM2-0 bits
ZTM1-0 bits
RGAIN1-0 bits = “10”
ALC
ALC
ALC
ALC
ALC
SPGA
WTM2-0 bits
ALC
ALC
(LMTH bit)
ALC
(
) ≤ (ALC
)<(
(
) > (ALC
)
ALC
ALC
)
ALC
WTM2 bit
0
0
0
0
1
1
1
1
Recovery Waiting Timer
typ.
max
0
0
16.4ms
26.3ms
0
1
32.8ms
51.5ms
1
0
65.6ms
105.0ms
1
1
131.2ms
210.0ms
0
0
262.4ms
419.9ms
0
1
524.8ms
839.7ms
1
0
1049.6ms
1679.4ms
1
1
2099.2ms
3358.8ms
Table 8. ALC Recovery Waiting Timer Period
WTM1 bit
RGAIN1
0
0
1
1
WTM0 bit
RGAIN0
GAIN STEP
0
1 step
0.5dB
1
2 step
1.0dB
0
0 step
0dB
1
Reserved
Table 9. ALC Recovery GAIN Step
REF5-0 bits
GAIN (dB)
3FH
+19.5
3EH
+19.0
3DH
+18.5
3CH
+18.0
:
:
19H
+0.5
18H
0.0
17H
−0.5
:
:
02H
−11.0
01H
−11.5
00H
−12.0
Table 10. ALC
MS0949-J-01
ZTM1-0 bits
- 18 -
(default)
(default)
(Only limiter operation)
Step
(default)
0.5dB
2008/07
[AK4213]
ALC
Table 11
ALC
ALC SPGA5-0 bit
Register Name
LMTH
ZELMN
WTM2-0
REF5-0
LMAT1-0
RGAIN1-0
ZTM1-0
ALC
Comment
Limiter detection Level
Limiter Zero crossing Enable
Recovery waiting period
Maximum gain at recovery operation
Limiter ATT Step
Recovery GAIN Step
Zero-crossing Timeout
ALC Enable bit
Table 11. ALC
ALC
(PMSPK bit = “0”)
ALC
Data
0
0
101
3CH
00
00
01
1
Parameter
−7.5dBV
Limiter Zero Crossing Enable
typ.524.8ms
+18dB
0.5dB
0.5dB
typ.32.8ms
Enable
(ALC bit = “0” )
- LMTH, LMAT1-0, WTM2-0, RGAIN1-0, REF5-0, ZTM1-0, ZELMN
Example:
Limiter: Zero Crossing Enable
Recovery Cycle = typ. 524.8ms
Limiter and Recovery Step = 1
Maximum Gain = +18dB
Limiter Detection Level = −7.5dBV
ALC bit = “1”
ALC=OFF
WR (SPGA5-0)
* The value of SPGA should be
(1) Addr=0EH, Data=3CH
the same or smaller than REF’S.
WR (REF5-0)
(2) Addr=0FH, Data=3CH
WR (ZTM1-0, WTM2-0)
(3) Addr=10H, Data=0DH
WR (ZELMN, LMAT1-0, RGAIN1-0, LMTH, ALC=”1”)
(4) Addr =11H, Data=40H
ALC Operation
Note : WR : Write
Figure 13. ALC
MS0949-J-01
- 19 -
2008/07
[AK4213]
■
(SPGA:
ALC bit = “0”
1.
2.
3.
)
SPGA5-0 bits
ALC
ALC
SPGA
(ZTM1-0, LMTH
SPGA5-0 bits
ZTM1-0 bits
1.6ms
SPGA5-0 bits
(PMSPK bit = “1”)
SPGA5-0 bits
SPGA5-0
3FH
3EH
3DH
3CH
:
19H
18H
17H
:
02H
01H
00H
)
PMSPK bit = “0”
PMSPK bit = “1”
0dB
GAIN (dB)
Step
+19.5
+19.0
+18.5
+18.0
:
+0.5
0.5dB
0.0
−0.5
:
−11.0
−11.5
−12.0
Table 12. Speaker-Amp Volume Setting
(default)
SPGA5-0 bits
ALC bit
ALC Status
Disable
Enable
SPGA5-0 bits
Internal SPGA
3CH(+18dB)
3CH(+18dB)
3CH(+18dB) --> 19H(+0.5dB)
(1)
SPGA
3CH(+18dB)
(2)
Figure 14. ALC
(1) ALC bit = “1”
(2) ALC
SPGA
Disable
SPGA
ALC
ALC Disable
ALC Enable
2
ALC bit = “0”
ALC bit = “1”
MS0949-J-01
- 20 -
2008/07
[AK4213]
■
PVDD pin
(PVEE)
PMCP bit = “1”
PMVCM=PMOSC bits= “1”
typ. 6.2ms, max. 10ms
PMHPR bit = “1”
Figure 17
■
(PMHPL or
)
(HPL/HPR pins)
SVDD
PVDD
VSS3 (0V)
min. 16Ω
0.69Vrms (= 30mW @ 16Ω)
L/R
DC
(HPGA4-0 bits = “19H” (0dB)) 0.7Vrms
HPL/HPR
HPGA4-0 bits
HPGA4-0 bit
+12dB
-50dB
2dB step
HPGA4-0 bits
GAIN (dB)
Step
1FH
+12
1EH
+10
:
1AH
+2
19H
0
18H
−2
2dB
17H
−4
16H
−6
:
:
2H
−46
1H
−48
0H
−50
Table 13. Headphone-Amp Volume Setting
Input
(default)
Input Volume
Mixing & Selector
HP Volume
HP-Amp
(-1.94dB @ Vol =0dB)
(0dB)
(HPGA=0dB)
(+1.94dB)
Figure 15. Headphone-Amp Path Level Diagram
MS0949-J-01
- 21 -
2008/07
[AK4213]
HPMTN bit
ON/OFF
“1”
PMHPL, PMHPR bit
HPR pin VSS3
(typ)
PMCP/PMVCM
x
x
1
1
HPMTN bit
“0”
PTS1-0 bits, MOFF bit
“0”
HPZ bit= 0”
20
HPL,
25k
(typ) HPZ bit = “1”
typ. 16.4ms, max. 26.3ms
PMHPL/R
0
0
1
1
HPMTN
x
x
0
1
Table 14.
HPZ
0
1
0
0
Mode
HPL/R pins
Power-down & Mute Pull-down by 20Ω (typ) (default)
Power-down
Pull-down by 25kΩ (typ)
Mute
VSS3
Normal Operation
Normal Operation
(x: Don’t’ care)
Wired OR
PMVCM=PMCP=PMOSC=HPZ bits = “1”
HP-Amp Wired OR
HP-Amp
HP-Amp
PVDD[Vpp]
AK4213 HP-Amp
HPL pin
AK4213
Headphone
HPR pin
Another
HP-Amp
Figure 16.
MS0949-J-01
Wired OR
- 22 -
2008/07
[AK4213]
■
Headphone-Amp
ON/OFF
PTS1-0 bits
Enable/Disable MOFF bit
HPMTN bit
Disable
Enable
“1”
ON/OFF
Table 15
PTS1-0 bits
Address
Register Name
Enable / Disable
0DH
HPMTN bit
MOFF bit
Table 15. Registers with Transition Time
MUTE ON/OFF Time
typ.
max.
0
0
16.4ms
26.3ms
0
1
32.8ms
51.5ms
1
0
65.6ms
105.0ms
1
1
131.2ms
210.0ms
Table 16. Headphone-Amp Mute ON/OFF Transition Time
PTS1
PTS0
(default)
■
CLASS-D
THDET bit
“1”
PDN pin
THDET bit
PMVCM bit = “1”
1.
2.
3.
4.
5.
Bypass Mode
VCOM Power-Up; PMVCM bit = “0” Æ “1”
Wait more than 1ms
Bypass Mode Enable: BYPE bit = “0” Æ “1”
Bypass Mode Disable: BYPE bit = “1” Æ “0”
VCOM Power-down; PMVCM bit = “1” Æ “0”
■
PDN pin = “L”
(AVDD, PVDD, SVDD, TVDD)
PDN pin “H”
(PDN pin = “L” Æ “H”)
Input Volume, VCOM,
Mixer, Headphone-Amp, Speaker-Amp, Charge-Pump
PDN pin
MS0949-J-01
- 23 -
2008/07
[AK4213]
■
Power-Up/Down
1) HP-Amp
Power Supply
(1)
PDN pin
(2)
PMVCM bit
PMOSC bit
PMMHL/R bit
PMCP bit
(3)
PVEE pin
0V
0V
PVEE
≥ 0s
(10)
PMVx bits
Input Volume
Output State
(4)
Hi-z
PMHPL/R bit
Hi-z
VCOM
(5)
HPMTN bits
HPL/HPR pins
0V
Normal
MUTE
(6)
(7)
MUTE
(8)
0V
(9)
Figure 17. HP-Amp
(1)
PDN pin “L”Æ“H”
AK4213
150ns
“L”
PDN pin = “L”
(AVDD, TVDD, PVDD, SVDD)
PDN pin “H”
(2) PTS1-0, MOFF, HPGA4-0, SD -1 bits
(3) Regulator
VCOM HP-Amp Mixer & Selector
PMCP = PM HL = PMMHR = PMOSC = PMVCM bit = “0” Æ “1”
PVEE pin
max. 10ms
PVEE
(4)
: PMVx bit = “0” Æ “1”
(L1V3-0, L2V3-0, L3V3-0, R1V3-0, R2V3-0, R3V3-0 bits)
HPLL3-1, HPLR3-1, HPRR3-1, HPRL3-1 its
max. 26.3ms
(5) PMCP PMHPL/R bits
“1”
(6)
(7)
(8)
(9)
(10)
“1”
Charge-Pump
Headphone-Amp Charge-Pump
: PMHPL/R bits = “0” Æ “1”
GND
: HPMTN bit = “0” Æ “1”
PTS1-0 bits
: HPMTN bit = “1” Æ “0”
PTS1-0 bits, MOFF bit
: PMHPL//R bits = “1” Æ “0”
VCOM HP-Amp Mixer & Selector
:
PMCP bit = PM
bit = PMMHR = PMOSC = PMVCM bit = “1” Æ “0”
PVEE pin
PVEE pin
typ.17.5kΩ
MS0949-J-01
- 24 -
:
PMHPL/R bits
max 26.3ms
MOFF bit
0V
2008/07
[AK4213]
2) SPK-Amp
Power Supply
(1)
PDN pin
(2)
PMVCM bit
PMOSC bit
Don’t care
Clock Input
Don’t care
≥ 0s
PMVx bits
Input Volume
Output State
PMMSP bit
PMSPK bit
(3)
Hi-Z
VCOM
Hi-Z
(8)≥ 500us
(4)≥ 0s
(5) ≥ 1.6ms
(5)≥ 1.6ms
SPGA bits
Default
Default
xxH
xxH
Default
ALC bit
(6)
ALC state
(6)
Disable
Enable
(7)
SPP/SPN pins
Enable
Disable
Disable
(7)
Hi-Z
Normal
Hi-Z
Normal
Hi-Z
150ns
“L”
Figure 18. SPK-Amp
(1)
PDN pin “L” Æ “H”
AK4213
PDN pin = “L”
(AVDD, TVDD, PVDD, SVDD)
PDN pin “H”
(2) VCOM
: PMVCM= PMOSC: “0” Æ “1”
SD3-1 bits
(3)
: PMVx bit = “0” Æ “1”
(L1V3-0, L2V3-0, L3V3-0, R1V3-0, R2V3-0, R3V3-0 bits)
SPKL3-1, SPKR3-1 its
max. 26.3ms
(4) SPK-Amp Mixer & Selector SPK-Amp
(5) SPGA5-0bit
: PMSPK bit
1
(6) ALC
:max. 30ms
ALC Enable
(7) PMSPK bit = “0” Æ “1”
(8)
PMMSP, PMSPK bit = “1” Æ “0”
MS0949-J-01
: PM SP=PMSPK bits = “0”Æ “1”
1.6ms
SPGA5-0 bit
ALC
ALC
”
max 48ms
500us
min 0.5ms
- 25 -
PMVCM,PMOSC bit = 1” Æ “0”
2008/07
[AK4213]
3) HP-Amp or SPK-Amp
: HP-Amp
LIN1/RIN1
LIN2/RIN2
(1)
HPLL1/R1 bits
(2)
≥ 0s
PMV1 bit
VCOM
LIN1/RIN1 Volume
Output State
Hi-Z
Output
(5)
≥ 0s
HPLL2/R2 bits
(3)
PMV2 bit
(4)
LIN2/RIN2 Volume
Output State
Hi-Z
Output
Figure 19. HP-Amp
(1)
(2)
(3)
(4)
(5)
LIN1/RIN1
HP-Amp
LIN1/RIN1 Input Volume
RLIN2/RIN2 Input Volume
LIN2/RIN2
LIN2/RIN2
HP-Amp
MS0949-J-01
OFF: HPLL1 = HPLR1 = “1” Æ “0”
: PMV1 = “1” Æ “0”
: PMV2 = “0” Æ “1”
max.26.3ms
ON: HPLL2 = HPLR2 = “0” Æ “1”
- 26 -
2008/07
[AK4213]
■
AK4213 I2C
Fast-Mode (max:400kHz)
SDA, SCL pins
(TVDD+0.3)V
1. WRITE
I2C
(Start Condition)
(Figure 26)
8
Figure 20
“H”
SCL
(R/W)
AK4213
“0”
(
7
“0010011”
(Acknowledge)
SDA
“1”
R/W
(Figure 27)
)
8
8
(Stop Condition)
(Figure 26)
“H”
“L”
7
(Figure 21)
2
22)
3
(Figure 23) AK4213
IC
“H”
SDA
SCL
MSB first
MSB first
“H”
AK4213
R/W
(Figure
SDA
“L”
1
“12H”
“00H”
“H”
SDA
SCL
“L”
(Figure 28)
“H”
SCL
“L”
“H”
SDA
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 20. I2C
0
0
1
0
Figure 21.
0
0
0
D6
D5
Figure 23.
MS0949-J-01
1
1
R/W
A3
A2
A1
A0
D3
D2
D1
D0
1
A4
Figure 22.
D7
0
2
D4
3
- 27 -
2008/07
[AK4213]
2. READ
R/W bit
“1”
AK4213
READ
“12H”
“00H”
AK4213
2
READ
2-1.
AK4213
AK4213
(READ
WRITE
“n+1”
(R/W bit = “1”)
READ
)
“n”
1
READ
S
T
A
R
T
S
T
O
P
R/W="1"
Slave
S Address
SDA
Data(n)
Data(n+1)
Data(n+2)
MA
AC
SK
T
E
R
A
C
K
Data(n+x)
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
P
MN
AA
SC
T
EK
R
Figure 24. CURRENT ADDRESS READ
2-2.
READ
(R/W bit = “1”)
WRITE
WRITE
= “0”)
AK4213
(R/W bit = “1”)
READ
(R/W bit
AK4213
1
READ
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
MA
AC
S K
T
E
R
Data(n+x)
MA
AC
S
T K
E
R
MA
AC
S
T K
E
R
P
MN
A A
S
T C
E K
R
Figure 25. RANDOM ADDRESS READ
MS0949-J-01
- 28 -
2008/07
[AK4213]
SDA
SCL
S
P
start condition
stop condition
Figure 26.
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 27. I2C
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 28. I2C
MS0949-J-01
- 29 -
2008/07
[AK4213]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
Register Name
Power Management 0
Power Management 1
Power Management 2
Mode Control 0
Lch Headphone Mixer
Rch Headphone Mixer
Speaker Mixer
Reserved
Input Volume #1
Input Volume #2
Input Volume #3
Reserved
Mode Control 1
Headphone PGA Control
Speaker PGA Control
ALC Mode Control 1
ALC Mode Control 2
ALC Mode Control 3
TEST
D7
D6
D5
D4
D3
D2
D1
D0
0
PMMHR
PMMHL
PMHPR
PMHPL
PMCP
PMOSC
PMVCM
0
0
0
0
0
PMMSP
0
PMSPK
0
0
0
0
0
PMV3
PMV2
PMV1
THDET
0
0
BYPE
0
SD3
SD2
SD1
0
0
HPLR3
HPLL3
HPLR2
HPLL2
HPLR1
HPLL1
0
0
HPRR3
HPRL3
HPRR2
HPRL2
HPRR1
HPRL1
0
0
SPKR3
SPKL3
SPKR2
SPKL2
SPKR1
SPKL1
0
0
0
0
0
0
0
0
R1V3
R1V2
R1V1
R1V0
L1V3
L1V2
L1V1
L1V0
R2V3
R2V2
R2V1
R2V0
L2V3
L2V2
L2V1
L2V0
R3V3
R3V2
R3V1
R3V0
L3V3
L3V2
L3V1
L3V0
0
0
0
0
0
0
0
0
0
0
MOFF
0
PTS1
PTS0
0
0
0
HPZ
HPMTN
HPGA4
HPGA3
HPGA2
HPGA1
HPGA0
0
0
SPGA5
SPGA4
SPGA3
SPGA2
SPGA1
SPGA0
0
0
REF5
REF4
REF3
REF2
REF1
REF0
0
0
0
ZTM1
ZTM0
WTM2
WMT1
WMT0
0
ALC
ZELMN
LMAT1
LMAT0
RGAIN1
RGAIN0
LMTH
0
0
0
0
0
0
0
0
PDN pin = “L”
PDN pin “L”
Note 29: “0”
Note 30:
MS0949-J-01
“1”
00H ∼ 12H
- 30 -
2008/07
[AK4213]
■ Register Definitions
Addr
00H
Register Name
Power Management 0
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
PMMHR
PMMHL
PMHPR
PMHPL
PMCP
PMOSC
PMVCM
RD
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PMVCM: VCOM, Headphone AMP
0: Power OFF (default)
1: Power ON
Regulator
PMOSC: Internal Oscillator
0: Power OFF (default)
1: Power ON
PMCP: Charge Pump
0: Power OFF (default)
1: Power ON
PMHPL: Lch Headphone-Amp
0: Power OFF (default)
1: Power ON
PMHPR: Rch Headphone-Amp
0: Power OFF (default)
1: Power ON
PMMHL: Lch Headphone-Amp
0: Power OFF (default)
1: Power ON
Mixing & Selector
PMMHR: Rch Headphone-Amp
0: Power OFF (default)
1: Power ON
Mixing & Selector
MS0949-J-01
- 31 -
2008/07
[AK4213]
Addr
01H
Register Name
Power Management 1
R/W
Default
D7
0
RD
0
D6
0
RD
0
PMSPK: Speaker-Amp
0: Power OFF (default)
1: Power ON
PMSPK bit = 0
SPP pin
D5
0
RD
0
SPN pin
D4
0
RD
0
D4
0
RD
0
D3
D2
0
PMMSP
RD
0
R/W
0
D1
0
RD
0
D3
0
RD
0
D2
PMV3
R/W
0
D1
PMV2
R/W
0
D0
PMSPK
R/W
0
Hi-Z
PMMSK: Speaker-Amp Mixing & Selector
0: Power OFF (default)
1: Power ON
Addr
02H
Register Name
Power Management 2
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D0
PMV1
R/W
0
PMV1: Input Volume #1
0: Power OFF (default)
1: Power ON
PMV2: Input Volume #2
0: Power OFF (default)
1: Power ON
PMV3: Input Volume #3
0: Power OFF (default)
1: Power ON
PDN pin
“L”
00H, 01H, 02H
“0”
18μA(typ)
PDN pin = “L”
MS0949-J-01
- 32 -
2008/07
[AK4213]
Addr
03H
Register Name
Mode Control 0
R/W
Default
D7
THDET
RD
0
D6
0
RD
0
D5
0
RD
0
D4
BYPE
R/W
0
D3
0
RD
0
D2
SD3
R/W
0
D1
SD2
R/W
0
D0
SD1
R/W
0
SD1: Input mode setting of LIN1/IN1- and RIN1/IN1+ pins
0: Single-ended Mode (default)
1: Differential Mode
SD2: Input mode setting of LIN2/IN2- and RIN2/IN2+ pins
0: Single-ended Mode (default)
1: Differential Mode
SD3: Input mode setting of LIN3/IN3- and RIN3/IN3+ pins
0: Single-ended Mode (default)
1: Differential Mode
BYPE: Bypass Mode
0: Disable (default)
1: Enable
PMSPK bit = “0”
BYPE bit
“ ”
“1”
PMSPK bit = “1”
AK4213 speaker-amp
BYPE bit
THDET: Thermal Shutdown
0: Normal Operation (default)
1: Thermal Shutdown
Addr
04H
05H
06H
07H
Register Name
Lch Headphone Mixer
Rch Headphone Mixer
Speaker Mixer
Reserved
R/W
Default
D7
0
0
0
0
RD
0
D6
0
0
0
0
RD
0
D5
HPLR3
HPRR3
SPKR3
0
R/W
0
D4
HPLL3
HPRL3
SPKL3
0
R/W
0
D3
HPLR2
HPRR2
SPKR2
0
R/W
0
D2
HPLL2
HPRL2
SPKL2
0
R/W
0
D1
HPLR1
HPRR1
SPKR1
0
R/W
0
D0
HPLL1
HPRL1
SPKL1
0
R/W
0
D7
R1V3
R2V3
R3V3
0
R/W
1
D6
R1V2
R2V2
R3V2
0
R/W
0
D5
R1V1
R2V1
R3V1
0
R/W
1
D4
R1V0
R2V0
R3V0
0
R/W
0
D3
L1V3
L2V3
L3V3
0
R/W
1
D2
L1V2
L2V2
L3V2
0
R/W
0
D1
L1V1
L2V1
L3V1
0
R/W
1
D0
L1V0
L2V0
L3V0
0
R/W
0
Input Mixers: (Figure 7)
0: OFF (default)
1: ON
Addr
08H
09H
0AH
0BH
Register Name
Input Volume #1
Input Volume #2
Input Volume #3
Reserved
R/W
Default
Input Volumes: Default: 0dB (Table 1)
MS0949-J-01
- 33 -
2008/07
[AK4213]
Addr
0CH
Register Name
Mode Control 1
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
MOFF
R/W
0
D4
0
RD
0
D3
PTS1
R/W
0
D2
PTS0
R/W
0
D1
0
RD
0
D0
0
RD
0
R/W
0
D4
HPGA4
R/W
1
D3
HPGA3
R/W
1
D2
HPGA2
R/W
0
D1
HPGA1
R/W
0
D0
HPGA0
R/W
1
D5
SPGA5
R/W
0
D4
SPGA4
R/W
1
D3
SPGA3
R/W
1
D2
SPGA2
R/W
0
D1
SPGA1
R/W
0
D0
SPGA0
R/W
0
PTS1-0: Headphone-Amp Mute ON/OFF Transition Time
Default: “00”; typ. 16.4ms (Table 16)
MOFF: HPMTN bit
0: Enable (default)
1: Disable
Addr
0DH
Register Name
Headphone PGA Control
R/W
Default
D7
0
RD
0
D6
HPZ
R/W
0
D5
HPMTN
HPGA4-0: Headphone-Amp Volume Setting
Default: 19H; 0dB (Table 13)
HPMTN: Headphone-Amp Mute
0: Mute (default)
1: Normal Output
HPZ: Headphone-Amp
0: Ground Mode (default)
HPL/HPR pins
VSS3
1: Hi-Z Mode
HPL/HPR pins
Hi-Z (typ. 25kΩ)
Addr
0EH
Register Name
Speaker PGA Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
SPGA5-0: Speaker-Amp Volume Setting
Default: 18H; 0dB (Table 12)
PMSPK bit = “0”
SPGA5-0 bits
PMSPK bit = “1”
SPGA5-0 bits
Addr
0FH
Register Name
ALC Mode Control 1
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
REF5
R/W
1
PMSPK bit = “0”
0dB
D4
REF4
R/W
1
D3
REF3
R/W
1
D2
REF2
R/W
1
D1
REF1
R/W
0
D0
REF0
R/W
0
REF5-0: ALC
Default: 3CH; +18dB (Table 10)
MS0949-J-01
- 34 -
2008/07
[AK4213]
Addr
10H
Register Name
ALC Mode Control 2
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
ZTM1
R/W
0
D3
ZTM0
R/W
1
D2
WTM2
R/W
1
D1
WTM1
R/W
0
D0
WTM0
R/W
1
WTM2-0: ALC
Default: “101”, typ. 524.8ms (Table 8)
ZTM1-0: ALC
Default: “01”, typ. 32.8ms (Table 7)
Addr
11H
Register Name
ALC Mode Control 3
R/W
Default
LMTH: ALC
Default: “0” (Table 5)
D7
0
RD
0
D6
ALC
R/W
0
D5
D4
D3
D2
D1
ZELMN
LMAT1
LMAT0
RGAIN1
RGAIN0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
D0
LMTH
R/W
0
D3
0
RD
0
D2
0
RD
0
D1
0
RD
0
D0
0
RD
0
/
RGAIN1-0: ALC
Default: “00”; 1 step (Table 9)
LMAT1-0: ALC
ATT
Default: “00”; 1 step (Table 6)
ZELMN: ALC
0: Enable (default)
1: Disable
ALC: ALC
0: ALC Disable (default)
1: ALC Enable
“1” ALC
Addr
12H
Register Name
TEST
R/W
Default
“0”(Disable)
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
“0”
MS0949-J-01
- 35 -
2008/07
[AK4213]
Figure 29
(AKD4213)
0.22µ
0.22µ
0.22µ
0.22µ
0.22µ
2.2µ
+
0.22µ
Analog Input
Analog Input
0.1µ
Power Supply
3.0∼5.5V
Headphone
LIN3/IN3-
HPR
VCOM
RIN1/IN+
SVDD
+
LIN1/IN1-
0.1µ
RIN3/IN3+
HPL
RIN2/IN2+
SPN
VSS2
10µ
SPP
Speaker
(Note)
2.2µ
PVEE
VSS3
+
PDN
LIN2/IN2-
TEST
SPIN
RVINN
RVINP
3.9
Top View
3.9
0.1µ
PVDD
SDA
TVDD
Analog Input
0.1µ
CP
CN
SCL
VSS1
AVDD
MIXO
+
2.2µ
(Note)
0.1µ
0.1µ
uP
Power Supply
Power Supply
2.6∼3.6V
+
1.6∼3.6V
10µ
Analog Ground
Digital Ground
Figure 29.
Note:
-
CP pin
CN pin
PVSS pin
PVEE pin
CP
-
VSS1, VSS2, VSS3
VCOM pin
2.2μF
VCOM pin
LINx/RINx(x=1~3) pins
VSS1
-
MS0949-J-01
ESR(
VSS3
- 36 -
)
0.1μF
0.22μF
2008/07
[AK4213]
29pin CSP ( 3.0mm
3.0mm, 0.5mm pitch, BGA)
Bottom View
Top View
B
0.23
2.96 ± 0.05
0.50
0.48
5
5
4213
3
XXXX
2
A
4
2.96 ± 0.05
4
3
2
1
1
B
C
D
E
F
F
E
D
φ 0.30 ± 0.05
0.65 ± 0.05
A
C
B
φ 0.05
A
M
S AB
S
0.25 ± 0.05
0.08
MS0949-J-01
S
- 37 -
2008/07
[AK4213]
4213
XXXX
1
A
XXXX: Date code (4 digit)
Pin #A1 indication
Date (YY/MM/DD)
08/05/19
08/07/09
Revision
00
01
Reason
Page
Contents
3
■
32
AK4213EC → AK4213ECB
■ Register Definitions
01H GDDLY bit
37
•
•
•
(
)
•
•
•
MS0949-J-01
- 38 -
2008/07