[AK4440] AK4440 192kHz 24-Bit 8ch DAC with 2Vrms Output AK4440 DAC 2Vrms 24 8ch ΔΣ (SCF) 192kHz Set-Top-Box, DVD/BD, AV Receivers, Home Theaters 2Vrms AK4440 30pin VSOP : 8kHz ~ 192kHz 128 64 2 32 4 Slow roll-off 24 8 FIR SCF 2Vrms (32kHz, 44.1kHz, 48kHz ) µP I/F (I2C, 3 ) I/F : , (16bit, 20bit, 24bit), I2S, TDM : 256fs, 384fs, 512fs or 768fs or 1152fs ( ) 128fs, 192fs, 256fs or 384fs (2 ) 128fs or 192fs (4 ) THD+N: -93dB Dynamic Range: 105dB : +4.5V ~ +5.5V Ta = -20 to 85°C : 30 VSOP (9.7mm x 7.6mm) MS1088-J-00 2009/10 -1- [AK4440] Audio I/F LOUT1 LPF SCF DAC ROUT1 LPF SCF DAC LOUT2 LPF SCF DAC ROUT2 LPF SCF DAC LOUT3 LPF SCF DAC ROUT3 LPF SCF DAC LOUT4 LPF SCF DAC ROUT4 LPF SCF DAC MCLK LRCK BICK SDTI1 SDTI2 SDTI3 SDTI4 PCM Control Register 3-wire 2 or I C AK4440 Charge Pump CP CN 1μ VEE VSS2 VDD VSS1 AVDD 1μ Block Diagram MS1088-J-00 2009/10 -2- [AK4440] ■ AK4440EF AKD4440 -20 ∼ +85°C 30pin VSOP Evaluation Board for AK4440 ■ MCLK 1 30 VDD BICK 2 29 VSS2 SDTI1 3 28 CP LRCK 4 27 CN TEST 5 26 VEE SMUTE/CSN/CAD0 6 25 LOUT1 ACKS/CCLK/SCL 7 24 ROUT1 DIF0/CDTI/SDA 8 23 LOUT2 SDTI2 9 22 ROUT2 SDTI3 10 21 LOUT3 SDTI4 11 20 ROUT3 TDM0B 12 19 LOUT4 DEM0 13 18 ROUT4 I2C/DEM1 14 17 VSS1 P/S 15 16 AVDD AK4440 Top View MS1088-J-00 2009/10 -3- [AK4440] No. 1 Pin Name MCLK I/O I 2 3 4 5 6 BICK SDTI1 LRCK TEST SMUTE CSN CAD0 ACKS I I I O I I I I I 9 10 11 12 CCLK SCL DIF0 CDTI SDA SDTI2 SDTI3 SDTI4 TDM0B I I I/O I I I I 13 14 DEM0 I2C I I 15 DEM1 P/S I I 16 17 18 19 20 21 22 23 24 25 26 AVDD VSS1 ROUT4 LOUT4 ROUT3 LOUT3 ROUT2 LOUT2 ROUT1 LOUT1 VEE O O O O O O O O O 27 CN I 28 CP I 7 8 Function Master Clock Input Pin An external TTL clock should be input on this pin. Audio Serial Data Clock Pin DAC1 Audio Serial Data Input Pin L/R Clock Pin TEST pin. This pin should be open. Soft Mute Pin in parallel mode “H”: Enable, “L”: Disable Chip Select Pin in serial 3-wire mode Chip Address Pin in serial I2C mode Auto Setting Mode Pin in parallel mode “L”: Manual Setting Mode, “H”: Auto Setting Mode Control Data Clock Pin in serial 3-wire mode Control Data Clock Pin in serial I2C mode Audio Data Interface Format Pin in parallel mode Control Data Input Pin in serial 3-wire mode Control Data Pin in serial I2C mode DAC2 Audio Serial Data Input Pin DAC3 Audio Serial Data Input Pin DAC4 Audio Serial Data Input Pin TDM I/F Format Mode in parallel control mode “L”: TDM256 mode, “H”: Normal mode De-emphasis Filter Enable Pin. in parallel mode Control Mode Select Pin in serial mode “L”: 3-wire Serial, “H”: I2C Bus De-emphasis Filter Enable Pin in parallel mode Parallel/Serial Select Pin (Internal pull-up pin, typ 100kΩ) “L”: Serial control mode, “H”: Parallel control mode DAC Analog Power Supply Pin: 4.5V∼5.5V Ground Pin DAC4 Rch Analog Output Pin DAC4 Lch Analog Output Pin DAC3 Rch Analog Output Pin DAC3 Lch Analog Output Pin DAC2 Rch Analog Output Pin DAC2 Lch Analog Output Pin DAC1 Rch Analog Output Pin DAC1 Lch Analog Output Pin Negative Voltage Output Pin Connect to VSS2 with a 1.0μF capacitor that should have the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the VSS2 pin. Non polarity capacitors can also be used. Negative Charge Pump Capacitor Terminal Pin Connect to CP with a 1.0μF capacitor that should have the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used. Positive Charge Pump Capacitor Terminal Pin Connect to CN with a 1.0μF capacitor that should have the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used. MS1088-J-00 2009/10 -4- [AK4440] ( No. 29 30 Pin Name VSS2 VDD I/O - ) Function Ground Pin Charge Pump and DAC Digital Power Supply Pin: 4.5V∼5.5V Note: P/S pin ■ Classification Pin Name Analog LOUT4-1, ROUT4-1 SDTI4-1 DEM0, TDM0B (Serial control mode) Digital TEST (VSS1=VSS2=0V; Note 1) Parameter Power Supply Input Current (any pins except supplies) Input Voltage Ambient Operating Temperature Storage Temperature Note 1. Note 2. VSS1 VSS2 Setting Leave open. Connect to VSS2. Connect to VDD or VSS2. Leave open. Symbol VDD AVDD IIN VIND Ta Tstg min -0.3 -0.3 -0.3 -20 -65 max +6.0 +6.0 ±10 VDD+0.3 85 150 Units V V mA V °C °C : (VSS1=VSS2=0V; Note 1) Parameter Power Supply Symbol VDD AVDD min +4.5 typ +5.0 VDD max +5.5 Units V V Note 3. VDD AVDD : MS1088-J-00 2009/10 -5- [AK4440] ( Ta = 25°C; VDD=AVDD = +5.0V; fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ) Parameter min typ max Units Resolution 24 Bits Dynamic Characteristics (Note 4) THD+N (0dBFS) fs=44.1kHz, BW=20kHz -93 -84 dB fs=96kHz, BW=40kHz -92 dB fs=192kHz, BW=40kHz -92 dB Dynamic Range (-60dBFS with A-weighted, Note 5) 98 105 dB S/N (A-weighted, Note 6) 98 105 dB Interchannel Isolation (1kHz) 90 100 dB Interchannel Gain Mismatch 0.2 0.5 dB DC Accuracy DC offset (at output pin) -60 0 +60 mV Gain Drift 100 ppm/°C Output Voltage (Note 7) 1.97 2.12 2.27 Vrms Load Capacitance (Note 8) 25 pF Load Resistance 5 kΩ Power Supplies Power Supply Current: (Note 9) 80 110 mA Normal Operation (fs≤96kHz) 85 120 mA Normal Operation (fs=192kHz) 20 100 Power-Down Mode (Note 10) μA Note 4. Audio Precision (System Two) Note 5. 98dB at 16bit data Note 6. S/N Note 7. (0dB) AVDD AOUT (typ.@ 0dB) = 2.12Vrms × VDD/5. Note 8. Note 9. VDD AVDD Note 10. P/S pin VDD (MCLK, BICK, LRCK) VSS2 MS1088-J-00 2009/10 -6- [AK4440] (Ta = 25°C; VDD=AVDD = 4.5 ∼ 5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “0”) Parameter Symbol min typ Digital filter PB 0 Passband ±0.05dB (Note 11) 22.05 -6.0dB Stopband (Note 11) SB 24.1 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 12) GD 19.3 Digital Filter + SCF + LPF Frequency Response 20.0kHz Fs=44.1kHz FR ±0.05 40.0kHz Fs=96kHz FR ±0.05 80.0kHz Fs=192kHz FR ±0.05 Note 11. fs ( ) SB=0.546×fs Note 12. 16/24 max Units 20.0 - - kHz kHz kHz dB dB 1/fs - dB dB dB ± 0.02 PB=0.4535×fs(@±0.05dB) (Ta = 25°C; VDD= AVDD = 4.5~5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “1”) Parameter Symbol min (Note 13) PB (Note 13) (Note 12) SB PR SA GD 0 39.2 fs=44.kHz fs=96kHz fs=192kHz FR FR FR typ max Units 18.2 8.1 - kHz kHz kHz dB dB 1/fs Digital Filter Passband ±0.04dB -3.0dB Stopband Passband Ripple Stopband Attenuation Group Delay ± 0.005 72 - 19.3 - +0.1/-4.3 +0.1/-3.3 +0.1/-3.7 - Digital Filter + SCF + LPF Frequency Response Note 13. 20.0kHz 40.0kHz 80.0kHz fs ( ) dB dB dB PB = 0.185×fs (@±0.04dB), SB = 0.888×fs. DC (Ta = 25°C; VDD=AVDD = 4.5 ∼ 5.5V) Parameter High-Level Input Voltage Low-Level Input Voltage Low-Level Output Voltage DIF0/CDTI/SDA (Iout = 3mA) Input Leakage Current (Note 14) Note 14. P/S pin P/S pin Symbol VIH VIL min 2.2 - VOL Iin - MS1088-J-00 typ (typ.100kΩ). max 0.8 0.4 ± 10 Units V V V V μA 2009/10 -7- [AK4440] (Ta = 25°C; VDD=AVDD = 4.5 ∼ 5.5V; CL = 20pF) Parameter Master Clock Frequency Duty Cycle LRCK Frequency Normal Mode (TDM0= “0”, TDM1= “0”) Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle TDM256 mode (TDM0= “1”, TDM1= “0”) Normal Speed Mode High time Low time TDM128 mode (TDM0= “1”, TDM1= “1”) Normal Speed Mode Double Speed Mode High time Low time Audio Interface Timing BICK Period BICK Pulse Width Low Pulse Width High BICK “↑” to LRCK Edge (Note 15) LRCK Edge to BICK “↑” (Note 15) SDTI Hold Time SDTI Setup Time Control Interface Timing (3-wire Serial mode): CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN High Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 16) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Capacitive load on bus Note 15. LRCK BICK “↑” Note 16. 300ns(SCL ) Note 17. I2C-bus NXP B.V. MS1088-J-00 Symbol fCLK dCLK min 2.048 40 fsn fsd fsq Duty typ max 36.864 60 Units MHz % 8 60 120 45 48 96 192 55 kHz kHz kHz % fsn tLRH tLRL 8 1/256fs 1/256fs 48 kHz ns ns fsn fsd tLRH tLRL 8 60 1/128fs 1/128fs 48 96 kHz kHz ns ns tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 81 30 30 20 20 10 10 ns ns ns ns ns ns ns tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP Cb 1.3 0.6 1.3 0.6 0.6 0 0.1 0.6 0 - 400 0.3 0.3 50 400 kHz μs μs μs μs μs μs μs μs μs μs ns pF 2009/10 -8- [AK4440] ■ 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Figure 1. Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDH tSDS VIH SDTI VIL Figure 2. Audio Serial Interface Timing MS1088-J-00 2009/10 -9- [AK4440] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS C1 CDTI tCDH C0 R/W VIH A4 VIL Figure 3. WRITE Command Input Timing tCSW VIH CSN VIL tCSH VIH CCLK VIL CDTI D3 D2 D1 VIH D0 VIL Figure 4. WRITE Data Input Timing VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Figure 5. I2C Bus mode Timing MS1088-J-00 2009/10 - 10 - [AK4440] ■ MCLK, LRCK, BICK Register 00H) MCLK bit (MCLK) MCLK (LRCK) ΔΣ MCLK (Manual Setting Mode) (Auto Setting Mode) 2 Manual Setting Mode (ACKS bit = “0”: DFS1-0 bit (Table 1) MCLK (Table 2~Table 4) Auto Setting Mode (ACKS bit = “1”: Default) (Table 5) (Table 6) DFS1-0 ACKS pin Normal Speed Mode ACKS pin “H” Double Speed Mode 128fs 192fs ACKS pin MCLK, LRCK, BICK 0V (typ) MCLK, LRCK, BICK ON MCLK, LRCK, BICK LRCK fs 32.0kHz 44.1kHz 48.0kHz Table 2. AK4440 DFS1 bit DFS0 bit 0 0 Normal Speed Mode 8kHz~48kHz 0 1 Double Speed Mode 60kHz~96kHz 1 0 Table 1. 256fs 8.1920MHz 11.2896MHz 12.2880MHz “L” Auto Setting Mode Sampling Rate (fs) Quad Speed Mode (default) 120kHz~192kHz (Manual Setting Mode) MCLK BICK 384fs 512fs 768fs 1152fs 64fs 12.2880MHz 16.3840MHz 24.5760MHz 36.8640MHz 2.0480MHz 16.9344MHz 22.5792MHz 33.8688MHz N/A 2.8224MHz 18.4320MHz 24.5760MHz 36.8640MHz N/A 3.0720MHz (Normal Speed Mode Manual Setting Mode) (N/A: Not Available) MS1088-J-00 2009/10 - 11 - [AK4440] LRCK fs 128fs 88.2kHz 11.2896MHz 96.0kHz 12.2880MHz Table 3. LRCK fs 176.4kHz 192.0kHz Table 4. MCLK BICK 192fs 256fs 384fs 64fs 16.9344MHz 22.5792MHz 33.8688MHz 5.6448MHz 18.4320MHz 24.5760MHz 36.8640MHz 6.1440MHz (Double Speed Mode Manual Setting Mode) MCLK BICK 128fs 192fs 64fs 22.5792MHz 33.8688MHz 11.2896MHz 24.5760MHz 36.8640MHz 12.2880MHz (Quad Speed Mode Manual Setting Mode) MCLK 512fs 768fs 256fs 384fs 128fs 192fs Table 5. LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs 22.5792 24.5760 192fs 256fs 22.5792 24.5760 33.8688 36.8640 Table 6. Sampling Speed Normal Double Quad (Auto Setting Mode) MCLK (MHz) 384fs 512fs 768fs 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640 33.8688 36.8640 (Auto Setting Mode) MS1088-J-00 1152fs 36.8640 - Sampling Speed Normal Double Quad 2009/10 - 12 - [AK4440] ■ 4 DIF0 bit (Table 8) 11 “010” Mode 2 (Table 7) MSB 16/20 (Table 7) DIF0 pin TDM0 bit DIF2-0 bit TDM1-0 bit 2’s Complement LSB TDM0B pin = “L” DAC 8channels BICK 256fs TDM0B pin DIF2-0 bit BICK “0” TDM256 SDTI1 pin SDTI2-4 pin TDM0 bit “1” I/F TDM TDM1 bit “0” TDM256 (Table 8) SDTI1 pin DAC(8ch) SDTI2-4 BICK 256fs LRCK “H” “L” 1/256fs(min) TDM128 (TDM1-0 bit = “11”, Table 8) SDTI1 pin DAC (L1,R1,L2,R2) SDTI2 pin DAC (L3,R3,L4,R4) 4ch SDTI3-4 BICK 128fs MSB 2’s complement SDTI1 BICK Mode Normal TDM256 Mode Normal 0 1 2 3 4 TDM256 5 6 7 TDM128 8 9 10 2 3 5 6 TDM0B pin DIF0 pin SDTI Format LRCK H L 24-bit MSB Justified H/L 2 L/H H H 24-bit I S Compatible L L 24-bit MSB Justified ↑ L H 24-bit I2S Compatible ↓ Table 7. Audio Data Formats (Parallel control mode) BICK ≥48fs ≥48fs 256fs 256fs TDM1 TDM0 DIF2 DIF1 DIF0 SDTI Format LRCK bit bit bit bit bit 0 0 0 0 0 16-bit LSB Justified H/L 0 0 0 0 1 20-bit LSB Justified H/L 0 0 0 1 0 24-bit MSB Justified H/L 0 0 0 1 1 24-bit I2S Compatible L/H 0 0 1 0 0 24-bit LSB Justified H/L 0 1 0 0 0 N/A 0 1 0 0 1 N/A 0 1 0 1 0 24-bit MSB Justified ↑ 2 0 1 0 1 1 24-bit I S Compatible ↓ 0 1 1 0 0 24-bit LSB Justified ↑ 1 1 0 0 0 N/A 1 1 0 0 1 N/A 1 1 0 1 0 24-bit MSB Justified ↑ 1 1 0 1 1 24-bit I2S Compatible ↓ 1 1 1 0 0 24-bit LSB Justified ↑ Table 8. Audio Data Formats (Serial control mode) (N/A: Not available) MS1088-J-00 Figure Figure 8 Figure 9 Figure 10 Figure 11 BICK Figure ≥32fs ≥40fs ≥48fs ≥48fs ≥48fs Figure 6 Figure 7 Figure 8 Figure 9 Figure 7 256fs 256fs 256fs Figure 10 Figure 11 Figure 12 128fs 128fs 128fs Figure 13 Figure 14 Figure 15 2009/10 - 13 - [AK4440] LRCK 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 BICK (32fs) SDTI Mode 0 15 14 6 1 0 5 14 4 15 3 16 2 1 17 0 31 15 0 14 6 5 14 1 4 15 3 16 2 1 17 0 31 15 14 0 1 0 1 0 1 BICK (64fs) SDTI Mode 0 Don’t care 15 14 0 Don’t care 15 14 0 15:MSB, 0:LSB Lch Data Rch Data Figure 6. Mode 0 Timing LRCK 0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 BICK (64fs) SDTI Mode 1 Don’t care 19 0 Don’t care 19 0 Don’t care 19 0 19 0 19:MSB, 0:LSB SDTI Mode 4 Don’t care 23 22 21 20 23 22 20 21 23:MSB, 0:LSB Lch Data Rch Data Figure 7. Mode 1/4 Timing LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 BICK (64fs) SDTI 23 22 1 0 Don’t care 23 22 1 0 Don’t care 23 22 23:MSB, 0:LSB Lch Data Rch Data Figure 8. Mode 2 Timing MS1088-J-00 2009/10 - 14 - [AK4440] LRCK 0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1 BICK (64fs) SDTI 0 1 23 22 Don’t care 23 22 0 1 23 Don’t care 23:MSB, 0:LSB Lch Data Rch Data Figure 9. Mode 3 Timing 256 BICK LRCK BICK(256fs) SDTI1(i) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK Figure 10. Mode 5 Timing 256 BICK LRCK BICK(256fs) SDTI1(i) 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 Figure 11. Mode 6 Timing 256 BICK LRCK BICK(256fs) SDTI1(i) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 0 23 Figure 12. Mode 7 Timing MS1088-J-00 2009/10 - 15 - [AK4440] 128 BICK LRCK BICK(128fs) SDTI1(i) SDTI2(i) 23 22 23 22 0 0 23 22 23 22 0 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 23 22 0 23 22 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 0 23 22 0 23 22 0 23 0 23 Figure 13. Mode 8 Timing 128 BICK LRCK BICK(128fs) SDTI1(i) SDTI2(i) 23 22 0 23 22 0 0 23 22 L1 R1 L2 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 23 22 23 22 0 R2 32 BICK 23 22 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK Figure 14. Mode 9 Timing 128 BICK LRCK BICK(128fs) SDTI1(i) SDTI2(i) 23 22 0 23 22 0 23 22 0 23 22 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 23 22 0 23 22 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 0 19 0 19 Figure 15. Mode 10 Timing MS1088-J-00 2009/10 - 16 - [AK4440] ■ AK4440 ESR( (Figure 16) (Figure 17) 2Vrms Ca VSS(0V,typ) 1.0μF CP VSS2 Cb ) (Figure 16) AK4440 VSS (0V,typ) AK4440 VDD Charge Pump CP Negative Power CN (+) 1uF VEE VSS2 Cb 1uF (+) Ca Figure 16. AK4440 2.12Vrms 0V LOUT (ROUT) Figure 17. Audio ■ IIR (50/15μs OFF 3 (32kHz, 44.1kHz, 48kHz) Double Speed Mode, Quad Speed Mode DEM1-0 bit DEMA-D bit DAC DEM1-0 pin (Table 10) (Table 9) DEM1 bit DEM0 bit Mode 0 0 1 1 0 1 0 1 44.1kHz OFF 48kHz 32kHz Table 9 ) (default) in Serial Mode (Normal Speed Mode) MS1088-J-00 2009/10 - 17 - [AK4440] DEM1 pin DEM0 pin Mode L L H H L H L H 44.1kHz OFF 48kHz 32kHz Table 10 (default) in Parallel Mode (Normal Speed Mode) ■ SMUTE pin/bit 1024LRCK -∞ 1024LRCK “1” -∞ (“0”) 0dB Normal Speed Mode SMUTE pin/bit “0” -∞ 1024LRCK 0dB SMUTE pin/bit 1024/fs 0dB 1024/fs (1) (3) Attenuation -∞ GD (2) GD LOUT/ROUT DZF pin (4) 8192/fs : 1024LRCK (1024/fs) -∞(“0”) (1) Normal Speed Mode Double Speed Mode 2048LRCK (2048/fs) Quad Speed Mode (4096/fs) -∞(“0”) (GD) (2) 1024LRCK Normal Speed Mode (3) 0dB 4096LRCK Figure 18. MS1088-J-00 2009/10 - 18 - [AK4440] ■ ON “↑” AK4440 MCLK LRCK LRCK tW<20ms Power Supply 0.8xVDD (VDD, AVDD) 0.3V (1) MCLK 20 µs (3) Internal Reset Reset Release 10ms (max) (2) Reset Audio circuit Power-up 8~10 LRCK Clocks (4) Charge Pump Circuit Power-up Power down Time A VEE Pin 0V (5) “0” data D/A In (Digital) 0V D/A Out (Analog) Active (D/A Out) MUTE (D/A Out) : (1) (2) (3) Internal Reset (4) (5) tW 0.3V 80%VDD 10msec(max) Internal Reset MCLK 20us 20msec 8 10 LRCK 1024/(fs * 16): Normal speed mode DAC time A = 1024/(fs * 16): Normal speed mode time A = 1024/(fs * 8): Double speed mode time A = 1024/(fs * 4): Quadruple speed mode Figure 19. System Reset Diagram MS1088-J-00 2009/10 - 19 - [AK4440] ■ MCLK LRCK VSS(0V,typ) BICK AK4440 DAC MCLK LRCK BICK Clock In (1) (2) MCLK, BICK, LRCK MCLK or BICK or LRCK Stop Internal State Normal Operation Reset D/A In (Digital) Normal Operation (3) GD (5) D/A Out (Analog) : (1) (MCLK (2) MCLK 2048fs LRCK LRCK LRCK LRCK BICK BICK (4) (5) VSS ) (MCLK, BICK, LRCK) LRCK BICK BICK BICK “0” (3) MCLK LRCK BICK (GD) (4) (5) Figure 20. MS1088-J-00 2009/10 - 20 - [AK4440] ■ 2 I2C (3 I2C ) 3 pin “11” CAD0 RSTN bit “0” * AK4440 P/S pin * RSTB bit * Function Parallel Control Mode Serial Control Mode X X X - X X X X X X Double sampling mode at 128/192fs De-emphasis SMUTE 16/20/24bit LSB justified format TDM256 mode TDM128 mode Table 11 (1) 3 (X: Available, -: Not Available) (I2C pin = “L”) 3 I/F : CSN, CCLK, CDTI I/F ), Read/Write (1bit, “1” , Write only), Register address (MSB first, 5bit) address (2bit, C1/0, “11” CCLK “↑” Control data (MSB first, 8bit) “↑” CCLK 5MHz (max) Chip CSN CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (Fixed to “11”) READ/WRITE (Fixed to “1”, Write only) Register Address Control Data Figure 21. Control I/F Timing MS1088-J-00 2009/10 - 21 - [AK4440] (2) I2C (I2C pin = “H”) AK4440 I2C (max:400kHz) I2C (Start Condition) (Figure 26) 8 1 IC R/W bit “0” AK4440 AK4440 “1” 2 Figure 22 “H” SCL (R/W) (Figure 23) CAD0 pin (Acknowledge) Write (Figure 27) ( ) (Figure 24) 3 (Figure 25) AK4440 “0” MSB first IC “H” SDA 8 “L” 7 “001001” 6 R/W bit MSB first 3 8 (Stop Condition) SDA “L” “H” SCL “H” (Figure 26) AK4440 1 “03H” “00H” “H” SDA SCL “H” (Figure 28) SCL “L” “L” “H” SDA S T A R T SDA S S T O P R/W Slave Address Sub Address(n) A C K Data(n) Data(n+x) Data(n+1) A C K A C K A C K A C K P A C K Figure 22. I2C 0 0 1 0 0 (CAD0 Figure 23. 0 0 0 D6 D5 Figure 25. CAD0 R/W A3 A2 A1 A0 D3 D2 D1 D0 ) 1 A4 Figure 24. D7 1 2 D4 3 MS1088-J-00 2009/10 - 22 - [AK4440] SDA SCL S P start condition stop condition Figure 26. DATA OUTPUT BY MASTER not acknowledge DATA OUTPUT BY SLAVE(AK4440) acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 27. I2C SDA SCL data line stable; data valid change of data allowed Figure 28. I2C MS1088-J-00 2009/10 - 23 - [AK4440] ■ Addr 00H 01H 02H 03H Register Name Control 1 Control 2 Power Down Control DEM Control D7 ACKS RRST 0 0 D6 TDM1 0 0 0 D5 TDM0 SLOW 0 0 D4 DIF2 DFS1 0 0 D3 DIF1 DFS0 PW4 DEMA D2 DIF0 DEM1 PW3 DEMB D1 0 DEM0 PW2 DEMC D0 RSTN SMUTE PW1 DEMD Note: 04H RSTN bit= “0” 10msec PW1-4 bit RSTN bit “0” ■ Addr 00H Register Name Control 1 Default D7 ACKS D6 TDM1 D5 TDM0 D4 DIF2 D3 DIF1 D2 DIF0 D1 0 D0 RSTN 1 0 0 0 1 0 0 1 RSTN: 0: Reset. 1: Normal operation DIF2-0: (Table 8) Default: “010” TDM0-1: TDM Mode Select Mode Normal TDM256 TDM128 TDM1 0 0 1 TDM0 0 1 1 BICK 32fs∼ 256fs fixed 128fs fixed SDTI 1-4 1 1-2 Sampling Speed Normal, Double, Quad Speed Normal Speed Normal, Double Speed ACKS: 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode ACKS bit “1” ACKS bit “0” DFS1-0 bit Addr 01H Register Name Control 2 Default D7 RRST 0 DFS1-0 bit D6 0 0 D5 SLOW D4 DFS1 D3 DFS0 D2 DEM1 D1 DEM0 D0 SMUTE 0 0 0 0 1 0 SMUTE: 0: Normal operation 1: DAC outputs soft-muted DEM1-0: Default: “01”, OFF (Table 9, Table 10) DFS1-0: (Table 1) 00: Normal speed 01: Double speed 10: Quad speed Normal/Double/Quad Speed Mode MS1088-J-00 2009/10 - 24 - [AK4440] SLOW: Slow Roll-off Filter Enable 0: Sharp Roll-off Filter 1: Slow Roll-off Filter RRST: 0: Normal Operation 1: Reset. Addr 02H Register Name Power Down Control Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 PW4 1 D2 PW3 1 D1 PW2 1 D0 PW1 1 D4 0 0 D3 DEMA 0 D2 DEMB 0 D1 DEMC 0 D0 DEMD 0 PW4-1: Power-down control (0: Power-down, 1: Power-up) PW1: Power down control of DAC1 PW2: Power down control of DAC2 PW3: Power down control of DAC3 PW4: Power down control of DAC4 Addr 03H Register Name DEM Control Default D7 0 0 D6 0 0 D5 0 0 DEMA-D: De-emphasis Enable bit of DAC1/2/3/4 0: Disable 1: Enable MS1088-J-00 2009/10 - 25 - [AK4440] Figure 29, Figure 30 (AKD4440) 0.1u 10u Master Clock 1 MCLK VDD 30 BICK VSS2 29 28 Analog 5V + 64fs 2 24bit Audio Data 3 SDTI1 CP fs 4 LRCK CN 27 5 TEST VEE 26 6 SMUTE LOUT1 25 L1ch Out + 1u (1) ModeSetting AK4440 + 1u (1) ACKS ROUT1 24 R1ch Out 8 DIF0 LOUT2 23 L2ch Out 24bit Audio Data 9 SDTI2 ROUT2 22 R2ch Out 24bit Audio Data 10 SDTI3 LOUT3 21 L3ch Out 24bit Audio Data 11 SDTI4 ROUT3 20 R3ch Out 12 TDM0B LOUT4 19 L4ch Out 13 DEM0 ROUT4 18 R4ch Out 14 DEM1 VSS1 17 P/S AVDD 16 7 ModeSetting 15 Digital Ground + Analog 5V 0.1u 10u Analog Ground Figure 29. Typical Connection Diagram (Parallel Control Mode) Notes: - LRCK = fs, BICK=64fs. - AOUT - ESR CP, VSS2 - P/S pin MS1088-J-00 2009/10 - 26 - [AK4440] 0.1u 10u Master Clock 1 Analog 5V MCLK VDD 30 64fs 2 BICK VSS2 29 24bit Audio Data 3 SDTI1 CP 28 fs 4 LRCK CN 27 5 TEST VEE 26 6 CSN LOUT1 25 L1ch Out + + 1u (1) Microcontroller AK4440 + 1u (1) 7 CCLK ROUT1 24 R1ch Out 8 CDTI LOUT2 23 L2ch Out 24bit Audio Data 9 SDTI2 ROUT2 22 R2ch Out 24bit Audio Data 10 SDTI3 LOUT3 21 L3ch Out 24bit Audio Data 11 SDTI4 ROUT3 20 R3ch Out 12 TDM0B LOUT4 19 L4ch Out 13 DEM0 ROUT4 18 R4ch Out 14 I2C VSS1 17 15 P/S AVDD 16 + 0.1u Digital Ground Analog 5V 10u Analog Ground Figure 30. Typical Connection Diagram (3-wire Serial Control Mode) Notes: - LRCK = fs, BICK=64fs. - AOUT - ESR CP, VSS2 - P/S pin MS1088-J-00 2009/10 - 27 - [AK4440] 1. VDD AVDD AVDD VDD AVDD VSS VDD VDD AVDD VSS2 2. VSS(0V,typ) 5V) ΔΣ ( (SCF) LPF(Figure 31) 2.12Vrms(typ, @AVDD= ) (CTF) 2’s complement (2 800000H(@24bit) DC ±60 V 1 ) 7FFFFFH(@24bit) 000000H(@24bit) VAOUT 0V(VSS) AK4440 560 Analog Out AOUT 2.12Vrms (typ) 3.3nF (fc = 86.1kHz, gain = -0.85dB @ 40kHz, gain = -2.70dB @ 80kHz) Figure 31. External 1st order LPF Circuit Example MS1088-J-00 2009/10 - 28 - [AK4440] 30pin VSOP (Unit: mm) 1.5MAX *9.7±0.1 0.3 30 16 15 1 0.22±0.1 7.6±0.2 5.6±0.1 A 0.15 +0.10 -0.05 0.65 0.12 M 0.08 0.45±0.2 +0.10 0.10 -0.05 1.2±0.10 Detail A NOTE: Dimension "*" does not include mold flash. ■ : : : ( ) RoHS * RoHS MS1088-J-00 2009/10 - 29 - AKM CONFIDENTIAL [AK4440] AKM AK4440EF XXXBYYYYC XXXBYYYYC Date code identifier XXXB : Lot number (X: Digit number, B: Alpha character) YYYYC : Assembly date (Y: Digit number, C: Alpha character) Date (YY/MM/DD) 09/10/15 Revision 00 Reason Page MS1088-J-00 Contents 2009/10 - 30 - AKM CONFIDENTIAL [AK4440] • • • • • • MS1088-J-00 2009/10 - 31 -