[AK7601A] AK7601A High Feature Digital Audio Processor with SRC GENERAL DESCRIPTION AK7601A is a high feature audio processor with audio CODEC (3ch ADC, 6ch DAC) and delay line memory operates 5.0V single power supply. The analog inputs support quasi-differential/single-ended with 4:1 stereo selector in front of 2-channeled 97dB ADC, and monaural ADC for guidance sound. The digital inputs supports 3:1 input selector with asynchronous Sample Rate Converter (SRC) for digital source such as DVD, Blu-ray, digital broadcasting, etc. The high performance 6-channeled DAC integrates full-range digital volume control and achieves 102dB with single end outputs. The delay line memory covers 36ms in total. Time alignment of 6m or less is possible since the delay line memory can store for 18ms data for both left and right channels. The AK7601A can achieve high performance car audio system easily by supporting two stereo 7-band EQ and time alignment functions. FEATURES 1. 2ch 24bit ADC - Quasi-Differential/Single-ended inputs with 4:1 Stereo Selector - S/(N+D): 90dB - DR, S/N: 97dB - Digital HPF for cancelling DC offset 2. 1ch 24bit ADC for Monaural Audio Input - Single-ended input - S/(N+D): 90dB - DR, S/N: 97dB - Digital HPF for cancelling DC offset 3. 6ch 24bit DAC - Single-ended output - S/(N+D): 90dB - DR, S/N: 102dB 4. Asynchronous Sample Rate Converter(SRC) for Digital Input - 3:1 Input Selector - Input Sampling Rate: 8kHz 96kHz - Data Format: MSB justified, LSB justified, I2S compatible (slave mode only) 5. Digital Processing - Two Stereo 7Band EQ (Second-order IIR-filter setting is also available) - Digital De-emphasis Filter - Adjustable Delay Memory Control Maximum Delay Time: Lch 18ms, Rch 18ms (for 1 stereo input / 3 stereo outputs) Delay Resolution: 1/fs - X’Over filter: Front L, Front R: 2nd order IIR Filter x 3 stages Rear L, Rear R, Subwoofer L, Subwoofer R: 2nd order IIR Filter x 2 stages - Spectrum analyzer: Variable 4-Band - Soft Mute - Zero Detect Function 6. Smooth Volume 7. Master Clock - Master Mode: 22.5792MHz 8. P Interface: I2C Bus (Ver 1.0, 400kHz mode) MS1446-E-01 2015/05 -1- [AK7601A] 9. Power Supply - Analog: AVDD = 4.5 5.5V - Digital: DVDD = 3.0 5.5V 10. Power Consumption: 80mA 11. Ta = - 40 85°C 12. Package: 48LQFP(0.5mm pitch) ■ Block Diagram SDTO1/SDTO3 2ch DAC 2ch DAC 2ch DAC Delay Control 14Band EQ nd (2 IIR x 14) nd 2 IIR x 2 x2ch AOUT2L AOUT2R AOUT3L AOUT3R D-Vol Function Switch 2ch ADC nd 2 IIR x 2 x2ch DZF AOUT1L AOUT1R O D-Vol nd 2 IIR x 3 x2ch D-Vol AINL1 GNDIN1 AINR1 AINL2 GNDIN2 AINR2 AINL3 AINR3 AINL4 AINR4 D-Vol Switch 1ch ADC MONOIN SDTO2/SDTI4 IBICK1 1 IBICK2 IBICK3 2ch SRC OBICK OLRCK ILRCK1 1ILRCK2 ILRCK3 VSS1 PDN 2 SDTI1 1 SDTI2 SDTI3 AVDD MCKO MUTEN 4Band Spectrum Analyser Filter nd st (2 IIR x 1 IIR) x 4 VSS2 VCOM VREFH REF18 VSS3 DVDD VSS4 IC Interface SDA X’tal Oscillator XTI SCL XTO CLKMODE Figure 1. Block Diagram MS1446-E-01 2015/05 -2- [AK7601A] ■ Ordering Guide -40 +85C 48pin LQFP(0.5mm pitch) Evaluation board for AK7601A AK7601AVQ AKD7601A XTO XTI ILRCK1 ILRCK2 ILRCK3 IBICK1 IBICK2 IBICK3 SDTI1 SDTI2 SDTI3 DVDD 36 35 34 33 32 31 30 29 28 27 26 25 ■ Pin Layout MUTEN 37 24 VSS2 VSS3 38 23 SDTO1/SDTO3 CLKMODE 39 22 SDTO2/SDTI4 REF18 40 21 OLRCK VSS4 41 20 OBICK MONOIN 42 19 MCKO AINL1 43 18 SCL 17 SDA AK7601AVQ Top View 9 10 11 12 AOUT1R AOUT2L AOUT2R AOUT3L AOUT1L 13 8 48 VREFH AINR2 7 AOUT3R VSS1 14 6 47 AVDD GNDIN2 5 DZF VCOM 15 4 46 AINR4 AINL2 3 PDN AINL4 16 2 45 AINR3 AINR1 1 44 AINL3 GNDIN1 Figure 2. Pin Layout MS1446-E-01 2015/05 -3- [AK7601A] PIN FUNCTION No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin Name AINL3 AINR3 AINL4 AINR4 VCOM AVDD VSS1 VREFH AOUT1L AOUT1R AOUT2L AOUT2R AOUT3L AOUT3R DZF I/O I I I I O O O O O O O O 16 PDN 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 SDA SCL MCKO OBICK OLRCK VSS2 DVDD SDTI3 SDTI2 SDTI1 IBICK3 IBICK2 IBICK1 ILRCK3 ILRCK2 ILRCK1 XTI XTO I/O I O O O I/O O I I I I I I I I I I O 37 MUTEN I 38 VSS3(DVSS) - 39 CLKMODE I 40 41 42 43 44 45 46 47 48 REF18 VSS4 MONOIN AINL1 GNDIN1 AINR1 AINL2 GNDIN2 AINR2 O I I I I I I I SDTO2/SDTI4 SDTO1/SDTO3 I Function Lch Single-ended Input 3 Pin Rch Single-ended Input 3 Pin Lch Single-ended Input 4 Pin Rch Single-ended Input 4 Pin VCOM pin Analog Power Supply Pin 4.5~5.5V Ground Pin, 0V Positive Voltage Reference Input Pin, AVDD DAC1 Lch Output pin. DAC1 Rch Output pin DAC2 Lch Output pin DAC2 Rch Output pin DAC3 Lch Output pin DAC3 Rch Output pin Zero detect pin Power-Down & Reset Pin When “L”, the AK7601A is powered-down and the control registers are reset to default state. Control Data Input Pin : SDA (I2C Bus) (Note 2) Control Data Clock Pin : SCL (I2C Bus) Master Clock Output Pin Output Audio Serial Data Clock Pin Output Channel Clock Pin Audio Serial Data Input 4 / Output 2 Pin (Note 3) Audio Serial Data Output 1/3 Pin Ground Pin, 0V Digital Power Supply 1 Pin, 3.0 ~5.5V Audio Serial Data Input 1 Pin Audio Serial Data Input 2 Pin Audio Serial Data Input 3 Pin Input Audio Serial Data Clock Pin 3 Pin Input Audio Serial Data Clock Pin 2 Pin Input Audio Serial Data Clock Pin 1 Pin Input Channel Clock 3 Pin Input Channel Clock 2 Pin Input Channel Clock 1 Pin X’tal Input Pin X’tal Output Pin AK7601A Mute Pin L: Mute H: Normal Operation Ground Pin 0V CLK Mode Pin (X’tal/External CLK select pin) L: X’tal Mode H External CLK Input Mode The PDN pin must set “H” → “L” → “H” before changing this pin “L” → “H”. Internal regulator 1.8V Output pin Ground Pin, 0V Monaural ADC Input Pin Lch Differential Input 1 Pin Input Ground 1 Pin Rch Differential Input 1 Pin Lch Differential Input 2 Pin Input Ground 2 Pin Rch Differential Input 2 Pin MS1446-E-01 2015/05 -4- [AK7601A] Note 1. All digital input pins must not be allowed to float. Note 2. Input pin when powered-down. Note 3. Output pin when powered-down ■Handling of Unused Pin The unused I/O pins should be processed appropriately as below Classification Analog Digital Pin Name AINL1, GNDIN1, AINR1, AINL2, GNDIN2, AINR2, AINL3, AINR3, AINL4, AINR4, MONOIN AOUT1L, AOUT1R, AOUT2L, AOUT2R, AOUT3L, AOUT3R IBICK1, IBICK2, IBICK3, ILRCK1, ILRCK2, ILRCK3, SDTI1, SDTI2, SDTI3, SDTI4 OBICK, OLRCK, MCKO, SDTO1/SDTO3, SDTO2, XTO MS1446-E-01 Setting Open Open Connect to VSS2 Open 2015/05 -5- [AK7601A] ABSOLUTE MAXMUM RATING (VSS1=VSS2=VSS3=VSS4=0V; Note 4) Parameter Symbol min max Unit Power Supplies Analog AVDD -0.3 6.0 V Digital DVDD -0.3 6.0 V Input Current (any pins except for supplies) IIN mA 10 Analog Input Voltage (Note 5) VINA -0.3 AVDD+0.3 V Digital Input Voltage (Note 6) VIND -0.3 DVDD+0.3 V Ambient Temperature (power applied) Ta -40 85 C Storage Temperature Tstg -65 150 C Note 4. All indicated voltages are with respect to ground VSS1, VSS2, VSS3 and VSS4 must be connected to the analog ground plane. Note 5. Analog input pins are AINL1-4, AINR1-4, GNDIN1-2 and MONOIN. Note 6. Digital input pins are SDTI1-4, ILRCK1-3, IBICK1-3, MUTEN, SDA, and SCL. WARNING: Operating at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these critical conditions. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=VSS3=VSS4 =0V; Note 4) Parameter Symbol min typ max Unit Power Supplies Analog AVDD 4.5 5.0 5.5 V (Note 7) Digital DVDD 3.0 5.0 AVDD V Note 7. AVDD must be supplied after DVDD is ON. The PDN pin must be “L” until all power supplies are ON, then put the PDN pin to “H”. All power supplies of the AK7601A are must be ON. Do not turn any power supply off (means the same voltage as ground or floating) independently. When using the AK7601A with I²C bus, the power supply of the AK7601A must not be turned off unless the power supplies of the surrounding device are turned off. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS1446-E-01 2015/05 -6- [AK7601A] ANALOG CHARACTERISTICS (Ta=25C; AVDD=5.0V, DVDD =5.0V; VSS1=VSS2=VSS3=VSS4=0V; VREFH=AVDD, fs=44.1kHz; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz20kHz at; unless otherwise specified) Parameter min typ max Unit ADC Analog Input Characteristics (Pseudo differential inputs) Resolution 24 Bits S/(N+D) BW=20kHz -1dBFS 83 90 dB -60dBFS 35 DR (-60dBFS with A-weighted) 90 97 dB S/N (A-weighted) 90 97 dB Interchannel Isolation 90 110 dB Interchannel Gain Mismatch 0 0.5 dB Gain Drift 20 ppm/C Input Voltage AIN=0.65xVREFH 3.09 3.25 3.41 Vpp Input Resistance AINL1, AINR1, AINL2, AINR2 22 45 k GNDIN1, GNDIN2 22 90 k Power Supply Rejection (Note 8) 55 dB Common Mode Rejection Ratio (CMRR) (Note 9) 40 dB ADC Analog Input Characteristics (Single-ended inputs) Resolution 24 Bits S/(N+D) BW=20kHz -1dBFS 83 90 dB -60dBFS 35 DR (-60dBFS with A-weighted) 90 97 dB S/N (A-weighted) 90 97 dB Interchannel Isolation 90 110 dB Interchannel Gain Mismatch 0 0.5 dB Gain Drift 20 ppm/C Input Voltage AIN=0.65xVREFH 3.09 3.25 3.41 Vpp Input Resistance (AINL3, AINR3, AINL4, AINR4) 22 45 k Power Supply Rejection (Note 8) 55 dB ADC Analog Input Characteristics (Monaural input) Resolution 24 Bits S/(N+D) BW=20kHz -1dBFS 83 90 dB -60dBFS 35 DR (-60dBFS with A-weighted) 90 97 dB S/N (A-weighted) 90 97 dB Gain Drift 20 ppm/C Input Voltage AIN=0.65xVREFH 3.09 3.25 3.41 Vpp Input Resistance 22 45 k Power Supply Rejection (Note 8) 55 dB DAC Analog Output Characteristics (single outputs) Resolution 24 Bits S/(N+D) BW=20kHz 0dBFS 83 90 dB -60dBFS 39 DR (-60dBFS with A-weighted) 93 102 dB S/N (A-weighted) 93 102 dB Interchannel Isolation 90 110 dB Interchannel Gain Mismatch 0 0.5 dB Gain Drift 20 ppm/C Output Voltage AOUT=0.65xVREFH 3.09 3.25 3.41 Vpp Load Resistance (AC Load) 5 k Load Capacitance 30 pF Power Supply Rejection (Note 8) 55 dB MS1446-E-01 2015/05 -7- [AK7601A] ADC to DAC Characteristics (single outputs) Resolution S/(N+D) BW=20kHz 24 Bits 87 dB 34 DR (-60dBFS with A-weighted) 87 96 dB S/N (A-weighted) 87 96 dB Note 8. PSR is applied to AVDD and DVDD with 1kHz, 50mVpp. This is the value of convoluted sinusoidal voltage of 1kHz and 50mVpp when the VREFH pin is held +5V. Note 9. This is a value when the frequency range is 20Hz ~ 20kHz assuming an external capacitor is 10uF±30% and GDNIN1/2 amplitude is 100mVpp. -1dBFS -60dBFS 80 SRC CHARACTERISTICS (Ta=25C; AVDD=5.0V, DVDD =5.0V; VSS1=VSS2=VSS3=VSS4=0V; VREFH=AVDD, fs=44.1kHz; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz20kHz; unless otherwise specified) Parameter Symbol min typ max SRC Characteristics: Resolution 24 Input Sample Rate FSI 8 96 Output Sample Rate FSO 44.1 THD+N (Input = 1kHz, 0dBFS, Note 10) FSI =48kHz -130 -100 Dynamic Range (Input = 1kHz, 60dBFS, Note 10) FSI = 48kHz Dynamic Range (Input = 1kHz, -60dBFS, A-weighted, Note 10) FSI = 48kHz Ratio between Input and Output Sample Rate Note 10. Measured by Audio Precision System Two Cascade. 136 Bits kHz kHz dB 120 dB 44.1/8 dB - 140 FSO/FSI 44.1/96 Parameter min typ max Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) AVDD 54 73 DVDD 11 15 Power-down mode (PDN pin = “L”) AVDD+DVDD (Note 12) 10 100 Note 11. Power supply current values are for when ADC, DAC and SRC are in operation. Note 12. When the AK7601A is not in operation. All digital input pins including clock pins are held to VSS2. MS1446-E-01 Unit Unit mA mA µA 2015/05 -8- [AK7601A] FILTER CHARACTERISTICS (Ta= -40 +85C; AVDD=4.5 5.5V, DVDD=3.0 5.5V) Parameter Symbol min typ max Unit ADC Digital Filter (Decimation LPF): Passband (Note 13) 0.1dB PB 0 17.3 kHz 0.2dB 18.3 kHz 3.0dB 21.1 kHz Stopband (Note 13) SB 25.7 kHz Passband Ripple PR 0.04 dB Stopband Attenuation SA 68 dB Group Delay Distortion GD 0 s Group Delay (Note 14) GD 16 1/fs ADC Digital Filter (HPF): Frequency Response (Note 13) 3dB FR 0.86 Hz 0.1dB 5.9 Hz DAC Digital Filter (LPF): Passband (Note 13) 0.06dB PB 0 20.0 kHz 6.0dB 22.05 kHz Stopband (Note 13) SB 24.1 kHz Passband Ripple PR 0.1 dB Stopband Attenuation SA 54 dB Group Delay Distortion GD 0 s Group Delay (Note 14) GD 20 1/fs DAC Digital Filter + Analog Filter: Frequency Response (Note 15) 20~20kHz FR 0.1 dB Note 13. The passband and stopband frequencies scale with fs (system sampling rate). For example, when fs= 44.1kHz, DAC is PB=0.45412*fs (@±0.06dB). Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting of 24bit data both channels to the ADC output register for ADC. This time is from the set of 24bit data to the input registers to the output of analog signal for DAC. Note 15. The reference frequency of these responses is 1kHz. SRC Digital Filter Passband -0.01dB Symbol min typ max Unit PB 0 0.4583FSI kHz PB 0 0.4167FSI kHz PB 0 0.2177FSI kHz PB 0 0.1948FSI kHz Stopband SB 0.5417FSI kHz SB 0.5021FSI kHz SB 0.2813FSI kHz SB 0.2604FSI kHz Passband Ripple PR dB 0.01 Stopband Attenuation 0.985 ≤ FSO/FSI < 5.513 SA 121.2 dB 0.656 ≤ FSO/FSI < 0.985 SA 121.4 dB 0.492 ≤ FSO/FSI < 0.656 SA 100.2 dB 0.459 ≤ FSO/FSI < 0.492 SA 103.3 dB Group Delay (Ts=1/fs) (Note 16) GD 64 Ts Note 16.This delay is the period from the rising edge of ILRCK, just after the SDTI data is input, to the rising edge of OLRCK, just after the SDTO data is output, when there is no phase difference between ILRCK and OLRCK. 0.985 ≤ FSO/FSI < 5.513 0.656 ≤ FSO/FSI < 0.985 0.492 ≤ FSO/FSI < 0.656 0.459 ≤ FSO/FSI < 0.492 0.985 ≤ FSO/FSI < 5.513 0.656 ≤ FSO/FSI < 0.985 0.492 ≤ FSO/FSI < 0.656 0.459 ≤ FSO/FSI < 0.492 MS1446-E-01 2015/05 -9- [AK7601A] DC CHARACTERISTICS (Ta=-40C+85C; AVDD= 4.55.5V, DVDD=3.05.5V) Parameter High-Level Input Voltage (PDN, SDA, SCL, SDTI1-4, ILRCK1-3, IBICK1-3, MUTEN, XTI pins) (CLKMODE pin) Low-Level Input Voltage (PDN, SDA, SCL, SDTI1-4, ILRCK1-3, IBICK1-3, MUTEN, XTI pins) (CLKMODE pin) High-Level Output Voltage (SDTO1-3, OLRCK, OBICK, OMCLK, SDA, DZF pins: Iout=-100µA) Low-Level Output Voltage (SDTO1-3, OLRCK, OBICK, OMCLK, DZF pins: Iout= 100µA) (SDA pin: Iout= 3mA) Input Leakage Current PDN, SDA, SCL, SDTI1-4, ILRCK1-3, IBICK1-3, MUTEN, XTI MS1446-E-01 Symbol min typ max Unit VIH 70%DVDD - - V VIH 80%DVDD - - V VIL - - 30%DVDD V VIL - - 20%DVDD V VOH DVDD-0.5 - - V VOL VOL - - 0.5 0.4 V V Iin - - 10 µA 2015/05 - 10 - [AK7601A] SWITCHING CHARACTERISTICS (Ta=-40+85C; AVDD=4.5~5.5V; DVDD=3.05.5V; CL=20pF; unless otherwise specified) Parameter Symbol min typ max Unit Master Clock Timing Crystal Resonator Frequency fXTAL 22.5792 MHz MCKO Output fMCK 22.5792 MHz Frequency MCKO1-0 bit = “10” fMCK 11.2896 MHz MCKO1-0 bit = “01” Duty cycle 512fs (Note 17) dMCK 40 50 60 % 256fs (Note 17) dMCK 45 50 55 % External Clock Frequency fCLK 22.35 22.5792 22.80 MHz Pulse Width Low tCLKL 18 ns Pulse Width High tCLKH 18 ns MCKO Output fMCK 22.35 22.5792 22.80 MHz Frequency 512fs Duty cycle (Note 18) dMCK 40 50 60 % Input LRCK (ILRCK1-3) Frequency FSI 8 96 kHz Duty Cycle Duty 48 50 52 % Output LRCK (OLRCK) Frequency FSO 44.1 kHz Duty Cycle Duty 50 % Audio Interface Timing OBICK Frequency 64fs Hz fBCK OBICK Duty 50 % dBCK 20 ns OBICK “” to OLRCK 20 tMBLR 20 ns OBICK “” to SDTO1~3 20 tBSD ns 30 SDTI3-4 Hold Time tSDH ns 30 SDTI3-4 Setup Time tSDL Input PORT ns 1/64fs tBCK IBICK1-3 Period ns 65 tBCKL IBICK1-3 Pulse Width Low ns 65 tBCKH Pulse Width High ns tLRB 30 ILRCK1-3 Edge to IBICK1-3 “” (Note 19) ns tBLR 30 IBICK1-3 “” to ILRCK1-3 Edge (Note 19) ns tSDH 30 SDTI1-3 Hold Time from IBICK1-3 “” tSDS ns 30 SDTI1-3 Setup Time to IBICK1-3 “” Note 17. According to the crystal oscillator values in Table 2. Note 18. In the case of MCKO1-0bits = “10” (22.5792MHz), these are the values when External Clock Duty is 50%. Note 19. BICK rising edge must not occur at the same time as LRCK edge. MS1446-E-01 2015/05 - 11 - [AK7601A] Parameter Symbol min typ max Unit Control Interface Timing (I2C Bus mode): SCL Clock Frequency fSCL 400 kHz Bus Free Time Between Transmissions tBUF 1.3 s Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 s Clock Low Time tLOW 1.3 s Clock High Time tHIGH 0.6 s Setup Time for Repeated Start Condition tSU:STA 0.6 s SDA Hold Time from SCL Falling (Note 20) tHD:DAT 0 s SDA Setup Time from SCL Rising tSU:DAT 0.1 s Rise Time of Both SDA and SCL Lines tR 0.3 s Fall Time of Both SDA and SCL Lines tF 0.3 s Setup Time for Stop Condition tSU:STO 0.6 s Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 50 ns Capacitive load on bus Cb 400 pF Power-up Timing DVDD to AVDD tPU >0 ns Power-down & Reset Timing PDN “L” Width after AVDD is ON (Note 21) tPD1 150 ns PDN Pulse Width (Note 21) tPD2 200 ms Note 20. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 21. The AK7601A can be reset by bringing the PDN pin = “L”. The PDN pin must held “L” for more than 200 ms for a certain reset. Note 22. I2C-bus is a trademark of NXP B.V. MS1446-E-01 2015/05 - 12 - [AK7601A] ■ Timing Diagram 1/fCLK VIH XTI VIL tCLKH tCLKL 1/fMCK MCKO 50%DVDD tdMCKH tdMCKL dMCK = tdMCKH (or tdMCKL) x fMCK x 100 1/fs LRCK 50%DVDD tdLRKH tdLRKL dLRK = tdLRKH (or tdLRKL) x fs x 100 1/fBCK 50%DVDD BICK tdBCKH tdBCKL dBCK = tdBCKH (or tdBCKL) x fs x 100 Figure 3. Clock Timing VIH LRCK1-3 VIL tBLR tLRB VIH BICK1-3 VIL tSDS tSDH VIH SDTI1-3 VIL Figure 4. Audio Interface Timing (Input Port) MS1446-E-01 2015/05 - 13 - [AK7601A] OLRCK 50%DVDD tMBLR 50%DVDD OBICK tBSD 50%DVDD SDTO1-3 tSDS tSDH VIH SDTI4 VIL Figure 5. Audio Interface Timing (Output Port) VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT Start DVDD tSU:DAT tSU:STA tSU:STO Start Figure 6. I2C Bus Mode Timing Stop tPU AVDD tPD2 tPD1 VIH VIL PDN “L” “H” “L” “H” Figure 7. Power Up & Power Down Timing MS1446-E-01 2015/05 - 14 - [AK7601A] OPERATION OVERVIEW ■System Clock The external clock input or X’tal input is available for MCLK clock source. (Figure 8, Figure 9) The required clock is 22.579MHz MCLK only. In the normal operation, if the clock is stopped, click noise may occur when the clock supply is restarted. It can be prevented by external mute. OLRCK 44.1kHz MCKO (MHz) OBICK (MHz) 22.5792 2.8224 Table 1. System Clock Example ■ Clock Source The clock for the XTI pin can be generated by two methods: 1) External Clock (CLKMODE pin= “H”) XTI External Clock AK7601A XTO Figure 8. External Clock Mode Note. Do not input the clock over DVDD. 2) X’tal (CLKMODE pin= “L”) XTI AK7601A XTO Figure 9. X’tal Mode C0 0.78pF~1.2pF L1 C1 R1 20.475mH~11.8mH 2.428fF~4.2fH 24.1Ω~16.0Ω Table 2. Recommended Parameters of Crystal Oscillator L1 C1 CL 12pF~8pF R1 CL CL C0 Figure 10. Equivalent Circuit and Load Capacitance of Crystal Oscillator MS1446-E-01 2015/05 - 15 - [AK7601A] ■ Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 0.86Hz. ■ Master Clock Output Pin The MCKO pin is the output pin for master clock. MCKO1-0 bits control the master clock frequency. MCKO1 bit 0 0 1 1 MCKO0 bit Master Clock Speed 0 “L” Output 1 256fs (11.2896MHz) 0 512fs (22.5792MHz) 1 Reserved Table 3. Master Clock Output Select (default) ■ Audio Interface Input Format In all modes the serial data is MSB-first, two’s complement format and SDTI1-4 are latched on the rising edge of IBICK1-3 and OBICK respectively. IDIF1-0 bits setting is reflected on SDTI1-3 and IDIF41-40 bits setting is reflected on SDIT4. Use OLRCK, OBICK and IDIF when the SDTI3 data is input to Input2 instead of being used for SRC. Mode IDIF1 bit IDIF0 bit 0 1 2 0 0 1 0 1 0 3 1 1 SDTI1-3 Format ILRCK1-3 pins 16bit, LSB justified 24bit, LSB justified 24bit, MSB justified Input 24 or 16bit I2S Compatible 16bit, I2S Compatible Table 4. SDTI1~3 Input Audio Interface Format Mode IDIF41 bit IDIF40 bit 0 1 2 3 0 0 1 1 0 1 0 1 SDTI4 Format OLRCK pin 16bit, LSB justified 24bit, LSB justified Output 24bit, MSB justified 2 24 or 16bit I S Compatible Table 5. SDTI4 Input Audio Interface Format MS1446-E-01 IBICK1-3 pins Input IBICK1-3 Freq 32~64fs 48~64fs 48~64fs 48~64fs 32fs OBICK pin OBICK Freq Output 64fs (default) (default) 2015/05 - 16 - [AK7601A] ILRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 IBICK(32fs) SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 0 1 2 3 17 18 19 20 7 6 5 4 3 2 1 0 15 31 0 1 2 3 17 18 19 20 31 0 1 IBICK(64fs) SDTI(i) Don't Care 15 14 13 12 1 0 Don't Care 15 14 13 12 2 1 0 15:MSB, 0:LSB Lch Data Rch Data Figure 11. Mode 0 Timing (16bit, LSB justified) ILRCK 0 1 2 8 9 24 31 0 1 2 8 9 24 31 0 1 IBICK(64fs) SDTI(i) Don't Care 23 8 1 0 Don't Care 23 8 1 0 23:MSB, 0:LSB Lch Data Rch Data Figure 12. Mode 1 Timing (24bit, LSB justified) ILRCK 0 1 2 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1 IBICK(64fs) SDTI(i) 23 22 4 3 2 1 0 Don't Care 23 22 4 3 2 1 0 Don't Care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 13. Mode 2 Timing (24bit, MSB justified) ILRCK 0 1 2 3 21 22 23 24 25 0 1 2 21 22 23 24 25 0 1 IBICK(64fs) SDTI(i) 23 22 4 3 2 1 0 Don't Care 23 22 4 3 2 1 0 Don't Care 23:MSB, 0:LSB Lch Data Rch Data 2 Figure 14. Mode 3 Timing (24bit I S) Note : SDTI represents SDTI1, SDTI2, SDTI3 and SDTI4, ILRCK represents ILRCK1, ILRCK2, ILRCK3 and OLRCK, BICK represents IBICK1 IBICK2, IBICK3 and OBICK in the figures above. MS1446-E-01 2015/05 - 17 - [AK7601A] ■ Audio Interface Output Format DIF bit selects between two serial data modes as shown in Table 6. In all modes the serial data is MSB-first, two’s complement format and SDTO1-3 are latched on the rising edge of OBICK. DIF Mode OLRCK I/O SDTO1-3 24bit, Left justified 24bit, I2S 0 1 OBICK I/O H/L O 64fs O L/H O 64fs O (default) Table 6. Audio Data Format (Stereo mode) OLRCK 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 1 OBICK(64fs) 23 22 SDTO(o) 12 11 10 0 23 22 12 11 10 0 23 SDTO-23:MSB, 0:LSB Lch Data Rch Data Figure 15. Mode 0 Timing (Left justified mode) OLRCK 0 1 2 3 22 23 24 25 29 30 31 0 1 2 3 22 23 24 25 29 30 31 0 1 OBICK(64fs) SDTO(o) 23 22 2 1 0 23 22 2 1 0 23:MSB, 0:LSB Lch Data Rch Data Figure 16. Mode 1 Timing (I2S Mode) MS1446-E-01 2015/05 - 18 - [AK7601A] ■ Zero Detect Function The AK7601A has independent zeros detect function for each DAC. This function is always enabled. Channel grouping can be selected by DZD1-3 bits of CONT1 and its covers 6-channel outputs. Counting on “AND” for zero detected flags of selected channels, when the input data is continuously zeros for 8192 LRCK cycles, the DZF pin goes to “H” if DZLH bit (CONT1) is “0”, the DZF pin goes to “L” if DZLH bit (CONT1) is “1”. The DZF pin immediately returns to “L” (DZLH bit “0”) or “H” (DZLH bit “1”) if the input data is not zero after the zero detection. ■ Digital Volume AK7601A has a channel-independent digital attenuator (256 levels, 0.5dB steps). Attenuation level of each channel can be set by each the ATT7-0 bits (Table 7). ATT7-0 00H 01H 02H : 7DH 7EH 7FH FEH FFH Attenuation Level 0dB -0.5dB -1.0dB : -62.5dB -63.0dB -63.5dB : -127.0dB MUTE (-∞) (default) Table 7. Attenuation Level The transition between set values is a soft transition of 4096 levels eliminating switching noise in the transition. It takes 4096/fs (23.2ms) from 00H(0dB) to FFH(MUTE). If the PDN pin goes to “L”, the ATT7-0 bits are initialized to 00H. The ATTs also become 00H when RSTN bit = “0”, and fade to their current setting value when RSTN bit returns to “1”. MS1446-E-01 2015/05 - 19 - [AK7601A] ■ Soft Mute (MUTE1, MUTE2) (Figure 33) Soft mute operation is performed in the digital domain. When the MUTEN pin is set to “L” or SMUTE bit is set “0”, the output signal is attenuated to -∞ in the time set by MCONT bit. When the SMUTE bit is returned to “1”, the mute is cancelled and the output attenuation level gradually changes to 0dB in the time set by MCONT bit. If the soft mute is cancelled before attenuating -∞, the attenuation is discontinued and the attenuation level is returned to 0dB by the same cycle. Soft mute is effective for changing the signal source without stopping the signal transmission. MUTEN pin or SMUTEN bit D-Volume1 Full Level (1) (3) (5) (2) ATT Level - (2) GD (4) GD AOUT DZF (6) 8192/fs Note: (1) The transition time to attenuate input data to -∞ in linear steps is set by MCONT bit. (2) There is delay, which is set by the Delay block, from a falling edge of the MUTEN pin or SMUTEN bit to start the attenuation. (3) The transition time to return to the full scale of the input signal to LG1, RG1, LG2 and RG2 is set by MCONT bit. (4) Analog output corresponding to digital input has a group delay (GD). (5) If the soft mute is cancelled before attenuating -∞ after starting the operation, the attenuation is discontinued and the digital volume is returned to the full scale level by the same cycle. (6) When the input data for both channels are continuously zero for 8192 LRCK cycles and DZLH bit is “0”, the DZF pin goes to “H” (the DZF pin goes to “L” if the DZLH bit is “1”). The DZF pin immediately returns to “L” if the input data are not zero after going to DZF “H” (DZLH bit =“0”). Figure 17. Soft Mute and Zero Detect Function MS1446-E-01 2015/05 - 20 - [AK7601A] ■ Soft Mute (FMUTE, RMUTE, SWMUTE, MOMUTE) (Figure 33) Soft mute operation is performed in the digital domain. When the FMUTE, RMUTE, SWMUTE or MOMUTE bit is set “1”, the output signal is attenuated to -∞ in 1024 LRCK cycles. When these bits are returned to “0”, the mute is cancelled and the output attenuation level gradually changes to 0dB in 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles after starting this operation, the attenuation is discontinued and the attenuation level is returned to 0dB by the same cycle. Soft mute is effective for changing the signal source without stopping the signal transmission. FMUTE bit RMUTE bit SWMUTE bit MOMUTE bit D-Volume1 Full Level (1) (2) (4) ATT Level - GD (3) GD AOUT DZF (5) 8192/fs Note: (1) The transition time to attenuate input data to -∞ in linear steps is 1024 LRCK cycles (1024/fs). (2) The transition time to return to the full scale of digital volume output signal is 1024 LRCK cycles (1024/fs). (3) Analog output corresponding to digital input has group delay (GD). (4) If the soft mute is cancelled before attenuating -∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. (5) When the input data for both channels are continuously zero for 8192 LRCK cycles and DZLH bit is “0”, the DZF pin goes to “H” (the DZF pin goes to “L” if DZLH bit is “1”). The DZF pin immediately returns to “L” if the input data are not zero after going to DZF “H” (DZLH bit =“0”). Figure 18 Soft Mute and Zero Detect Function MS1446-E-01 2015/05 - 21 - [AK7601A] ■ Pseudo-Differential Input (AINL1/AINR1, AINL2/AINR2) The AK7601A has two sets of pseudo-differential input channels. LIN1 + AAF + GND1 VCOM=AVDD/2 + - AAF RIN1 Figure 19. Pseudo-Differential Input Block When power-on the AK7601A, capacitors that connected to the pseudo-differential input pin are charged in high speed (Fast mode). This first mode is controlled by a register (FCHA0 bit). The charging time in fast mode is 40ms (typ) and 100ms (max). (01H: D4 bit) FCHA0 1 0 Fast Charge ON OFF Table 8. Fast Charge (default) ■ Input Selector The AK7601A has an analog input selector for ADC and a digital input selector for SRC. SEL01-00 bits and SEL11-10 bits control these input selectors. Click noise may occur when SEL01-00 bits and SEL11-10 bits are changed. Mute digital output if the click noise affects system performance. SEL01 0 0 1 1 SEL00 0 1 0 1 ADC Input AINL1/AINR1 AINL2/AINR2 AINL3/AINR3 AINL4/AINR4 (default) Table 9. Analog Input Selector SEL11 0 0 1 1 SEL10 0 1 0 1 SRC Input SDTI1 SDTI2 SDTI 3 Reserved (default) Table 10. Digital Input Selector MS1446-E-01 2015/05 - 22 - [AK7601A] ■ Power-up Sequence The PDN pin must be “L” until all power supplies are ON. AVDD must be supplied after DVDD is ON. DVDD AVDD PDN “L” “H” Figure 20. Power-up Sequence ■ System Reset The internal regulator will be powered-up by inputting the master clock to the XTI pin or connecting a X’tal after setting the PDN pin to “H”. In X’tal mode, the internal regulator is powered-up in 5ms after the PDN pin becomes “H”. In external clock mode, the internal regulator is powered-up in 5ms after clock input. When the regulator is powered-up, the internal master clock starts by setting RSTN bit to “1”. MS1446-E-01 2015/05 - 23 - [AK7601A] ■ Power Down The ADC and DAC parts of the AK7601A are placed in the power-down mode by bringing the PDN pin “L” and the digital filter is also reset at the same time. The internal registers are initiated to their default value by the PDN pin = “L”. This reset should always be made after power-up. In the power-down mode, SDTO1/SDTO3, SDTO2/SDTI4, OBICK, OLRCK and DZF pins go to “L” and the analog output is VSS. When exiting the power-down mode, the AK7601A will be in reset state since the RSTN bit = “0”. Figure 21 shows the power on/off sequence example. PDN 5ms(1) PDN Internal (2) RSTN Regulator ADC Internal State DAC Internal State ADC In (Analog) Normal Operation Normal Operation Power Down Normal Operation Power Down GD(4) “0” data(5) SDTO1~3 DAC Out (Analog) Clock In XTI(external) Clock In X'tal DZF (3) Power Down GD(4) (7) (6) (8) (9) DZLH= “1” (10) DZLH= “0” Note: (1) After the PDN pin = “H”, the internal PDN is “L” until X’tal and regulator are powered-up. (Register writing is not valid for 5ms of this period) (2) During the RSTN bit is “0”, all circuits will be powered down except the regulator and X’tal even when the internal PDN is “H”. (3) Regulator will be powered-up after the PDN pin becomes “H”. (4) The DAC and SDTO1-3 outputs corresponding to the ADC input has group delay (GD). (5) The SDTP1-3 outputs are “0” when the AK7601A is powered-down. (6) The DAC output is VSS voltage when the AK7601A is powered-down. (7) Click noise occurs at the falling edge of PDN. (8) In case of connecting a X’tal, the clock output is “L” when the PDN pin =“L”. The X’tal will be powered up after the PDN pin =“H”. (9) In power down mode (PDN pin = “L”), the DZF pin = “L”. (10) The DZF pin output will reflects the DZLH bit setting when internal PDN is “H”. Figure 21. Power Up/Down Sequence Example MS1446-E-01 2015/05 - 24 - [AK7601A] ■ Reset Function When the RSTN bit = “0”, ADC and DAC parts of the AK7601A is powered down, but the internal register values are not initialized. The analog outputs settle to VCOM voltage, SDTO1/SDTO3, SDTO2/SDTI4, OBICK and OLRCK pins go to “L” and the DZF pins for both channels go to “H” or “L” depending on the DZLH bit setting. Click noise occurs at this timing. Mute the analog output externally if the click noise influences system application. Figure 22 shows the example of reset by RSTN bit. RSTN bit Internal RSTN(ADC) Internal RSTN(IIR) Internal RSTN(DAC) ADC Internal State IIR Internal State DAC Internal State ADC In (Analog) ~1/fs(2) 4~5/fs(1) 8/fs (3) Normal Operation Power Down Normal Operation Power Down Normal Operation Power Down Normal Operation 7~8/fs (4) Init Normal Operation 1.5~2.5/fs (5) Normal Operation Init GD(6) GD(6) "0" data(7) SDTO13~ DAC Out (Analog) Init Cycle GD(6) (9) (10) (8) (9) GD(6) (8) Don't care(11) Clock In XTI(external) Clock In X'tal DZF 9/fs DZLH="0" (12) Note: (1) (2) (3) (4) (5) (6) (7) (8) Internal RSTN will be “L”, 4~5/fs after RSTN bit changed to “0”. ADC internal RSTN will be “H”, within 1/fs from RSTN bit = “1”. The reset cycle is 8/fs after ADC internal RSTN became “H”. Internal RSTN for IIR will be “H” after 7~8/fs from RSTN bit =“1”. Internal RSTN for DAC will be “H” after 1.5~2.5/fs from RSTN bit = “1”. The DAC, SDTO1/SDTO3 and SDTO2/SDTI4 outputs corresponding to the ADC input has group delay (GD). The SDTO1/SDTO3 and SDTO2/SDTI4 outputs are “0” data when the AK7601A is in powered down mode. Click noise occurs when the initialization of ADC block is finished. Mute digital output if click noise adversely affects system performance. (9) Click noise occurs at the edge of internal RSTN. (10) Analog output is VCOM voltage (AVDD/2) when RSTN bit = “0”. (11) In case of inputting CLK from the XTI pin, the clock should be input before the RSTN bit is changed to “1” after the RSTN bit was set to “0”. (12) The DZF pin reflects the setting of DZLH bit. This pin changes to “L” or “H” 9/fs after the RSTN bit was set to “0”. (13) Register settings for path switching except SEL01-00, SEL11-10 and SW1 bits, and command code change should be made during RSTN bit = “0”. Figure 22. Reset Sequence Example MS1446-E-01 2015/05 - 25 - [AK7601A] ■ I2C BUS INTERFACE (Microcontroller Interface) Access to the AK7601A registers and RAM is processed by I²C bus. The format of the I²C is complement with fast mode (max: 400kHz). The AK7601A does not support Hs mode. (max: 3.4MHz). ■ Data Transfer In order to access any IC devices on the I2C BUS, input a start condition first, followed by a single Slave address which includes the Device Address. IC devices on the BUS compare this Slave address with their own addresses and the IC device which has an identical address with the Slave-address generates an acknowledgement. An IC device with the identical address then executes either a read or a write operation. After the command execution, input a Stop condition. 1-1. Data Change Change the data on the SDA line while SCL line is “L”. SDA line condition must be stable and fixed while the clock is “H”. Change the Data line condition between “H” and “L” only when the clock signal on the SCL line is “L”. Change the SDA line condition while SCL line is “H” only when the start condition or stop condition is input. SCL SDA DATA LINE STABLE : DATA VALID CHANGE OF DATA ALLOWED Figure 23. Data Transition 1-2. Start condition and Stop condition Start condition is generated by the transition of “H” to “L” on the SDA line while the SCL line is “H”. All instructions are initiated by Start condition. Stop condition is generated by the transition of “L” to “H” on SDA line while SCL line is “H”. All instructions end by Stop condition. SCL SDA START CONDITION STOP CONDITION Figure 24. Start Condition and Stop Condition MS1446-E-01 2015/05 - 26 - [AK7601A] 1-3. Repeated Start Condition When a start condition is received again instead of a stop condition, the bus changes to repeated start condition. A repeated start condition is functionally the same as a start condition. SCL SDA START CONDITION Repeated Start CONDITION Figure 25. Repeated Start Condition 1-4. Acknowledge An external device that is sending data to the AK7601A releases the SDA line (“H”) after receiving one-byte of data. An external device that receives data from the AK7601A then sets the SDA line to “L” at the next clock. This operation is called “acknowledgement” and it enables verification that the data transfer has been properly executed. The AK7601A generates an acknowledgement upon receipt of Start condition and Slave address. For a write instruction, an acknowledgement is generated whenever receipt of each byte is completed. For a read instruction, succeeded by generation of an acknowledgement, the AK7601A releases the SDA line after outputting data at the designated address, and it monitors the SDA line condition. When the Master side generates an acknowledgement without sending a Stop condition, the AK7601A outputs data at the next address location. When no acknowledgement is generated, the AK7601A ends data output (not acknowledged). Clock pulse for acknowledge SCL FROM MASTER 1 8 DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER 9 not acknowledge acknowledge START CONDITION Figure 26. Acknowledge MS1446-E-01 2015/05 - 27 - [AK7601A] 1-5. The First byte The First Byte which includes the Slave-address is input after the Start condition is set, and a target IC device that will be accessed on the bus is selected by the Slave-address. The Slave-address is configured with the upper 7-bits. Data of the upper 7-bits is “0011000”. The address bits that select the desired IC are fixed. When the Slave-address is inputted, an external device that has the identical device address generates an acknowledgement and instructions are then executed. The 8th bit of the First Byte (lowest bit) is allocated as the R/W Bit. When the R/W Bit is “1”, the read instruction is executed, and when it is “0”, the write instruction is executed. Note 23. In this document, there is a case that describes a “Write Slave-address assignment” when both address bits match and a Slave-address at R/W Bit = “0” is received. There is a case that describes “Read Slave-address assignment” when both address bits matches and a Slave-address at R/W Bit = “1” is received. 0 0 1 1 0 0 0 R/W Slave Address is fixed 30H(write) or 31H(read). Figure 27. The First Byte Structure 1-6. The Second and Succeeding Bytes The data format of the second and succeeding bytes of the AK7601A Transfer / Receive Serial data (command code, address and data in microcontroller interface format) on the I 2C BUS are all configured with a multiple of 8-bits. When transferring or receiving those data on the I 2C BUS, they are divided into an 8-bit data stream segment and they are transferred / received with the MSB side data first with an acknowledgement in-between. When transferring / receiving A1B2C3 (hex) 24-bit serial data in microprocessor interface format: (1)I2C Format A1 B2 C3 A 8BIT A 8BIT 8BIT A Acknowledge Figure 28. Division of the Data Note 24. In this document, there is a case that describes a write instruction command code which is received at the second byte as “Write Command”. There is a case that describes a read instruction command code which is received at the second byte as “Read Command” MS1446-E-01 2015/05 - 28 - [AK7601A] ■ Command Code BIT7 BIT6 8/16(*1)/16(*2)/32 flag BIT5 BIT4 BIT3 BIT2 Area to be accessed BIT1 BIT0 (1) 8/16(*1)/16(*2)/32 flag When BIT[7:6] bits are “00”, the following data will be 8bit. The data will be 16bit 1word in 2byte transfer when “01”, 16bit 1word x 5 in 10byte transfer when “10”, and 32bit 1word x 5 in 20byte transfer when “11”. (2) Accompanying data to the access area BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 BIT1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 BIT0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 MS1446-E-01 Command and Content 01H Control Register CONT1 Setting 02H Control Register CONT2 Setting 03H Control Register CONT3 Setting 04H Control Register CONT4 Setting 05H Control Register CONT5 Setting 06H Control Register LOUT1VOL Setting 07H Control Register ROUT1VOL Setting 08H Control Register LOUT2VOL Setting 09H Control Register ROUT2VOL Setting 0AH Control Register LOUT3VOL Setting 0BH Control Register ROUT3VOL Setting 0CH Control Register MONOLVOL Setting 0DH Control Register MONORVOL Setting 0EH Control Register SWCONT1 Setting 0FH Control Register SWCONT2 Setting 40H EQ Gain1 Setting 41H EQ Gain2 Setting 42H Cross Over Fout Gain Setting 43H Cross Over Rout Gain Setting 44H Cross Over SWout Gain Setting 45H FrontL1 Delay Setting 46H FrontR1 Delay Setting 47H RearL2 Delay Setting 48H RearR2 Delay Setting 49H SWL3 Delay Setting 4AH SWR3 Delay Setting 50H Read SpeAna 1Band (125Hz) 51H Read SpeAna 2Band (500Hz) 52H Read SpeAna 3Band (2KHz) 53H Read SpeAna 4Band (8KHz) 2015/05 - 29 - [AK7601A] BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0 1 0 1 0 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 1 1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 1 0 Command and Content 80H Input Gain Setting 81H function1 Gain1 Setting 82H function1 Gain2 Setting 84H function1 in Filter Coefficient Setting Preparation 85H function1 out Filter Coefficient Setting Preparation 88H function2 LPF2 Filter Coefficient Setting Preparation 8CH function2 Gain1 Setting 8DH funciotn2 Gain Low Setting 90H Function3 Gain1 Coefficient Setting Preparation 91H Function3 Gain2 Coefficient Setting Preparation 92H Function3 Filter Coefficient Setting Preparation 93H Function4 Gain Coefficient Setting Preparation 94H Function5 Gain Coefficient Setting Preparation 95H Function5 Filter Coefficient Setting Preparation 96H EQ Bind2 Coefficient Setting Preparation 97H EQ Band5 Coefficient Setting Preparation 98H EQ Band6 Coefficient Setting Preparation 99H EQ Band7 Coefficient Setting Preparation 9AH EQ Band9 Coefficient Setting Preparation 9BH EQ Band12 Coefficient Setting Preparation 9CH EQ Band13 Coefficient Setting Preparation 9DH EQ Band14 Coefficient Setting Preparation 9EH X’ Over Filter1-3 Coefficient Setting Preparation 9FH SpeAna3Band Coefficient Setting Preparation A0H SpeAna4Band Coefficient Setting Preparation A1H FR Gain Setting A2H SW Gain Setting MS1446-E-01 2015/05 - 30 - [AK7601A] BIT7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT6 BIT5 BIT4 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 BIT3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 BIT2 BIT1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 BIT0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MS1446-E-01 Command and Content C0H function2 LPF0 Filter Coefficient Setting Preparation C2H Function4 Filter Coefficient Setting Preparation C3H EQ Band1 Coefficient Setting Preparation C4H EQ Band3 Coefficient Setting Preparation C5H EQ Band4 Coefficient Setting Preparation C6H EQ Band8 Coefficient Setting Preparation C7H EQ Bnad10 Coefficient Setting Preparation C8H EQ Band11 Coefficient Setting Preparation C9H X’ Over Filter1-1 Coefficient Setting Preparation CAH X’ Over Filter2-1 Coefficient Setting Preparation CBH X’ Over Filter3-1 Coefficient Setting Preparation CCH X’ Over Filter1-2 Coefficient Setting Preparation CDH X’ Over Filter2-2 Coefficient Setting Preparation CEH X’ Over Filter3-2 Coefficient Setting Preparation CFH SpeAna1Band Coefficient Setting Preparation D0H SpeAna2Band Coefficient Setting Preparation D1H SpeAna SDS Coefficient Setting Preparation 2015/05 - 31 - [AK7601A] Write Sequence In the AK7601A, when a “Write-Slave-address assignment” is received at the first byte, the write command at the second byte and data at the third and succeeding bytes are received. At the data block, address and write data are received in a single-byte unit each in accordance with a command code. The number of write data bytes (*1 in Figure 29) is fixed by the received command code. Usable command codes in write sequence are listed below as “Table 11. List of Usable Command Codes in Write Sequence”. S SLAD W A Cmd A Data A Stp repeat N times (*1) Figure 29. Write Sequence Command Code 40H ~ 4AH 80H ~ A2H C0H ~ D1H 01H ~ 0F Data Length 2-byte 10-byte 20-byte 1byte Content Transferring 16bit coefficient data in 1-coefficient unit Transferring 16bit coefficient data in 5-coefficient or 1-filter unit Transferring 28bit coefficient data in 5-coefficient or 1-filter unit Writing Control Register Table 11. List of Usable Command Codes in Write Sequence MS1446-E-01 2015/05 - 32 - [AK7601A] Data Format Data Write (1) Control Register Write SDA (1) COMMAND 01H~0F (2) DATA D7~D0 (2) 16bit Coefficient (1-coefficient unit) or Delay Data Write SDA (1) COMMAND 40H~4AH (2) DATA1-1 D15~D8 (3) DATA1-2 D7~D0 (3)16bit Coefficient (5-coefficient unit) Write SDA (1) COMMAND 80H~A2H (2) DATA1-1 D15~D8 (3) DATA1-2 D7~D0 (4) DATA2-1 D15~D8 (5) DATA2-2 D7~D0 (6)~(11) (Continues in 2byte unit from DATA3 to DATA5. In total 10byte DATA) (4)28bit Coefficient Data Write SDA (1) COMMAND C0H~D1H (2) DATA1-1 0 0 0 0 D27~D24 (3) DATA1-2 D23~D16 (4) DATA1-3 D15~D8 (5) DATA1-4 D7~D0 (6)~(21) (Continues in 4byte unit from DATA2 to DATA5. In total 20byte DATA) MS1446-E-01 2015/05 - 33 - [AK7601A] Read Sequence In the AK7601A, when a “write- slave-address assignment” is received at the first byte, the command is send from micro controller in the second byte. When the slave address is received after the start condition, the AK7601A starts outputting the data regarding to command code. When cancelling read operation before the AK7601A sends all data, assure that a “not acknowledged” signal is received by the AK7601A. If this “not acknowledged” signal is not received, the AK7601A continues to send data until specified number, and since it did not release the BUS, the stop condition cannot be properly received. Usable command codes in read sequence are listed in Table 12 S SLAD W A Cmd A rS SLAD R A Data A repeat N times Data Na Stp * Cancel Figure 30. Read Sequence Command Code 40H ~ 4AH 80H ~ A2H C0H ~ D1H 01H ~ 0F 50H ~ 53H Data Length 2-byte 10-byte 20-byte 1byte 2-byte Content Reading 16bit coefficient data in 1-coefficient unit Reading 16bit coefficient data in 5-coefficient or 1-filter unit. Reading 28bit coefficient data in 5-coefficient or 1-filter unit. Reading Control Register Reading Spectrum Analyzer Data Table 12. List of Usable Read Command Codes in Read Sequence MS1446-E-01 2015/05 - 34 - [AK7601A] Data Read (1) Control Register Read SDA (1) COMMAND 01H~0F (Input) (2) DATA D7~D0 (2) 16bit Coefficient (1-coefficient unit) or Delay Time Read SDA (1) COMMAND 40H~4AH (Input) (2) DATA1-1 D15~D8 (Output) (3) DATA1-2 D7~D0 (3)16bit Coefficient (5-coefficient unit) Read SDA (1) COMMAND 80H~A2H (Input) (2) DATA1-1 D15~D8 (Output) (3) DATA1-2 D7~D0 (4) DATA2-1 D15~D8 (5) DATA2-2 D7~D0 (6)~(11) (Continues in 4byte unit from DATA3 to DATA5. In total 10byte DATA) (4)28bit Coefficient Data Read SDA (1) COMMAND C0H~D1 (Input ) (2) DATA1-1 0 0 0 0 D27~D24 (Output ) (3) DATA1-2 D23~D16 (4) DATA1-3 D15~D8 (5) DATA1-4 D7~D0 (6)~(21) (Continues in 4byte unit from DATA2 to DATA5. In total 20byte DATA) (5) Spectrum Analyzer Data Read SDA (1) COMMAND 50H, 51H, 52H, 53H (Input) (2) DATA2 D15 D14 D13 D12 D11 D10 D9 D8 (Output) (3) DATA1 D7 D6 D5 D4 D3 D2 D1 D0 MS1446-E-01 2015/05 - 35 - [AK7601A] ■ Register Map Command 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Register Name CONT1 CONT2 CONT3 CONT4 CONT5 LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control LOUT3 Volume Control ROUT3 Volume Control MONOIN L Volume Control MONOINR Volume Control SWCONT1 SWCONT2 D7 0 DZD3 D6 0 DZD2 D5 0 DZD1 D4 FCHA DZLH MOMUTE FMUTE RMUTE SWMUTE LRCK 0 BICK 0 MCKO1 0 ATT7 ATT6 ATT7 D3 MCKO0 0 ODIF IDIF41 DO21 SEL11 D2 PMADC 0 IDIF40 DO20 SEL10 D1 PMDAC MCONT IDIF1 DO11 SEL01 D0 RSTN SMUTEN IDIF0 DO10 SEL00 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 0 0 SW51 0 SW50 0 SW4 SWSW SW31 RSW SW30 FSW SW2 EQSW1 SW1 EQSW0 PMADCM Note: All registers are initialized by the PDN pin = “L”. When RSTN bit becomes “0”, the internal timing is reset but the registers are not initialized. Data must not be written into addresses from 10H to 1FH. The bits defined as 0 must contain a “0” value. MS1446-E-01 2015/05 - 36 - [AK7601A] ■ Register Definitions Command Register name 01H CONT1 Default R/W D7 0 0 RD D6 0 0 RD D5 0 0 RD D4 FCHA 1 R/W D3 PMADCM 1 R/W D2 PMADC 1 R/W D1 PMDAC 1 R/W D0 RSTN 0 R/W FCHA: High Speed Charge Mode Enable 0: High Speed Charge Disable 1: High Speed Charge Enable (default) PMADCM: ADC Mono Power Management 0: ADC Power Down 1: Normal Operation PMADC: ADC Power Management 0: ADC Power Down 1: Normal Operation PMDAC: DAC1-3 Power Management 0: All DACs Power Down 1: Normal Operation RSTN: Internal Timing Reset 0: Reset The DZF pin becomes “H” or “L” depending on DZLH bit but registers are not initialized. 1: Normal Operation MS1446-E-01 2015/05 - 37 - [AK7601A] Command 02H Register Name CONT2 Default R/W D7 DZD3 0 R/W D6 DZD2 0 R/W D5 DZD1 0 R/W D4 DZLH 0 R/W D3 DIF 1 R/W D2 0 0 RD D1 MCONT 0 R/W D0 SMUTEN 0 R/W DZD3: DZF Setting 0: The DZF pin reflects the zero-detection of DAC3 1: The DZF pin ignores the zero-detection of DAC3 DZD2: DZF Setting 0: The DZF pin reflects the zero-detection of DAC2 1: The DZF pin ignores the zero-detection of DAC2 DZD1: DZF Setting 0: The DZF pin reflects the zero-detection of DAC1 1: The DZF pin ignores the zero-detection of DAC1 DZLH: DZF pin polarity setting 0: Output “H” when the zero data is detected. 1: Output “L” when the zero data is detected D7 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D6 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DAC3 Zero Zero Zero Zero Zero Zero Zero Zero - DAC2 DAC1 DZF pin output Level Zero Zero H Zero H Zero H H Zero Zero H Zero H Zero H H Zero Zero L Zero L Zero L L Zero Zero L Zero L Zero L L Table 13. Zero Detection Control DIF: Digital Output Format (DIF mode setting) 0: Left justified mode 1: I2S mode (default) MCONT: Soft Mute Time Setting 0: 1024/fs (default) 1: 22/fs SMUTEN: MUTE1, MUTE2 Block MUTEN pin L H SMUTEN bit All Analog Outputs Status 0 Mute 1 Mute 0 Mute 1 Unmute Table 14. Soft Mute Control MS1446-E-01 (default) (default) 2015/05 - 38 - [AK7601A] Command Register Name 03H CONT3 Default R/W D7 MOMUTE 0 R/W D6 FMUTE 0 R/W D5 RMUTE 0 R/W D4 SWMUTE 0 R/W D3 IDIF41 1 R/W D2 IDIF40 1 R/W D1 IDIF1 1 R/W D0 IDIF0 1 R/W MOMUTE: MOMUTE Block 0: Un-mute (default) 1: Mute (Refer to p44; DSP Block Construction) FMUTE: FMUTE Block 0: Un-mute (default) 1: Mute (Refer to p44; DSP Block Construction) RMUTE: RMUTE Block 0: Un-mute (default) 1: Mute (Refer to p44; DSP Block Construction) SWMUTE: SWMUTE Block 0: Un-mute (default) 1: Mute (Refer to p44; DSP Block Construction) IDIF41-IDIF40: Digital Input Format, IDIF Mode Setting (SDIT4) 00: 16bit LSB Justified Mode 01: 24bit LSB Justified Mode 10: 24bit MSB Justified Mode 11: 16bit/24bit I2S Mode (default) IDIF1-IDIF0: SRC Digital Input Format, IDIF Mode Setting (SDIT1, SDTI2, SDTI3) 00: 16bit LSB Justified Mode 01: 24bit LSB Justified Mode 10: 24bit MSB Justified Mode 11: 16bit/24bit I2S Mode (default) MS1446-E-01 2015/05 - 39 - [AK7601A] Command 04H Register Name CONT4 Default R/W D7 LRCK 0 R/W D6 BICK 0 R/W D5 MCKO1 0 R/W D4 MCKO0 0 R/W D3 DO21 0 R/W D2 DO20 0 R/W D1 DO11 0 R/W D0 DO10 0 R/W LRCK: LRCK Output Enable 0: The OLRCK pin outputs “L”. (default) 1: The OLRCK pin outputs LRCK(1fs). BICK: BIT Clock Output Enable 0: The OBICK pin outputs “L”. (default) 1: The OBICK pin outputs 64fs BIT clock. MCKO1-0: Master Clock Output Enable MCKO1 MCKO0 Master Clock Speed 0 0 “L” Output (default) 0 1 256fs (11.2896MHz) 1 0 512fs (22.5792MHz) 1 1 Reserved Table 3. Master Clock Output Select DO21-DO20: SDTO2/SDTI4 In/Output Enable DO21 DO20 SDTO2/SDTI4 pin 0 0 “L” Output 0 1 SDTO2 1 0 SDTI4 (Input) 1 1 Reserved Table 15. SDTO2/SDTI4 Input/Output Select (default) DO11-DO10: SDTO1/SDTO3 Output Enable DO11 DO10 SDTO1/SDTO3 pin 0 0 “L” Output 0 1 SDTO1 1 0 SDTO3 1 1 Reserved Table 16. SDTO1/SDTO3 Output Select MS1446-E-01 (default) 2015/05 - 40 - [AK7601A] Command 05H Register Name CONT5 Default R/W D7 0 0 RD D6 0 0 RD D5 0 0 RD D4 0 0 RD D3 SEL11 0 R/W D2 SEL10 0 R/W D1 SEL01 0 R/W D0 SEL00 0 R/W SEL11-10: SRC Input Selector Control SEL11 SEL10 SRC Input 0 0 SDTI1 0 1 SDTI2 1 0 SDTI3 1 1 Reserved Table 10. Digital Input Selector (default) SEL01-00: Analog Input Selector Control SEL01 SEL00 ADC Input 0 0 AINL1/AINR1 0 1 AINL2/AINR2 1 0 AINL3/AINR3 1 1 AINL4/AINR4 Table 9. Analog Input Selector MS1446-E-01 (default) 2015/05 - 41 - [AK7601A] Command 06H 07H 08H 09H 0AH 0BH 0CH 0DH Register Name LOUT1VOL ROUT1VOL LOUT2VOL ROUT2VOL LOUT3VOL ROUT3VOL MONOLVOL MONORVOL Default R/W D7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 0 R/W D6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 0 R/W D5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 0 R/W D4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 0 R/W D3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 0 R/W D2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 0 R/W D1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 0 R/W D0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 0 R/W ATT7-ATT0: Attenuation Level ATT7-0 00H 01H 02H : 7DH 7EH 7FH FEH FFH Attenuation Level (default) 0dB -0.5dB -1.0dB : -62.5dB -63.0dB -63.5dB : -127.0dB MUTE (-∞) Table 7. Attenuation Level MS1446-E-01 2015/05 - 42 - [AK7601A] Command 0EH Register Name SWCONT1 Default R/W D7 0 0 RD D6 SW51 0 R/W SW51-50: SDTO3, SDTI4 Selector Control Mode SW51 SW50 Switch a Mode1 0 0 GND Mode2 0 1 SDTO EQ Mode3 1 0 SDTO Delay Mode4 1 1 - D5 SW50 0 R/W Switch b SDTOEQ SDTI4 SDTOEQ - D4 SW4 0 R/W D3 SW31 0 R/W Switch c SDTO Delay SDTO Delay SDTI4 - D2 SW30 1 R/W D1 SW2 0 R/W D0 SW1 0 R/W Comment No In/Output In/Output before Delay In/Output after Delay Reserved Refer to Figure 33 Table 17. SDTO3/SDTI4 Selector Control SDTI4 SDTO3 a SDTO Delay c SDTO EQ R1 Delay Control L1 b Figure 31. SDTO3/SDTI4 Block Diagram SW4: AOUT3L/R pin Output Control 0: Outputs AOUT3L/R (default) 1: Outputs AOUT2L/R Refer to Figure 33 SW31-30: MG2 Selector Control Refer to Figure 33 SW31 0 0 1 1 SW30 MG2 Input 0 SRC 1 ADC (default) 0 SDTI3 1 Table 18. MG2 Selector Control SW2: MG1 Selector Control 0: SRC (default) 1: ADC Refer to Figure 33 SW1: De-emphasis Control 0: Dem-OFF (default) 1: Dem-ON (44.1kHz) Refer to Figure 33 MS1446-E-01 2015/05 - 43 - [AK7601A] Command 0FH Register Name SWCONT2 Default R/W D7 0 0 RD D6 0 0 RD D5 0 0 R/W D4 SWSW 0 R/W D3 RSW 0 R/W D2 FSW 0 R/W D1 EQSW1 0 R/W D0 EQSW0 0 R/W SWSW: SW Input Source Select 0: Input1 (default) 1: Input2 Refer to Figure 33 RSW: Rear Input Source Select 0: Input1 (default) 1: Input2 Refer to Figure 33. FSW: Front Input Source Select 0: Input1 (default) 1: Input2 Refer to Figure 33 EQSW2-1: Equalizer Block Setting Mode EQSW2 EQSW1 Mode1 0 0 Mode2 0 1 Mode3 1 0 Mode4 1 1 Switch A EQBand2 EQBand9 EQBand2 EQBand2 Switch B Comment EQBand7 14 band mode (default) EQBand2 4 band + 5 band x 2 mode EQGain2 7 band x 2 mode1 EQGain1 7 band x 2 mode2 Refer to Figure 39 about Switch A and B Table 19. EQSW Mode Select Mode1 2Band 5Band 2Band 2Band Mode2 2Band 5Band 5Band 5Band Mode3 2Band 5Band 2Band 5Band 2Band 5Band 2Band 5Band Mode4 Figure 32. EQSW1-0 Setting Examples MS1446-E-01 2015/05 - 44 - [AK7601A] ■ Blocks and Circuits Construction of Command Setting SDTO2/SDTI4 SDTO1/3 D-volume * set by CONT5-12(06H~0D) SDTO1 SDTO2 ADC SW1 RMV b SW2 DAC FMUTE AOUT1L AOUT1R SDTO1 R2V L2 AOUT2L DAC RMUTE MUTE2 AOUT2R SDTO2 SW4 R2 Input2 Xover <<2 SW3 L3V R3V DAC RG2 L2V SWMUTE AIN4L/R ADC AIN3L/R Selector AIN2L/R LG2 R1V Xover Spectrum Analyzer <<2 L1V Input1 Delay R1 <<2 AIN1L/R Xover L1 Equalizer 14Band Function5 Function4 Function3 Function2 RG1 Function1 LG1 c MUTE1 De-emp SRC SDTI3 DZF <<2 SDTI1 SDTI2 LMV MOMUTE a MCLKO OBICK OLRCK CLK MONOIN AOUT3L AOUT3R *Refer to Figure 42 for delay block. Figure 33. DSP Block Construction Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 80H LG1 RG1 LG2 RG2 Dummy Shift Setting 2bit Left x 4 2bit Left x 4 2bit Left x 4 2bit Left x 4 - MS1446-E-01 R/W R/W R/W R/W R/W - Default 0x 2000 0x 2000 0x 2000 0x 2000 - 2015/05 - 45 - [AK7601A] Function1 (High Frequency Expansion) ThrGainL Lch <<1 HighOut HiIn <<1 a00 Multiplier a01 a11 -1 -1 Z Z a12 b02 Single Precision Single Precision HiIn HighOut <<1 a00 Multiplier a10 -1 -1 a01 a11 b11 -1 Z Z Z a02 -1 Z -1 -1 Z HighGainR <<1 <<1 Z b01 -1 b12 -1 Z Z a12 b02 HighGainL b11 -1 Z a02 Z Z b01 -1 Z -1 -1 Z Z <<1 <<1 a10 -1 -1 Single Precision b12 Single Precision <<1 Rch ThrGainR Figure 34. Function1 Block Diagram Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 81H ThrGainL ThrGainR Dummy Dummy Dummy Shift Setting 1bit Left x 2 1bit Left x 2 - R/W R/W R/W - Default 0x 4000 0x 4000 - Comment Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 82H HighGainL HighGainR Multiplier1 Multiplier2 Multiplier3 Shift Setting 1bit Left x 2 1bit Left x 2 - R/W R/W R/W R/W R/W R/W Default 0x 0000 0x 0000 0x 4000 0x 0000 0x 0000 Comment Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 84H HiIn_a02 HiIn_a01 HiIn_a00 HiIn_b02 HiIn_b01 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 0000 0x 0000 0x 4000 0x 0000 0x 0000 Comment Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 85H HiOut_a12 HiOut_a11 HiOut_a10 HiOut_b12 HiOut_b11 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 0000 0x 0000 0x 4000 0x 0000 0x 0000 Comment MS1446-E-01 Control register of Lch through gain Control register of Rch through gain Control register of Lch IIR out gain Control register of Rch IIR out gain Control register of Multiplier block Control register of Multiplier block Control register of Multiplier block Control register of Hi In IIR Filter Control register of Hi In IIR Filter Control register of Hi In IIR Filter Control register of Hi In IIR Filter Control register of Hi In IIR Filter Control register of Hi Out IIR Filter Control register of Hi Out IIR Filter Control register of Hi Out IIR Filter Control register of Hi Out IIR Filter Control register of Hi Out IIR Filter 2015/05 - 46 - [AK7601A] Function2 (Compressor) Thr_G Lch <<1 LPF Z-1 a01 b01 a02 b02 -1 -1 Z Z Double Precision Compressor <<1 a00 -1 Z LPF a00 <<1 -1 -1 Z Z a01 b01 Z-1 Z-1 a02 b02 Double Precision Thr_G <<1 Rch Figure 35. Function2 Block Diagram Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) C0H LPF_a02 LPF_a01 LPF_a00 LPF_b02 LPF_b01 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 00000000 0x 00000000 0x 04000000 0x 00000000 0x 00000000 Comment Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 88H LPF_a21 LPF_a20 LPF_b21 Dummy Dummy Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 - R/W R/W R/W R/W - Default 0x 0000 0x 0000 0x 0000 Comment Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 8CH Thr_G Dummy Dummy Dummy Dummy Shift Setting 1bit Left x 2 - Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 8DH Compressor1 Compressor2 Compressor3 Compressor4 Dummy Shift Setting - R/W R/W R/W R/W R/W R/W R/W - MS1446-E-01 - Default 0x 4000 Control register of LPF Control register of LPF Control register of LPF Control register of LPF Control register of LPF Control register of Compressor block Control register of Compressor block Control register of Compressor block Control register of Compressor block Control register of Compressor block Comment Control register of through gain - Default 0x 0000 0x 0000 0x 0000 0x 0000 Comment Control register of Compressor block Control register of Compressor block Control register of Compressor block Control register of Compressor block - 2015/05 - 47 - [AK7601A] Function3 (Surround Effect) F3ThrG Lch <<1 F3D F3InL Z-n F3OutL Max0x2D Sample F3FBG F3IIR <<1 a00 Z -1 Z a01 F3InR Z -1 b01 F3OutR Z-1 -1 a02 Single Precision b02 <<1 Rch F3ThrG Figure 36. Function3 Block Diagram Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 90H F3ThrG F3OutL F3OutR Dummy Dummy Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 - R/W R/W R/W R/W - Default 0x 4000 0x 0000 0x 0000 Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 91H F3InL F3InR F3D F3FBG Dummy Shift Setting - R/W R/W R/W R/W R/W - Default 0x 0000 0x 0000 0x 0000 0x 0000 Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 92H F3IIR_a02 F3IIR_a01 F3IIR_a00 F3IIR_b02 F3IIR_b01 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 0000 0x 0000 0x 4000 0x 0000 0x 0000 MS1446-E-01 Comment Control register of through gain Control register of Lch F3 IIR out gain Control register of Rch F3 IIR out gain - Comment - Comment 2015/05 - 48 - [AK7601A] Function4 (Bass Boost) F4ThrL Lch <<1 F4InL F4IIR <<1 a00 Z -1 Z a01 F4InR Z -1 b01 Z-1 -1 a02 b02 Double Precision <<1 Rch F4ThrR Figure 37. Function4 Block Diagram Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 93H F4ThrL F4ThrR F4InL F4InR Dummy Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) C2H F4IIR_a02 F4IIR_a01 F4IIR_a00 F4IIR_b02 F4IIR_b01 Shift Setting 1bit Left x 2 1bit Left x 2 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MS1446-E-01 Default 0x 4000 0x 4000 0x 0000 0x 0000 Comment Control register of through gain Control register of Rch through gain Control register of Lch F4 IIR input gain Control register of Rch F4 IIR input gain - Default 0x 00000000 0x 00000000 0x 04000000 0x 00000000 0x 00000000 Comment Control register of F4IIR Filter Control register of F4 IIR Filter Control register of F4 IIR Filter Control register of F4 IIR Filter Control register of F4 IIR Filter 2015/05 - 49 - [AK7601A] Function5 (Loudness) F5ThrG F5IIR Lch <<1 <<1 a00 F5OutG Z-1 Z-1 a01 Z-1 b01 Z-1 F3IIR a02 Single Precision b02 F5ThrG F5IIR a00 <<1 <<1 Rch a01 Z F5OutG Z-1 Z-1 b01 Z-1 -1 a02 Single Precision b02 Figure 38. Function5 Block Diagram Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 94H F5ThrG F5OutG Dummy Dummy Dummy Shift Setting 1bit Left x 2 1bit Left x 2 - R/W R/W R/W - Default 0x 4000 0x 0000 Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 95H F5IIR_a02 F5IIR_a01 F5IIR_a00 F5IIR_b02 F5IIR_b01 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 0000 0x 0000 0x 4000 0x 0000 0x 0000 MS1446-E-01 Comment Control register of through gain Control register of F5 IIR out gain - Comment Control register of F5 IIR Filter Control register of F5 IIR Filter Control register of F5 IIR Filter Control register of F5 IIR Filter Control register of F5 IIR Filter 2015/05 - 50 - [AK7601A] Equalizer EQGain1 EQBanzd1 Z-1 a01 b01 a02 b02 Double Precision Z-1 Single Precision Z-1 Z Z-1 a00 a00 a01 b01 a02 b02 Z-1 Z-1 <<1 Z-1 a02 b02 a02 b02 Z a00 a01 b01 a02 b02 Z-1 b01 a02 b02 <<1 Z-1 a01 b01 a02 b02 Z-1 Z Single Precision a00 -1 Single Precision EQBand13 <<1 EQBanzd14 <<1 <<1 a00 Z-1 -1 <<1 a00 a01 EQBanzd12 Z b02 EQBanzd7 <<1 Z-1 Single Precision Z-1 a02 Single Precision Z-1 a00 b01 EQBand6 -1 <<1 Z-1 a01 Z-1 Z-1 EQBand11 <<1 Single Precision <<1 a00 b01 a00 b01 Z-1 Double Precision <<1 a01 EQBanzd5 a01 EQBanzd10 Z-1 b02 Z-1 Double Precision a00 a02 Z-1 Single Precision Z-1 <<1 b01 EQBand4 <<1 EQBand9 <<1 a01 <<1 a00 Z-1 Z-1 Z-1 Single Precision EQBanzd8 <<1 A -1 b02 a02 Double Precision b02 Double Precision Z-1 b01 Z-1 b02 a02 Z-1 a00 Z-1 a01 b01 a00 b02 b01 EQBanzd3 Z-1 EQGain2 a02 a01 EQBanzd7 <<1 a00 Z-1 Double Precision <<1 a00 a02 b01 EQBand2 a00 a01 a01 EQBand6 <<1 a00 Z-1 Z-1 Z-1 b02 a02 EQBanzd5 <<1 a00 Z-1 b01 EQBand1 Z-1 R1 a01 EQBand4 <<1 a00 Z-1 Z-1 EQGain1 <<1 EQBanzd3 <<1 a00 Z-1 L1 EQBand2 a00 <<1 Z-1 <<1 Z -1 L2 Z a01 b01 a02 b02 -1 a01 b01 a02 b02 Z-1 Z-1 Double Precision a00 <<1 R2 a02 b02 Z-1 a00 b01 a02 b02 Z-1 a02 b02 Z a01 b01 a02 b02 -1 Z-1 Z-1 b01 a02 b02 Z-1 Single Precision b02 a01 b01 a02 b02 Z-1 Z a00 b01 a02 b02 a01 b01 a02 b02 a00 b02 Z-1 EQBanzd14 <<1 a01 b01 a02 b02 <<1 a00 Z-1 Z-1 Single Precision a02 -1 Single Precision Z-1 Z-1 Double Precision b01 EQBand13 <<1 Z-1 a01 a01 Single Precision EQBanzd12 <<1 Z-1 Double Precision a02 EQBand11 a00 Z-1 a01 b01 Single Precision Double Precision <<1 a00 a01 Z-1 EQBanzd10 <<1 Z-1 Double Precision b01 Double Precision Z-1 a01 a01 Z-1 EQBand9 <<1 Z-1 B b01 Single Precision EQBand8 EQGain2 a01 <<1 Z-1 a01 b01 a02 b02 Z-1 Z-1 Single Precision Single Precision Figure 39. Equalizer Block Diagram Command Data 1 (2byte) 40H EQGain1 Shift Setting 1bit Left x 2 R/W R/W Default 0x 4000 Command Data 1 (2byte) 41H EQGain2 Shift Setting 1bit Left x 2 R/W R/W Default 0x 4000 Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) C3H EQBand1_a2 EQBand1_a1 EQBand1_a0 EQBand1_b2 EQBand1_b1 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 00000000 0x 00000000 0x 04000000 0x 00000000 0x 00000000 Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 96H EQBand2_a2 EQBand2_a1 EQBand2_a0 EQBand2_b2 EQBand2_b1 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 0000 0x 0000 0x 4000 0x 0000 0x 0000 MS1446-E-01 2015/05 - 51 - [AK7601A] Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) C4H EQBand3_a2 EQBand3_a1 EQBand3_a0 EQBand3_b2 EQBand3_b1 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 00000000 0x 00000000 0x 04000000 0x 00000000 0x 00000000 Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) C5H EQBand4_a2 EQBand4_a1 EQBand4_a0 EQBand4_b2 EQBand4_b1 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 00000000 0x 00000000 0x 04000000 0x 00000000 0x 00000000 Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 97H EQBand5_a2 EQBand5_a1 EQBand5_a0 EQBand5_b2 EQBand5_b1 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 0000 0x 0000 0x 4000 0x 0000 0x 0000 Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 98H EQBand6_a2 EQBand6_a1 EQBand6_a0 EQBand6_b2 EQBand6_b1 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 0000 0x 0000 0x 4000 0x 0000 0x 0000 Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 99H EQBand7_a2 EQBand7_a1 EQBand7_a0 EQBand7_b2 EQBand7_b1 Shift Setting 1bit Left x 2 1bit Left x 2 2bit Left x 4 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 0000 0x 0000 0x 2000 0x 0000 0x 0000 Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) C6H EQBand8_a2 EQBand8_a1 EQBand8_a0 EQBand8_b2 EQBand8_b1 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 00000000 0x 00000000 0x 04000000 0x 00000000 0x 00000000 Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 9AH EQBand9_a2 EQBand9_a1 EQBand9_a0 EQBand9_b2 EQBand9_b1 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 0000 0x 0000 0x 4000 0x 0000 0x 0000 MS1446-E-01 2015/05 - 52 - [AK7601A] Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) C7H EQBand10_a2 EQBand10_a1 EQBand10_a0 EQBand10_b2 EQBand10_b1 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 00000000 0x 00000000 0x 04000000 0x 00000000 0x 00000000 Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) C8H EQBand11_a2 EQBand11_a1 EQBand11_a0 EQBand11_b2 EQBand11_b1 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 00000000 0x 00000000 0x 04000000 0x 00000000 0x 00000000 Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 9BH EQBand12_a2 EQBand12_a1 EQBand12_a0 EQBand12_b2 EQBand12_b1 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 0000 0x 0000 0x 4000 0x 0000 0x 0000 Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 9CH EQBand13_a2 EQBand13_a1 EQBand13_a0 EQBand13_b2 EQBand13_b1 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 0000 0x 0000 0x 4000 0x 0000 0x 0000 Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 9DH EQBand14_a2 EQBand14_a1 EQBand14_a0 EQBand14_b2 EQBand14_b1 Shift Setting 1bit Left x 2 1bit Left x 2 2bit Left x 4 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 0000 0x 0000 0x 2000 0x 0000 0x 0000 MS1446-E-01 2015/05 - 53 - [AK7601A] Cross Over XO1IIR XO1IIR FL <<1 a00 XO1IIR <<1 a10 -1 Z-1 a01 b02 b12 a12 Single Precision XO1IIR <<1 a10 a20 Z-1 Z-1 a01 b02 a02 b12 a12 <<1 <<1 a10 -1 <<1 -1 Z Z-1 Z a01 a11 b01 -1 Z Z-1 Z b02 a02 b12 a12 Double Precision Double Precision XO2IIR XO2IIR <<1 <<1 a10 Z-1 <<1 Z-1 a01 Z-1 a11 b01 Z-1 b02 a02 Z-1 b12 a12 Double Precision Double Precision XO3IIR XO3IIR a10 ~ b12 a00 ~ c02 SWR ROutGain b11 Z-1 SWL ROutGain b11 -1 a00 b22 Single Precision XO2IIR XO2IIR RR Z-1 a22 Double Precision FOutGain b21 Z-1 Double Precision a00 <<1 Z-1 a21 b11 Z-1 Z <<1 Z-1 a11 b01 -1 b22 a22 XO1IIR <<1 RL Z-1 Double Precision XO1IIR a00 FOutGain b21 Z-1 Double Precision FR a21 b11 Z-1 a02 Z-1 Z a11 b01 <<1 -1 Z Z-1 <<1 a20 Double Precision SWOutGain Double Precision Figure 40. Cross Over Block Diagram Command Data 1 (2byte) 42H Fout Gain Shift Setting 1bit Left x 2 R/W R/W Default 0x 4000 Command Data 1 (2byte) 43H Rout Gain Shift Setting 1bit Left x 2 R/W R/W Default 0x 4000 Command Data 1 (2byte) 44H SWout Gain Shift Setting 1bit Left x 2 R/W R/W Default 0x 4000 Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) C9H XO1IIR_a02 XO1IIR_a01 XO1IIR_a00 XO1IIR_b02 XO1IIR_b01 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 00000000 0x 00000000 0x 04000000 0x 00000000 0x 00000000 MS1446-E-01 2015/05 - 54 - [AK7601A] Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) CAH XO2IIR_a02 XO2IIR_a01 XO2IIR_a00 XO2IIR_b02 XO2IIR_b01 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 00000000 0x 00000000 0x 04000000 0x 00000000 0x 00000000 Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) CBH XO3IIR_a02 XO3IIR_a01 XO3IIR_a00 XO3IIR_b02 XO3IIR_b01 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 00000000 0x 00000000 0x 04000000 0x 00000000 0x 00000000 Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) CCH XO1IIR_a12 XO1IIR_a11 XO1IIR_a10 XO1IIR_b12 XO1IIR_b11 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 00000000 0x 00000000 0x 04000000 0x 00000000 0x 00000000 Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) CDH XO2IIR_a12 XO2IIR_a11 XO2IIR_a10 XO2IIR_b12 XO2IIR_b11 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 00000000 0x 00000000 0x 04000000 0x 00000000 0x 00000000 Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) CEH XO3IIR_a12 XO3IIR_a11 XO3IIR_a10 XO3IIR_b12 XO3IIR_b11 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 00000000 0x 00000000 0x 04000000 0x 00000000 0x 00000000 Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 9EH XO1IIR_a22 XO1IIR_a21 XO1IIR_a20 XO1IIR_b22 XO1IIR_b21 Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 R/W R/W R/W R/W R/W R/W Default 0x 0000 0x 0000 0x 4000 0x 0000 0x 0000 MS1446-E-01 2015/05 - 55 - [AK7601A] Spectrum Analyzer SASIIR SAIIR1 Lch >>3 a00 Rch Z <<1 -1 |X| Z -1 Z a02 Z -1 b51 Double Precision Z-1 -1 -1 a51 b01 Z Resister a50 b02 Double Precision SAIIR2 a10 ~ c12 Double Precision a50 ~ b52 Double Precision SAIIR3 a20 ~ c22 Single Precision a50 ~ b52 Double Precision SAIIR4 a30 ~ c32 Single Precision a50 ~ b52 Double Precision Figure 41. Spectrum Analyzer Block Diagram Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) CFH SAIIR1_a02 SAIIR1_a00 SAIIR1_b02 SAIIR1_b01 Dummy Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 - R/W R/W R/W R/W R/W - Default 0x 0FFE2D4D 0x 0001D2B3 0x 0C009B92 0x 07FF1150 Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) D0H SAIIR2_a02 SAIIR2_a00 SAIIR2_b02 SAIIR2_b01 Dummy Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 - R/W R/W R/W R/W R/W - Default 0x 0FF51627 0x 000AE9D9 0x 0C03A349 0x 07F72D4D Command Data 1 (4byte) Data 2 (4byte) Data 3 (4byte) Data 4 (4byte) Data 5 (4byte) D1H SASIIR_a51 SASIIR_a50 SASIIR_b51 Dummy Dummy Shift Setting - R/W R/W R/W R/W - Default 0x 00031773 0x 00031773 0x 07FBA0B8 Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) 9FH SAIIR3_a22 SAIIR3_a20 SAIIR3_b22 SAIIR3_b21 Dummy Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 - R/W R/W R/W R/W R/W - Default 0x FD52 0x 02AE 0x C0E5 0x 79FB Command Data 1 (2byte) Data 2 (2byte) Data 3 (2byte) Data 4 (2byte) Data 5 (2byte) A0H SAIIR4_a32 SAIIR4_a30 SAIIR4_b32 SAIIR4_b31 Dummy Shift Setting 1bit Left x 2 1bit Left x 2 1bit Left x 2 1bit Left x 2 - R/W R/W R/W R/W R/W - Default 0x F779 0x 0887 0x C2D8 0x 3449 MS1446-E-01 - - - - - 2015/05 - 56 - [AK7601A] Each data level read of spectrum analyzer. Command Data1 (2byte) 50H 125Hz (default) R/W RD Command Data1 (2byte) 51H 500Hz (default) R/W RD Command Data1 (2byte) 52H 2kHz (default) R/W RD Command Data1 (2byte) 53H 8kHz (default) R/W RD Delay Block (1/fs = 1/44100 = approximately 0.0226ms)= one unit Command 45H Data 1 (2byte) Front L1 out delay time Set range (0x0000~0x031A) Command 46H Data 1 (2byte) Front R1 out delay time Set range (0x0000~0x031A) Command 47H Data 1 (2byte) Rear L2 out delay time Set range (0x0000~0x031A) Command 48H Data 1 (2byte) Rear R2 out delay time Set range (0x0000~0x031A) Command 49H Data 1 (2byte) SW L3 out delay time Set range (0x0000~0x031A) Command 4AH Data 1 (2byte) SW R3 out delay time Set range (0x0000~0x031A) Setting Unit Delay time: 1/fs unit R/W R/W Default 0x 0000 Setting Unit Delay time: 1/fs unit R/W R/W Default 0x 0000 Setting Unit Delay time: 1/fs unit R/W R/W Default 0x 0000 Setting Unit Delay time: 1/fs unit R/W R/W Default 0x 0000 Setting Unit Delay time: 1/fs unit R/W R/W Default 0x 0000 Setting Unit Delay time: 1/fs unit R/W R/W Default 0x 0000 MS1446-E-01 2015/05 - 57 - [AK7601A] Command Data 1 (2byte) Data 1 (2byte) Data 1 (2byte) Data 1 (2byte) Data 1 (2byte) A1H Front L Gain Setting Coefficient Front R Gain Setting Coefficient Rear L Gain Setting Coefficient Rear R Gain Setting Coefficient Dummy Shift Setting 1bit Left x2 1bit Left x2 1bit Left x2 1bit Left x2 - R/W R/W R/W R/W R/W - Command A2H Shift Setting R/W Data 1 (2byte) SW L Gain Setting Coefficient 1bit Left x2 R/W Data 1 (2byte) SW R Gain Setting Coefficient 1bit Left x2 R/W Data 1 (2byte) Dummy Data 1 (2byte) Dummy Data 1 (2byte) Dummy Note: All data are R/W. When the delay time is set over its limit, it will be set to the maximum value. Default 0x 4000 0x 4000 0x 4000 0x 4000 - Default 0x 4000 0x 4000 - <Delay Amount Setting Example> SWSW, RSW and FSW bits in 0FH control input source setting. Lch input 1 Example1. Input1 → L1, L2, L3 Input2 → No data FL RL NL Delay Memory 1word=24bit 18ms Delay = 794word (44.1kHz x 0.018) << 1 << 1 L1 out (Front) L2 out (Rear) L3 out (SW) << 1 Example2. Input1 →L2, L3 Input2 → L1 Lch input 1 Lch input 2 FL RL NL Delay Memory 1word=24bit 18ms Delay = 794word (44.1kHz x 0.018) << 1 << 1 L1 out (Front) L2 out (Rear) L3 out (SW) << 1 Figure 42. Delay Amount Setting Example MS1446-E-01 2015/05 - 58 - [AK7601A] SYSTEM DESIGN Figure 43 shows system connection diagram. An evaluation board (AKD7601A) is available for fast evaluation as well as suggestions for peripheral circuitry. DSP1 DSP2 DSP3 DVDD 25 10u SDTO1/SDTO3 23 39 CLKMODE 0.1u 0.1u VSS2 24 38 VSS3 2.2u SDTI3 26 SDTI2 27 SDTI1 28 IBICK3 29 IBICK2 30 IBICK1 31 ILRCK3 32 ILRCK2 33 XTI 35 37 MUTEN ILRCK1 34 XTO 36 Digital 5V SDTO2/SDTI4 22 40 REF18 OLRCK 21 41 VSS4 OBICK 20 AK7601AVQ 42 MONOIN MCKO 19 Top View 43 AINL1 DSP4 SCL 18 44 GNDIN1 SDA 17 45 AINR1 PDN 16 46 AINL2 μP DZF 15 AOUT3R 14 AOUT3L 13 12 AOUT2R 11 AOUT2L 9 AOUT1L 10 AOUT1R 7 VSS1 6 AVDD 5 VCOM 4 AINR4 3 AINL4 2 AINR3 1 AINL3 48 AINR2 8 VREFH 47 GNDIN2 0.1u MUTEN Mute Mute Mute Analog Ground Digital Ground Mute 2.2u 0.1u 10u Mute Mute 0.1u 10u Analog 5V Figure 43. System Connection Diagram • X’tal mode (CLKMODE pin = “L”) • SDTO3, SDTI4 Select Mode (DO21-20 bits = “10”, DO11-10 bits = “10”) Note: Do not take current from the REF18 pin. MS1446-E-01 2015/05 - 59 - [AK7601A] 1. Grounding and Power Supply Decoupling The AK7601A requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually supplied from the system’s analog supply. If AVDD and DVDD are supplied separately, AVDD must be ON after DVDD is ON. VSS1, VSS2, VSS3 and VSS4 of the AK7601A should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK7601A as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference Inputs The input voltage to the VREFH pin sets the analog output range. Usually the VREFH pin is connected to the AVDD pin and a 0.1F ceramic capacitor is connected between the AVDD pin and the VSS1 pin. VCOM is a signal ground of this chip (AVDD/2). The electrolytic capacitor around 2.2µF attached between the VCOM pin an the VSS1 pin eliminates the effects of high frequency noise. The ceramic capacitor in particular should be connected as close as possible to the pin. No load current may be taken from the VCOM pin. All signals, especially clock, should be kept away from the VREFH pin and the VCOM pin in order to avoid unwanted coupling into the AK7601A. 3. Analog Inputs The ADC supports single-ended and pseudo-differential inputs. It is biased to VCOM voltage (AVDD/2) internally by 45kΩ(typ). The inputs signal range scales with nominally at 0.65 x VREFH Vpp (typ). The AK7601A can accept input voltage from VSS1 to AVDD. The output code format is 2's complement. Input DC offset is canceled by an integrated high-pass filter. The AK7601A samples the analog input at 64fs. A digital filter removes the noise over the stopband attenuation level, except for a band of integral multiplication of 64fs. AK7601A has an integrated anti-alias RC filter in order to reduce the noise at 64fs. 4. Analog output The DAC output is single-ended and output range is 0.65xVREFH Vpp (typ) centered on VCOM. The bias voltage of the external summing circuit is supplied externally. The input data format is two’s compliment. Positive full-scale output corresponds to 7FFFFFH (@24bit) input code, Negative full scale is 800000H (@24bit) and VCOM voltage ideally is 000000H (@24bit). The Out-of-Band noise (shaping noise) generated by the internal delta-sigma modulator is attenuated by an integrated switched capacitor filter (SCF) and a continuous time filter (CTF). DC offsets on analog outputs are eliminated by AC coupling since analog outputs has DC offset of VCOM. MS1446-E-01 2015/05 - 60 - [AK7601A] PACKAGE 48pin LQFP(Unit: mm) 1.70Max 9.0 0.13 0.13 7.0 36 1.40 0.05 24 48 13 7.0 37 1 9.0 25 12 0.09 0.20 0.5 0.22 0.08 0.10 M 0° 10° S 0.10 S 0.30 ~ 0.75 ■ Materials and Lead Specification Package: Epoxy Lead frame: Copper Lead-finish: Soldering plate (Pb free) MS1446-E-01 2015/05 - 61 - [AK7601A] MARKING AK7601AVQ XXXXXXX 1 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK7601AVQ REVISION HISTORY Date (Y/M/D) 12/07/11 15/05/18 Revision 00 01 Reason First Edition Specification Change Page Contents 6 RECOMMENDED OPERATING CONDITIONS Note 7 was changed. SWITCHING CHARACTERISTICS “Power-up Timing” was added. “tPD2” was added. ■ Timing Diagram Figure 7: “Power Down & Reset Timing” → “Power Up & Power Down Timing” “■ Power-up Sequence” was added. ■ System Reset “The AK7601A should be powered-up when the PDN pin = “L”.” was deleted. SYSTEM DESIGN 1. Grounding and Power Supply Decoupling Description was changed. 12 14 23 23 60 MS1446-E-01 2015/05 - 62 - [AK7601A] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS. 2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in writing. 3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. MS1446-E-01 2015/05 - 63 -