Data Sheet

[AK4141]
AK4141
NICAM/A2/EIA-J Digital Stereo Decoder
GENERAL DESCRIPTION
The AK4141 is a NICAM/A2/EIA-J stereo decoder, which is optimized for Digital TV application. The
AK4141 achieves no alignment, few external components and high audio performance by digital stereo
decoding architecture. The AK4141 integrates a stereo sample rate converter (SRC) for asynchronous
digital audio sources such as digital tuners, digital switches and sound processing functions like 5-band
equalizers. The AK4141 supports major audio data formats (MSB/LSB justified, I2S and TDM) to
interface with DSP, ADC, DAC. Therefore, the AK4141 is suitable for the AV systems such as Digital TV
and DVR.
FEATURES
1. Stereo Decoding
 Capable of receiving Sound Intermediate Frequency (SIF) with Selector
and FM Demodulation
 Automatic Gain Control (AGC: 100mVpp ~ 1Vpp) for SIF input
 Alignment Free Digital Stereo Decoding
EIA-J
NICAM: B/G, L, I, D/K with FM/AM Mono
A2: B/G, D/K1, D/K2, D/K3, M/N
 Automatic/Manual Stereo Decoding Standard Selection
 Automatic/Manual Audio Mode (Stereo/MONO/two sounds) Selection
 Signal Quality Detection for Auto Selection Mode
 High FM Deviation Option (max: 540kHz)
 I2S sampling rate (fs): 32k/44.1k/48kHz
2. Audio Processing (Two Stereos)
 Automatic Level Control (ALC)
 Balance
 5-band Equalizer
 Stereo Separation Emphasis
 Digital Volume Control with Soft Mute (+12dB~-115dB, 0.5dB/step)
 Audio Data Interface:
I2S input x 5 (2 inputs: SRC available)
I2S output x 3
Master/Slave Mode
Audio Format: 24bit Left justified /Right justified / I2S or TDM
3. Asynchronous Sample Rate Converter (SRC)
 Input Sample Rate: 8k~192kHz
 fso/fsi: 1/6~6
4. Digital Audio Interface Transmitter (DIT) with Through Mode
5. Integrated X’tal Oscillator
6. Master Clock: 256fs/384fs/512fs/768fs/1024fs
7. I2C-bus Control Interface
8. Power Supply: DVDD=1.8V±0.1V, AVDD=3.3V±0.3V, TVDD=1.7V~3.6V
9. Ta: -20 ~ 85C
10. Package: 48pin LQFP
MS0952-E-03
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[AK4141]
VCOM LFLT1 LFLT2 AVDD2 GND5 AVDD1 GND3 GND4 LRCK SCLK
DVDD
GND1
TVDD GND2
VREFH
VREFL
AGC
SIF1
ADC
(SIF)
SIF2
FM Demod &
Stereo Decode
EIAJ
NICAM
A2
SDTI1
SDTI2
SDTI3
DIT
Prescale
1/2/3/4
LRCK4
SCLK4
SDTI4
LRCK5
SCLK5
SDTI5
TXOUT
Decoder
Prescale
TXIN
ALC, Vol1
Balance1
Bass/Tre1
3D
Switch
Matrix
SDTO1
ALC, Vol2
Balance2
Bass/Tre2
3D
SDTO2
SRC
SRC
Prescale
X’tal Osc PLL
Clock Gen
MCLKI XTI XTO MCKO
SDTO3
Control
Register
CAD0 CAD1 SCL SDA INT
MS0952-E-03
PDN
6M5 4M50 4M51 4M52 MSN
IIS
2013/12
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[AK4141]
■ Ordering Guide
AK4141EQ
AKD4141
-20  +85C 48pin LQFP (0.5mm pitch)
Evaluation Board for AK4141
LFLT1
CAD1
CAD0
MSN
A6M5
INT
SDTO1
SDTO2
SDTO3
LRCK
SCLK
MCLKO
36
35
34
33
32
31
30
29
28
27
26
25
■ Pin Layout
VREFH
37
24
TXOUT
VREFL
38
23
A4M52
GND3
39
22
SDA
SIF2
40
21
TVDD
VCOM
41
20
GND2
SIF1
42
19
GND1
AVDD1
43
18
DVDD
17
TXIN
AK4141EQ
Top View
9
10
11
12
SDTI2
SDTI1
A4M50
A4M51
SDTI3
13
8
48
SDTI4
AVDD2
7
SCL
SCLK4
14
6
47
LRCK4
GND5
5
PDN
SDTI5
15
4
46
SCLK5
XTO
3
MCLKI
LRCK5
16
2
45
IIS
XTI
1
44
LFLT2
GND4
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[AK4141]
PIN/FUNCTION
No.
Pin Name
I/O
1
FILT2
O
2
IIS
I
3
4
5
6
7
LRCK5
SCLK5
SDTI5
LRCK4
SCLK4
I
I
I
I
I
8
SDTI4
I
9
10
11
SDTI3
SDTI2
SDTI1
I
I
I
12
A4M50
I
13
A4M51
I
14
SCL
I
15
PDN
I
16
MCKI
I
17
TXIN
I
18
19
20
21
22
DVDD
GND1
GND2
TVDD
SDA
I/O
23
A4M52
I
24
25
TXOUT
MCKO
O
O
26
SCLK
I/O
27
LRCK
I/O
28
SDTO3
O
29
SDTO2
O
30
SDTO1
O
Function
PLL Loop Filter 2 Pin
A 0.68F capacitor should be connected to GND5 externally.
Hi-Z when PDN Pin = “L”.
Audio Data Format Select Pin. ORed with ODIF bit, ORed with IDIF0 bit.
“L”: 24bit Left justified if IDIF0 bit = “0”(default)
“H”: 24/16 bit IIS
Input Channel Clock 5 Pin
Audio Serial Data Clock 5 Pin
Audio Serial Data Input 5 Pin
Input Channel Clock 4 Pin
Audio Serial Data Clock 4 Pin
Audio Serial Data Input 4 Pin
Should be synchronized to LRCK and SCLK when SRC is not used.
Audio Serial Data Input 3 Pin
Audio Serial Data Input 2 Pin
Audio Serial Data Input 1 Pin
Decoder Standard Preference Control 0 Pin for 4.5MHz Carrier
This pin is internally XORed with A4M50 bit (default = “1”).
Decoder Standard Preference Control 1 Pin for 4.5MHz Carrier
This pin is internally XORed with A4M51 bit (default = “1”).
Control Data Clock Pin for I2C bus
Power-Down Mode & Reset Pin
When “L”, the AK4141 is powered-down, all registers are reset. And then all
digital output pins go “L”. The AK4141 must be reset once upon power-up.
Master Clock Input Pin
S/PDIF Input Pin
For through output. No Input Amplifier integrated.
Digital Power Supply Pin, 1.7V~1.9V
Ground Pin, 0V
Ground Pin, 0V
I/O Buffer Power Supply Pin, 1.7V~3.6V
Control Data Pin for I2C bus
Decoder Standard Preference Control 2 Pin for 4.5MHz Carrier
This pin is internally ORed with A4M52 bit (default = “0”).
S/PDIF Output pin. Outputs “L” when PDN Pin = “L”.
Master Clock Output Pin. Outputs “L” when PDN Pin = “L”.
Audio Serial Data Clock Pin.
Outputs “L” when PDN Pin = “L” and MSN Pin = “H”.
Hi-Z when PDN Pin = “L” and MSN Pin = “L”.
Input Channel Clock Pin
Outputs “L” when PDN Pin = “L” and MSN Pin = “H”.
Hi-Z when PDN Pin = “L” and MSN Pin = “L”.
Audio Serial Data Output 3 Pin
Outputs “L” when PDN Pin = “L”.
Audio Serial Data Output 2 Pin
Outputs “L” when PDN Pin = “L”.
Audio Serial Data Output 1 Pin
Outputs “L” when PDN Pin = “L”.
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[AK4141]
PIN/FUNCTION
Interrupt Pin
Outputs “L” when PDN Pin = “L”.
Decoder Standard Preference Control for 6.5MHz carrier.
“L”: SECAM L NICAM
32
A6M5
I
“H”: D/K1, D/K2, D/K3 or D/K NICAM
This Pin is internally ORed with A6M5 bit (default = “0”).
Master Mode Select Pin
33
MSN
I
“L”: Slave mode if CKS[2:0] bits = “000”(default)
“H”: Master mode of MCLK = 256fs if CKS2 bit = “0”(default)
Chip Address 0 pin
34
CAD0
I
Should match CAD0 bit in I2C first byte.
Chip Address 1 pin
35
CAD1
I
Should match CAD1 bit in I2C first byte.
PLL Loop Filter 1 Pin
36
FILT1
O
A 4.7nF capacitor should be connected to GND3 externally.
Hi-Z when PDN Pin = “L”.
ADC Voltage Reference High Pin
37
VREFH
O
A 0.1F capacitor should be connected to GND3, and another 0.1F capacitor
should be connected to VREFL Pin externally. Hi-Z when PDN Pin = “L”.
ADC Voltage Reference Low Pin
38
VREFL
O
A 0.1F capacitor should be connected to GND3 externally.
Hi-Z when PDN Pin = “L”.
39
GND3
Ground Pin, 0V
40
SIF2
I
Sound Intermediate Frequency(SIF) Input 2 Pin
ADC Common Voltage Output Pin.
41
VCOM
O
A 1F capacitor should be connected to GND3 externally. Hi-Z when PDN Pin =
“L”.
42
SIF1
I
Sound Intermediate Frequency(SIF) Input 1 Pin
43
AVDD1
Analog Power Supply Pin, 3.0V~3.6V
44
GND4
Ground Pin, 0V
45
XTI
I
X'tal Input Pin
X'tal Output Pin.
46
XTO
O
Outputs “L” when PDN pin = “L”.
47
GND5
Ground Pin, 0V
48
AVDD2
Analog Power Supply Pin, 3.0V~3.6V
Note: All digital input pins should not be left floating.
31
INT
O
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[AK4141]
■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Pin Name
Analog
SIF1, SIF2
Digital
TXOUT, MCLKO, SDTO1, SDTO2, SDTO3, INT,
LRCK(master mode), SCLK(master mode)
LRCK5, SCLK5, SDTI5, LRCK4, SCLK4, SDTI4,
LRCK(slave mode), SCLK(slave mode), SDTI3,
SDTI2, SDTI1, A4M50, A4M51, A4M52, A6M5,
SCL, MCLKI, TXIN, SDA, IIS, MSN, CAD1, CAD0
Setting
These pins should be connected to GND
through 10nF capacitor.
These pins should be open.
These pins should be connected to GND.
ABSOLUTE MAXIMUM RATINGS
(GND1=GND2=GND3=GND4=GND5=0V; Note 1)
Parameter
Power Supplies
Analog
Digital
Digital I/O
Input Current, Any Pin Except Supply
Analog Input Voltage (SIF1, SIF2 pin)
Digital Input Voltage (Note 2)
Ambient Temperature (powered applied)
Storage Temperature
Symbol
AVDD
DVDD
TVDD
IIN
VINA
VIND
Ta
Tstg
min
-0.3
-0.3
-0.3
0.3
0.3
20
65
max
4.3
2.4
4.3
10
AVDD+0.3
TVDD+0.3
85
150
Unit
V
V
V
mA
V
V
C
C
Note 1. All voltages with respect to ground.
Note 2. LRCK5, SCLK5, SDTI5, LRCK4, SCLK4, SDTI4, LRCK(slave mode), SCLK(slave mode), SDTI3, SDTI2,
SDTI1, A4M50, A4M51, A4M52, A6M5, SCL, MCLKI, TXIN, SDA, IIS, MSN, CAD1 and CAD0 pin.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(GND1=GND2=GND3=GND4=GND5=0V; Note 1)
Parameter
Symbol
Power Supplies
AVDD
AVDD
DVDD
DVDD
TVDD
TVDD
min
3.0
1.7
DVDD
typ
3.3
1.8
3.3
max
3.6
1.9
3.6
Unit
V
V
V
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0952-E-03
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[AK4141]
AUDIO CHARACTERISTICS
(Ta=25C; AVDD=3.3V, DVDD=1.8V, TVDD=3.3V; GND1=GND2=GND3=GND4=GND5=0V; fs=48kHz;
SCLK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=50Hz  13kHz; unless otherwise specified)
SIF & Demodulator Parameter
min
typ
max
Unit
SIF Input Impedance
GSEL bit = 0
4.05
4.50
kohm
GSEL bit = 1
5.09
5.66
kohm
SIF Separation (Note 3)
30
50
dB
AGC step width
0.64
dB
Input Voltage
1 or 2 FM Carriers
GSEL bit = “0”
0.1
1.4
Vpp
GSEL bit = “1”
0.1
1.0
Vpp
1 FM and 1 NICAM Carrier
GSEL bit = “0”
0.1
1.4
Vpp
GSEL bit = “1”
0.1
1.0
Vpp
1 AM and 1 NICAM Carrier
GSEL bit = “0”
0.1
0.8
Vpp
GSEL bit = “1”
0.1
0.8
Vpp
1 NICAM Only
GSEL bit = “0”
0.05
1.0
Vpp
GSEL bit = “1”
0.05
1.0
Vpp
Max FM-deviation (approx.)
Normal
+/-180
kHz
High deviation
+/-360
kHz
Very High Deviation
+/-540
kHz
NICAM Characteristics
min
typ
max
Unit
Output level (1kHz, 0dBr)
-1.5
+1.5
dB
S/N
74
80
dB
THD+N
0.05
0.15
%
NICAM Bit Error Rate (FM+ NICAM, normal condition)
1
10-7
Frequency response (20 ~ 15kHz, -12dB, dual)
-1
+1
dB
NICAM Crosstalk attenuation (dual)
80
dB
Channel separation (stereo)
80
dB
FM Characteristics (Note 4)
min
typ
max
Unit
Output level (1kHz, 0dBr)
-1.5
+1.5
dB
S/N
67
73
dB
THD+N
0.1
0.3
%
Frequency response (20 ~ 12kHz, -12dB, dual)
-1
+1
dB
FM Crosstalk attenuation (dual)
75
85
dB
Channel separation (stereo)
30
40
dB
AM Characteristics
min
typ
max
Unit
S/N
47
62
dB
THD+N
1.2
3
%
Frequency response (20 ~ 12kHz, -12dB, dual)
-2.5
+1
dB
Note 3. Selected SIF pin is connected to GND through 10nF capacitor.
Note 4. 1 FM-Carrier, 5.5MHz.
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[AK4141]
AUDIO CHARACTERISTICS (Continued)
(Ta=25C; AVDD=3.3V, DVDD=1.8V, TVDD=3.3V; GND1=GND2=GND3=GND4=GND5=0V; fs=48kHz;
SCLK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=50Hz  13kHz; unless otherwise specified)
EIAJ Characteristics
min
typ
max
Unit
S/N
Stereo
54
60
dB
Sub
54
60
dB
THD+N (1kHz L or R or Sub 100%)
Stereo
0.3
0.9
%
Sub
0.3
0.9
%
Frequency response
Stereo (20 ~ 12kHz, 100%EIM)
-1
+1
dB
Sub (20 ~ 12kHz, 100%EIM)
-1
+1
dB
Channel separation (stereo)
30
40
dB
SRC CHARACTERISTICS
(Ta=25C; AVDD=3.3V, DVDD=1.8V, TVDD=3.3V; GND1=GND2=GND3=GND4=GND5=0V; fs=48kHz;
SCLK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ~ FSO/2; unless otherwise specified)
Parameter
Symbol
min
typ
max
Unit
SRC Characteristics:
Resolution
20
Bits
Input Sample Rate
FSI
8
216
kHz
Output Sample Rate
FSO
32
48
kHz
THD+N
(Input = 1kHz, 0dBFS, Note 5)
FSO/FSI = 48kHz/8kHz
-100
dB
FSO/FSI = 48kHz/32kHz
-100
dB
FSO/FSI = 48kHz/192kHz
-100
dB
Worst Case (FSO/FSI = 32kHz/176.4kHz)
-91
-81
dB
Dynamic Range (Input = 1kHz, 60dBFS, A-weighted, Note 5)
FSO/FSI = 48kHz/8kHz
115
dB
FSO/FSI = 48kHz/32kHz
115
dB
FSO/FSI = 48kHz/192kHz
115
dB
Worst Case (FSO/FSI = 48kHz/32kHz)
111
115
dB
Ratio between Input and Output Sample Rate
FSO/FSI
1/6
6
Note 5. Measured by Audio Precision System Two Cascade.
Power Supplies
Parameter
min
Power Supply Current
Normal Operation (PDN pin = “H”)
TVDD
AVDD1+AVDD2
DVDD
Power-Down Mode (PDN pin = “L”; Note: 1)
TVDD
AVDD1+AVDD2
DVDD
typ
max
Unit
5
20
61
8
28
92
mA
mA
mA
10
10
10
100
100
100
A
A
A
Note: 1. All digital inputs including clock pins are held at DVDD or GND.
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[AK4141]
SRC FILTER CHARACTERISTICS
(Ta=25C; AVDD=3.0  3.6V, DVDD=1.7V 1.9V, TVDD=1.7  3.6V; GND1=GND2=GND3=GND4=GND5=0V)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
0.4583FSI
Passband 0.01dB
0.985  FSO/FSI  6.000
PB
0
kHz
0.4167FSI
0.905  FSO/FSI  0.985
PB
0
kHz
0.3195FSI
0.714  FSO/FSI  0.905
PB
0
kHz
0.2852FSI
0.656  FSO/FSI  0.714
PB
0
kHz
0.2182FSI
0.536  FSO/FSI  0.656
PB
0
kHz
0.2177FSI
0.492  FSO/FSI  0.536
PB
0
kHz
0.1948FSI
0.452  FSO/FSI  0.492
PB
0
kHz
0.1458FSI
0.357  FSO/FSI  0.452
PB
0
kHz
0.1302FSI
0.324  FSO/FSI  0.357
PB
0
kHz
0.0917FSI
0.246  FSO/FSI  0.324
PB
0
kHz
0.0826FSI
0.226  FSO/FSI  0.246
PB
0
kHz
0.0583FSI
0.1667  FSO/FSI  0.226
PB
0
kHz
Stopband
0.985  FSO/FSI  6.000
SB
0.5417FSI
kHz
0.905  FSO/FSI  0.985
SB
0.5021FSI
kHz
0.714  FSO/FSI  0.905
SB
0.3965FSI
kHz
0.656  FSO/FSI  0.714
SB
0.3643FSI
kHz
0.536  FSO/FSI  0.656
SB
0.2974FSI
kHz
0.492  FSO/FSI  0.536
SB
0.2813FSI
kHz
0.452  FSO/FSI  0.492
SB
0.2604FSI
kHz
0.357  FSO/FSI  0.452
SB
0.2116FSI
kHz
0.324  FSO/FSI  0.357
SB
0.1969FSI
kHz
0.246  FSO/FSI  0.324
SB
0.1573FSI
kHz
0.226  FSO/FSI  0.246
SB
0.1471FSI
kHz
0.1667  FSO/FSI  0.226
SB
0.1020FSI
kHz
Passband Ripple
PR
0.01
dB
Stopband
0.985  FSO/FSI  6.000
SA
102.2
dB
Attenuation
0.905  FSO/FSI  0.985
SA
100.4
dB
0.714  FSO/FSI  0.905
SA
99.0
dB
0.656  FSO/FSI  0.714
SA
101.6
dB
0.536  FSO/FSI  0.656
SA
99.5
dB
0.492  FSO/FSI  0.536
SA
95.2
dB
0.452  FSO/FSI  0.492
SA
96.6
dB
0.357  FSO/FSI  0.452
SA
97.0
dB
0.324  FSO/FSI  0.357
SA
94.4
dB
0.246  FSO/FSI  0.324
SA
95.8
dB
0.226  FSO/FSI  0.246
SA
95.0
dB
0.1667  FSO/FSI  0.226
SA
73.7
dB
Group Delay
(Note 6)
GD
56
1/fs
Note 6. This value is the time from the rising edge of LRCK after data is input to rising edge of LRCK after data is output,
when LRCK for Output data corresponds with LRCK for Input.
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[AK4141]
DC CHARACTERISTICS
(Ta=25C; AVDD=3.0  3.6V, DVDD=1.7V 1.9V, TVDD=1.7  3.6V; GND1=GND2=GND3=GND4=GND5=0V)
Parameter
Symbol
min
typ
max
Unit
High-Level Input Voltage
TVDD < 2.7V
VIH
80%TVDD
V
VIH
70%TVDD
V
TVDD  2.7V
Low-Level Input Voltage
VIL
20%TVDD
V
TVDD < 2.7V
VIL
30%TVDD
V
TVDD  2.7V
High-Level Output Voltage ( Iout=-400A)
VOH
TVDD-0.4
V
Low-Level Output Voltage
VOL
0.4
V
(Iout= -400A(except SDA pin), 3mA(SDA pin))
Input Leakage Current
Iin
10
A
SWITCHING CHARACTERISTICS
(Ta=-20 85C; AVDD= 3.0~3.6V, DVDD=1.7~1.9V TVDD=1.7~3.6V; GND1=GND2=GND3=GND4=GND5=0V;
CL=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
Unit
Crystal Resonator Frequency
fXTAL
256fs
fs=32kHz
8.192
MHz
fs=44.1kHz
11.2896
MHz
fs=48kHz
12.288
MHz
Master Clock Timing
Master Clock
128fs:
fCLK
4.096
6.144
MHz
Pulse Width Low
tCLKL
65
ns
Pulse Width High
tCLKH
65
ns
192fs:
fCLK
6.144
9.216
MHz
Pulse Width Low
tCLKL
43
ns
Pulse Width High
tCLKH
43
ns
256fs:
fCLK
8.192
12.288
MHz
Pulse Width Low
tCLKL
27
ns
Pulse Width High
tCLKH
27
ns
384fs:
fCLK
12.288
18.432
MHz
Pulse Width Low
tCLKL
20
ns
Pulse Width High
tCLKH
20
ns
512fs:
fCLK
16.384
24.576
MHz
Pulse Width Low
tCLKL
16
ns
Pulse Width High
tCLKH
16
ns
768fs:
fCLK
24.576
36.864
MHz
Pulse Width Low
tCLKL
11
ns
Pulse Width High
tCLKH
11
ns
1024fs:
fCLK
32.768
49.152
MHz
Pulse Width Low
tCLKL
8
ns
Pulse Width High
tCLKH
8
ns
MS0952-E-03
2013/12
- 10 -
[AK4141]
SWITCHING CHARACTERISTICS (Continued)
(Ta=-20 85C; AVDD= 3.0~3.6V, DVDD=1.7~1.9V TVDD=1.7~3.6V; GND1=GND2=GND3=GND4=GND5=0V;
CL=20pF; unless otherwise specified)
Parameter (Note 8)
Symbol
min
typ
max
Unit
LRCK Timing (Slave Mode)
Normal mode (TDM=“0”)
LRCK Frequency
fs
32
48
kHz
Duty Cycle
Duty
45
55
%
TDM256 mode (TDM=“1”)
LRCK Frequency
fs
32
48
kHz
“H” time
tLRH
1/256fs
ns
“L” time
tLRL
1/256fs
ns
SRC Input
LRCK Frequency
fs
8
192
KHz
Duty Cycle
Duty
45
55
%
LRCK Timing (Master Mode)
Normal mode (TDM=“0”)
LRCK Frequency
fs
32
48
kHz
Duty Cycle
Duty
50
%
TDM256 mode (TDM=“1”)
LRCK Frequency
fs
32
48
kHz
“H” time
(Note 7)
tLRH
1/8fs
ns
Audio Interface Timing (Slave mode)
Normal mode (TDM=“0”)
SCLK Period
tBCK
160
ns
SCLK Pulse Width Low
tBCKL
65
ns
Pulse Width High
tBCKH
65
ns
LRCK Edge to SCLK “”
(Note 9)
tLRB
30
ns
SCLK “” to LRCK Edge
(Note 9)
tBLR
30
ns
LRCK to SDTO(MSB) (Except I2S mode)
tLRS
35
ns
SCLK “” to SDTO
tBSD
35
ns
SDTI Hold Time
tSDH
10
ns
SDTI Setup Time
tSDS
10
ns
TDM256 mode (TDM=“1”)
SCLK Period
tBCK
81
ns
SCLK Pulse Width Low
tBCKL
32
ns
Pulse Width High
tBCKH
32
ns
LRCK Edge to SCLK “”
(Note 9)
tLRB
20
ns
SCLK “” to LRCK Edge
(Note 9)
tBLR
20
ns
SCLK “” to SDTO
tBSD
20
ns
TDMIN Hold Time
tSDH
10
ns
TDMIN Setup Time
tSDS
10
ns
SRC Input (Note 10)
SCLK Period
tBCK
81
ns
SCLK Pulse Width Low
tBCKL
32
ns
Pulse Width High
tBCKH
32
ns
LRCK Edge to SCLK “”
(Note 9)
tLRB
20
ns
SCLK “” to LRCK Edge
(Note 9)
tBLR
20
ns
SDTI Hold Time
tSDH
10
ns
SDTI Setup Time
tSDS
10
ns
MS0952-E-03
2013/12
- 11 -
[AK4141]
SWITCHING CHARACTERISTICS (Continued)
(Ta=-20 85C; AVDD= 3.0~3.6V, DVDD=1.7~1.9V TVDD=1.7~3.6V; GND1=GND2=GND3=GND4=GND5=0V;
CL=20pF; unless otherwise specified)
Parameter (Note 8)
Symbol
min
typ
max
Unit
Audio Interface Timing (Master mode)
Normal mode (TDM=“0”)
SCLK Frequency
fBCK
64fs
Hz
SCLK Duty
dBCK
50
%
SCLK “” to LRCK
tMBLR
20
20
ns
SCLK “” to SDTO
tBSD
40
40
ns
TDM256 mode (TDM=“1”)
SCLK Frequency
fBCK
256fs
Hz
SCLK Duty
(Note 11)
dBCK
50
%
SCLK “” to LRCK
tMBLR
12
12
ns
SCLK “” to SDTO
tBSD
20
20
ns
TDMIN Hold Time
tSDH
10
ns
TDMIN Setup Time
tSDS
10
ns
Power-Down & Reset Timing
PDN Pulse Width
(Note 12)
tPD
150
ns
PDN “” to SDTO valid
(Note 13)
tPDV
TBD
1/fs
Note 7. “L” time at I2S format.
Note 8. SCLK= SCLK/SCLK4/SCLK5, LRCK= SCLK/LRCK4/LRCK5 unless otherwise specified.
Note 9. SCLK rising edge must not occur at the same time as LRCK edge.
Note 10. SCLK= SCLK4/SCLK5, LRCK= LRCK4/LRCK5.
Note 11. This value is when fs=48kHz or 44.1kHz. When fs=32kHz, L=(5/9x100)% and H=(4/9x100)%.
Note 12. The AK4141 can be reset by bringing the PDN pin = “L”.
Note 13. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
Parameter
Symbol
min
typ
Control Interface Timing (I2C Bus):
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time
tHD:STA
0.6
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 14)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise
tSP
0
Suppressed by Input Filter
Capacitive load on SDA
Cb
0
Note 14. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 15. I2C is a registered trademark of Philips Semiconductors.
MS0952-E-03
max
Unit
400
-
kHz
s
s
0.9
0.3
0.3
50
s
s
s
s
s
s
s
s
ns
400
pF
2013/12
- 12 -
[AK4141]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
SCLK
VIL
tBCKH
tBCKL
Figure 1. Clock Timing (TDM bit = “0”)
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRH
tLRL
tBCK
VIH
SCLK
VIL
tBCKH
tBCKL
Figure 2. Clock Timing (TDM bit = “1”)
MS0952-E-03
2013/12
- 13 -
[AK4141]
VIH
LRCK
VIL
tBLR
tLRB
VIH
SCLK
VIL
tLRS
tBSD
SDTO
50%TVDD
Figure 3. Audio Interface Timing (Slave mode, Normal Mode)
VIH
LRCK
VIL
tBLR
tLRB
VIH
SCLK
VIL
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 4. Audio Interface Timing (Slave mode, TDM Mode)
MS0952-E-03
2013/12
- 14 -
[AK4141]
LRCK
50%TVDD
tMBLR
50%TVDD
SCLK
tBSD
50%TVDD
SDTO
tDXS
tDXH
VIH
SDTI
VIL
Figure 5. Audio Interface Timing (Master mode, Normal Mode)
LRCK
50%TVDD
tMBLR
50%TVDD
SCLK
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
TDMIN
VIL
Figure 6. Audio Interface Timing (Master mode, TDM Mode)
MS0952-E-03
2013/12
- 15 -
[AK4141]
VIH
PDN
VIL
tPDV
50%TVDD
SDTO
tPD
VIL
PDN
Figure 7. Power Down & Reset Timing
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
Figure 8. I2C Bus mode Timing
MS0952-E-03
2013/12
- 16 -
[AK4141]
OPERATION OVERVIEW
■ System Clock
The external clocks, which are required to operate the AK4141, are MCLK(or XTI), LRCK and SCLK. The MCLK(or
XTI) should always be present whenever the AK4141 is in normal operation, and should be synchronized with LRCK but
the phase is not critical. The on-chip X’tal oscillator or external system clock through MCKI can be used for the AK4141
operation. If the external clocks are not present, the AK4141 should be in the power-down mode (PDN pin = “L”) or in the
reset mode (RSTN bit = “0”). After exiting reset at power-up etc., the AK4141 is in the power-down mode until MCLK(or
XTI) and LRCK are input.
The AK4141 supports both master mode (SCLK, LRCK = output) and slave mode (SCLK, LRCK = input). The AK4141
is master mode when MSN pin = “H”, slave mode when MSN pin = “L”. SRC inputs (SCLK4/5, LRCK4/5) are always
slave mode (input) and can operate asynchronously.
PDN pin
MSN pin
L
H
L
H
L
H
SCLK, LRCK
SCLK4/5, LRCK4/5
Input (slave mode)
Input (slave mode)
Output “L” (master mode)
Input (slave mode)
Input (slave mode)
Input (slave mode)
Output (master mode)
Input (slave mode)
note: when CKS2-0 bits are default.
Table 1. Master/Salve Mode
The MSN pin and the CKS2-0 bits select the clock frequency (Table 2). The external clock (X’tal or MCKI) should always
be supplied except in the power-down mode. The AK4141 is in power-down mode until the clock is supplied.
MSN pin
CKS2 bit
CKS1 bit
CKS0 bit
Master
/Slave
L
0
0
0
Slave
L
L
L
L
L
L
L
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Master
Master
Master
Master
Master
Master
Master
128fs, 192fs, 256fs, 384fs, 512fs, 768fs, 1024fs
(register default)
128fs
192fs
256fs
384fs
512fs
768fs
1024fs
H
H
0
1
x
x
x
x
Master
Master
256fs
1024fs
Master Clock Speed
(register default)
(x: Don’t care.)
Table 2. System clock control
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
128fs
4.0960
5.6448
6.1440
192fs
6.1440
7.5264
9.2160
MCLK (MHz)
256fs
384fs
512fs
8.1920
12.2880
16.3840
11.2896
16.9344
22.5792
12.2880
18.4320
24.5760
Table 3. System clock example
MS0952-E-03
768fs
1024fs
24.5760
33.8688
36.8640
32.7680
45.1584
49.1520
2013/12
- 17 -
[AK4141]
■ Multi-standard Stereo Decoding
The AK4141 receives the Sound IF(SIF) signal and demodulates/decodes according to NICAM/A2/EIA-J standards. The
AK4141 can automatically select the stereo standard according to the actual input signal, the A4M5[2-0] pins(XORed with
A4M5[2-0] bits, default = “011”) and the A6M5 pin (XORed with A6M5 bit) setting.
A6M5 bit
A6M5 pin
Decoder Standard Preference1
0 (default)
L
SECAM L NICAM
0 (default)
H
D/K1, D/K2, D/K3 or D/K NICAM
1
L
D/K1, D/K2, D/K3 or D/K NICAM
1
H
SECAM L NICAM
Table 4. Decoder Standard Preference 1 (for 6.5MHz carrier)
Decoder Standard Preference2
LLL
PAL (Chroma Carrier)
LLH
M-Korea
LHL
EIAJ
LHH
Reserved
HLL
Reserved
HLH
Reserved
HHL
Reserved
HHH
Reserved
Table 5. Decoder Standard Preference 2 (for 4.5MHz carrier. Pin control. A4M5[2-0] bits = “011”(default))
A4M5[2-0] pins
Decoder Standard Preference2
00H
Reserved
01H
EIAJ
02H
M-Korea
03H
PAL (Chroma Carrier)
04H
Reserved
05H
Reserved
06H
Reserved
07H
Reserved
Table 6. Decoder Standard Preference 2 (for 4.5MHz carrier. Register control. A4M5[2-0] pins = “LLL”)
A4M5[2-0] bits
MS0952-E-03
2013/12
- 18 -
[AK4141]
■ Audio Serial Interface Format
The IDIF[1-0] and ODIF bit control the audio format for SCLK, SCLK4/5, LRCK, LRCK4/5, SDTI[1-5] and SDTO[1-3].
ODIF bit and IDIF0 bit are ORed with DIF pin. When the TDM bit = “1”, the TDM mode is enabled. The SRC inputs
(SDTI [4-5]) ignore the TDM bit and operate in normal mode. In all modes the serial data is MSB-first, 2’s complement
format. The SDTO1-3 pins are clocked out on the falling edge of SCLK pin and the SDTI[1-3] pins are latched on the
rising edge of SCLK pin. The SDTI[4-5] pins are latched on the rising edge of SCLK[4-5] pins. In SRC bypass mode, The
SCLK[4-5] and LRCK[4-5] should be synchronized to LRCK.
1. Normal mode: TDM bit = “0”
The TDM bit = “0” sets the AK4141 audio serial interface format to the normal mode. The IIS pin, DIF1-0 bits and
ODIF bit select following serial data format (Table 7, Table 8)
MSN
pin
IIS
pin
LRCK
L/R
I/O
BICK
speed
I/O
20bit Right Justified
24bit Right Justified
24bit Left Justified
(register default)
H/L
 16fs
 48fs
3
24/16bit I2S
L/H
2
24bit Right Justified
24/16bit I2S
(register default)
16bit Right Justified
24bit Right Justified
24bit Left Justified
(register default)
24/16bit I2S
H/L
24bit Right Justified
24/16bit I2S
(register default)
H/L
IDIF1
bit
IDIF0
bit
Mode
0
0
1
0
1
0
2
1
L
1
L
0
H
x
1
0
L
1
H
3
0
1
4
5
0
6
1
7
0
H
6
x
1
7
Input Audio Data
Format
 48fs
I
32fs or
 48fs
 48fs
32fs or
 48fs
I
O
64fs
O
L/H
H/L
L/H
L/H
(x: Don’t care.)
Table 7. Input Audio Data Format control
MSN
pin
IIS
pin
ODIF
bit
Mode
0
8
1
9
x
9
0
10
1
11
x
11
L
L
H
L
H
H
Output Audio Data
Format
24bit Left Justified
(register default)
24/16bit I2S
24/16bit I2S
(register default)
24bit Left Justified
(register default)
24/16bit I2S
24/16bit I2S
(register default)
LRCK
L/R
I/O
SCLK
speed
I/O
H/L
 48fs
L/H
I
L/H
32fs or
 48fs
32fs or
 48fs
I
H/L
L/H
O
64fs
O
L/H
(x: Don’t care.)
Table 8. Output Audio Data Format control
MS0952-E-03
2013/12
- 19 -
[AK4141]
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
SCLK(64fs)
SDTO(o)
23 22
SDTI(i)
12 11 10
Don’t Care
0
19 18
23 22
8
7
1
12
11 10
Don’t Care
0
0
19 18
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
23
8
7
1
0
Rch Data
Figure 9. Mode 0/4/8/10 Timing
LRCK
0
1
2
8
9
10
24
25
31
0
1
2
8
9
10
24
25
31
0
1
SCLK(64fs)
SDTO(o)
23 22
SDTI(i)
16 15 14
Don’t Care
0
23 22
23:MSB, 0:LSB
23 22
8
7
1
16 15 14
Don’t Care
0
0
23 22
Lch Data
23
8
7
1
0
Rch Data
Figure 10. Mode 1/5 Timing
LRCK
0
1
2
21
22
23
24
28
29
30
31
0
1
2
22
23
24
28
29
30
31
0
1
SCLK(64fs)
SDTO(o)
23 22
2
1
0
SDTI(i)
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
23
Don’t Care
23
Rch Data
Figure 11. Mode 2/6 Timing
LRCK
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
SCLK(64fs)
SDTO(o)
23 22
2
1
0
SDTI(i)
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
Don’t Care
Rch Data
Figure 12. Mode 3/7/9/11 Timing
MS0952-E-03
2013/12
- 20 -
[AK4141]
2. TDM mode: TDM bit = “1”
The TDM bits = “1” set the AK4141 audio serial interface format to the TDM mode. The eight channel serial data
(SDTI1/2/3 and SDTI4 at non-SRC mode) is input through the SDTI1 pin. The six channel serial data is output through
the SDTO1 pin. The SDTI2/3/4/5 pins are not used for TDM input and the SDTO2/3 pins outputs “L”.
256 BICK
LRCK (slave)
(master)
SCLK(256fs)
SDTO1(o)
SDTI1(i)
23 22
0
23 22
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
L3
R3
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
32 BICK
23 22
0
23 22
R1
L1
SDTI5(i)
0
0
32 BICK
23 22
0
23 22
0
23 22
0
23 22
0
23 22
23 22
0
23 22
0
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0
L5
R5
32 BICK
32 BICK
23 22
23 22
Figure 13. TDM MSB Justified Timing
256 BICK
LRCK (slave)
(maser)
SCLK(256fs)
SDTO1(o)
23
0
23
L1
32 BICK
SDTI1(i)
SDTI5(i)
23
0
23
R1
0
32 BICK
23
0
L2
0
0
23
R2
32 BICK
23
23
0
32 BICK
23
0
23
L3
0
32 BICK
23
23
0
R3
0
32 BICK
23
0
23
0
23
0
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
Figure 14. TDM IIS Timing
MS0952-E-03
2013/12
- 21 -
[AK4141]
■ Digital Block
The digital block consists of block diagram as shown in Figure 15.
(Audio Data from selector)
Audio
Processing
Block
FIL3 bit
Stereo
Separation
EQ0 bit
GN1-0 bits
Gain
Compensation
EQ5-1 bit
5 Band
EQ
ALC1/2 bits
ALC
BAL1/2 bits
Balance
VOL1/2 bits
Main
Volume
SDTO1, 2
(1) Stereo Separation: Digital Separation Emphasis Filter (See “Digital Programmable Filter Circuit”)
(2) Gain Compensation: Composed of the Equalizer (EQ0) and the Gain (0bB/+12dB/+24dB). Compensate the frequency
response and the gain after the Stereo Separation Emphasis Filter.
(3) 5-Band Notch: Applicable to use as Equalizer or Notch Filter. (See “Digital Programmable Filter”)
(4) ALC: Input Digital Volume with ALC function. (See “ALC Operation”)
(5) Balance: Stereo Balance Control.
(6) Main Volume: Stereo Main Volume Control.
Figure 15 Audio Processing Block
MS0952-E-03
2013/12
- 22 -
[AK4141]
■ Digital Programmable Filter Circuit
(1) Stereo Separation Emphasis Filter (FIL3)
FIL3 is used to emphasize the stereo separation of stereo data. F3A1[13:0], F3A2[13:0] and F3B1[13:0], F3B1[13:0] bits
set the filter coefficient of FIL3 for SDTO1/2 respectively. FIL3 becomes High Pass Filter (HPF) at F3AS1/2 bit = “1”, and
Low Pass Filter (LPF) at F3AS1/2 bit = “0”. F3BP1/2 bit controls ON/OFF of FIL3. When Stereo Separation Emphasis
Filter is OFF, the audio data passes this block by 0dB gain. The coefficient should be set when F3BP1/2 bit = “0”.
1) When FIL3 is set to “HPF”
fs: Sampling frequency
fc: Cut-off frequency
K: Filter gain [dB] (0dB  K  10dB)
Register setting (Figure 15)
FIL3: F3AS1/2 bit = “1”, F3A1[13:0], F3A1[13:0] bits =A, F3B1[13:0], F3B2[13:0] bits =B
(MSB=F3A113(F3A213), F3B13(F3B213); LSB=F3A10(F3A20), F3B10(F3B20))
1  1 / tan (fc/fs)
1 / tan (fc/fs)
A = 10K/20 x
,
B=
1 + 1 / tan (fc/fs)
1 + 1 / tan (fc/fs)
Transfer function
1  z 1
H(z) = A
1 + Bz 1
2) When FIL3 is set to “LPF”
fs: Sampling frequency
fc: Cut-off frequency
K: Filter gain [dB] (0dB  K  10dB)
Register setting (Figure 15)
FIL3: F3AS1/2 bit = “0”, F3A1[13:0], F3A1[13:0] bits =A, F3B1[13:0], F3B2[13:0] bits =B
(MSB= F3A113(F3A213), F3B13(F3B213); LSB= F3A10(F3A20), F3B10(F3B20))
1  1 / tan (fc/fs)
1
A = 10K/20 x
,
1 + 1 / tan (fc/fs)
B=
1 + 1 / tan (fc/fs)
Transfer function
1 + z 1
H(z) = A
1 + Bz 1
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[AK4141]
(2) Gain Compensation (EQ0)
Gain Compensation is used to compensate the frequency response and the gain that is changed by Stereo Separation
Emphasis Filter. Gain Compensation is composed of the Equalizer (EQ0) and the Gain (0dB/+12dB/+24dB). E0A1[15:0],
E0A215:0], E0B1[15:0] and E0B2[15:0] bits set the coefficient of EQ0. GN1[1:0], GN2[1:0] bits set the gain (Table 9).
fs: Sampling frequency
fc1: Pole frequency
fc2: Zero-point frequency
K: Filter gain [dB] (Maximum +12dB)
Register setting (Figure 15)
E0A1[15:0], E0A2[15:0] bits =A, E0B1[13:0], E0B2[13:0] bits =B, E0C1[15:0], E0C2[15:0] bits =C
(MSB=E0A115(E0A215),E0B113(E0B213), E0C115(E0C215); LSB=E0A10(E0A20), E0B10(E0B20),
E0C10(E0C20))
A = 10K/20 x
1  1 / tan (fc1/fs)
1 + 1 / tan (fc2/fs)
,
1 + 1 / tan (fc1/fs)
B=
,
C =10K/20 x
1 + 1 / tan (fc1/fs)
1  1 / tan (fc2/fs)
1 + 1 / tan (fc1/fs)
Transfer function
A + Cz 1
H(z) =
1 + Bz 1
Gain[dB]
K
fc1
fc2
Frequency
Figure 16. EQ0 Frequency Response
GN1
GN0
Gain
0
0
0dB
(default)
0
1
+12dB
1
x
+24dB
Table 9. Gain select of gain block (x: Don’t care)
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[AK4141]
(3) 5 Band Equalizer
The center frequencies and cut/boost amount are the followings.
 Center frequency: 100Hz, 250Hz, 1kHz, 3.5kHz, 10kHz (Note 16, Note 17)
 Cut/Boost amount: Minimum –10.5dB, Maximum +12dB, Step 1.5dB
Note 16: These are the frequencies when the sampling frequency is 44.1kHz. These frequencies are proportional to the
sampling frequency.
Note 17: 100Hz is not center frequency but the frequency component lower than 100Hz is controlled.
Note 18: 10kHz is not center frequency but the frequency component higher than 10kHz is controlled.
EQ1/2 bits control ON/OFF of this Equalizer and these Boost amount are set by EQx3-0 bit as shown in Table 23.
EQA3-0:
EQB3-0:
EQC3-0:
EQD3-0:
EQE3-0:
Select the boost level of 100Hz
Select the boost level of 250Hz
Select the boost level of 1kHz
Select the boost level of 3.5kHz
Select the boost level of 10kHz
EQx3-0
Boost amount
0H
+12.0dB
1H
+10.5dB
2H
+9.0dB
3H
+7.5dB
:
:
8H
0dB
(default)
:
:
DH
7.5dB
EH
9.0dB
FH
10.5dB
Table 10. Boost amount of 5 Band Equalizer
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[AK4141]
■ ALC Operation
1.
ALC Limiter Operation
During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 11), the VOL
value (same value for both L and R) is attenuated automatically by the amount defined by the ALC limiter ATT step (Table
12). The VOL is then set to the same value for both channels.
When ZELMN bit = “0” (zero cross detection is enabled), the VOL value is changed by ALC limiter operation at the
individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing timeout
period of both ALC limiter and recovery operation (Table 13).
When ZELMN bit = “1” (zero cross detection is disabled), VOL value is immediately (period: 1/fs) changed by ALC
limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits.
The attenuate operation is executed continuously until the input signal level becomes ALC limiter detection level (Table
11) or less. After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the
input signal level exceeds LMTH1-0 bits.
LMTH1
0
0
1
1
LMTH0 ALC Limiter Detection Level
ALC Recovery Waiting Counter Reset Level
0
ALC Output  2.5dBFS
2.5dBFS > ALC Output  4.1dBFS
1
ALC Output  4.1dBFS
4.1dBFS > ALC Output  6.0dBFS
0
ALC Output  6.0dBFS
6.0dBFS > ALC Output  8.5dBFS
1
ALC Output  8.5dBFS
8.5dBFS > ALC Output  12dBFS
Table 11. ALC Limiter Detection Level / Recovery Counter Reset Level
(default)
ALC1 Limiter ATT Step
LMAT1
LMAT0
0
0
1
1
0
1
0
1
ZTM1
ZTM0
0
0
1
1
0
1
0
1
ALC1 Output ALC1 Output
 LMTH
 FS
ALC1 Output
 FS + 6dB
1
1
2
2
2
4
1
2
Table 12. ALC Limiter ATT Step
ALC1 Output
 FS + 12dB
1
2
4
4
Zero Crossing Timeout Period
32kHz
44.1kHz
48kHz
128/fs
4.0ms
2.9ms
2.7ms
256/fs
8.0ms
5.8ms
5.3ms
512/fs
16.0ms
11.6ms
10.7ms
1024/fs
32.0ms
23.2ms
21.3ms
Table 13. ALC Zero Crossing Timeout Period
MS0952-E-03
1
2
8
8
(default)
(default)
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[AK4141]
2.
ALC Recovery Operation
The ALC recovery operation waits for the WTM2-0 bits (Table 14) to be set after completing the ALC limiter operation.
If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 11) during the wait time, the ALC
recovery operation is executed. The VOL value is automatically incremented by RGAIN1-0 bits (Table 15) up to the set
reference level (Table 16) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 13). Then the
IVL and IVR are set to the same value for both channels. The ALC recovery operation is executed at a period set by
WTM2-0 bits. When zero cross is detected at both channels during the wait period set by WTM2-0 bits, the ALC recovery
operation waits until WTM2-0 period and the next recovery operation is executed.
For example, when the current VOL value is 30H and RGAIN1-0 bits are set to “01”, VOL is changed to 32H in the auto
limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the VOL value exceeds the
reference level (REF7-0), the VOL values are not increased.
When
“ALC recovery waiting counter reset level (LMTH1-0)  Output Signal < ALC limiter detection level (LMTH1-0)”
during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When
“ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”,
the waiting timer of ALC recovery operation starts.
The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation
becomes faster than a normal recovery operation. When large noise is input to microphone instantaneously, the quality of
small signal level in the large noise can be improved by this fast recovery operation. The speed of fast recovery operation
is set by RFST1-0 bits(Table 17).
WTM2
WTM1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
ALC Recovery Operation Waiting Period
32kHz
44.1kHz
48kHz
0
128/fs
4.0ms
2.9ms
2.7ms
1
256/fs
8.0ms
5.8ms
5.3ms
0
512/fs
16.0ms
11.6ms
10.7ms
1
1024/fs
32.0ms
23.2ms
21.3ms
0
2048/fs
64.0ms
46.4ms
42.7ms
1
4096/fs
128.0ms
92.9ms
85.3ms
0
8192/fs
256.0ms
185.8ms
170.7ms
1
16384/fs
512.0ms
371.5ms
341.3ms
Table 14. ALC Recovery Operation Waiting Period
WTM0
RGAIN1
0
0
1
1
RGAIN0
GAIN STEP
0
1 step
0.375dB
1
2 step
0.750dB
0
3 step
1.125dB
1
4 step
1.500dB
Table 15. ALC Recovery GAIN Step
MS0952-E-03
(default)
(default)
2013/12
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[AK4141]
IREF17-10bits
GAIN(0dB)
Step
IREF27-10bits
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
E1H
+30.0(default)
0.375dB
:
:
92H
+0.375
91H
0.0
90H
-0.375
:
:
2H
-53.625
1H
-54.0
0H
MUTE
Table 16. Reference Level at ALC Recovery operation for ALC1/2
RFST1 bit
RFST0 bit
Recovery Speed
0
0
x4
(default)
0
1
x8
1
0
x 16
1
1
N/A
Table 17. Fast Recovery Speed Setting (N/A: Not available)
3.
Example of ALC Operation
Table 18 shows the example of the ALC setting.
Register Name
LMTH1-0
ZELMN
ZTM1-0
WTM2-0
IREF5-0
LMAT1-0
RGAIN1-0
RFST1-0
Comment
Data
01
0
11
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same data
100
as ZTM1-0 bits
Maximum gain at recovery operation
28H
Limiter ATT step
00
Recovery GAIN step
00
Fast Recovery Speed
00
Table 18. Example of the ALC Setting
fs=44.1kHz
Operation
4.1dBFS
Enable
23.2ms
46.4ms
+6dB
1 step
1 step
4 times
The following registers should not be changed during the ALC operation.
 LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0
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[AK4141]
■ Basic Operation Sequence Example
Condition:
Master mode (MSN pin = “H”), Audio Data Format = I2S (IIS pin = “H”), Clock source = X’tal (12.288MHz, 256fs),
fs=48kHz, SIF input = SIF1 pin.
PDN pin ="L" to "H"
Write
11H, 10H E0A1[15:0] = “2000H”: SDTO1 unmute,
(1BH, 1AH E0A2[15:0] = “2000H”: SDTO2 unmute)
(Input SIF signal)
Write
41H ASD = “1”: run the Auto System Detection
53H ASDC = "1"
N
Y
41H SYS[3:0] = "0FH"
N
Y: (system unknown.
rerun the ASD.)
Auto System Detection completed.
Normal Operation
Figure 17. Basic Operation Sequence Example
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[AK4141]
■ Serial Control Interface
The AK4141 supports fast-mode I2C-bus system (max: 400kHz).
1. Data transfer
All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4141
recognizes the START condition, the device interfaced to the bus waits of the slave address to be transmitted over the SDA
line. If the transmitted slave address matches an address for one of the devices, the designated slave device pulls the SDA
line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition generated by the master
device.
1-1. Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can
only be changed when the clock signal on the SCL line is LOW except for the START and the STOP condition.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 18. Data transfer
1-2. START and STOP condition
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from the
START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the
STOP condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 19. START and STOP conditions
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[AK4141]
1-3. ACKNOWLEDGE
ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitter will release the
SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the acknowledge clock
pulse so that that it remains stable “L” during “H” period of this clock pulse. The AK4141 generates an acknowledge after
each byte is received.
In read mode, the slave, the AK4141 transmits eight bits of data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue
transmitting data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the STOP
condition.
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
START
CONDITION
acknowledge
Figure 20. Acknowledge on the I2C-bus
1-4. FIRST BYTE
The first byte, which includes seven bits of slave address and one bit of R/W bit, is sent after the START condition. If the
transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down the
SDA line.
The most significant four bits of the slave address are fixed as “1000”. The next three bits are CAD1, CAD0 (device
address bits) and “0”. These three bits identify the specific device on the bus. The setting such as CAD/CAD0 = “11” is not
available. The eighth bit (LSB) of the first byte (R/W bit) defines whether the master requests a write or read condition. A
“1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be executed.
1
0
0
0
CAD1
CAD0
0
R/W
(CAD1-CAD0 bits should match with CAD1-CAD0 pins)
Figure 21. The First Byte
CAD1 pin
L
L
L
L
H
H
H
H
CAD0 pin
L
L
H
H
L
L
H
H
R/W
Write
Read
Write
Read
Write
Read
Write
Read
First Byte
80H
81H
84H
85H
88H
89H
N/A
N/A
(N/A: Not available)
Table 19. The First Byte Setting
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[AK4141]
(2)-2. WRITE Operations
Set R/W bit = “0” for the WRITE operation of the AK4141.
After receipt the start condition and the first byte, the AK4141 generates an acknowledge, and awaits the second byte
(register address). The second byte consists of the address for control registers of AK4141. The format is MSB first.
A7
A6
A5
A4
A3
A2
A1
A0
Figure 22. The Second Byte
After receipt the second byte, the AK4141 generates an acknowledge, and awaits the third byte. Those data after the second
byte contain control data. The format is MSB first, 8bits.
D7
D6
D5
D4
D3
D2
D1
D0
Figure 23. Byte structure after the second byte
The AK4141 is capable of more than one byte write operation by one sequence.
After receipt of the third byte, the AK4141 generates an acknowledge, and awaits the next data again. The master can
transmit more than one word instead of terminating the write cycle after the first data word is transferred. After the receipt
of each data, the internal 8bits address counter is incremented by one, and the next data is taken into next address
automatically. If the address exceeds TBDH prior to generating the stop condition, the address counter will “roll over” to
00H and the previous data will be overwritten.
S
T
A
R
T
SDA
Slave
Address
Register
Address(n)
Data(n)
S
T
Data(n+x) O
P
Data(n+1)
S
P
A
C
K
A
C
K
A
C
K
A
C
K
Figure 24. WRITE Operation
MS0952-E-03
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[AK4141]
(2)-3. READ Operations
Set R/W bit = “1” for the READ operation of the AK4141.
After transmission of the data, the master can read next address’s data by generating the acknowledge instead of
terminating the write cycle after the receipt of the first data word. After the receipt of each data, the internal 5bits address
counter is incremented by one, and the next data is taken into next address automatically. If the address exceed TBDH prior
to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The AK4141 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
ADC/DAC part register can not be read.
(2)-3-1. CURRENT ADDRESS READ
The AK4141 contains an internal address counter that maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would access
data from the address “n+1”.
After receipt of the slave address with R/W bit set to “1”, the AK4141 generates an acknowledge, transmits 1byte data
which address is set by the internal address counter and increments the internal address counter by 1. If the master does not
generate an acknowledge but generate the stop condition, the AK4141 discontinues transmission
S
T
A
R
T
SDA
Slave
Address
Data(n)
Data(n+1)
S
Data(n+x) T
O
P
Data(n+2)
S
P
A
C
K
A
C
K
A
C
K
A
C
K
Figure 25. CURRENT ADDRESS READ
(2)-3-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address with
the R/W bit set to “1”, the master must first perform a “dummy” write operation.
The master issues the start condition, slave address(R/W=“0”) and then the register address to read. After the register
address’s acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to
“1”. Then the AK4141 generates an acknowledge, 1byte data and increments the internal address counter by 1. If the
master does not generate an acknowledge but generate the stop condition, the AK4141 discontinues transmission.
S
T
A
R
T
SDA
Slave
Address
S
T
A
R
T
Word
Address(n)
S
Slave
Address
Data(n)
S
Data(n+x) T
O
P
Data(n+1)
S
A
C
K
P
A
C
K
A
C
K
A
C
K
A
C
K
Figure 26. RANDOM READ
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[AK4141]
■ Register Map
Addr
Register Name
General Control
00H
Power Management
01H
Clock Control
02H
Audio Data Format
Switch
03H
Switch Matrix 0
04H
Switch Matrix 1
05H
Switch Matrix 2
Prescale
06H
Decoder Prescale
07H
Input 1 Prescale
08H
Input 2 Prescale
09H
Input 3 Prescale
0AH
Input 4 Prescale
0BH
SRC Prescale
3D Enhancement
0CH
FIL3 Coefficient 0
0DH
FIL3 Coefficient 1
0EH
FIL3 Coefficient 2
0FH
FIL3 Coefficient 3
10H
EQ0-efficient 0
11H
EQ0-efficient 1
12H
EQ0-efficient 2
13H
EQ0-efficient 3
14H
EQ0-efficient 4
15H
EQ0-efficient 5
16H
FIL3 Coefficient 0
17H
FIL3 Coefficient 1
18H
FIL3 Coefficient 2
19H
FIL3 Coefficient 3
1AH
EQ0-efficient 0
1BH
EQ0-efficient 1
1CH
EQ0-efficient 2
1DH
EQ0-efficient 3
1EH
EQ0-efficient 4
1FH
EQ0-efficient 5
EQ
20H EQ1 Control 250Hz/100Hz
21H EQ1 Control 3.5kHz/1kHz
22H
EQ1 Control 10kHz
23H EQ2 Control 250Hz/100Hz
24H EQ2 Control 3.5kHz/1kHz
25H
EQ2 Control 10kHz
ALC
26H
Timer Select1
27H
ALC1 Mode Control 1
28H
ALC1 Mode Control 2
29H
Timer Select2
27H
ALC2 Mode Control 1
2BH
ALC2 Mode Control 2
D7
D6
D5
PWDT
MCKE
TDM
PWSR
MCKD
0
BPSR
V
0
SWSR
SWCK
DIT[2:0]
SD2[2:0]
GSEL2
GSEL1
0
PWOS PWDE
FS[1:0]
IDIF[1:0]
0
0
0
0
0
F3AS1
GN1[1:0]
F3BP2
0
GN2[1:0]
EQ2
0
ALC1
0
ALC2
D2
D1
D0
AFEM1
0
0
ROLL
CKS[2:0]
RSTN
0
SMUT3
DIT16
0
ODIF
SMUT2 SMUT1 SMUTT
SD1[2:0]
SD3[2:0]
DPRE[4:0]
F3A1[7:0]
F3A1[13:8]
F3B1[7:0]
F3B1[13:8]
E0A1[7:0]
E0A1[15:8]
E0B1[7:0]
E0B1[13:8]
E0C1[7:0]
E0C1[15:8]
F3A2[7:0]
F3A2[13:8]
F3B2[7:0]
F3B2[13:8]
E0A2[7:0]
E0A2[15:8]
E0B2[7:0]
E0B2[13:8]
E0C2[7:0]
E0C2[15:8]
0
EQ1
SWSF
D3
I1PRE[4:0]
I2PRE[4:0]
I3PRE[4:0]
I4PRE[4:0]
SPRE[4:0]
F3BP1
F3AS2
D4
EQB1[3:0]
EQD1[3:0]
0
EQB2[3:0]
EQD2[3:0]
0
EQA1[3:0]
EQC1[3:0]
EQE1[3:0]
EQA2[3:0]
EQC2[3:0]
EQE2[3:0]
WTM1[2:0]
ZTM1[1:0]
RGAIN1[1:0]
LMAT1[1:0]
IREF1[7:0]
WTM2[2:0]
ZTM2[1:0]
ZELMN2
RGAIN2[1:0]
LMAT2[1:0]
IREF2[7:0]
ZELMN1
MS0952-E-03
RFST1[1:0]
LMTH1[1:0]
RFST2[1:0]
LMTH2[1:0]
2013/12
- 34 -
[AK4141]
Addr
Register Name
Balance
2CH
Balance Mode Control
2DH
Balance 1 Control
2EH
Balance 2 Control
Volume
2FH
Main Volume 1 Control
30H
Main Volume 2 Control
DIT C bit
31H
Channel Status 1
32H
Channel Status 2
33H
Channel Status 3
34H
Channel Status 4
Decoder
40H
SIF AGC Manual Control
41H
System Select
42H
Standard Select
43H
Sample Rate
44H
FM/AM Demod Control
45H Demod 1 Carrier Freq Ctrl 1
46H Demod 1 Carrier Freq Ctrl 0
47H
FM/DQPSK Dem Ctrl
48H Demod 2 Carrier Freq Ctrl 1
49H Demod 2 Carrier Freq Ctrl 0
4AH
Decoder Output Control
4BH
Audio Mode Detect
4CH
Pilot PLL Status
4DH
NICAM Error Rate 1
4EH
NICAM Error Rate 0
4FH
NICAM Control Bits 1
50H
NICAM Control Bits 0
51H
SIF AGC Control
52H
AGC Control for AM
53H
Status
54H
Status Pin Control
55H
A/D headroom
56H
AGC Freeze
57H
Stereo Carrier Search Ctrl
58H Stereo Carrier Search Result
59H
Audio Output Result
5AH
Mute Control / Status
5BH Auto System Detect Control
5CH
Decoder AVC
5DH
Level Prescaler Control
5EH
Prescaler L
5FH
Prescaler R
60H
Manual Output Level L
61H
Manual Output Level R
D7
D6
D5
D4
D3
D2
0
BAL1[7:0]
BAL2[7:0]
D1
D0
BMOD
VOL1[7:0]
VOL2[7:0]
0
CS[27:24]
CS3
CS[41:40]
0
CS2
CS1
CS[29:28]
CS[15:8]
CS[39:36]
AGOFF
0
0
0
CS[35:33]
CS32
IFVOL[5:0]
SYS[3:0]
STD[2:0]
0
DECFS[1:0]
DM1LP[2] DM1DV[2]
0
DM1LP[1:0]
DM1MD DM1DV[1:0]
DM1F[15:8]
DM1F[7:0]
0
DM2LP[1:0]
DM2MD
0
DM2F[15:8]
DM2F[7:0]
LOR
ROL
LRSM AUTO
LSEL[1:0]
RSEL[1:0]
0
AMOD[1:0]
0
LOCK
NERR[15:8]
NERR[7:0]
NIAD[10:3]
NIAD[2:0]
NICT[4:0]
AGAT[3:0]
AGDC[3:0]
AMAT[3:0]
AMDC[3:0]
ASDC
BI
IMONO MONO
SNDST[1:0]
C2DET C1DET
0
ASTAT STAP STAE
0
HDRM[2:0]
0
AGFRZ
0
CHMD[1:0]
SREN[1:0]
0
SRIND SRCMP SRST
SRRSL[3:0]
LOR
ROL LRSUM
0
LRSL[1:0]
RRSL[1:0]
0
AAOMT ASDMT LMT
RMT MANMT MUTEL MUTER
0
A6M5
A4M5[2:0]
0
DATK[1:0]
DDEC[1:0]
AVCE
PRECTL
0
PREL[7:0]
PRER[7:0]
LEVL[7:0]
LEVR[7:0]
ASD
ID[1:0]
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[AK4141]
Addr
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
80H
81H
82H
83H
84H
85H
86H
87H
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
90H
91H
92H
93H
94H
95H
Register Name
Carrier 1 Average Frequency 1
Carrier 1 Average Frequency 0
Carrier 1 Phase Noise 1
Carrier 1 Phase Noise 0
Carrier 1 Average Magnitude 1
Carrier 1 Average Magnitude 0
Carrier 1 Magnitude Noise 1
Carrier 1 Magnitude Noise 0
Carrier 1 Signal Quality 1
Carrier 1 Signal Quality 0
Carrier 2 Average Frequency 1
Carrier 2 Average Frequency 0
Carrier 2 Average Magnitude 1
Carrier 2 Average Magnitude 0
Carrier 2 Magnitude Noise 1
Carrier 2 Magnitude Noise 0
Carrier 2 Signal Quality 1
Carrier 2 Signal Quality 0
Pilot Magnitude
FM Subcarrier Magnitude
FM Subcarrier Noise
N/A
N/A
N/A
N/A
Carrier 1 Quality Threshold High
Carrier 1 Quality Threshold Low
Carrier 2 Quality Threshold High
Carrier 2 Quality Threshold Low
Carrier 1 Phase Noise Threshold High
Carrier 1 Phase Noise Threshold Low
FM Sub Magnitude Threshold High
FM Sub Magnitude Threshold Low
FM Sub Noise Threshold High
FM Sub Noise Threshold Low
NCM Err Rate Threshold High
NCM Err Rate Threshold Low
N/A
N/A
N/A
N/A
Carrier Magnitude ASD Threshold
Carrier Freq ASD Threshold
Carrier FM Quality ASD Threshold
Carrier AM Noise ASD Threshold
NICAM Noise ASD Threshold
NICAM Noise High
NICAM Noise Low
Carrier FM Quality SCS Threshold
NICAM Noise SCS Threshold
AVC Level Threshold High
AVC Level Threshold Low
D7
D6
MS0952-E-03
D5
D4
D3
CR1F[15:8]
CR1F[7:0]
CR1P[15:8]
CR1P[7:0]
CR1M[15:8]
CR1M[7:0]
CR1N[15:8]
CR1N[7:0]
CR1Q[15:8]
CR1Q[7:0]
CR2F[15:8]
CR2F[7:0]
CR2M[15:8]
CR2M[7:0]
CR2N[15:8]
CR2N[7:0]
CR2Q[15:8]
CR2Q[7:0]
PLTM[7:0]
SUBM[7:0]
SUBN[7:0]
00H
00H
00H
00H
C1QTH[7:0]
C1QTL[7:0]
C2QTH[7:0]
C2QTL[7:0]
C1PTH[7:0]
C1PTL[7:0]
FSMTH[7:0]
FSMTL[7:0]
FSNTH[7:0]
FSNTL[7:0]
NERTH[7:0]
NERTL[7:0]
00H
00H
00H
00H
ASDMT[7:0]
ASDFT[7:0]
ASQT[7:0]
AANT[7:0]
ANNT[7:0]
NICN[15:8]
NICN[ 7:0]
SQLT[7:0]
SNST[7:0]
AVCH[7:0]
AVCL[7:0]
D2
D1
D0
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[AK4141]
Note:
For addresses from 96H ~ 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default values.
The bits shown as “0” should be written “0”.
■ Register Definitions
General Control
Addr
00H
Register Name
Power Management
R/W
Default
D7
PWDT
R/W
1
D6
PWSR
R/W
1
D5
PWOS
R/W
1
D4
PWDE
R/W
1
D3
AFEM1
R/W
0
D2
0
R/W
0
D1
ROLL
R/W
0
D0
RSTN
R/W
1
RSTN: Timing Reset Control
0: Timing Reset
1: Normal Operation (default)
ROLL: Roll Over Address Control
0: roll-over to 00H from 61H and 95H (default)
1: roll-over to 00H from 95H but not from 61H.
AFEM[1]: AFE Mode 1
Write “1” into this bit.
0: SIF HPF ON (default)
1: SIF HPF OFF
PWDE: Stereo Decoder Power Control
0: Power down
1: Power up (default)
PWOS: X’tal Oscillator Power Control
0: Power down
1: Power up (default)
PWSR: SRC Power Control
0: Power down
1: Power up (default)
PWDT: DIT Power Control
0: Power down
1: Power up (default)
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Addr
01H
Register Name
Clock Control
R/W
Default
D7
MCKE
R/W
0
D6
MCKD
R/W
0
D5
D4
FS[1:0]
R/W
R/W
0
0
D3
0
R/W
0
D2
R/W
0
D1
CKS[2:0]
R/W
0
D0
R/W
0
CKS[2:0]
CKS1 bit is ORed with the MSN pin. CKS0 bit is ORed with the MSN pin.
CKS[2:0]
00
01
02
03
04
05
06
07
Master/Slave
Slave (default)
Master 128fs
Master 192fs
Master 256fs
Master 384fs
Master 512fs
Master 768fs
Master 1024fs
Table 20. Master/Slave
FS[1:0]: Sampling Rate Control
FS[1:0] bits should be changed when the RSTN bit = “L”
FS[1:0]
00
01
02
Sample Rate
48kHz (default)
32kHz
44.1kHz
03
reserved
Table 21. Sample Rate
MCKD/MCKE: Master clock output control
MCKD bit
0
0
1
1
MCKE bit
0
1
0
1
Sample Rate
Outputs “L” (default)
Outputs X’tal (or MCKI) frequency x 1/4.
Outputs X’tal (or MCKI) frequency x 1/2.
Outputs X’tal (or MCKI) frequency.
Note: MCKO≤512fs
Table 22. Sample Rate
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[AK4141]
Addr
02H
Register Name
Audio Data Format
R/W
Default
D7
TDM
R/W
0
D6
0
R/W
0
D5
D4
IDIF[1:0]
R/W
R/W
1
0
D3
D2
0
R/W
0
R/W
0
D1
R/W
0
D0
ODIF
R/W
0
ODIF: Output Data Format
ODIF bit is ORed with IIS pin.
0: 24bit Left Justified (default)
1: 24/16bit I2S
IDIF[1:0]: Input Data Format
IDIF0 bit is ORed with IIS pin.
00: 16bit Right Justified
01: 24bit Right Justified
02: 24bit Left Justified (default)
03: 24/16bit I2S
TDM: TDM mode enable
0: Normal Data Format Mode (default)
1: TDM Data Format Mode
256 BICK
LRCK (slave)
(master)
BICK(256fs)
SDTO1(o)
SDTI1(i)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
L3
R3
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
23 22
0
23 22
0
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23 22
Figure 27. TDM MSB Justified Timing
256 BICK
LRCK (slave)
(maser)
BICK(256fs)
SDTO1(o)
SDTI1(i)
23
0
23
0
23
0
23
0
23
0
23
L1
R1
L2
R2
L3
R3
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
Figure 28. TDM IIS Timing
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[AK4141]
Switch
Addr
Register Name
D7
D6
D5
D4
03H
Switch Matrix 0
BPSR
SWSR
SWCK
SWSF
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Default
D3
D2
D1
D0
SMUT3 SMUT2 SMUT1 SMUTT
R/W
0
R/W
0
R/W
0
R/W
0
MUTET: DIT Audio Data Soft Mute Control
0: Unmute (default)
1: Soft Mute
MUTE1: SDTO1 Soft Mute Control
0: Unmute (default)
1: Soft Mute
MUTE2: SDTO2 Soft Mute Control
0: Unmute (default)
1: Soft Mute
MUTE3: SDTO3 Soft Mute Control
0: Unmute (default)
1: Soft Mute
SWSF: SIF Input Control
0: SIF1 (default)
1: SIF2
SWCK: MCLK/X’tal Control
0: X’tal (default)
1: MCLK
SWSR: SRC Input Control
0: SDTI4 (default)
1: SDTI5
BPSR: SRC Bypass
0: SRC Mode (default)
1: SRC Bypass Mode
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[AK4141]
Addr
04H
Register Name
Switch Matrix 1
R/W
Default
D7
V
R/W
0
D6
R/W
0
D5
DIT[2:0]
R/W
0
D4
R/W
0
D3
0
R/W
0
D2
R/W
0
D1
SD1[2:0]
R/W
0
D0
R/W
0
SD1[2:0]: SDTO1 Source Data Control
00: Decoder (default)
01: SDTI1
02: SDRI2
03: SDRI3
04: SDRI4
05: SRC
06: reserved
07: Mute
DIT[2:0]: DIT Source Data Control
00: Decoder (default)
01: SDTI1
02: SDRI2
03: SDRI3
04: SDRI4
05: SRC
06: TXIN (TX through)
07: Mute
V: DIT Validity bit Control
0: V bit = “0” (default)
1: V bit = “1”
Addr
05H
Register Name
Switch Matrix 2
R/W
Default
D7
0
R/W
0
D6
R/W
0
D5
SD2[2:0]
R/W
0
D4
R/W
0
D3
0
R/W
0
D2
R/W
0
D1
SD3[2:0]
R/W
0
D0
R/W
0
SD2[2:0]: SDTO2 Source Data Control
00: Decoder (default)
01: SDTI1
02: SDRI2
03: SDRI3
04: SDRI4
05: SRC
06: reserved
07: Mute
SD3[2:0]: SDTO3 Source Data Control
00: Decoder (default)
01: SDTI1
02: SDRI2
03: SDRI3
04: SDRI4
05: SRC
06: reserved
07: Mute
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Prescale
Addr
06H
07H
08H
09H
0AH
0BH
Register Name
Decoder Prescale
Input 1 Prescale
Input 2 Prescale
Input 3 Prescale
Input 4 Prescale
SRC Prescale
R/W
Default
D7
GSEL2
R/W
0
D6
GSEL1
0
0
0
0
0
R/W
0
D5
0
D4
D3
R/W
0
R/W
0
R/W
1
D2
DPRE[4:0]
I1PRE[4:0]
I2PRE[4:0]
I3PRE[4:0]
I4PRE[4:0]
SPRE[4:0]
R/W
1
D1
D0
R/W
0
R/W
1
DPRE[4:0]: Decoder Prescale
I1PRE[4:0]: SDTI1 Prescale
I2PRE[4:0]: SDTI2 Prescale
I3PRE[4:0]: SDTI3 Prescale
I4PRE[4:0]: SDTI4 Prescale
SPRE[4:0]: SRC Prescale
1F: +18dB
1E: +17dB
…
0E: +1dB
0D: 0dB (default)
…
01: -12dB
00: Mute
GSEL2
0 : SIF2 high gain mode S2D-Gain=7.5dB(default)
1 : SIF2 low gain mode S2D-Gain=4.5dB
GSEL1
0 : SIF1 high gain mode S2D-Gain=7.5dB(default)
1 : SIF1 low gain mode S2D-Gain=4.5dB
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[AK4141]
3D Enhancement 1
Addr
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
Register Name
FIL3 Coefficient 0
FIL3 Coefficient 1
FIL3 Coefficient 2
FIL3 Coefficient 3
EQ0-efficient 0
EQ0-efficient 1
EQ0-efficient 2
EQ0-efficient 3
EQ0-efficient 4
EQ0-efficient 5
R/W
D7
D6
F3AS1
F3BP1
D5
0
GN1[1:0]
R/W
R/W
R/W
D4
D3
D2
F3A1[7:0]
F3A1[13:8]
F3B1[7:0]
F3B1[13:8]
E0A1[7:0]
E0A1[15:8]
E0B1[7:0]
E0B1[13:8]
E0C1[7:0]
E0C1[15:8]
R/W
R/W
R/W
D1
D0
R/W
R/W
F3A1[13:0], F3B1[13-0]: FIL3 (Stereo Separation Emphasis Filter) Coefficient (14bit x 2)
Default: “0000H”
F3BP1: FIL3 (Stereo Separation Emphasis Filter) Bypass
0: ON
1: Bypass (default)
F3AS1: FIL3 (Stereo Separation Emphasis Filter) Select 1
0: LPF (default)
1: HPF
E0A1[15:0], E0B1[13:0], E0C1[15:0]: EQ (Gain Compensation Filter) Coefficient (14bit x 2 + 16bit x 1)
default: “2000H”
GN1[1:0]: Additional Gain Select 1
0: 0dB (default)
1: +12dB
2: +24dB
3: +24dB
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3D Enhancement 2
Addr
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Register Name
FIL3 Coefficient 0
FIL3 Coefficient 1
FIL3 Coefficient 2
FIL3 Coefficient 3
EQ0-efficient 0
EQ0-efficient 1
EQ0-efficient 2
EQ0-efficient 3
EQ0-efficient 4
EQ0-efficient 5
R/W
D7
D6
F3AS2
F3BP2
D5
0
GN2[1:0]
R/W
R/W
R/W
D4
D3
D2
F3A2[7:0]
F3A2[13:8]
F3B2[7:0]
F3B2[13:8]
E0A2[7:0]
E0A2[15:8]
E0B2[7:0]
E0B2[13:8]
E0C2[7:0]
E0C2[15:8]
R/W
R/W
R/W
D1
D0
R/W
R/W
F3A2[13:0], F3B2[13-0]: FIL3 (Stereo Separation Emphasis Filter) Coefficient (14bit x 2)
Default: “0000H”
F3BP2: FIL3 (Stereo Separation Emphasis Filter) Bypass
0: ON
1: Bypass (default)
F3AS2: FIL3 (Stereo Separation Emphasis Filter) Select 2
0: LPF (default)
1: HPF
E0A2[15:0], E0B2[13:0], E0C2[15:0]: EQ (Gain Compensation Filter) Coefficient (14bit x 2 + 16bit x 1)
default: “2000H”
GN2[1:0]: Additional Gain Select 2
0: 0dB (default)
1: +12dB
2: +24dB
3: +24dB
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[AK4141]
Equalizer 1
Addr
20H
21H
22H
Register Name
EQ Control 250Hz/100Hz
EQ Control 3.5kHz/1kHz
EQ Control 10kHz
R/W
Default
D7
EQ1
R/W
1
D6
D5
EQB1[3:0]
EQD1[3:0]
0
R/W
R/W
0
0
D4
D3
R/W
0
R/W
1
D4
D3
R/W
0
R/W
1
D2
D1
EQA1[3:0]
EQC1[3:0]
EQE1[3:0]
R/W
R/W
0
0
D0
R/W
0
EQA1[3:0]: Select the boost level of 100Hz
EQB1[3:0]: Select the boost level of 250Hz
EQC1[3:0]: Select the boost level of 1kHz
EQD1[3:0]: Select the boost level of 3.5kHz
EQE1[3:0]: Select the boost level of 10kHz
EQ1: Equalizer1 Enable
0: Disable
1: Enable (default)
Equalizer 2
Addr
23H
24H
25H
Register Name
EQ Control 250Hz/100Hz
EQ Control 3.5kHz/1kHz
EQ Contro2 10kHz
R/W
Default
D7
EQ2
R/W
1
D6
D5
EQB2[3:0]
EQD2[3:0]
0
R/W
R/W
0
0
D2
D1
EQA2[3:0]
EQC2[3:0]
EQE2[3:0]
R/W
R/W
0
0
D0
R/W
0
EQA2[3:0]: Select the boost level of 100Hz
EQB2[3:0]: Select the boost level of 250Hz
EQC2[3:0]: Select the boost level of 1kHz
EQD2[3:0]: Select the boost level of 3.5kHz
EQE2[3:0]: Select the boost level of 10kHz
EQ2: Equalizer2 Enable
0: Disable
1: Enable (default)
EQx1[3:0], EQx2[3:0]
Boost amount
0H
+12.0dB
1H
+10.5dB
2H
+9.0dB
3H
+7.5dB
:
:
8H
0dB
(default)
:
:
DH
7.5dB
EH
9.0dB
FH
10.5dB
Table 23. Boost amount of 5 Band Equalizer
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[AK4141]
ALC1
Addr
Register Name
D7
26H
Timer Select
0
R/W
Default
R/W
0
D6
D5
D4
WTM1[2:0]
R/W
0
R/W
0
D3
D2
D1
ZTM1[1:0]
R/W
0
R/W
0
D0
RFST1[1:0]
R/W
0
R/W
0
R/W
0
WTM1[2:0]: ALC1 Recovery Waiting Period
WTM1[2-0] bits set a period of recovery operation when no limiter operation occurs during ALC1 operation.
Default= “000” (128/fs).
WTM12
WTM11
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
ALC Recovery Operation Waiting Period
32kHz
44.1kHz
48kHz
0
128/fs
2.9ms
4.0ms
2.7ms
1
256/fs
5.8ms
8.0ms
5.3ms
0
512/fs
11.6ms
16.0ms
10.7ms
1
1024/fs
23.2ms
32.0ms
21.3ms
0
2048/fs
46.4ms
64.0ms
42.7ms
1
4096/fs
92.9ms
128.0ms
85.3ms
0
8192/fs
185.8ms
256.0ms
170.7ms
1
16384/fs
371.5ms
512.0ms
341.3ms
Table 24. ALC Recovery Operation Waiting Period
WTM10
(default)
ZTM1[1:0]: ALC1 Zero Crossing Timeout Period
At ALC1 recovery operation, the gain changes only when zero crossing or timeout. Default= “00” (128/fs).
ZTM11
ZTM10
0
0
1
1
0
1
0
1
ALC1 Zero Crossing Timeout Period
32kHz
44.1kHz
48kHz
2.9ms
128/fs
4.0ms
2.7ms
5.8ms
256/fs
8.0ms
5.3ms
11.6ms
512/fs
16.0ms
10.7ms
23.2ms
1024/fs
32.0ms
21.3ms
Table 25. ALC1 Zero Crossing Timeout Period
(default)
RFST1[1:0]: ALC1 Fast Recovery Speed
Default: “00”(x 4 speed)
RFST11 bit
RFST10 bit
Fast Recovery Speed
0
0
x4
(default)
0
1
x8
1
0
x 16
1
1
N/A
Table 26. ALC1 Fast Recovery Speed (N/A: NOT available)
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Addr
27H
Register Name
ALC Mode Control 1
R/W
Default
D7
ALC1
R/W
0
D6
ZELMN1
R/W
0
D5
D4
RGAIN1[1:0]
R/W
R/W
0
0
D3
D2
LMAT1[1:0]
R/W
R/W
0
0
D1
D0
LMTH1[1:0]
R/W
R/W
0
0
LMTH1[1:0]: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
Default: “00”
LMTH11 LMTH10
Limiter Detection Level
Recovery Waiting Counter Reset Level
0
0
ALC Output  2.5dBFS
2.5dBFS > ALC Output  4.1dBFS
0
1
ALC Output  4.1dBFS
4.1dBFS > ALC Output  6.0dBFS
1
0
ALC Output  6.0dBFS
6.0dBFS > ALC Output  8.5dBFS
1
1
ALC Output  8.5dBFS
8.5dBFS > ALC Output  12dBFS
Table 27. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
(default)
LMAT1[1:0]: ALC1 Limiter ATT Step
Default: “00”
ALC1 Limiter ATT Step
LMAT11
LMAT10
0
0
1
1
0
1
0
1
ALC1 Output ALC1 Output
 LMTH
 FS
ALC1 Output
 FS + 6dB
1
1
2
2
2
4
1
2
Table 28. ALC1 Limiter ATT Step
ALC1 Output
 FS + 12dB
1
2
4
4
1
2
8
8
(default)
RGAIN1[1:0]: ALC1 Recovery GAIN Step
Default: “00”
RGAIN11
0
0
1
1
RGAIN10
GAIN STEP
0
1 step
0.375dB
1
2 step
0.750dB
0
3 step
1.125dB
1
4 step
1.500dB
Table 29. ALC1 Recovery GAIN Step
(default)
ZELMN1: Enable zero crossing detection at ALC1 Limiter operation
0: Enable (default)
1: Disable
ALC1: ALC1 Enable
0: ALC Disable (default)
1: ALC Enable
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[AK4141]
Addr
28H
Register Name
ALC Mode Control 2
R/W
Default
D7
D6
D5
R/W
1
R/W
0
R/W
0
D4
D3
IREF1[7:0]
R/W
R/W
1
0
D2
D1
D0
R/W
0
R/W
0
R/W
1
IREF1[7-0]: Reference value at ALC1 Recovery Operation
0.375dB step, 242 Level. Default: “91H” (0.0dB)
IREF1[7-0]bits
GAIN(0dB)
Step
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
C5H
+19.5
0.375dB
:
:
92H
+0.375
91H
0.0 (default)
90H
-0.375
:
:
02H
-53.625
01H
-54.0
00H
MUTE
Table 30. Reference value at ALC1 Recovery Operation
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[AK4141]
ALC2
Addr
29H
Register Name
Timer Select
R/W
Default
D7
0
R/W
0
D6
R/W
0
D5
WTM2[2:0]
R/W
0
D4
R/W
0
D3
D2
ZTM2[1:0]
R/W
R/W
0
0
D1
D0
RFST2[1:0]
R/W
R/W
0
0
WTM2[2:0]: ALC2 Recovery Waiting Period
WTM2[2-0] bits set a period of recovery operation when any limiter operation does not occur during ALC2
operation. Default= “000” (128/fs).
ALC Recovery Operation Waiting Period
32kHz
44.1kHz
48kHz
128/fs
2.9ms
4.0ms
2.7ms
256/fs
5.8ms
8.0ms
5.3ms
512/fs
11.6ms
16.0ms
10.7ms
1024/fs
23.2ms
32.0ms
21.3ms
2048/fs
46.4ms
64.0ms
42.7ms
4096/fs
92.9ms
128.0ms
85.3ms
8192/fs
185.8ms
256.0ms
170.7ms
16384/fs
371.5ms
512.0ms
341.3ms
Table 31. ALC2 Recovery Waiting Period
WTM22
WTM21
WTM20
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(default)
ZTM2[1:0]: ALC2 Zero Crossing Timeout Period
At ALC2 recovery operation, the gain changes only when zero crossing or timeout. Default= “00” (128/fs).
ZTM21
ZTM20
0
0
1
1
0
1
0
1
ALC2 Zero Crossing Timeout Period
32kHz
44.1kHz
48kHz
2.9ms
128/fs
4.0ms
2.7ms
5.8ms
256/fs
8.0ms
5.3ms
11.6ms
512/fs
16.0ms
10.7ms
23.2ms
1024/fs
32.0ms
21.3ms
Table 32. ALC2 Zero Crossing Timeout Period
(default)
RFST2[1:0]: ALC2 Fast Recovery Speed
Default: “00”(x 4 speed)
RFST21 bit
RFST20 bit
Fast Recovery Speed
0
0
x4
(default)
0
1
x8
1
0
x 16
1
1
N/A
Table 33. ALC2 Fast Recovery Speed (N/A: Not available)
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[AK4141]
Addr
2AH
Register Name
ALC Mode Control 1
R/W
Default
D7
ALC2
R/W
0
D6
ZELMN2
R/W
0
D5
D4
RGAIN2[1:0]
R/W
R/W
0
0
D3
D2
LMAT2[1:0]
R/W
R/W
0
0
D1
D0
LMTH2[1:0]
R/W
R/W
0
0
LMTH2[1:0]: ALC2 Limiter Detection Level / Recovery Waiting Counter Reset Level
Default: “00”
LMTH21
0
0
1
1
LMTH20
Limiter Detection Level
Recovery Waiting Counter Reset Level
0
ALC Output  2.5dBFS
2.5dBFS > ALC Output  4.1dBFS (default)
1
ALC Output  4.1dBFS
4.1dBFS > ALC Output  6.0dBFS
0
ALC Output  6.0dBFS
6.0dBFS > ALC Output  8.5dBFS
1
ALC Output  8.5dBFS
8.5dBFS > ALC Output  12dBFS
Table 34. ALC2 Limiter Detection Level / Recovery Waiting Counter Reset Level
LMAT2[1:0]: ALC2 Limiter ATT Step
Default: “00”
ALC2 Limiter ATT Step
LMAT21
LMAT20
0
0
1
1
0
1
0
1
ALC2 Output ALC2 Output
 LMTH
 LMTH
ALC2 Output
 LMTH
1
1
2
2
2
4
1
2
Table 35. ALC2 Limiter ATT Step
ALC2 Output
 LMTH
1
2
4
4
1
2
8
8
(default)
RGAIN21[1:0]: ALC2 Recovery GAIN Step
Default: “00”
RGAIN21
0
0
1
1
RGAIN20
GAIN STEP
0
1 step
0.375dB
1
2 step
0.750dB
0
3 step
1.125dB
1
4 step
1.500dB
Table 36. ALC2 Recovery GAIN Step
(default)
ZELMN2: Enable zero crossing detection at ALC2 Limiter operation
0: Enable (default)
1: Disable
ALC2: ALC2 Enable
0: ALC Disable (default)
1: ALC Enable
MS0952-E-03
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[AK4141]
Addr
2BH
Register Name
ALC Mode Control 2
R/W
Default
D7
D6
D5
R/W
1
R/W
0
R/W
0
D4
D3
IREF2[7:0]
R/W
R/W
1
0
D2
D1
D0
R/W
0
R/W
0
R/W
1
IREF2[7:0]: Reference value at ALC2 Recovery Operation
0.375dB step, 242 Level. Default: “91H” (0.0dB)
IREF2[7:0]bits
GAIN(0dB)
Step
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
C5H
+19.5
0.375dB
:
:
92H
+0.375
91H
0.0 (default)
90H
-0.375
:
:
2H
-53.625
1H
-54.0
0H
MUTE
Table 37. Reference value at ALC2 Recovery Operation
MS0952-E-03
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[AK4141]
Balance
Addr
2CH
Register Name
Balance Mode Control
R/W
Default
D7
D6
D5
R/W
0
R/W
0
R/W
0
D7
D6
D5
R/W
0
R/W
0
R/W
0
D4
0
R/W
0
D3
D2
D1
R/W
0
R/W
0
R/W
0
D0
BMODE
R/W
1
D2
D1
D0
R/W
0
R/W
0
R/W
0
BMODE: Balance Mode
0: Linear step
1: Log step (default)
Addr
2DH
2EH
Register Name
Balance 1 Control
Balance 2 Control
R/W
Default
D4
D3
BAL1[7:0]
BAL2[7:0]
R/W
R/W
0
0
BAL1[7:0]: Balance 1 Control
BAL2[7:0]: Balance 2 Control
Linear Mode
7F: L=mute, R=100%
7E: L=0.8%, R=100%
…
01: L=99.2%, R=100%
00: L=100%, R=100% (default)
FF: L=100%, R=99.2%
…
82: L=100%, R=0.8%
81: L=100%, R=Mute
Log Mode
7F: L=mute, R=0dB
7E: L=-126dB, R=0dB
…
01: L=-1dB, R=0dB
00: L=0dB, R=0dB (default)
FF: L=0dB, R=-1dB
…
81: L=0dB, R=-127dB
80: L=0dB, R=-Mute
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[AK4141]
Main Volume
Addr
2FH
30H
Register Name
Main Volume 1 Control
Main Volume 2 Control
R/W
Default
D7
D6
D5
R/W
0
R/W
0
R/W
0
D4
D3
VOL1[7:0]
VOL2[7:0]
R/W
R/W
1
1
D2
D1
D0
R/W
0
R/W
0
R/W
0
VOL1[7:0]: Main Volume 1 Control
VOL2[7:0]: Main Volume 2 Control
VOL1[7:0], VOL2[7:0]
Volume Gain
+12dB
+11.5dB
+11.0dB
:
+0.5dB
0dB
(default)
-0.5dB
:
FEH
-115dB
FFH
MUTE (-)
Table 38. Main Volume Control 1/2
00H
01H
02H
:
17H
18H
19H
MS0952-E-03
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[AK4141]
DIT C-bit control
Addr
31H
Register Name
Channel Status 1
R/W
Default
D7
0
R/W
0
D6
D5
D4
CS[27:24]
R/W
R/W
0
1
R/W
0
D3
R/W
0
D2
CS3
R/W
0
D1
CS2
R/W
1
D0
CS1
R/W
0
CS1
0: Audio (default)
1: Non-Audio
CS2
0: Copyright
1: Non-Copyright (default)
CS3
0: No Pre-emphasis (default)
1: 50/15µsec Pre-emphasis
CS24, 25, 26, 27: Sampling Frequency
0010: 22.05kHz
0000: 44.1kHz
0001: 88.2kHz
0011: 176.4kHz
0110: 24kHz
0100: 48kHz (default)
0101: 96kHz
0111: 192kHz
1100: 32kHz
1000: Sampling frequency is not indicated
1001: 768kHz
Others: reserved
Addr
32H
Register Name
Channel Status 2
R/W
Default
D7
D6
D5
D4
R/W
0
R/W
0
0
R/W
0
R/W
0
D3
D2
CS[41:40]
R/W
R/W
0
0
D1
D0
CS[29:28]
R/W
R/W
0
0
CS28, 29: Clock Accuracy
00: Standard mode (default)
01: Variable pitch mode
10: High accuracy mode
11: Reserved
CS40, 41: CGMS-A
00: Copying is permitted without restriction (default)
01: Copying not be used
10: One generation of copies may be used
11: No copying is permitted
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[AK4141]
Addr
33H
Register Name
Channel Status 3
R/W
Default
D7
D6
D5
R/W
0
R/W
0
R/W
0
D4
D3
CS[15:8]
R/W
R/W
0
0
D2
D1
D0
R/W
0
R/W
0
R/W
0
D2
CS[35:33]
R/W
0
D1
D0
CS32
R/W
0
CS8-15: Category code (refer IEC60958-3.)
00110000: Digital Audio Broadcast Reception in Europe (default)
Addr
34H
Register Name
Channel Status 4
R/W
Default
D7
R/W
0
D6
D5
CS[39:36]
R/W
R/W
0
0
D4
D3
R/W
0
R/W
0
R/W
0
CS32: Maximum word length
0: Maximum sample word length is 20 bits (default)
1: Maximum sample word length is 24 bits
CS33, 34, 35: Word length
If the bit32 (CS32 bit) = “1”
000: Word length not indicated (default)
100: 20 bit
010: 22 bit
001: 23 bit
101: 24 bit
011: 21 bit
If the bit32 (CS32 bit) = “0”
000: Word length not indicated (default)
100: 16 bit
010: 18 bit
001: 19 bit
101: 20 bit
011: 17 bit
CS36, 37, 38, 39:Original Sampling Frequency
1111: 44.1kHz
1110: 88.2kHz
1101: 22.05kHz
1100: 176.4kHz
1011: 48kHz
1010: 96kHz
1001: 24kHz
1000: 192kHz
0111: Reserved
0110: 8kHz
0101: 11.025kHz
0100: 12kHz
0011: 32kHz
0010: Reserved
0001: 16kHz
0000: Original Sampling frequency is not indicated (default)
All other C bits are fixed to “0”.
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[AK4141]
Decoder
Addr
40H
Register Name
SIF AGC Manual Control
R/W
Default
D7
AGOFF
R/W
0
D6
0
R/W
0
D5
D4
R/W
0
R/W
0
D3
D2
IFVOL[5:0]
R/W
R/W
0
0
D1
D0
R/W
0
R/W
0
AGOFF: AGC disable
AGOFF
0
1
AGC status
Enabled
Disabled
Table 39. AGC disable
(default)
IFVOL[5:0]: SIF volume control
These bits are ignored when AGOFF bit = “0”. PGA-Gain = (52+IFVOL*2)/(75-IFVOL). The total gain of the system
is the sum of IFVOL bits setting and GSEL1/GSEL2 bits setting.
IFVOL[5:0]
SIF Gain
00H
-3.18dB
01H
-2.74dB
02H
-2.30dB
:
:
2DH
+21.89dB
2EH
+22.63dB
2FH
+23.42dB
Table 40. SIF volume control
MS0952-E-03
(default)
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[AK4141]
Addr
41H
Register Name
System Select
D7
D6
0
D5
D4
ASD
D3
D2
D1
SYS[3:0]
D0
R/W
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
ASD
Enable automatic system detection. ASD is initiated when a 1 is written to this bit. Automatically returns to 0 when
ASD is complete.
ASD
00H
01H
Automatic system detection
Disabled
Enabled
Table 41. Automatic system detection
(default)
SYS[3:0]
TV system select. This register is overridden by automatic system detection when it is initiated. It Becomes read-only
while ASD is enabled, but returns to R/W when ASD is completed. Note that if ASD cannot identify the system,
SYS[3:0] will be set to 0xF and the decoder will be set to the FM-Stereo (Radio-Europe) mode.
SYS[3:0]
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH-0EH
0FH
TV System
Sound Carrier Positions Sound Modulation
B/G
5.5/5.7421875
FM-Stereo (A2)
B/G
5.5/5.85
FM-Mono/NICAM
L
6.5/5.85
AM-Mono/NICAM
I
6.0/6.552
FM-Mono/NICAM
D/K
6.5/6.2578125
FM-Stereo (A2, D/K1)
D/K
6.5/6.7421875
FM-Stereo (A2, D/K2)
D/K
6.5/5.7421875
FM-Stereo (A2, D/K3)
D/K
6.5/5.85
FM-Mono/NICAM (D/K, NICAM)
M/N
4.5/4.724212
FM-Stereo (A2)
M/N
4.5
FM-Stereo (EIA-J)
M/N
4.5
N/A
FM-Radio
4.5
FM-Stereo (Radio - US)
FM-Radio
4.5
FM-Stereo (Radio - Europe)
FM-Radio
4.5
Unknown/FM-Stereo (Radio - Europe)
Table 42. TV system select (N/A: NOT available) (N/A: Not available)
MS0952-E-03
(default)
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[AK4141]
Addr
42H
Register Name
Standard Select
R/W
Default
D7
D6
0
R/W
0
R/W
0
D5
R/W
0
D4
D3
ID[1:0]
R/W
R/W
0
0
D2
R/W
1
D1
STD[2:0]
R/W
1
D0
R/W
1
ID[1:0]
ID detector mode. EIA-J and A2 may carry identification tones used to identify the transmitted audio mode: mono,
stereo, or bilingual. This word determines the standard that the ID detector assumes the received audio to be in. A2
has two variations of the identification tone, A2 and A2M. Normally, the contents of this word are updated
automatically to reflect the standard chosen in the system select (SYS[3:0]) register, but this word may also be
overwritten manually.
ID Detector Mode
EIAJ
A2
A2M
A2M
Table 43. ID Detector Mode
ID[1:0]
00H
01H
02H
03H
(default)
STD[2:0]
Decoding standard select. Normally, the contents of this word are updated automatically to reflect the standard
chosen in the system select (SYS[3:0]) register, but this word may also be overwritten manually.
Decoding Standard
reserved
reserved
reserved
EIA-J
A2
FM Radio (75µs)
FM Radio (50µs)
NICAM
Table 44. Decoding Standard
STD[2:0]
00H
01H
02H
03H
04H
05H
06H
07H
Addr
43H
Register Name
Decoder Sample Rate
R/W
Default
(default)
D7
D6
D5
D4
D3
D2
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DECFS[1:0]
00H
01H
02H
03H
D1
D0
DECFS[1:0]
R/W
R/W
0
0
Decoder Sample Rate
48kHz (default)
32kHz
44.1kHz
reserved
Table 45. Sample Rate
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[AK4141]
Addr
44H
Register Name
FM/AM Demod Control
R/W
Default
D7
0
R/W
0
D6
D5
D4
DM1LP[2] DM1DV[2]
R/W
0
R/W
0
D3
DM1LP[1:0]
R/W
0
D2
DM1MD
R/W
0
R/W
0
D1
D0
DM1DV[1:0]
R/W
0
R/W
0
DM1LP[2:0]
Demod 1 filter select. This word is ignored while ASD is running.
DM1LP[2:0]
00H
01H
02H
03H
04H
05H
06H
07H
Demod 1 Filter
50 kHz lowpass
100 kHz lowpass
384 kHz lowpass
540kHz lowpass
200kHz lowpass
Reserved
Reserved
Reserved
Table 46. Demod 1 Filter
(default)
DM1MD
Demod 1 FM/AM mode. This bit is ignored while ASD is running.
DM1MD
00H
01H
Demod 1 FM/AM Mode
FM
AM
Table 47. Automatic system detection
(default)
DM1DV [2:0]
Demod 1 maximum FM deviation. This word is ignored while ASD is running
DM1DV [2:0]
00H
01H
02H
03H
04H
05H
06H
07H
Demod 1 Maximum FM Deviation
50 kHz
100 kHz
384 kHz
540 kHz
200 kHz
Reserved
Reserved
Reserved
Table 48. Demod 1 Maximum FM Deviation
MS0952-E-03
(default)
2013/12
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[AK4141]
Addr
45H
46H
Register Name
Dem1 Carrier Freq Ctrl 1
Dem1 Carrier Freq Ctrl 0
R/W
Default
D7
D6
D5
R/W
0
R/W
0
R/W
0
D4
D3
DM1F[15:8]
DM1F[7:0]
R/W
R/W
0
0
D2
D1
D0
R/W
0
R/W
0
R/W
0
DM1F[15:0]
Demod 1 carrier frequency. This word is ignored while ASD is running. This value represents the frequency shift
required to bring the carrier to 0Hz, so it typically has a negative value. A positive value shifts the carrier up.
DM1F = -Fc/Fs x 216 (in 2’s complement)
Fc = Nominal frequency of carrier to be demodulated (in Hz)
Fs = Input sample rate (in Hz), see the Sample Rate Register table (Table 45) for the input sample rate that
corresponds to the selected output sample rate. The Table 49 represents typical values, which is not meant to be
restrictive. Any 16-bit value may be used as needed.
Standard Values for Fc
4.5MHz
5.5MHz
6.0MHz
6.5MHz
DM1F[15:0]
fs=48kHz/32kHz
0xC180
0xB39C
0xACAB
0xA5B9
Table 49. Demod 1 carrier frequency
MS0952-E-03
fs=44.1kHz
0xBBF9
0xACDB
0xA54C
0x9DBD
2013/12
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[AK4141]
Addr
Register Name
47H
FM/DQPSK Dem Ctrl
D7
D6
D5
D4
0
R/W
Default
R/W
0
R/W
0
D3
DM2LP[1:0]
R/W
0
R/W
0
D2
D1
DM2MD
R/W
0
R/W
0
D0
0
R/W
0
R/W
0
DM2MD
Demod 2 FM/DQPSK mode. This bit is ignored while ASD is running.
DM2MD
00H
01H
Demod 2 FM/DQPSK Mode
FM
DQPSK
Table 50. Automatic system detection
(default)
DM2LP[1:0]
Demod 2 filter select. This word is ignored while ASD is running.
DM2LP[1:0]
00H
01H
02H
03H
Addr
48H
49H
Register Name
Dem2 Carrier Freq Ctrl 1
Dem2 Carrier Freq Ctrl 0
R/W
Default
Demod 2 Filter
50 kHz lowpass
728kbit/s Root Raised Cosine 40% rolloff lowpass
728kbit/s Root Raised Cosine 100% rolloff lowpass
Reserved
Table 51. Demod 2 Filter
D7
D6
D5
R/W
0
R/W
0
R/W
0
D4
D3
DM2F[15:8]
DM2F[7:0]
R/W
R/W
0
0
(default)
D2
D1
D0
R/W
0
R/W
0
R/W
0
DM2F[15:0]
Demod 2 carrier frequency. This word is ignored while ASD is running. This value represents the frequency shift
required to bring the carrier to 0 Hz, so it typically has a negative value. A positive value shifts the carrier up.
DM2F = -Fc/Fs x 216 (in 2’s complement)
Fc = Nominal frequency of carrier to be demodulated (in Hz)
Fs = Input sample rate (in Hz), see the Sample Rate Register table for the input sample rate that corresponds to the
selected output sample rate. The following table represents typical values, and is not meant to be restrictive. Any
16-bit value may be used as needed.
Standard Values for Fc
4.724212MHz
5.7421875MHz
5.85MHz
6.2578125MHz
6.552MHz
6.7421875MHz
DM2F[15:0]
fs=48kHz/32kHz
0xBE63
0xB03F
0xAEC0
0xA916
0xA500
0xA25C
Table 52. Demod 2 carrier frequency
MS0952-E-03
fs=44.1kHz
0xB895
0xA932
0xA791
0xA166
0x9CF4
0x9A14
(default)
2013/12
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[AK4141]
Addr
Register Name
D7
D6
D5
D4
4AH
Decoder Output Control
LOR
ROL
LRSM
AUTO
R/W
0
R/W
0
R/W
0
R/W
1
R/W
Default
D3
D2
LSEL[1:0]
R/W
0
R/W
1
D1
D0
RSEL[1:0]
R/W
0
R/W
1
AUTO
Automatic audio output select enable. When it is enabled, the automatic output select monitors the signal conditions
and outputs the appropriate audio signals continuously. When disabled, and in dual sound carrier mode, the
applicable demodulator output is muted if the quality of the signal is too poor.
AUTO
00H
01H
Automatic audio output
Disabled
Enabled
Table 53. Automatic audio output
(default)
LSEL[1:0]
Left output select. When automatic audio output select is disabled, the left output will output a signal according to the
value of this word. When AUTO is enabled, this word is used to determine the preferred output as shown in the Table
55.
Left Preferred Outputs for AUTO = “0”
EIA-J
A2
NICAM
Mono
Mono
AMono
L
L
L
A
A
A
B
B
B
Table 54. Left Output for AUTO= “0”
LSEL[1:0]
00H
01H
02H
03H
LSEL[1:0]
00H
01H
02H
03H
FM Radio
Mono
L
Mono
L-R
Left Preferred Outputs for AUTO = “1”
(in poor signal conditions, the output in parentheses is automatically selected)
EIA-J, A2
(Stereo or
EIAJ, A2
EIA-J, A2
NICAM
NICAM
Unknown),
(Mono)
(Dual Mono)
(Stereo)
(Mono/ Data)
FM Radio
L
(Mono)
Mono
A
L
(AMono)
B(A)
Table 55. Left Output for AUTO= “1”
MS0952-E-03
A (AMono)
(default)
NICAM
(Dual Mono)
A (AMono)
B (AMono)
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[AK4141]
RSEL[1:0]
Right output select. When automatic audio output select is disabled, the right output will output a signal according to
the value of this word. When AUTO is enabled, this word is used to determine the preferred output as shown in the
Table 70.
RSEL[1:0]
00H
01H
02H
03H
RSEL[1:0]
00H
01H
02H
03H
EIA-J
Mono
R
A
B
Right Outputs for AUTO = “0”
A2
NICAM
Mono
AMono
R
R
A
A
B
B
Table 56. Right Output for AUTO= “0”
FM Radio
Mono
R
Mono
L-R
Right Outputs for AUTO = “1”
(in poor signal conditions, the output in parentheses is automatically selected)
EIA-J, A2
(Stereo or
EIAJ, A2
EIA-J, A2
NICAM
NICAM
Unknown),
(Mono)
(Dual Mono)
(Stereo)
(Mono/ Data)
FM Radio
R(Mono)
Mono
A
R (AMono)
(default)
NICAM
(Dual Mono)
A (AMono)
B(A)
Table 57. Right Output for AUTO= “1”
A (AMono)
B (AMono)
LRSM
Left and right summing mode. Provides capability to sum the left and right channels.
LRSM
00H
01H
Left / Right Outputs
Standard Mode
Left and right outputs are unchanged.
Summing Mode
L = R = (LStndrd + RStndrd) / 2
LStndrd and RStndrd are defined as what the left and right
outputs would be if LRSM were 0(inactive)
Table 58. LSEL Definition
(default)
ROL
Right channel outputs left channel audio. Provides capability for the right channel to output the left channel audio.
ROL
00H
01H
RSEL Definition
Standard Definition
(LSEL defined according to Table 54, Table 55)
Left Channel Definition
(LSEL defined according to Table 56, Table 57)
Table 59. LSEL Definition
MS0952-E-03
(default)
2013/12
- 63 -
[AK4141]
LOR
Left channel outputs right channel audio. Provides capability for the left channel to output the right channel audio.
LOR
00H
LSEL Definition
Standard Definition
(LSEL defined according to Table 56, Table 57)
Right Channel Definition
(LSEL defined according to Table 54, Table 55)
Table 60. LSEL Definition
01H
Addr
4BH
Register Name
Audio Mode Detect
R/W
Default
D7
D6
D5
Default
D4
D3
D2
RD
0
RD
0
RD
0
0
RD
0
RD
0
RD
0
D1
D0
AMOD[1:0]
RD
RD
0
0
AMOD[1:0]
Audio mode detected. Some of the audio standards include an identification signal used to identify whether a mono,
stereo, or bilingual signal is broadcasted. This word contains the decoded result.
Value
00H
01H
02H
03H
Addr
4CH
EIA-J
A2
NICAM
Mono
Mono
N/A
Stereo
Stereo
N/A
Bilingual
Bilingual
N/A
N/A
N/A
N/A
Table 61. Detected Audio mode (N/A: Not available)
Register Name
Pilot PLL Lock
R/W
Default
D7
D6
D5
RD
0
RD
0
RD
0
D4
0
RD
0
FM Radio
N/A
N/A
N/A
N/A
D3
D2
D1
RD
0
RD
0
RD
0
D0
LOCK
RD
0
LOCK
Pilot PLL lock status.
LOCK
00H
01H
Pilot PLL lock status
PLL unlocked
PLL locked
Table 62. Pilot PLL lock status
MS0952-E-03
(default)
2013/12
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[AK4141]
Addr
4DH
4EH
Register Name
NICAM Error Rate 1
NICAM Error Rate 0
R/W
Default
D7
D6
D5
RD
0
RD
0
RD
0
D4
D3
NERR[15:8]
NERR[7:0]
RD
RD
0
0
D2
D1
D0
RD
0
RD
0
RD
0
NERR[15:0]
NICAM error rate high/low byte. Minimum achievable value is 0x003F. When reading these registers, always read the
high byte first. The low byte is only updated when the high byte is read. This ensures that the values read from the two
registers come from the same 16-bit word.
Addr
4FH
50H
Register Name
NICAM Control Bits 1
NICAM Control Bits 0
R/W
Default
D7
D6
D5
D4
D3
NIAD[10:3]
RD
0
NIAD[2:0]
RD
0
RD
0
RD
0
RD
0
D2
D1
D0
NICT[4:0]
RD
0
RD
0
RD
0
NIAD[10:0]
NICAM additional data bits reserved for future use.
NICT[4:0]
NICAM control bits high byte. When reading these registers always read the high byte first. The low byte is only
updated when the high byte is read. This ensures that the values read from the two registers come from the same
16-bit word.
NICT4
0
Definition
The analog sound signal is not carrying the same program as the
digital signal.
The analog sound signal is carrying the same program as the digital
stereo signal (or mono signal in M1 frames.)
Table 63. NICAM control bits 1
1
Application Control Information
NICT 3
NICT 2
NICT 1
0
0
0
0
0
1
0
1
1
1
1
1
0
0
1
1
Contents of 704-bit sound/data block
Stereo signal comprising alternate A-channel and
B-channel samples.
One mono signal and one 352 kbit/s transparent
1
data channel transmitted in alternate frames.
Two independent mono sound signals transmitted in
0
alternate frames (designated M1 and M2.)
1
One 704 kbit/s transparent data channel.
0
Undefined.
1
Undefined.
0
Undefined.
1
Undefined.
Table 64. NICAM control bits 2
0
NICT0 – Frame Flag Bit – Value is 0 for 8 consecutive frames and 1 for next eight frames.
MS0952-E-03
2013/12
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[AK4141]
Addr
51H
Register Name
SIF AGC Control
R/W
Default
D7
R/W
0
D6
D5
AGAT[3:0]
R/W
R/W
0
0
D4
D3
R/W
0
R/W
0
D2
D1
AGDC[3:0]
R/W
R/W
0
0
D0
R/W
0
AGAT[3:0]: AGC attack time control
These bits set the attack time of the Automatic Gain Control.
AGAT[3:0]
0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Attack Time (ms)
0.055
0.075
0.11
0.15
0.22
0.30
0.45
0.9
1.2
1.8
2.4
7.1
14.2
28.5
56.9
113.8
Table 65. AGC attack time
(default)
AGDC [3:0]: AGC decay time control
These bits set the decay time of the Automatic Gain Control.
AGDC [3:0]
0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Decay Time (ms)
0.9
1.2
1.8
2.4
3.6
4.8
7.1
14.2
19.0
28.5
38.0
113.8
227.6
455
910
1820
Table 66. AGC decay time
MS0952-E-03
(default)
2013/12
- 66 -
[AK4141]
Addr
52H
Register Name
AGC Control for AM
R/W
Default
D7
D6
D5
AMAT[3:0]
R/W
R/W
1
1
R/W
0
D4
D3
R/W
1
R/W
0
D2
D1
AMDC[3:0]
R/W
R/W
1
1
D0
R/W
1
AMAT[3:0]: AGC attack time control AM
These bits set the attack time of the Automatic Gain Control when the input signal is AM.
AMAT[3:0]
Attack Time (ms)
0H
0.11
1H
0.15
2H
0.22
3H
0.30
4H
0.44
5H
0.59
6H
0.89
7H
1.8
8H
2.4
9H
3.6
AH
4.7
BH
14.2
CH
28.4
DH
56.9
EH
113.8
FH
227.6
Table 67. AGC attack time AM
(default)
AMDC [3:0]: AGC decay time control AM
These bits set the decay time of the Automatic Gain Control when the input signal is AM. The decay time should
always be much slower than the attack time. Best results are obtained if the same value is written to both the attack
and decay registers.
AMDC [3:0]
0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Decay Time (ms)
1.8
2.4
3.6
4.7
7.1
9.5
14.2
28.4
37.9
56.9
75.9
227.6
455.1
910.2
1820
3640
Table 68. AGC decay time AM
MS0952-E-03
(default)
2013/12
- 67 -
[AK4141]
Addr
53H
Register Name
Status
R/W
Default
D7
ASDC
RD
0
D6
BI
RD
0
D5
IMONO
RD
0
D4
MONO
RD
0
D3
D2
SNDST[1:0]
RD
RD
0
0
D1
C2DET
RD
0
D0
C1DET
RD
0
ASDC:
When high, this bit indicates that the Automatic Standard Detection algorithm has completed.
BI:
When high, this bit indicates that a bilingual mode has been detected. It is high under any of the following conditions.
1) SYS[3:0] indicates either EIAJ or A2 and the ID signal (AMOD[1:0]) indicates bilingual (0x2).
2) SYS[3:0] indicates NICAM, NICAM reception is good, and NICT[2:1] indicate bilingual (0x2.)
IMONO
When high, this bit indicates independent mono sound (NICAM only). This bit is set to high when the NICT value is
0xa, 0x2, 0x1 and 0x0.
MONO:
When high, this bit indicates that the received signal has been identified as a stereo signal. When low, this bit
indicates that stereo is not available. It is high under any of the following conditions.
1) SYS[2:0] indicates either EIAJ or A2 and the ID signal (AMOD[1:0]) indicates stereo (0x1.)
2) SYS[2:0] indicates NICAM, NICAM reception is good, and NICT[2:1] indicate stereo (0x0.)
SNDST[1:0]:
These bits reflect the sound status of the applicable sound standard.
SNDST[1:0]
00H
01H
02H
03H
Status
Analog Sound Standard (AM/FM) active
Bad reception condition of analog sound
Digital Sound (NICAM) available
Bad reception condition of digital sound
Table 69. Sound Status
C2DET:
When high, this bit indicates that a valid secondary carrier (2nd A2 carrier) has been detected.
C1DET:
When high, this bit indicates that a valid primary carrier has been detected.
MS0952-E-03
2013/12
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[AK4141]
Addr
54H
Register Name
Status Pin Control
R/W
Default
D7
D6
R/W
0
R/W
0
D5
0
R/W
0
D4
D3
R/W
0
R/W
0
D2
ASTAT
R/W
0
D1
STAP
R/W
0
D0
STAE
R/W
0
ASTAT
Audio Output Result drives status change. Enabling this bit causes a change in the audio output result register (either
LRSL or RRSL) to make the INT pin active (if the INT pin is enabled with STAE.) Reading the status register clears
the INT pin.
ASTAT
0
1
Status Change Output (only active when STAE = 1)
LRSL or RRSL change does not affect INT pin.
LRSL or RRSL change makes INT pin active.
Table 70. Status Change Output
(default)
STAP
Status change output polarity (INT pin polarity)
STAP
0
1
Status Change Output Polarity
Active high
Active low
Table 71. Status Change Output Polarity
(default)
STAE
Status change output enable. The INT pin is enabled or disabled by this bit. When enabled, the INT pin indicates any
change in the status register (64H). Reading the status register clears the INT pin.
STAE
0
1
Status Change Output
Disabled
Enabled
Table 72. Status Change Output
MS0952-E-03
(default)
2013/12
- 69 -
[AK4141]
Addr
55H
Register Name
A/D headroom
R/W
Default
D7
D6
R/W
0
R/W
0
D5
0
R/W
0
D4
D3
D2
R/W
0
R/W
0
R/W
1
D1
HDRM[2:0]
R/W
0
D0
R/W
1
HDRM[2:0]
These bits set the A/D headroom for the Automatic Gain Control to control the input signal to.
HDRM[2:0]
0H
1H
2H
3H
4H
5H
6H
7H
Addr
56H
Register Name
AGC Freeze
R/W
Default
A/D Headroom (dBFS)
-24
-21
-18
-15
-12
-9
-6
-3
Table 73. A/D Headroom
D7
D6
D5
R/W
0
R/W
0
R/W
0
D4
0
R/W
0
(default)
D3
D2
D1
R/W
0
R/W
0
R/W
0
D0
AGFRZ
R/W
0
AGFRZ
AGC Freeze. Freezes the current value of the AGC feedback.
AGFRZ
0
1
AGC Feedback State
Running
Frozen
Table 74. AGC Feedback State
MS0952-E-03
(default)
2013/12
- 70 -
[AK4141]
Addr
57H
Register Name
Stereo Carrier Search Ctrl
R/W
Default
D7
D6
D5
D4
R/W
0
R/W
0
0
R/W
0
R/W
0
D3
D2
CHMD[1:0]
R/W
R/W
0
0
D1
D0
SREN[1:0]
R/W
R/W
0
0
CHMD[1:0]
Stereo search system change mode.
CHMD[1:0]
0H
1H
2H
3H
Stereo Search System Change Mode
SYS[2:0] does not change automatically.
SYS[2:0] changes when the Stereo Carrier Result Register is read
after a stereo carrier is detected.
SYS[2:0] changes automatically when a stereo carrier is detected.
SYS[2:0] changes automatically when a stereo carrier is detected.
Table 75. Stereo Search System Change Mode
(default)
SREN[1:0]
Stereo search enable. Whenever the stereo carrier search is enabled (either for one-time search or continuous search),
the ASTAT output bit will indicate a status change when the SRCMP bit in the Stereo Carrier Search Result register
changes from “0” to “1”, in addition to when the Status register changes.
SREN[1:0]
0H
1H
2H
3H
Stereo Search
Disabled
One-time Search Enabled
(search disabled and SREN[1:0] returns to 0x0 after stereo carrier detected)
Continuous Search Enabled
(search begins again if stereo carrier is lost after initial detection)
Continuous Search Enabled
(search begins again if stereo carrier is lost after initial detection)
Table 76. Stereo Search
MS0952-E-03
(default)
2013/12
- 71 -
[AK4141]
Addr
58H
Register Name
Stereo Carrier Search Result
R/W
Default
D7
0
RD
0
D6
SRIND
RD
0
D5
SRCMP
RD
0
D4
SRST
RD
0
D3
RD
1
D2
D1
SRRSL[3:0]
RD
RD
1
1
D0
RD
1
SRRSL[3:0]
Stereo carrier search result. This is only updated when a new stereo carrier is successfully detected.
SRRSL[3:0]
0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
TV System
Sound Modulation
B/G
FM-Stereo (A2)
B/G
FM-Mono/NICAM
reserved
reserved
D/K
FM-Stereo (A2, D/K1)
D/K
FM-Stereo (A2, D/K2)
D/K
FM-Stereo (A2, D/K3)
D/K
FM-Mono/NICAM (D/K, NICAM)
-reserved
-reserved
-reserved
-reserved
-reserved
-reserved
-reserved
-No result yet
Table 77. Stereo Carrier Search TV System Result
(default)
SRCMP
SRCMP
0
1
Stereo Carrier Search Result (SRRSL) Comparison to SYS
SRRSL and SYS are the same
(default)
SRRSL and SYS are different
Table 78. Stereo Carrier Search Result (SRRSL) Comparison to SYS
SRST
SRST
0
1
Stereo Carrier Search Status
Not searching
(either search is disabled or a stereo carrier has been detected)
Searching
(search is enabled and a stereo carrier is not currently detected)
Table 79. Stereo Carrier Search Status
(default)
SRIND
Stereo carrier search indicator. The SRIND bit indicates that System Select is B/G or D/K with NICAM or A2,
Carrier 1 is present, but Carrier 2 is not detected. This bit can be used to determine if Stereo Carrier Search should be
enabled.
SRIND
0
1
Stereo Carrier Search Indicator
SYS[3:0] is B/G or D/K, NICAM or A2 and Carrier 1
is detected and Carrier 2 is not detected
otherwise
Table 80. Stereo Carrier Search Indicator
MS0952-E-03
(default)
2013/12
- 72 -
[AK4141]
Addr
59H
Register Name
Audio Output Result
R/W
Default
D7
D6
D5
LOR
ROL
LRSUM
RD
0
RD
0
RD
0
D4
0
RD
0
D3
D2
LRSL[1:0]
RD
RD
0
0
D1
D0
RRSL[1:0]
RD
RD
0
0
RRSL[1:0]
Right channel audio output result.
RRSL[1:0]
00H
01H
02H
03H
EIA-J
Mono
R
A
B
Right Outputs for AUTO = “0”
A2
NICAM
Mono
AMono
R
R
A
A
B
B
Table 81. Right Output Result
FM Radio
Mono
R
Mono
L-R
Left Outputs for AUTO = “0”
A2
NICAM
Mono
AMono
L
L
A
A
B
B
Table 82. Left Output Result
FM Radio
Mono
L
Mono
L-R
(default)
LRSL[1:0]
Left channel audio output result.
LRSL[1:0]
00H
01H
02H
03H
EIA-J
Mono
L
A
B
(default)
LOR, ROL, LRSM
These bits are copied outputs of LOR, ROL and LRSM bits on 4AH. Read only.
Addr
5AH
Register Name
Mute Control / Status
R/W
Default
D7
0
R/W
0
D6
AAOMT
R/W
0
D5
ASDMT
R/W
0
D4
LMT
RD
0
D3
RMT
RD
0
D2
MANMT
R/W
0
D1
MUTEL
R/W
0
D0
MUTER
R/W
0
MUTER
Mute Control Rch
MUTER
0
1
Right Channel
Not Muted
Muted
Table 83. Mute Control Rch
(default)
MUTEL
Mute Control Lch
MUTEL
0
1
Left Channel
Not Muted
Muted
Table 84. Mute Control Lch
MS0952-E-03
(default)
2013/12
- 73 -
[AK4141]
MANMT
Manual Mute Control
MANMT
0
1
RMT
Mute Result Rch
RMT
0
1
LMT
Mute Result Lch
LMT
0
1
Mute Mode
Mute Determined Automatically
Mute determined by MUTEL,R.
Table 85. Manual Mute Control
Right Channel
Not Muted
Muted
Table 86. Mute Result Rch
Left Channel
Not Muted
Muted
Table 87. Mute Result Lch
(default)
(default)
(default)
ASDMT
Indicates whether automatic system detection is muting the outputs.
ASDMT
0
1
ASD Mute
Not Muting
Muting
Table 88. ASD Mute
(default)
AAOMT
Indicates whether AAOS is muting the outputs.
AAOMT
0
1
AAOS Mute
Output is not currently muted by AAOS.
Output is currently muted by AAOS.
Table 89. AAOS Mute
MS0952-E-03
(default)
2013/12
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[AK4141]
Addr
Register Name
5BH
Auto System Detect Control
R/W
Default
D7
D6
D5
D4
0
R/W
0
R/W
0
D3
D2
A6M5
R/W
0
R/W
0
R/W
0
D1
D0
A4M5[2:0]
R/W
0
R/W
1
R/W
1
A6M5: Decoder Standard Preference1. This bit is XORed with A6M5 Pin.
A6M5
00H
01H
Decoder Standard Preference1
SECAM L NICAM
D/K1, D/K2, D/K3 or D/K NICAM
Table 90. Decoder Standard Preference 1
(default)
A4M5[2:0]: Decoder Standard Preference2. These bits are XORed with A4M52-20 Pins respectively.
A4M5[2:0]
00H
01H
02H
03H
04H
05H
06H
07H
Decoder Standard Preference2
Reserved
EIAJ
M-Korea
PAL (Chroma Carrier)
Reserved
Reserved
Reserved
Reserved
Table 91. Decoder Standard Preference 2
MS0952-E-03
(default)
2013/12
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[AK4141]
Addr
5CH
Register Name
Decoder AVC
R/W
Default
D7
R/W
0
D6
0
R/W
0
D5
R/W
0
D4
D3
DATK[1:0]
R/W
R/W
0
0
D2
D1
DDEC[1:0]
R/W
R/W
0
0
D0
AVCE
R/W
0
AVCE: AVC Enable
AVC status
Disabled
Enabled
Table 92. AVC Enable
AVCE
00H
01H
(default)
DDEC[1:0]: Decoder AVC Decay time
AVC Decay time
85 msec
1.4 seconds
2.7 seconds
5.5 seconds
Table 93. Decoder AVC Decay time
DDEC[1:0]
0H
1H
2H
3H
(default)
DATK[1:0]: Decoder AVC Attack time
AVC Attack time
11 msec
21 msec
44 msec
85 msec
Table 94. AVC Decay time
DATK[1:0]
0H
1H
2H
3H
Addr
5DH
Register Name
Level Prescaler Control
R/W
Default
D7
R/W
0
D6
R/W
0
D5
R/W
0
D4
0
R/W
0
(default)
D3
D2
D1
D0
PRECTL
R/W
0
R/W
0
R/W
0
R/W
1
PRECTL
Level prescaler mode. The prescaler is positioned prior to the Automatic Volume control. When in automatic mode,
the left and right prescaler levels will be adjusted to output the same level from different standards of normal broad
cast’s signal.
PRECTL
00H
01H
Level Prescaler Mode
Automatic
Manual
Table 95. Level Prescaler Mode
MS0952-E-03
(default)
2013/12
- 76 -
[AK4141]
Addr
5EH
5FH
Register Name
Prescaler L
Prescaler R
R/W
Default
D7
D6
D5
R/W
1
R/W
1
R/W
1
D4
D3
PREL[7:0]
PRER[7:0]
R/W
R/W
1
1
D2
D1
D0
R/W
1
R/W
1
R/W
1
PREL[7:0]
PRER[7:0]
Prescaler output level for left channel. This register is only used when PRECTL is set to manual mode. Use the
following formula to set the desired output level. The gain must be a value from 1/256 to 1.
PREL[7:0], PRER[7:0] = Gain x 256 - 1 (unsigned)
Addr
60H
61H
Register Name
Manual Output Level L
Manual Output Level R
R/W
Default
D7
D6
D5
R/W
1
R/W
1
R/W
1
D4
D3
LEVL[7:0]
LEVR[7:0]
R/W
R/W
1
1
D2
D1
D0
R/W
1
R/W
1
R/W
1
LEVL[7:0]
LEVR[7:0]
Manual output level for left channel. This register is used to set the volume level at the left output. The level
adjustment is positioned after the Automatic Volume Control. By using the following formula, set the desired output
level. The gain must be a value from 1/256 to 1.
LEVL[7:0], LEVR[7:0] = Gain x 256 - 1 (unsigned)
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[AK4141]
Addr
62H
63H
Register Name
Carrier 1 Average Frequency 1
Carrier 1 Average Frequency 0
R/W
Default
D7
D6
D5
D4
D3
CR1F[15:8]
CR1F[7:0]
D2
D1
D0
RD
00000000
CR1F[15:0]
Carrier 1 average frequency. Represents the difference between the nominal carrier frequency and the actual carrier
frequency (2’s complement.)
Ferr = CR1F x Fs x 2-20
(Hz)
Fac = Fc + Ferr
(Hz)
Ferr = Frequency error. Difference between nominal and actual carrier frequencies (Hz)
Fac = Actual frequency of carrier to be demodulated (Hz)
Fc = Nominal carrier frequency set inDM1F (Hz)
Fs = Input sample rate (Hz), see the Sample Rate Register table (Table 45) for the input sample rate that corresponds
to the selected output sample rate.
When reading these registers, always read the high byte first. The low byte is only updated when the high byte is read.
This ensures that the values read from the two registers come from the same 16-bit word.
Addr
64H
65H
Register Name
Carrier 1 Phase Noise 1
Carrier 1 Phase Noise 0
R/W
Default
D7
D6
D5
D4
D3
CR1P[15:8]
CR1P[7:0]
D2
D1
D0
RD
00000000
CR1P[15:0]
Carrier 1 phase noise. Represents the average phase noise in terms of frequency deviation.
16
CR1P = Fadev / Fs x 2
(in 2’s complement)
Fadev = average frequency deviation (in Hz)
Fs = Input sample rate (in Hz), see the Sample Rate Register table (Table 45) for the input sample rate that
corresponds to the selected output sample rate.
When reading these registers always read the high byte first. The low byte is only updated when the high byte is read.
This ensures that the values read from the two registers come from the same 16-bit word.
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[AK4141]
Addr
66H
67H
Register Name
Carrier 1 Average Magnitude 1
Carrier 1 Average Magnitude 0
R/W
Default
D7
D6
D5
D4
D3
CR1M[15:8]
CR1M[7:0]
D2
D1
D0
RD
00000000
CR1M [15:0]
Carrier 1 average magnitude.
2
14
CR1M = Portion of full scale x 1.647 x 2 (unsigned)
When reading these registers, always read the high byte first. The low byte is only updated when the high byte is read.
This ensures that the values read from the two registers come from the same 16-bit word.
CR1M [15:0]
0xAD9B
0x7AE8
0x5702
0x3D99
0x2B9C
0x1EDF
0x15DB
0x0F79
0x0AF4
0x07C1
0x057D
Addr
68H
69H
Average Carrier Magnitude (dBFS)
0
-3
-6
-9
-12
-15
-18
-21
-24
-27
-30
Table 96. Carrier 1 average magnitude
Register Name
Carrier 1 Magnitude Noise 1
Carrier 1 Magnitude Noise 0
R/W
Default
D7
D6
D5
D4
D3
CR1N[15:8]
CR1N[7:0]
D2
D1
D0
RD
00000000
CR1N [15:0]
Carrier 1 average magnitude noise. An FM carrier has a constant magnitude. This is a measure of its average
difference from its average.
2
14
CR1N [15:0] = Portion of full scale x 1.647 * 2 (unsigned)
When reading these registers, always read the high byte first. The low byte is only updated when the high byte is read.
This ensures that the values read from the two registers come from the same 16-bit word.
CR1N[15:8]
0xAD9B
0x5702
0x2B9C
0x15DB
0x0AF4
0x057D
0x02C0
0x0161
0x00B1
0x0059
0x002C
0x0016
0x000B
Average Carrier Magnitude Noise (dBFS)
0
-6
-12
-18
-24
-30
-36
-42
-48
-54
-60
-66
-72
Table 97. Carrier 1 average magnitude noise
MS0952-E-03
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[AK4141]
Addr
6AH
6BH
Register Name
Carrier 1 Signal Quality 1
Carrier 1 Signal Quality 0
R/W
Default
D7
D6
D5
D4
D3
CR1Q[15:8]
CR1Q[7:0]
D2
D1
D0
RD
00000000
CR1Q[15:0]: Carrier 1 quality.
This is the ratio of CR1M to CR1N. This is an approximation of S/N ratio.
CR1Q = CR1M / CR1N x 26 (unsigned)
When reading these registers, always read the high byte first. The low byte is only updated when the high byte is read.
This ensures that the values read from the two registers come from the same 16-bit word.
CR1Q [15:0]
0xFFFF
0x4000
0x1000
0x0400
0x0100
0x0040
0x0010
0x0004
0x0001
Ratio of CR1M to CR1N (dB)
>60
48
36
24
12
0
-12
-24
<-36
Table 98. Carrier 1 quality
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[AK4141]
Addr
6CH
6DH
Register Name
Carrier 2 Average Frequency 1
Carrier 2 Average Frequency 0
R/W
Default
D7
D6
D5
D4
D3
CR2F[15:8]
CR2F[7:0]
D2
D1
D0
RD
00000000
CR2F[15:0]
Carrier 2 average frequency. Represents the difference between the nominal carrier frequency and the actual carrier
frequency (2’s complement.)
Ferr = CR2F x Fs x 2-20
(Hz)
Fac = Fc + Ferr
(Hz)
Ferr = Frequency error. Difference between nominal and actual carrier frequencies (Hz)
Fac = Actual frequency of carrier to be demodulated (Hz)
Fc = Nominal carrier frequency set in DM2F (Hz)
Fs = Input sample rate (Hz), see the Sample Rate Register table (Table 45) for the input sample rate that corresponds
to the selected output sample rate.
When reading these registers, always read the high byte first. The low byte is only updated when the high byte is read.
This ensures that the values read from the two registers come from the same 16-bit word.
Addr
6EH
6FH
Register Name
Carrier 2 Average Magnitude 1
Carrier 2 Average Magnitude 0
R/W
Default
D7
D6
D5
D4
D3
CR2M[15:8]
CR2M[7:0]
D2
D1
D0
RD
00000000
CR2M [15:0]
Carrier 2 average magnitude.
2
14
CR2M = Portion of full scale x 1.647 x 2 (unsigned)
When reading these registers, always read the high byte first. The low byte is only updated when the high byte is read.
This ensures that the values read from the two registers come from the same 16-bit word.
CR2M [15:0]
0xAD9B
0x7AE8
0x5702
0x3D99
0x2B9C
0x1EDF
0x15DB
0x0F79
0x0AF4
0x07C1
0x057D
Average Carrier Magnitude (dBFS)
0
-3
-6
-9
-12
-15
-18
-21
-24
-27
-30
Table 99. Carrier 2 average magnitude
MS0952-E-03
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[AK4141]
Addr
70H
71H
Register Name
Carrier 2 Magnitude Noise 1
Carrier 2 Magnitude Noise 0
R/W
Default
D7
D6
D5
D4
D3
CR2N[15:8]
CR2N[7:0]
D2
D1
D0
RD
00000000
CR2N [15:0]
Carrier 1 average magnitude noise. An FM carrier has a constant magnitude. This is a measure of its average
difference from its average.
2
14
CR2N [15:0] = Portion of full scale x 1.647 * 2 (unsigned)
When reading these registers, always read the high byte first. The low byte is only updated when the high byte is read.
This ensures that the values read from the two registers come from the same 16-bit word.
CR2N[15:8]
0xAD9B
0x5702
0x2B9C
0x15DB
0x0AF4
0x057D
0x02C0
0x0161
0x00B1
0x0059
0x002C
0x0016
0x000B
Addr
72H
73H
Average Carrier Magnitude Noise (dBFS)
0
-6
-12
-18
-24
-30
-36
-42
-48
-54
-60
-66
-72
Table 100. Carrier 2 average magnitude noise
Register Name
Carrier 2 Signal Quality 1
Carrier 2 Signal Quality 0
R/W
Default
D7
D6
D5
D4
D3
CR2Q[15:8]
CR2Q[7:0]
D2
D1
D0
RD
00000000
CR2Q[15:0]: Carrier 2 quality.
This is the ratio of CR2M to CR2N. This is an approximation of S/N ratio.
CR1Q = CR1M / CR1N x 26 (unsigned)
When reading these registers, always read the high byte first. The low byte is only updated when the high byte is read.
This ensures that the values read from the two registers come from the same 16-bit word.
CR2Q [15:0]
0xFFFF
0x4000
0x1000
0x0400
0x0100
0x0040
0x0010
0x0004
Ratio of CR2M to CR2N (dB)
>60
48
36
24
12
0
-12
-24
Table 101. Carrier 2 quality
MS0952-E-03
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[AK4141]
Addr
74H
Register Name
Pilot Magnitude
R/W
Default
D7
D6
D5
D4
D3
PLTM[7:0]
D2
D1
D0
D2
D1
D0
D2
D1
D0
RD
00000000
PLTM[7:0]
Pilot magnitude. The pilot is present in EIAJ and FM Radio stereo broadcasts.
PltMag7-0
255
200
0
Addr
75H
Register Name
FM Subcarrier Magnitude
R/W
Default
EIAJ Carrier Deviation
6.375kHz
5kHz (nominal)
0kHz
Table 102. Pilot magnitude
D7
D6
D5
D4
D3
SUBM[7:0]
RD
00000000
SUBM[7:0]
FM subcarrier magnitude. The fm subcarrier is present in EIA-J broadcast.
SUBM[7:0]
255
200
150
0
Addr
76H
Register Name
FM Subcarrier Noise
R/W
Default
FM subcarrier magnitude
25.5kHz
20kHz
15kHz
0kHz
Table 103. FM subcarrier magnitude
D7
D6
D5
D4
D3
SUBN[7:0]
RD
00000000
SUBNM[7:0]
FM subcarrier noise. The fm subcarrier is present in EIA-J broadcast. In the Table 104, the magnitude of the error is
expressed in terms of aural carrier deviation.
SUBM[7:0]
255
200
150
0
Carrier Deviation
25.5kHz
20kHz
15kHz
0kHz
Table 104. FM subcarrier magnitude
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[AK4141]
Addr
7BH
Register Name
Carrier 1 Quality Threshold High
R/W
Default
D7
D6
D5
D4
D3
C1QTH[7:0]
D2
D1
D0
R/W
00100010
C1QTH[7:0]
Carrier 1 Quality high threshold. This 8-bit threshold is compared against the top 13 bits of carrier 1 quality
(CR1Q[15:3]). The threshold is extended to 13 bits by concatenating five zeros above its MSB.
Addr
7CH
Register Name
Carrier 1 Quality Threshold Low
R/W
Default
D7
D6
D5
D4
D3
C1QTL[7:0]
D2
D1
D0
R/W
00010110
C1QTL[7:0]
Carrier 1 Quality low threshold. This 8-bit threshold is compared against the top 13 bits of carrier 1 quality
(CR1Q[15:3]). The threshold is extended to 13 bits by concatenating five zeros above its MSB.
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[AK4141]
Addr
7DH
Register Name
Carrier 2 Quality Threshold High
R/W
Default
D7
D6
D5
D4
D3
C2QTH[7:0]
D2
D1
D0
R/W
00110100
C2QTH[7:0]
Carrier 2 Quality high threshold. This 8-bit threshold is compared against the top 13 bits of carrier 1 quality
(CR2Q[15:3]). The threshold is extended to 13 bits by concatenating five zeros above its MSB.
Addr
7EH
Register Name
Carrier 2 Quality Threshold Low
R/W
Default
D7
D6
D5
D4
D3
C2QTL[7:0]
D2
D1
D0
R/W
00100001
C2QTL[7:0]
Carrier 2 Quality low threshold. This 8-bit threshold is compared against the top 13 bits of carrier 1 quality
(CR2Q[15:3]). The threshold is extended to 13 bits by concatenating five zeros above its MSB.
Addr
7FH
Register Name
Carrier 1 Phase Noise Threshold High
R/W
Default
D7
D6
D5
D4
D3
C1PTH[7:0]
D2
D1
D0
R/W
10000000
C1PTH[7:0]
Carrier 1 phase noise high threshold. This 8-bit threshold is compared against the top 11 bits of carrier 1 phase noise
(CR1P[15:5]). The threshold is extended to 11 bits by concatenating three zeros above its MSB.
Addr
80H
Register Name
Carrier 1 Phase Noise Threshold Low
R/W
Default
D7
D6
D5
D4
D3
C1PTL[7:0]
D2
D1
D0
R/W
00100000
C1PTL[7:0]
Carrier 1 phase noise low threshold. This 8-bit threshold is compared against the top 11 bits of carrier 1 phase noise
(CR1P[15:5]). The threshold is extended to 11 bits by concatenating three zeros above its MSB.
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[AK4141]
Addr
81H
Register Name
FM Sub Magnitude Threshold High
R/W
Default
D7
D6
D5
D4
D3
FSMTH[7:0]
D2
D1
D0
D1
D0
D2
D1
D0
D2
D1
D0
D2
D1
D0
D2
D1
D0
R/W
01111101
FSMTH[7:0]
FM subcarrier magnitude high threshold. Compared against FM subcarrier magnitude (SUBM[7:0].)
Addr
82H
Register Name
FM Sub Magnitude Threshold Low
R/W
Default
D7
D6
D5
D4
D3
FSMTL[7:0]
D2
R/W
01001011
FSMTL[7:0]
FM subcarrier magnitude low threshold. Compared against FM subcarrier magnitude (SUBM[7:0].)
Addr
83H
Register Name
FM Sub Noise Threshold High
R/W
Default
D7
D6
D5
D4
D3
FSNTH[7:0]
R/W
00010100
FSNTH[7:0]
FM subcarrier noise high threshold. Compared against FM subcarrier noise (SUBN[7:0].)
Addr
84H
Register Name
FM Sub Noise Threshold Low
R/W
Default
D7
D6
D5
D4
D3
FSNTL[7:0]
R/W
00001010
FSNTL[7:0]
FM subcarrier noise low threshold. Compared against FM subcarrier noise (SUBN[7:0].)
Addr
85H
Register Name
NCM Err Rate Threshold High
R/W
Default
D7
D6
D5
D4
D3
NERTH[7:0]
R/W
01010000
NERTH[7:0]
NICAM error rate low threshold. Compared against NICAM error rate (NERR[15:8].)
Addr
86H
Register Name
NCM Err Rate Threshold Low
R/W
Default
D7
D6
D5
D4
D3
NERTL[7:0]
R/W
00110000
NERTL[7:0]
NICAM error rate low threshold. Compared against NICAM error rate (NERR[15:8].)
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[AK4141]
Addr
8BH
Register Name
Carrier Magnitude ASD Threshold
R/W
Default
D7
D6
D5
D4
D3
ASDMT[7:0]
D2
D1
D0
R/W
00011001
ASDMT[7:0]
ASD threshold of carrier magnitude. This 8-bit threshold is compared against the top 11 bits of carrier 1 & 2 average
magnitude values that are the same as CR1M and CR2M except that their settling times are one-fourth as long. The
threshold is extended to 11 bits by concatenating three zeros above its MSB.
Addr
8CH
Register Name
Carrier Freq ASD Threshold
R/W
Default
D7
D6
D5
D4
D3
ASDFT[7:0]
D2
D1
D0
R/W
00011000
ASDFT[7:0]
ASD threshold of carrier average frequency. This 8-bit threshold is compared against the absolute value of the top 10
bits of carrier 1 & 2 average frequency (CR1F[15:6], CR2F[15:6]). The threshold is extended to 10 bits by
concatenating two zeros above its MSB.
Addr
8DH
Register Name
Carrier FM Quality ASD Threshold
R/W
Default
D7
D6
D5
D4
D3
ASQT[7:0]
D2
D1
D0
R/W
00000000
ASQT[7:0]
Carrier FM quality ASD threshold. This 8-bit threshold is is zero extended to 13 bits by concatenating 5 zeros above
its MSB and then it is compared against the top 13 bits of carrier 1 & 2 FM quality values(Figure 29, Table 105)
compare
13
Carrier1Quality[15:3]
0
ASQTh[7:0]
5
8
[12:0]
>=
Carrier1QualityGood
[12:8]
[7:0]
Figure 29. Carrier Quality Threshold
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[AK4141]
Carrier FM Quality Threshold (dB)= 20*log(ASQTh/8)
Carrier FM Quality
ASQT
Threshold (dB)
(decimal)
-INF
0
(default)
10.2
26
(Recommended)
15
45
20
80
25
142
30
253
Table 105. Table of Typical Carrier FM Quality Threshold Values
Addr
8EH
Register Name
Carrier AM Noise ASD Threshold
R/W
Default
D7
D6
D5
D4
D3
AANT[7:0]
D2
D1
D0
R/W
1111 1111
AANT[7:0]
Carrier AM Noise ASD threshold. This 8-bit threshold is compared against the top 8 bits of the carrier 1 phase noise
value. The definition of the threshold in terms of carrier frequency deviation is:
AANTh = Fadev / Fs * 212
Fadev = average frequency deviation (in Hz)
Fs = Input sample rate (in Hz), see the Sample Rate Register table for the input sample rate that corresponds to the
selected output sample rate.
Carrier AM Noise Threshold (kHz)
AANT
(for Fs = 18.432MSPS)
(decimal)
0
0
4.5
1
40.5
9
(Recommended)
225
50
450
100
1147.5
255
(default)
Table 106.Typical Carrier AM Noise Threshold Values
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Addr
8FH
Register Name
NICAM Noise ASD Threshold
R/W
Default
D7
D6
D5
D4
D3
ANNT[7:0]
D2
D1
D0
R/W
1111 1111
ANNT[7:0]
NICAM Noise ASD threshold. This 8-bit threshold is compared against the top 8 bits of the NICAM noise value.
ANNTh = Average Symbol Phase Error Magnitude (degrees) * 32 / 22.5 (degrees)
Average Symbol Phase Error
Magnitude (degrees)
0
7.0
21.1
22.5
ANNT
(decimal)
0
10
30
32
(default)
(Recommended)
179
255
Table 107.Typical NICAM Noise ASD Threshold Values
Addr
Register Name
90H
91H
NICAM Noise MSB
NICAM Noise LSB
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
RD
0
RD
0
RD
0
NICN[15:8]
NICN[7:0]
RD
0
RD
0
RD
0
RD
0
RD
0
ASQT[7:0]
NICAM Average Symbol Phase Error Magnitude. This value represents the average magnitude of the phase error for
each NICAM DQPSK symbol.
Average Symbol Phase Error Magnitude = NICNs * 22.5 / 8192
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[AK4141]
Addr
92H
Register Name
Carrier FM Quality SCS Threshold
R/W
Default
D7
D6
D5
D4
D3
SQLT[7:0]
D2
D1
D0
R/W
00000000
SQLT[7:0]
The Carrier FM quality SCS threshold is used by the stereo carrier search function to determine the quality of carrier 2.
This 8-bit threshold is zero extended to 13 bits by concatenating 5 zeros above its MSB and then it is compared against
the top 13 bits of the carrier 2 FM quality value (Figure 30, Table 108).
compare
13
Carrier2Quality[15:3]
0
SQLTh[7:0]
5
8
[12:0]
>=
Carrier2QualityGood
[12:8]
[7:0]
Figure 30. Carrier 2 Quality Threshold
Carrier FM Quality Threshold (dB)= 20*log(SQlTh/8)
Carrier FM Quality
SQLT
Threshold (dB)
(decimal)
-INF
0
(default)
6
16
10.2
26
15
45
20
80
25
142
30
253
Table 108.Typical Carrier FM Quality Threshold Values
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[AK4141]
Addr
93H
Register Name
NICAM Noise SCS Threshold
R/W
Default
D7
D6
D5
D4
D3
SNST[7:0]
D2
D1
D0
R/W
1111 1111
SNST[7:0]
The NICAM Noise SCS threshold is used by the stereo carrier search function to determine the quality based on
received symbol phase error. This 8-bit threshold is compared against the top 8 bits of the NICAM noise value.
SNSTh = Average Symbol Phase Error Magnitude (degrees) * 32 / 22.5 (degrees)
Average Symbol Phase
SNST
Error Magnitude (degrees)
(decimal)
0
0
7.0
10
21.1
30
(Recommended)
22.5
32
179
255
(default)
Table 109.Typical NICAM Noise ASD Threshold Values
Addr
94H
Register Name
AVC Level Threshold High
R/W
Default
D7
Register Name
AVC Level Threshold Low
R/W
Default
D7
Addr
95H
D6
D5
D4
D3
AVCH[7:0]
D2
D1
D0
D2
D1
D0
R/W
0010 0110
D6
D5
D4
D3
AVCL[7:0]
R/W
0001 1011
AVCH[7:0], AVCL[7:0]
These two thresholds are used to control the target audio level when AVC is active. AVC works by maintaining the
combined power of the left and right channels between these high and low level thresholds. The output volume, in dB,
relative to full scale is:
20*log10(threshold/128)
The values of these registers should not exceed 128.
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SYSTEM DESIGN
Figure 31 shows the system connection diagram. The evaluation board AKD4141 demonstrates application circuits, the
optimum layout, power supply arrangements and measurement results.
0.1u 10u
ROUT3 25
AVSS2 27
AVDD2 26
VCOM3 29
40 LIN4
ROUT2 21
41 RIN4
LOUT2 20
AK4682EQ
MUTE
MUTE
LRCKA
BICKA
8
9
0.1u
+
10u
5V Digital
SDA 13
12 SDTIA2
PDN
7
11 SDTIA1
SDTOB
10 MCLKA
BICKB
6
MCLKB
MUTE
10u
DVSS1
5
SCL 14
LRCKB
DVDD2 15
47 RIN6
4
46 LIN6
TVDD
DVSS2 16
3
LOUT1 17
45 NC
2
MUTE
+
10u
ROUT1 18
Audio CODEC with SW
1
0.1u
MSB 19
44 RIN5
0.1u
Analog Tuner
VCOM36 28
0.1u 10u
LIN1 32
PVDD 22
0.1u 10u
+ 48 DVDD1
MUTE
LOUT3 24
39 NC
+
3.3V Digital
4.7n
0.1u
25
MCKO
SCLK 26
LRCK 27
SDTO3 28
SDTO2 29
37 VREFH
SDTO1 30
INT 31
A6M5 32
MSN 33
CAD0 34
CAD1 35
0.1u
LFLT1 36
SIF
0.1u
38 VREFL
Digital Tuner
39 GND3
1u
10n
3.3V Analog
SDA 22
TVDD 21
41 VCOM
GND2 20
AK4141EQ
GND1 19
DVDD 18
NICAM/A2/EIAJ
Stereo Decoder
45 XTI
1.8V Digital
SCL 14
SCLK5
SDTI5
LRCK4
SCLK4
SDTI4
SDTI3
4
5
6
7
8
9
12 A4M50
LRCK5
3
11 SDTI1
IIS
10 SDTI2
LFLT2
2
A4M51 13
1
DIT
0.68µ
+
10u
PDN 15
48 AVDD2
10u 0.1u
IIS
+ 10u
0.1u
MCLKI 16
47 GND5
+
0.1u
TXIN 17
46 XTO
LRCK, SCLK, SDATA
O/E
TXO 24
40 SIF2
42 SIF1
10u 0.1u
43 AVDD1
+
12.288MHz
Optical Output
A4M52 23
44 GND4
MPEG Decoder
Analog out
MUTE
PVSS 23
43 LIN5
DSP
+
5V Analog
9V to 12V
Analog
38 RIN3
42 NC
5V Digital
+
+
AVDD1 31
NC 34
RIN1 33
LIN2 35
RIN2 36
37 LIN3
+
AVSS1 30
Analog in
LRCK, SCLK, SDATA
IIS
Micro
Controller
31
Digital Ground
Analog Ground
Figure 31. Typical Connection Diagram
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1. Grounding and Power Supply Decoupling
The AK4141 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and TVDD are
usually supplied from analog supply in system. If AVDD, DVDD and TVDD are supplied separately, the power up
sequence is not critical. All GND pins must be connected to analog ground plane. System analog ground and digital
ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling
capacitors should be as near to the AK4141 as possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference Inputs
The voltage of AVDD sets the analog input/output range. A 1F ceramic capacitor attached between VCOM pin and
GND4 pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals,
especially clocks, should be kept away from the AVDD and VCOM pins in order to avoid unwanted coupling into the
AK4141.
3. Analog Inputs
The AK4141 receives the analog SIF. Each input pins are biased internally.
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[AK4141]
PACKAGE
48pin LQFP(Unit:mm)
1.70Max
9.0 0.2
0.13 0.13
7.0
36
1.40 0.05
24
48
13
7.0
37
1
0.5
9.0 0.2
25
12
0.22 0.1
0.10 M
0
0.10
0.3~0.75
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
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[AK4141]
MARKING
AK4141EQ
XXXXXXX
1
XXXXXXX: Date code identifier
REVISION HISTORY
Date (YY/MM/DD)
08/05/09
10/09/17
Revision
00
01
Reason
First edition
Description
Change
Page
Contents
94
12/10/16
02
Description
Change
94
13/12/20
03
Error
Correction
1
PACKAGE
The dimension tolerance of package drawing was
changed.
Pin width: “0.22±0.1” → “0.22±0.08”
Pin height was added.
PACKAGE
The dimension tolerance of package drawing was
changed to the common value.
Pin width: “0.22±0.08” → “0.22±0.1”
Pin height was deleted.
GENERAL DESCRIPTION
The description was changed.
SYSTEM DESIGN
Figure 31 was changed.
92
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IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application of
AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor grants any
license to any intellectual property rights or any other rights of AKM or any third party with respect
to the information in this document. You are fully responsible for use of such information contained
in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR
ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH
INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact, including
but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry,
medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic
signaling equipment, equipment used to control combustions or explosions, safety devices, elevators
and escalators, devices related to electric power, and equipment used in finance-related fields. Do
not use Product for the above use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible
for complying with safety standards and for providing adequate designs and safeguards for your
hardware, software and systems which minimize risk and avoid situations in which a malfunction or
failure of the Product could cause loss of human life, bodily injury or damage to property, including
data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or related
technology or any information contained in this document, you should comply with the applicable
export control laws and regulations and follow the procedures required by such laws and regulations.
The Products and related technology may not be used for or incorporated into any products or
systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation,
the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth
in this document shall immediately void any warranty granted by AKM for the Product and shall not
create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
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