ASAHI KASEI [AK4565] AK4565 Low Power 20bit CODEC with built-in ALC AK4565 ALC 1. 2. 20bit Stereo CODEC IPGA 1.5V 3.6V 4 I/F AK4565 : 20bits •4 • ALC • • IPGA HPF (fc=3.7Hz@fs=48kHz) 3. • Digital De-emphasis Filter (tc=50/15µs, fs = 32kHz, 44.1kHz, 48kHz ) 4. 5. CODEC • • : 1.5Vpp@VA=2.5V (= 0.6 x VREF) • S/(N+D): 83dB(ADC), 86dB(DAC) @VREF=2.5V • DR, S/N: 87dB(ADC), 91dB(DAC) @VREF=2.5V 6. Master Clock: 256fs/384fs 7. Sampling Rate: 8kHz ∼50kHz 8. Audio Data Interface Format: MSB First, 2’s compliment • ADC: 20bit , I2S • DAC: 20bit , 16/20bit , I2S 9. 4 10. • CODEC, PGA: 2.3 ∼ 3.6V (typ.2.5V) • Digital I/F: 1.5 ∼ 3.6V(typ.2.5V) 11. • ALL Power ON: 12.5mA • (IPGA + ADC): 8mA • DAC: 5.5mA 12. Ta = -40 ∼ 85 13. : 28pin VSOP 14. AK4563A MS0132-J-02 2004/12 -1- ASAHI KASEI INTL0 INTL1 EXTL LIN [AK4565] IPGA ADC Audio I/F Controller HPF LRCK BCLK SDTO0 SDTO1 SDTI INTR0 INTR1 EXTR RIN VD VT DGND PDN LOUT DAC De-emp ROUT VCOM VREF VA AGND Control Register I/F CSN CCLK CDTI Clock Divider CDTO MCLK 1. AK4565 MS0132-J-02 2004/12 -2- ASAHI KASEI [AK4565] AK4565VF AKD4565 -40 ∼ +85°C AK4565 28pin VSOP (0.65mm pitch) LOUT 1 28 PDN ROUT 2 27 CCLK INTL1 3 26 CSN INTR1 4 25 CDTI INTL0 5 24 CDTO INTR0 6 23 BCLK EXTL 7 22 MCLK EXTR 8 21 LRCK LIN 9 20 SDTI RIN 10 19 SDTO1 VCOM 11 18 SDTO0 AGND 12 17 VT VA 13 16 DGND VREF 14 15 VD AK4565 Top View MS0132-J-02 2004/12 -3- ASAHI KASEI [AK4565] No. 1 2 3 4 5 6 7 8 9 10 LOUT ROUT INTL1 INTR1 INTL0 INTR0 EXTL EXTR LIN RIN I/O O O I I I I I I I I 11 VCOM O 12 13 AGND VA - 14 VREF I 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VD DGND VT SDTO0 SDTO1 SDTI LRCK MCLK BCLK CDTO CDTI CSN CCLK PDN O O I I I I O I I I I Lch Analog Output Pin Rch Analog Output Pin Lch INT #1 Input Pin Rch INT #1 Input Pin Lch INT #0 Input Pin Rch INT #0 Input Pin Lch EXT Input Pin Rch EXT Input Pin Lch Line Input Pin Rch Line Input Pin Common Voltage Output Pin, 0.45 x VA Bias voltage of ADC inputs and DAC outputs Analog Ground Pin Analog Power Supply Pin, +2.3 3.6V ADC & DAC Voltage Reference Input Pin, VA Used as a voltage reference of ADC & DAC. VREF is connected externally to filtered VA. Digital Power Supply Pin, +2.3 3.6V Digital Ground Pin Digital I/F Power Supply Pin, +1.5 3.6V Audio Serial Data Output Pin Audio Serial Data Output Pin Audio Serial Data Input Pin Input/Output Channel Clock Pin Master Clock Input Pin Audio Serial Data Clock Pin Control Data Output Pin Control Data Input Pin Chip Select Pin Control Data Clock Pin Power Down & Reset Pin, “L”: Power Down & Reset, “H”: Normal Operation : MS0132-J-02 2004/12 -4- ASAHI KASEI [AK4565] (AGND, DGND=0V; Parameter ( 1) (VA pin) 1(VD pin) 2 VT pin | DGND – AGND | ( 2) ) ( 3) ( 4) Symbol VA VD VT GND IIN VINA VIND Ta Tstg min -0.3 -0.3 -0.3 -0.3 -0.3 -40 -65 max 4.6 4.6 4.6 0.3 ±10 VA+0.3 VT+0.3 85 150 Units V V V V mA V V °C °C 1. 2. AGND DGND 3. INTL0, INTR0, INTL1, INTR1, EXTL, EXTR, LIN, RIN, VREF pins 4. PDN, MCLK, BCLK, LRCK, SDTI, CSN, CCLK, CDTI pins : (AGND, DGND=0V; Parameter 1) (VA pin) 1(VD pin) 5 2(VT pin) (VREF pin) ( 1. 5. Min 2.3V 6. VREF 6) Symbol VA VD VT VREF min 2.3 2.3 or VA-0.3 1.5 - typ 2.5 2.5 2.5 - max 3.6 VA VD VA Units V V V V VA-0.3V VA : MS0132-J-02 2004/12 -5- ASAHI KASEI [AK4565] ( Ta=25°C; VA, VD, VT=2.5V; fs=48kHz; Parameter PGA (IPGA): (INTL1-0, INTR1-0, EXTL, EXTR, LIN, RIN pins) ( 7) MIC(INTL1-0,INTR1-0,EXTL,EXTR pins) LINE (LIN, RIN pins) MIC LINE +28dB ∼ -8dB +6dB ∼ -30dB -8dB ∼ -16dB -30dB ∼ -38dB -16dB ∼ -32dB -38dB ∼ -54dB -32dB ∼ -40dB -54dB ∼ -62dB -40dB ∼ -52dB -62dB ∼ -74dB ADC : ( 8) S/(N+D) D-Range S/N (-2dBFS) (-60dBFS, A-Weighted) (A-Weighted) ( 9) DAC =1kHz; min =10Hz ∼ 20kHz typ max Units 1.35 1.5 1.65 Vpp 6.5 80 10 125 14.5 176 kΩ kΩ 0.1 0.1 0.1 - 0.5 1 2 2 4 0.9 1.9 3.9 - dB dB dB dB dB 20 74 81 81 85 83 87 87 100 0.2 Bits dB dB dB dB dB 0.5 : LOUT/ROUT 20 S/(N+D) D-Range S/N (0dBFS) (-60dBFS, A-Weighted) (A-Weighted) 77 85 85 85 1.35 10 10 86 91 91 100 0.2 1.5 0.5 1.65 20 Bits dB dB dB dB dB Vpp kΩ pF : VA+VD+VT (PDN=“H”) (PM3=“0”, PM2=PM1=PM0 = “1”) 12.5 19 mA IPGA + ADC (PM3=PM2=“0”, PM1=PM0=“1”) 8.0 mA DAC (PM3=“0”, PM2 =“1”, PM1=PM0=“0”) 5.5 mA (PDN= “L”) ( 11) 10 100 µA 7. IPGA = 0dB VREF Vin = 0.6 x VREF 8. INTL0/INTR0, INTL1/INTR1, EXTL/EXTR or LIN/RIN IPGA IPGA 0dB IPGA+ADC DC HPF 9. INTL0 INTR0 INTL1 INTR1 EXTL EXTR LIN RIN 10. VREF Vout = 0.6 x VREF 11. PDN VT DGND PDN DGND MS0132-J-02 2004/12 -6- ASAHI KASEI [AK4565] (Ta=25°C; VA, VD=2.3 ∼ 3.6V; VT=1.5∼ 3.6V; fs=48kHz; De-emphasis = OFF) Symbol min typ ADC (LPF): ( 12) ±0.1dB PB 0 -1.0dB 21.8 -3.0dB 23.0 SB 29.4 ( 12) PR SA 65 GD 17.0 ( 13) 0 ∆GD ADC (HPF): ( 12) -3.0dB FR 3.7 -0.56dB 10 -0.15dB 20 DAC : ( 12) ±0.1dB PB 0 -6.0dB 24.0 SB 26.2 ( 12) PR SA 43 GD 14.8 ( 13) 0 ∆GD DAC + : FR 0 ∼ 20.0kHz ±0.5 12. ADC 13. fs ( PB=0.454 x fs(@-1.0dB) DAC ADC HPF MS0132-J-02 max Units 18.9 - kHz kHz kHz kHz dB dB 1/fs µs ±0.1 - - Hz Hz Hz 21.7 - kHz kHz kHz dB dB 1/fs µs ±0.06 - dB ) PB=0.454 x fs(@-0.1dB) 20bit DAC 20bit 2004/12 -7- ASAHI KASEI [AK4565] DC (Ta=25°C; VA, VD=2.3 ∼ 3.6V, VT=1.5 ∼ 3.6V) Parameter Iout=-400µA Iout=400µA Symbol VIH VIL VOH VOL Iin min 80%VT VT-0.4 - typ - min typ max Units fCLK tCLKL tCLKH fCLK tCLKL tCLKH fs 2.048 28 28 3.072 23 23 8 45 12.288 12.8 18.432 19.2 48 50 50 55 MHz ns ns MHz ns ns kHz % tBLK tBLKL tBLKH tBLR tDLR tDSS tSDH tSDS 312.5 130 130 -tBLKH+50 tCCK tCCKL tCCKH tCKH2 tCDS tCDH tCSW tCSS tCSH tDCD tCCZ 200( 16) 80 80 80 50 50 150( 16) 50( 16) 50 tPDW tPDV 150 (Ta=25°C; VA, VD=2.3 ∼ 3.6V, VT=1.5 ∼ 3.6V; CL=20pF) Symbol (MCLK) 256fs: “L” “H” 384fs: “L” “H” (LRCK) BCLK BCLK “L” “H” BCLK “↓” LRCK LRCK SDTO0,1(MSB) BCLK “↓” SDTO0,1 SDTI SDTI CCLK CCLK “L” “H” “H” CDTI CDTI CSN ”H” CSN “↓” CCLK “↑” CDTO CSN “↑” PDN PDN “↑” ( 14) 1 2 CCLK “↑” CSN “↑” CDTO(Hi-Z) ( SDTO0,1 14. I2S 15. RL=1kΩ/10% 16. fs ≥ 22.4kHz fs < 22.4kHz ( VT 15) Max 20%VT 0.4 ±10 tBLKL-50 80 80 50 50 70 70 4128 Units V V V V µA ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1/fs ) 3 (tCSW + tCSS + 6 × tCCK) > 1/(32 × fs) fs = 8kHz , tCCK = 200ns, tCSS = 50ns tCSW(min) = 2657ns fs = 8kHz , tCSW = 150ns, tCSS = 50ns tCCK(min) = 618ns MS0132-J-02 2004/12 -8- ASAHI KASEI [AK4565] LRCK tBLR 50%VT tBLKH tBLKL BCLK 50%VT tDLR tDSS SDTO0,1 50%VT D19 (MSB) tSDS SDTI tSDH LSB 50%VT 2. ( I/F No.0 CSN ) 50%VT tCSS tCCKL tCCKH CCLK 50%VT tCDH tCDS CDTI op0 op1 op2 A0 50%VT Hi-Z CDTO 3. WRITE/READ tCSW CSN 50%VT tCSH CCLK CDTI CDTO 50%VT D4 D5 D6 D7 50%VT Hi-Z 4. WRITE MS0132-J-02 2004/12 -9- ASAHI KASEI [AK4565] CSN 50%VT tCKH2 CCLK CDTI 50%VT A3 A4 50%VT tDCD Hi-Z CDTO D0 5. READ D1 D2 50%VT 1 tCSW CSN 50%VT tCSH CCLK 50%VT CDTI 50%VT tCCZ CDTO D4 D5 D6 6. READ D7 50%VT 2 tPDW PDN 50%VT tPDV SDTO 50%VT 7. MS0132-J-02 2004/12 - 10 - ASAHI KASEI [AK4565] MCLK(256fs/384fs), LRCK(fs), BCLK(32fs∼) (LRCK) MCLK 256fs 384fs (MCLK) 384fs 2/3 *fs ADC DAC (MCLK, BCLK, LRCK) PDN “L” AK4565 ”0” PDN Addr=01H 4128/fs = 86ms @ fs = 48kHz ADC ADC 2’s DAC Addr=01H MS0132-J-02 2004/12 - 11 - ASAHI KASEI [AK4565] Power Supply PDN pin “L” ADC Internal State 4128/fs PD 4128/fs PM Normal INIT GD(1) Normal INIT GD (1) GD AIN SDTO0,1 (2) (3) “0”data Idle Noise “0”data DAC Internal State PD Normal (1) PM SDTI Normal “0”data GD (1) GD (1) AOUT GD (1) (4) (4) Control register INIT-1 INIT-2 Inhibit-1 Inhibit-2 Normal INIT-2 Normal W rite to register Normal Read from register Inhibit-1 Normal External clocks (5) The clocks may be stopped. 8. • INIT : • PD: • PM: / STAT bit ADC Power Management bit • INIT-1: • INIT-2: • Inhibit-1: • Inhibit-2: “0” “1” “0” DAC All Power-down ADC “0” INIT DAC / ) “ ” (1) (GD) GD (2) (3) (4) PDN= “↓ ↑” (5) ADC ADC “0” (PDN pin = “L” or PM3-0 bit = “0”) MS0132-J-02 2004/12 - 12 - ASAHI KASEI [AK4565] HPF ADC DC -0.15dB HPF HPF 3.7Hz @ fs = 48kHz 20Hz (fs) I/F BCLK LRCK 1 DIF1,DIF0 SDTI BCLK SDTI, SDTO0,SDTO1 MSB SDTO0, SDTO1 BCLK SDTO0 SDTO1 No. 0 1 2 3 SDTO1 DMUTE bit DIF1 bit 0 0 1 1 1 DIF0 bit 0 1 0 1 1 SDTO0, SDTO1(ADC) 20bit 20bit 20bit 16bit I2S 20bit I2S 1. 4 2’s “1” “L” SDTI(DAC) 16bit 20bit 20bit 16bit I2S 20bit I2S BCLK 32fs 40fs 40fs = 32fs 40fs Default 9 10 11 12 12 LRCK(i) 0 1 2 3 9 10 11 12 13 14 15 0 1 2 9 10 11 12 13 14 15 0 1 BCLK(i:32fs) SDTO0,1(o) 19 18 17 11 10 9 8 7 6 5 4 19 18 17 11 10 9 8 7 6 5 4 19 SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 5 4 3 2 1 0 15 0 1 2 3 17 18 19 20 30 31 0 1 2 3 6 17 18 19 20 31 0 1 BCLK(i:64fs) SDTO0,1(o) SDTI(i) 19 18 17 Don’t Care 3 2 1 0 15 14 13 12 11 19 18 17 2 1 0 Don’t Care 3 2 1 0 15 14 13 12 19 11 2 1 0 SDTO0,1-19:MSB, 0:LSB SDTI-15:MSB, 0:LSB Lch Data Rch Data 9. (No.0) MS0132-J-02 2004/12 - 13 - ASAHI KASEI [AK4565] LRCK(i) 0 1 2 12 13 14 20 21 31 0 1 2 12 13 14 20 21 31 0 1 BCLK(i:64fs) SDTO0,1(o) 19 18 SDTI(i) 8 7 Don’t Care 6 0 19 18 19 18 12 11 1 8 7 Don’t Care 0 6 0 19 18 19 12 11 1 0 19:MSB, 0:LSB Lch Data Rch Data 10. (No.1) LRCK(i) 0 1 2 17 18 19 20 21 0 1 2 17 18 19 20 21 0 1 BCLK(i:64fs) SDTO0,1(o) 19 18 3 2 1 0 SDTI(i) 19 18 3 2 1 0 19:MSB, 0:LSB Don’t Care 19 18 3 2 1 0 19 18 3 2 1 0 Lch Data 19 Don’t Care 19 Rch Data 11. (No.2) LRCK(i) 0 1 2 3 17 18 19 20 21 31 0 1 2 3 17 18 19 20 21 31 0 1 BCLK(i:64fs) SDTO0,1(o) 19 18 4 3 2 1 0 SDTI(i) 19 18 4 3 2 1 0 Don’t Care 19 18 4 3 2 1 0 19 18 4 3 2 1 0 Don’t Care 19:MSB, 0:LSB 0 1 2 3 8 9 10 11 12 14 13 15 0 1 2 3 8 9 10 11 12 14 13 15 1 0 BCLK(i:32fs) SDTO0,1(o) 4 19 18 12 SDTI(i) 0 15 14 8 11 10 7 6 9 8 7 6 5 4 19 18 12 5 4 3 2 1 0 15 14 8 11 10 7 6 9 8 7 6 5 4 5 4 3 2 1 0 SDTO0,1-19:MSB, 0:LSB SDTI-15:MSB, 0:LSB Lch Data Rch Data 12. (No.3) MS0132-J-02 2004/12 - 14 - ASAHI KASEI [AK4565] ALC 1. ALC ALC IPGA L/R ATT ALC (LMAT1-0) (LMTH) IPGA IPGA L/R ZELMN = “1” LTM1-0 IPGA ALC ZELMN = “0” FR bit = “0” ALC LMTH “0” IPGA LMTH ZTM1-0 IPGA ALC ALC ZELMN bit = “0” ZTM1-0 bit ZELMN bit = “1” ALC LTM1-0 bit ALC FR bit = “1” 2. ALC ALC WTM1-0 bit (LMTH)” ZTM1-0 bit (REF6-0) WTM1-0 bit ALC (LMTH)” ALC ” Output Signal” IPGA “ALC ALC ALC IPGA (L/R ) ALC IPGA L/R “ALC ALC ” ≤ IPGA Output Signal < “ALC “ALC “ALC FR bit = “0” ” > IPGA WTM1-0 bit, ZTM1-0 bit FR bit = “1” ALC ALC IPGA ALC ALC ZTM1-0 bit ZTM1-0 > WTM1-0 ALC IPGA ALC WTM1-0 bit ALC ZTM1-0 MS0132-J-02 2004/12 - 15 - ASAHI KASEI [AK4565] ALC LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT1-0, REF6-0, ZELMN WR (Power Management Control & Signal Select) WR (ZTM1-0, WTM1-0, LTM1-0) WR (LMAT1-0, RATT1-0, LMTH) WR (REF6-0) WR (IPGA6-0) IPGA REF WR (ALC= “1”,ZELMN) ALC No ALC ? Yes WR (ALC=”0”) RD (STAT) No STAT = “1” Yes ALC 13. ALC MS0132-J-02 2004/12 - 16 - ASAHI KASEI [AK4565] FDIN bit “0” FDTM1-0 bit IPGA REF “1” IPGA FDATT ALC FDIN = FDOUT = “1” FDOUT bit IPGA ALC bit FDIN bit (5) (1) (2) (3) (4) 14. (1) WR (ALC = FDIN = “0”): ALC Disable ”0” (2) WR (IPGA = “MUTE”): IPGA MUTE (3) WR (ALC = FDIN = “1”): (4) ALC (5) FDIN bit IPGA MUTE (LMTH) ALC (REF6-0) FDTM1-0, FDATT E.g. FDTM1-0 = 32ms, FDATT = 1step (96 x FDTM1-0) / FDATT = 96 x 32ms / 1 = 3.07s MS0132-J-02 2004/12 - 17 - ASAHI KASEI [AK4565] FDOUT bit “0” “1” FDTM1-0 bit IPGA FDATT ALC MUTE IPGA FDOUT bit “0” ALC bit “0” FDOUT bit FDIN = FDOUT = “1” IPGA IPGA FDOUT bit IPGA ALC bit FDOUT bit (2) (1) (3) (4) (5) (6) (7) (8) 15. (1) WR (FDOUT = “1”): (2) FDTM1-0, FDATT bit ALC Enable E.g. FDTM1-0 = 32ms, FDATT = 1step (96 x FDTM1-0) / FDATT = 96 x 32ms / 1 = 3.07s (3) IPGA MUTE FDOUT = “1” (4) (5) WR (ALC = FDOUT = “0”): ALC (6) WR (IPGA): IPGA MUTE (7) WR (ALC = “1”, FDOUT = “0”): ALC ALC bit (8) IPGA IPGA IPGA MS0132-J-02 MUTE MUTE (ZTM1-0) 2004/12 - 18 - ASAHI KASEI [AK4565] IPGA [ALC Enable ] ALC IPGA [ALC Disable ] L/R [ALC IPGA IPGA ] ALC “1” Æ “0”) IPGA IPGA IPGA IPGA ALC IPGA IPGA [ (ALC bit ] PM0 bit = “0” IPGA PM0 bit = “0” R/W 4 8 CSN I/F I/F ) CSN CSN ”H” (3 ) CCLK (LSB 5 “↓” “↑” CDTI CDTO 3 00H ∼ 09H R/W “L” 16 CCLK “↑” op0=op1= “1” CSN I/F “↑” ) (LSB “↑” Hi-Z CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK WRITE CDTI op0 op1 op2 A0 A1 A2 A3 A4 D0 D1 D2 D3 D4 D5 D6 D7 “1” “1” “1” Hi-Z CDTO CDTI READ op0 op1 op2 A0 A1 A2 A3 A4 “1” “1” “0” Hi-Z CDTO D0 D1 D2 D3 D4 D5 D6 D7 Hi-Z op0-op2: Op code (110:READ, 111:WRITE) A0-A4: Register Address D0-D7: Control data 16. MS0132-J-02 2004/12 - 19 - ASAHI KASEI [AK4565] Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H Register Name Input Select Power Management Mode Control Timer Select ALC Mode Control 1 ALC Mode Control 2 Operation Mode Input PGA Control Test Test D7 0 0 0 D6 0 0 0 D5 0 PM3 FDTM1 FDTM0 ZTM1 D4 0 PM2 FS ZTM0 D2 EXT PM1 DIF0 WTM0 RATT1 REF2 FDIN IPGA2 0 0 D1 INT1 0 DEM1 LTM1 RATT0 REF1 0 REF4 FR IPGA4 0 0 D3 LINE 0 DIF1 WTM1 FDATT REF3 STAT IPGA3 0 0 0 D0 INT0 PM0 DEM0 LTM0 LMTH REF0 ALC IPGA0 0 0 0 0 0 0 0 0 0 REF6 0 IPGA6 0 0 LMAT1 LMAT0 REF5 D3 LINE D2 EXT D1 INT1 D0 INT0 0 0 0 1 DMUTE ZELMN IPGA5 0 FDOUT IPGA1 0 PDN pin = “L” 08H,09H WRITE 0AH 1FH Addr 00H Register Name Input Select R/W Default INT0: INT1: EXT: LINE: READ “0” D7 0 D6 0 D5 0 D4 0 0 0 0 0 R/W INTL0, INTR0 ON/OFF(0: OFF, 1: ON) INTL1, INTR1 ON/OFF(0: OFF, 1: ON) EXTL, EXTR ON/OFF (0: OFF, 1: ON) LIN, RIN ON/OFF (0:OFF, 1:ON) LINE= “1” IPGA INT1-0,EXT bit LINE bit LINE = “0” INT1-0 bit, EXT bit INT1-0, EXT ON OFF LINE= “1” LINE 1 MS0132-J-02 2004/12 - 20 - ASAHI KASEI Addr 01H [AK4565] Register Name Power Management R/W Default D7 0 D6 0 D5 PM3 D4 PM2 0 0 0 1 D3 0 D2 PM1 D1 0 D0 PM0 0 1 0 1 R/W PM0: IPGA ALC 0: Power OFF 1: Power ON (Default) PM0 = “0” IPGA Default PM1: ADC 0: Power OFF 1: Power ON (Default) PM1 = “0” 4128/fs ADC “0” PM2: DAC 0: Power OFF 1: Power ON (Default) PM3: MUX PM3 = “1” MUX AMP PDN PM2 PM3 AMP 0: DAC DAC PM2 = PM3 = “0” DAC ON MUX MIXER DAC PM3-0 bit ON/OFF(“1” / “0”) PM3-0 bit IPGA “IPGA VCOM PM bit , 1: 1 PDN PM bit PM0 bit = “0” “L” ” ”0” PM0 = PM1 = PM2 = PM3 = “0” PDN= “L” MS0132-J-02 MCLK, BCLK, LRCK 2004/12 - 21 - ASAHI KASEI [AK4565] PM3 1) All Power ON PM0: 1 PM1: 1 PM2: 1 PM3: 0 2) REC Mode PM0: 1 PM1: 1 PM2: 0 PM3: 0 3) REC monitor PM0: 1 PM1: 1 PM2: 0 PM3: 1 PM0 PM1 PM2 IPGA ALC ADC DAC PM0 PM1 PM2 IPGA ALC ADC DAC PM0 PM1 IPGA ALC ADC MUX AMP MUX AMP PM3 PM0 PM1 IPGA ALC ADC MUX AMP 4) Play PM0: 0 PM1: 0 PM2: 1 PM3: 0 PM2 DAC 5) Analog-Through Mode PM0: 1 PM1: 0 PM0 PM2: 0 IPGA PM3: 1 ALC MUX AMP PM3 MUX AMP 17. MS0132-J-02 2004/12 - 22 - ASAHI KASEI Addr 02H [AK4565] Register Name Mode Control R/W Default D7 0 D6 0 DMUTE D5 D4 FS 0 0 0 1 D3 DIF1 D2 DIF0 D1 DEM1 D0 DEM0 0 0 0 1 R/W DEM1-0: IIR 3 (32kHz, 44.1kHz, 48kHz) DEM1, DEM0 bit DEM1 DEM0 Mode 0 0 1 1 0 1 0 1 44.1kHz OFF 48kHz 32kHz (50/15µs) Default 2. DIF1-0: No. DIF1 bit 0 0 1 0 2 1 1 3 1 DIF0 bit 0 1 0 1 1 3. SDTO0,1(ADC) 20bit 20bit 20bit 16bit I2S 20bit I2S SDTI(DAC) 16bit 20bit 20bit 16bit I2S 20bit I2S BCLK 32fs 40fs 40fs = 32fs 40fs 9 10 11 12 12 Default FS: 0:fs=32kHz 1:fs=48kHz (Default) fs=32kHz, fs=48kHz ZTM1-0 bit DMUTE:SDTO1 0: SDTO1 1: SDTO1 (LTM1-0 bit) (WTM1-0 bit) FDTM1-0 bit (Default) MS0132-J-02 2004/12 - 23 - ASAHI KASEI Addr 03H [AK4565] Register Name Timer Select R/W Default LTM1-0: ALC ALC LTM1-0 bit D7 D6 FDTM1 FDTM0 D5 ZTM1 0 0 0 D4 D3 ZTM0 WTM1 R/W 0 0 Disable (ZELMN = “1”) IPGA fs=32kHz FS bit = “0” LTM0 Period 0 0 1 1 0 1 0 1 63µs 125µs 250µs 500µs D1 LTM1 D0 LTM0 0 0 1 ALC IPGA fs=48kHz LTM1 D2 WTM0 FS bit = “1” Default 4. ALC WTM1-0: ALC ALC LMTH bit ADC ADC fs=32kHz FS bit = “0” fs=48kHz WTM1 WTM0 Period 0 0 1 1 0 1 0 1 8ms 16ms 64ms 512ms FS bit = “1” Default 5. ALC ZTM1-0: ALC ALC Enable (ZELMN = “0”) ALC fs=32kHz ALC FS bit = “0” IPGA fs=48kHz ZTM1 ZTM0 Period 0 0 1 1 0 1 0 1 8ms 16ms 64ms 512ms FS bit = “1” Default 6. MS0132-J-02 2004/12 - 24 - ASAHI KASEI [AK4565] FDTM1-0: FDIN FDOUT bit IPGA L/R “1” fs=32kHz FS bit = “0” fs=48kHz FDTM1 FDTM0 Period 0 0 1 1 0 1 0 1 24ms 32ms 48ms 64ms FS bit = “1” Default 7. MS0132-J-02 2004/12 - 25 - ASAHI KASEI Addr 04H [AK4565] Register Name ALC Mode Control 1 R/W Default D7 0 D6 0 D5 D4 LMAT1 LMAT0 D3 FDATT R/W 0 0 0 0 0 D2 RATT1 D1 RATT0 D0 LMTH 0 0 0 LMTH:ALC LMTH ALC 0 1 ALC ADC Input ADC Input 8. ALC RATT1-0:ALC ALC -4.0dB > ADC Input -2.0dB > ADC Input -6.0dB -4.0dB Default GAIN IPGA 30H RATT1-0 = “01” 1dB (=0.5dB x 2) IPGA IPGA –4.0dB –2.0dB 32H IPGA RATT1 0 0 1 1 9. ALC FDATT: ALC IPGA RATT0 GAIN Step 0 1 0 1 1 2 3 4 REF6-0 Default GAIN ATT IPGA 32H IPGA IPGA FDATT = “1” or 2EH REF6-0 30H IPGA 1dB (=0.5dB x 2) 00H FDATT ATT Step 0 1 1 2 Default 10. LMAT1-0: ALC ALC IPGA IPGA ATT ATT ALC ALC IPGA = “00H” MUTE LMAT1 0 0 1 1 11. ALC IPGA (LMTH) 68H LMTH1-0 = “11” 2dB =0.5dB x 4 64H “00H” LMAT0 ATT Step 0 1 0 1 1 2 3 4 Default ATT MS0132-J-02 2004/12 - 26 - ASAHI KASEI Addr 05H [AK4565] Register Name ALC Mode Control 2 R/W Default REF6-0:ALC ALC 31H ALC D7 0 D6 REF6 D5 REF5 D4 REF4 D3 REF3 D2 REF2 D1 REF1 D0 REF0 R/W 0 28H IPGA REF6-0 IPGA0,1 L/R REF=30H, RATT=2step, IPGA=2FH ALC REF=30H IPGA 30H IPGA DATA GAIN(dB) Level +6.0 +5.5 +5.0 • -22.0 -22.5 • -29.5 -30.0 0.5dB 73 -9.0 -10.0 • -15.0 -16.0 -31.0 -32.0 • -37.0 -38.0 1dB 8 -18.0 -20.0 • -38.0 -40.0 -40.0 -42.0 • -60.0 -62.0 2dB 12 4dB 3 LINE 60H 5FH 5EH • 28H 27H • 19H 18H +28.0 +27.5 +27.0 • +0.0 -0.5 • -7.5 -8.0 17H 16H • 11H 10H 0FH 0EH • 05H 04H -44.0 -48.0 -52.0 MUTE 12. ALC -66.0 -70.0 -74.0 MUTE MS0132-J-02 2FH + 2step = REF Step MIC 03H 02H 01H 00H IPGA 1 2004/12 - 27 - ASAHI KASEI Addr 06H [AK4565] Register Name Operation Mode R/W Default D7 0 D6 0 0 0 D5 ZELMN D4 FR R/W 0 0 D3 STAT RD 0 D2 FDIN FDOUT D1 D0 ALC 0 R/W 0 0 ALC: ALC 0: ALC Disable (Default) 1: ALC Enable FDOUT: 0: 1: Disable (Default) Enable FDIN: 0: 1: Disable (Default) Enable STAT: 0: ALC 1: PDN “1” ALC FR:ALC 0: 1: (Default) “0” ALC “0” ATT/GAIN ALC “1” (Default) ALC ZELMN: ALC 0: Enable (Default) 1: Disable “0” ALC IPGA ALC “1” ALC IPGA MS0132-J-02 2004/12 - 28 - ASAHI KASEI Addr 07H [AK4565] Register Name Input PGA Control R/W Default IPGA6-0: ALC D7 0 D6 IPGA6 D5 IPGA5 0 D4 D3 IPGA4 IPGA3 R/W 28H D2 IPGA2 D1 IPGA1 D0 IPGA0 PGA 97 levels L/R IPGA IPGA “IPGA PM0 bit = “1”, REF ALC bit = “0” ” DATA GAIN(dB) Step Level +6.0 +5.5 +5.0 • -22.0 -22.5 • -29.5 -30.0 0.5dB 73 -9.0 -10.0 • -15.0 -16.0 -31.0 -32.0 • -37.0 -38.0 1dB 8 -18.0 -20.0 • -38.0 -40.0 -40.0 -42.0 • -60.0 -62.0 2dB 12 4dB 3 MIC LINE 60H 5FH 5EH • 28H 27H • 19H 18H +28.0 +27.5 +27.0 • +0.0 -0.5 • -7.5 -8.0 17H 16H • 11H 10H 0FH 0EH • 05H 04H 03H 02H 01H 00H -44.0 -48.0 -52.0 MUTE 13. -66.0 -70.0 -74.0 MUTE 1 PM0 bit = “0” MS0132-J-02 2004/12 - 29 - ASAHI KASEI [AK4565] 18 (AKD4565) 1 LOUT PDN 28 2 ROUT CCLK 27 3 INTL1 CSN 26 4 INTR1 CDTI 25 5 INTL0 CDTO 24 6 INTR0 BCLK 23 7 EXTL MCLK 22 8 EXTR LRCK 21 9 LIN SDTI 20 10 RIN SDTO1 19 11 VCOM SDTO0 18 12 AGND VT 17 13 VA DGND 16 14 VREF VD 15 AK4565 Micro Controller Audio Controller 0.1µ 2.2µ + 2.3 ∼ 3.6V Analog Supply + 0.1µ 10µ + 0.1µ 10µ 1.5 ∼ 3.6V Digital Supply + 0.1µ 10µ 10 18. : - AK4565 AGND, DGND - LOUT/ROUT MS0132-J-02 2004/12 - 30 - ASAHI KASEI [AK4565] 1. VA VA VD VT IC VD VA 10 I/F VT AGND DGND PC 2. VREF 0.1µF AGND VREF VA AGND VCOM 0.45 x VA (typ.) 2.2µF 0.1µF AGND VCOM VREF, VCOM 3. MIC VCOM typ.10k , LINE 0.6 x VREF Vpp(typ.) fc = 1/ (2 RC) AK4565 (VA-0.1V) 2’s 2 DC HPF (fc = 3.7Hz @ fs = 48kHz) typ.125k DC Vpp (ADC DC ) AK4565 64fs 64fs AK4565 64fs (RC ) 4. DAC VCOM 2’s VCOM+ mV (2 ) ∆Σ DC 0.6 x VREF Vpp(typ) ( ) DC MS0132-J-02 2004/12 - 31 - ASAHI KASEI [AK4565] 28pin VSOP (Unit: mm) 9.8±0.2(* 1) 28 5.6 15 0.15 1.15±0.10 0.10 0.05 14 1 0.22 0.10 0.05 0.08 0.12 M 0° 0.5±0.2 0.10±0.05 0.65 10° 7.6±0.2 *1 Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0132-J-02 2004/12 - 32 - ASAHI KASEI [AK4565] AKM AK4565VF XXXBYYYYC XXXBYYYYC Date code identifier XXXB : Lot number X : Digit number, B : Alpha character YYYYC : Assembly date Y : Digit number, C Alpha character • • • • • • MS0132-J-02 2004/12 - 33 -