[AK4183] AK4183 I2C Touch Screen Controller AK4183 10 12 AK4183 2.5V TMSOP I2C A/D X (4 ) /Y 12bit ADC (2.5V 3.6V) (S/H 100KHz READ (91μA@ Package 10pin TMSOP ) 400KHz ) ) XP SDA YP SCL Control XN CAD0 Logic YN PENIRQN VREF + VREF- AIN+ AIN- 12bit ADC (SAR type) PEN INTERRUPT VCC MS0500-J-01 1 GND 2008/12 [AK4183] ■ AK4183VT AK4183KT -40°C ∼ +85°C -40°C ∼ +85°C 10 10 TMSOP (0.5mm TMSOP (0.5mm ) ) ■ No. 1 2 3 4 5 6 7 8 9 10 Signal Name VCC XP YP XN YN GND PENIRQN CAD0 SDA SCL MS0500-J-01 VCC 1 10 SCL XP 2 9 SDA YP 3 8 CAD0 XN 4 7 PENIRQN YN 5 6 GND Top View I/O Description I/O Power Supply Touch Screen X+ plate Voltage supply X Y ADC Z1 ADC 10kΩ Touch Screen Y+ plate Voltage supply X ADC Y Y+ OPEN Touch Screen X- plate Voltage supply X Y OPEN X OPEN Touch Screen Y- plate Voltage supply X OPEN Y Z2 ADC GND Ground Pen Interrupt Output Enable “H” Disable “L” I2C bus Slave Address bit 0 I2C serial data I2C serial clock I/O I/O I/O O I I/O I 2 X+ Y+ X- Y- “L” 2008/12 [AK4183] (GND = 0V (Note 1)) Parameter Power Supply Input Current (any pins except for supplies) Input Voltage Touch Panel Drive Current Ambient Temperature (power supplied) Storage Temperature Symbol VCC IIN VIN IOUTDRV Ta Tstg min -0.3 -0.3 max 6.0 ±10 6.0(VCC+0.3) 50 85 150 -40 -65 Units V mA V mA °C °C Note 1. : (GND = 0V (Note 1)) Parameter Power Supplies Symbol VCC min 2.5 typ 2.7 max 3.6 Units V Note 1. : MS0500-J-01 3 2008/12 [AK4183] (Ta = -40°C to 85°C, VCC = 2.7V, I2C bus SCL=400 KHz 12 bit mode) Parameter min. ADC for Touch Screen Resolution No Missing Codes 11 Integral Nonlinearity (INL) Error Differential Nonlinearity (DNL) Error Offset Error Gain Error Throughput Rate Touch Panel Driver On-Resistance XP, YP XN, YN XP Pull Up Register (when pen interrupt enable) Power Supply Current Normal Mode PD0= “0” Fast Mode: Addressed SCL=400KHz Standard Mode: SCL=100KHz Power Down PD0= “0” Fast Mode: Not Addressed SCL=400KHz Standard Mode: SCL=100KHz Full Power Down ( PD0= ”0“ SDA=SCL= VCC) MS0500-J-01 4 typ. max. 12 12 Units 8.2 Bits Bits LSB LSB LSB LSB ksps 5 5 10 Ω Ω kΩ ±2 ±1 ±6 ±4 91 200 μA 68 150 μA 23 μA 6 μA 0 3 μA 2008/12 [AK4183] DC (Logic I/O) (Ta=-40 to 85°C, VCC = 2.5V to 3.6V) Parameter “H” level input voltage “L” level input voltage Input Leakage Current “H” level output voltage (PENIRQN pin@ Iout = -250μA) “L” level output voltage (PENIRQN pin @ Iout = 250μA) (SDA pin @ Iout = 3mA) Tri-state Leakage Current All pins except for XP, YP, XN, YN pins XP, YP, XN, YN pins Symbol VIH VIL IILK VOH typ - -10 VCC-0.4 max 0.3xVCC 10 VOL IOLK (A/C (Ta = -40 to 85°C, VCC = 2.5V to 3.6V) Parameter (I2C Timing) SCL clock frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first Clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 2) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed By Input Filter Capacitive load on bus min 0.7xVCC Symbol fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP -10 -50 Units V V μA V 0.4 V 10 50 μA μA ) min 30 1.3 0.6 1.3 0.6 0.6 0 0.1 typ max 400 50 Units kHz μs μs μs μs μs μs μs μs μs μs ns 400 pF 0.3 0.3 0.6 0 Cb Note 2. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA tSU:STO Start Stop Figure 1. AK4183 Timing Diagram MS0500-J-01 5 2008/12 [AK4183] ■ A/D 12 bit A/D A/D 12 A/D Table 1 (ΔVREF-1.5LSB)~ ΔVREF (ΔVREF-2.5LSB) ~ (ΔVREF-1.5LSB) --------0.5LSB ~ 1.5LSB 0 ~ 0.5LSB ΔVREF (VREF+) – (VREF-) Table 1. FFFH FFEH --------001H 000H ■ (X (X ΔAIN=(AIN+ ) A/D ΔVREF = VXP – VXN) (X ΔAIN = VYP – VXN) - (AIN-)) ( Rin ) 2.5μs (400KHz 600 X (ΔVREF) A/D (Rin) 1tSCL) 2 Y A/D VCC VCC X-Plate XP-Driver SW ON XP VREF+ XP Y-Plate AIN+ VREF+ YP ADC VREF- X-Plate YP-Driver SW ON AIN+ YP ADC VREF- AIN- Y-Plate AIN- XN XN XN-Driver SW ON YN YN Touch Screen YN-Driver SW ON a) X-Position Measurement Differential Mode b) Y-Position Measurement Differential Mode X-plate Y-plate XP X-Plate (Top side) XN Y-Plate (Bottom side) YN YP c) 4-wire Touch Screen Construction Figure 2. MS0500-J-01 6 2008/12 [AK4183] ■ YP VREF+ XN VREF- XP YN 2 X Rxplate Z2 Z1 Rtouch = Rxplate X X Xposition/4096 * [ (Z2/Z1) – 1] Y Rxplate, Ryplate Y Z1 Rtouch = (Rxplate*Xposition/4096)*[(4096/Z1) – 1] – Ryplate*[1 – (Yposition/4096)] VCC VCC YP-Driver SW ON YP-Driver SW ON YP XP VREF+ YP Rtouch XP AIN+ ADC VREF+ AIN+ VREF- AIN- Rtouch ADC VREF- AIN- XN XN XN-Driver SWON XN-Driver SW ON YN a) YN b) Z1-Position Measurement Z2-Position Measurement Figure 3. MS0500-J-01 7 2008/12 [AK4183] ■ I/F I2Cbus AK4183 (3.4MHz) AK4183 (100KHz) I2C (400KHz) VCC=2.5V – 3.6V CAD0 MicroProcessor 2 I C bus controller VCC Rp Rp “L” or “H” AK4183 SCL SDA PENIRQN Figure 4. Digital I/F [ SCL ] “H” SDA “H” “L” · SCL · · “H” SDA “L” “H” · (Repeated Start) SDA SCL S P start condition stop condition Figure 5. [ ] · 1 · READ MS0500-J-01 WRITE · 8 2008/12 [AK4183] [ SDA ] SCL “L” “L” “H” “H” “H” SCL “L” SDA SCL SDA · · SDA SCL data line stable; data valid change of data allowed Figure 6. I2C [ ] IC 1 IC · SDA ) SDA ( (HIGH ) “L” AK4183 WRITE · READ SDA SDA AK4183 · SDA (NACK) “H” AK4183 AK4183 SDA DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 7. I2C MS0500-J-01 9 2008/12 [AK4183] [ I2C ] Figure 10 7 “100100” IC 8 1 (Figure 8) (R/W) 6 IC CAD0 VCC CAD0 GND AK4183 R/W R/W “1” 1 0 0 1 0 Figure 8. [WRITE “0” 0 CAD0 (CAD0 R/W ) ] 2 AK4183 8 MSB first WRITE WRITE (Figure 9) AK4183 AK4183 Table 3 D5 A1 Figure 9. D3 X1 D2 PD0 D0 X2 STOP D1 MODE P Command AK4183 ACK S Address AK4183 ACK SDA D4 A0 R/W=”0” D6 A2 START D7 S Figure 10. Single Write Transmission Sequence [READ ] AK4183 READ A/D READ WRITE 2 AK4183 READ A/D READ READ WRITE READ R/W READ A/D 1 2 MS0500-J-01 8 12 A/D LSB 4bit MSB 12 A/D 10 READ AK4183 “1” 1 2 MSB 8bit A/D 4bit “0” 2008/12 [AK4183] [ READ READ R/W= “1” (ACK) (ACK) AK4183 4bit A/D STOP P MASTER NACK A/D data MASTER ACK A/D data D0 1 D4 D11 S Address AK4183 ACK SDA AK4183 LSB 8bit LSB )8 D3 (12 (NACK) R/W=”1” “0” START A/D 4bit ] Figure 11. Single A/D data Read Sequence (12-bit mode) ( READ) STOP D0 D3 MASTER ACK A/D data N+X P MASTER NACK D4 D11 A/D data N+X Address AK4183 ACK Sr R/W=”1” RESTART D0 A/D data N MASTER NACK A/D data N D3 READ D4 D11 (Figure 12) A/D MASTER ACK S Address AK4183 ACK SDA R/W=”1” ] READ A/D WRTITE START [ READ AK4183 Repeat Figure 12. Continuous A/D data Read Sequence ■ (PD0) A/D PD0=“0” MS0500-J-01 11 2008/12 [AK4183] ■ AK4183 OPEN AK4183 MODE PD0 = “0” PD0 PENIRQN (Table 2) 0111XX1X 0111XX0X MODE bit 1 0 PENIRQN Hi-z H Open Open Table 2. MODE SCL16 AD READ SDA “H” (S=“1”) ■ ADC 8bit Table 3 AK4183 BIT 7 6-4 Name S A2-A0 3 2 1 0 X1 PD0 MODE X2 Function Start Bit. “1” Accelerate and Axis Command , “0”: Sleep mode Command Channel Selection Bits. Analog inputs to the A/D converter and the activated driver switches are selected. Please see the following table for the detail. Don’t care Power down bit ( ) Resolution of A/D converter. “0”: 12 bit output “1”: 8 bit output Don’t care Input S 0 1 1 1 1 1 1 1 1 A2 1 0 0 0 0 1 1 1 1 MS0500-J-01 A1 1 0 0 1 1 0 0 1 1 SCL AK4183 Status of Driver Switch A0 1 0 1 0 1 0 1 0 1 YN ADC input (ΔAIN) XP XN YP AIN+ ON OFF OFF OFF ON OFF OFF OFF ON OFF ON ON ON OFF ON ON OFF OFF YP XN ON ON XP YN ON OFF XP XN ON OFF YN XN OFF OFF YP XN ON ON XP YN ON OFF XP(Z1) XN ON OFF YN(Z2) XN Table 3. Control Command List 12 AIN- Reference Voltage (ΔVREF) VREF+ VREFXP YP YP YP XP YP YP YP XN YN XN XN XN YN XN XN Note Sleep Accelerate X-Driver Accelerate Y-Driver Accelerate Y+,XDriver X-axis Y-axis Z1 (Pen Pressure) Z2 (Pen Pressure) 2008/12 [AK4183] ■ PD0 A/D PD0 0 Enabled A/D OFF ON YN YN GND A/D 1 Disabled ADC ON X ON ADC PENIRQN Accelerate Y AD “L” Table 4. WRITE SCL18 ON (PD0= “0”, A2= “1”) PD0= “1” ON WRITE ■ WRITE (Accelerate) AD (Figure 13) 16SCL (Figure 13) Accelerate 18SCL 0 (A2=“0”) READ ON 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PD0 19 SCL Command Byte Address Byte R/ W SDA 1 0 0 1 0 0 CAD0 0 S 0 A2 A1 A0 AK4183 ACK START Touch Driver SW A2=0, PD0=0 or 1 A2=1, PD0=1 X1 PD0 MODE X2 0 AK4183 ACK STOP A2=1, PD0=0 I II III Figure 13. MS0500-J-01 IV Driver SW 13 2008/12 [AK4183] ■ AD AD (Figure14) AD SCL Sampling hold 12SCL AD MSB 8bitAD LSB 4bitAD 4bit ”0” (STOP Condition) Repeated Start AD Repeated Start SCL7 ~SCL8 ) AD ACK NACK ( READ ) READ AD8bit MSB AD ( (MODE=“1”) (NACK) 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 0 0 27 28 SCL R/ W 1 SDA 0 0 1 0 0 CAD0 1 0 D11 D10 D9 D8 D7 D6 AK4183 ACK START Address Byte D4 0 D3 D2 D1 D0 0 0 1 MASTER NACK STOP or MASTER ACK Data Byte (MSB) Sampling D5 Repeated START Data Byte (LSB) AD conversion Touch Driver SW “H” A2=“0” or A2=“1” , PD0=“1” A2=“0”, PD0=“0” A2=“1”, PD0=“0” IV V VI Figure14. AD MS0500-J-01 14 2008/12 [AK4183] ■ A/D YN PENIRQN Figure 13 Figure14 I. II. III. IV. V. VI. PD0 = “0” XP GND PENIRQN 2 (Figure 15) Ri typ.10K XP (VCC)--- (Ri)--- (XP)---(YN) PENIRQN “L” PENIRQN (Write Read SCL “H” ) Write SCL7 PENIRQN PD0= “0” PD0 “H” “L” WRITE PD0= “1” SCL7 ~SCL8 PENIRQN “L” Write SCL8 ∼SCL18 PENIRQN PD0= “0” “L” PD0= “1” Write SCL18 ∼Read SCL7 PENIRQN A2= “0” PD0= “1” PD0= “0” Read SCL7 ~SCL21 AD “L” Read SCL21 PENIRQN PD0= “0” “L” PD0 PD0 “H” “L” A2 PD0 “L” AD A2= “1” PENIRQN PD0 PD0= “1” “L” A/D PENIRQN VCC To uP PEN Interrupt VCC Ri = 10kΩ VCC EN2 Driver OFF XP EN1 YN Driver ON Figure 15 MS0500-J-01 15 2008/12 [AK4183] 10pin TMSOP 0.5mm pitch (Unit : mm) 0~10° 2.9±0.2 6 0.127 +0.1 -0.05 0.5 5 0.10 0.2±0.1 +0.1 -0.05 1.0 Max. 1 0.55±0.2 2.8±0.2 4.0±0.2 10 ■ : : Cu : Sn - Bi MS0500-J-01 16 2008/12 [AK4183] 10pin 6pin 1 8 3 (2) 1 (AK4183=183) YM A (4) (5) (3) (1) 1pin MS0500-J-01 5pin 17 2008/12 [AK4183] Date (YY/MM/DD) 06/04/18 08/12/09 Revision 00 01 Reason Page Contents 2 AK4183KT( ) ( ) • • • • • • MS0500-J-01 18 2008/12