AK4480EF

[AK4480]
AK4480
High Performance 114dB 32-Bit DAC
AK4480
BD
32-bit DAC
32bit Digital Filter
216kHz
PCM
(SCF)
DSD
BD, SACD
• 128
•
: 30kHz ∼ 216kHz
• 32
8
- Ripple: ±0.005dB, Attenuation: 70dB
, GD=7/fs
•
•
• DSD
• 32, 44.1, 48kHz
•
•
ATT(
256
)
• Mono Mode
•
• THD+N: -100dB
• DR, S/N: 114dB (Mono mode 117dB)
•
I/F
: 24/32
, 16/20/24/32
•
30kHz ~ 32kHz: 1152fs
30kHz ~ 54kHz: 512fs or 768fs
30kHz ~ 108kHz: 256fs or 384fs
108kHz ~ 216kHz: 128fs or 192fs
•
: 4.75 ∼ 5.25V
•
: TTL
•
: 30
VSOP
MS1146-J-03
, I2S, DSD
2012/01
-1-
[AK4480]
■
DVDD
BICK/DCLK
LRCK/DSDR/WCK
SDATA/DSDL
VSS3
PDN
DINL
VSS4
VSS2
VDDL
PCM
Data
Interface
8X
Interpolator
SCF
AOUTLP
AOUTLN
DSD
Data
Interface
BCK
AVDD
DATT
Soft Mute
ΔΣ
Modulator
External
DF
Interface
Bias
Vref
SCF
VREFHL
VREFLL
VREFLR
VREFLL
AOUTRP
AOUTRN
DINR
CSN/SMUTE
Control
Register
CCLK/DEM0
VDDR
Clock
Divider
CDTI/DEM1
VSS1
CAD0/SD
CAD1/DIF0 PSN
DZFL/DIF1 DIF2
MCLK
DZFR
Block Diagram
MS1146-J-03
2012/01
-2-
[AK4480]
■
−10 ∼ +70°C
AK4480
AK4480EF
AKD4480
30pin VSOP (0.65mm pitch)
■
SMUTE/CSN
1
30
LRCK/DSDR/WCK
SD/CAD0
2
29
SDATA/DSDL/DINL
DEM0/CCLK
3
28
BICK/DCLK/BCK
DEM1/CDTI
4
27
PDN
DIF0/CAD1
5
26
DVDD
DIF1/DZFL
6
25
VSS4
DIF2/DINR
7
24
MCLK
PSN
8
23
AVDD
ACKS/DZFR
9
22
VSS3
AOUTRP
10
21
AOUTLP
AOUTRN
11
20
AOUTLN
VSS1
12
19
VSS2
VDDR
13
18
VDDL
VREFHR
14
17
VREFHL
VREFLR
15
16
VREFLL
AK4480
Top
View
MS1146-J-03
2012/01
-3-
[AK4480]
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Pin Name
I/O
SMUTE
I
CSN
SD
CAD0
DEM0
CCLK
DEM1
CDTI
DIF0
CAD1
DIF1
DZFL
DIF2
DINR
I
I
I
I
I
I
I
I
I
I
O
I
I
PSN
I
ACKS
DZFR
AOUTRP
AOUTRN
VSS1
VDDR
VREFHR
VREFLR
VREFLL
VREFHL
VDDL
VSS2
AOUTLN
AOUTLP
VSS3
AVDD
MCLK
VSS4
DVDD
I
O
O
O
I
I
I
I
O
O
I
-
Function
Soft Mute in Parallel Control Mode
When this pin goes to “H”, soft mute cycle is initiated.
When returning to “L”, the output mute releases.
Chip Select in Serial Control Mode
Digital Filter Select Pin
Chip Address 0 in Serial Control Mode
De-emphasis Enable 0 in Parallel Control Mode
Control Data Clock in Serial Control Mode
De-emphasis Enable 1 in Parallel Control Mode
Control Data Input in Serial Control Mode
Digital Input Format 0 in PCM Mode
Chip Address 1 in Serial Control Mode
Digital Input Format 1 in PCM Mode
Left Channel Zero Input Detect in Serial Control Mode
Digital Input Format 2 in PCM Mode
Rch Audio Serial Data Input in External DF Mode.
Parallel/Serial Select
(Internal pull-up pin)
“L”: Serial Control Mode, “H”: Parallel Control Mode
Clock Auto Setting Mode Pin
Rch Zero Input Detect in Serial Control Mode
Right Channel Positive Analog Output
Right Channel Negative Analog Output
Connected to VSS2/3/4 Ground
Right Channel Analog Power Supply, 4.75~5.25V
Right Channel High Level Voltage Reference Input
Right Channel Low Level Voltage Reference Input
Left Channel Low Level Voltage Reference Input
Left Channel High Level Voltage Reference Input
Left Channel Analog Power Supply, 4.75~5.25V
Ground (connected to VSS1/3/4 ground)
Left Channel Negative Analog Output
Left Channel Positive Analog Output
Ground (connected to VSS1/2/4 ground)
Analog Power Supply, 4.75 to 5.25V
Master Clock Input
Connected to VSS1/2/3 Ground
Digital Power Supply, 4.75 ∼ 5.25V
Power-Down Mode
27 PDN
I
When at “L”, the AK4480 is in power-down mode and is held in reset.
The AK4480 should always be reset upon power-up.
Note: All input pins except internal pull-up/down pins should not be left floating.
MS1146-J-03
2012/01
-4-
[AK4480]
(
No.
Pin Name
I/O
)
Function
BICK
I
Audio Serial Data Clock in PCM Mode
28 DCLK
I
Audio Serial Data Clock in DSD Mode
BCK
I
Audio Serial Data Clock in EXDF Mode
SDATA
I
Audio Serial Data Input in PCM Mode
29 DSDL
I
Lch Audio Serial Data Clock in DSD Mode
DINL
I
Lch Audio Serial Data Clock in EXDF Mode
LRCK
I
L/R Clock in PCM Mode
30 DSDR
I
Rch Audio Serial Data Input Pin in DSD Mode
WCK
I
Word Clock Pin in EXDF Mode
Note: All input pins except internal pull-up/down pins must not be left floating.
■
(1)
(PCM mode
Analog
)
AOUTLP, AOUTLN
AOUTRP, AOUTRN
(2)
1. PCM Mode
Analog
Digital
AOUTLP, AOUTLN
AOUTRP, AOUTRN
DIF2, PSN
DZFL, DZFR
VSS4
2. DSD Mode
Analog
Digital
AOUTLP, AOUTLN
AOUTRP, AOUTRN
DIF2, PSN
DZFL, DZFR
VSS4
3. Ex DF Mode
Analog
Digital
AOUTLP, AOUTLN
AOUTRP, AOUTRN
DIF2, PSN
DZFL, DZFR
MS1146-J-03
VSS4
2012/01
-5-
[AK4480]
(VSS1-4 =0V; Note 1)
Parameter
Power Supplies:
Analog
Analog
Digital
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Temperature (Power applied)
Storage Temperature
Note 1.
Note 2. VSS1-4
Symbol
AVDD
VDDL/R
DVDD
IIN
VIND
Ta
Tstg
min
−0.3
-0.3
−0.3
−0.3
−10
−65
max
6.0
6.0
6.0
±10
DVDD+0.3
70
150
Unit
V
V
V
mA
V
°C
°C
:
(VSS1-4 =0V; Note 1)
Parameter
Symbol
min
typ
max
5.25
5.0
4.75
AVDD
Analog
Power Supplies
5.25
5.0
4.75
VDDL/R
Analog
(Note 3)
5.25
5.0
4.75
DVDD
Digital
Voltage
VREFHL/R
VREFHL/R
AVDD−0.5
AVDD
Reference
VREFLL/R
VREFLL/R
VSS
(Note 4)
Note 1.
Note 3. AVDD, VDDL/R, DVDD
Note 4. VREFLL/R pin VSS
(VREFH − VREFL)
AOUT ([email protected]) = (AOUT+) − (AOUT−) = ±2.4Vpp × (VREFHL/R − VREFLL/R)/5.
Unit
V
V
V
V
V
:
MS1146-J-03
2012/01
-6-
[AK4480]
(Ta=25°C; AVDD=VDDL/R=DVDD=5.0V; VSS1-4 =0V; VREFHL/R=AVDD, VREFLL/R= VSS;
Input data = 24bit; RL ≥ 1kΩ; BICK=64fs; Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz;
Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 20; unless otherwise specified.)
Parameter
min
typ
max
Resolution
32
Dynamic Characteristics
(Note 5)
0dBFS
-100
-93
fs=44.1kHz
THD+N
BW=20kHz
−60dBFS
-51
0dBFS
97
fs=96kHz
BW=40kHz
−60dBFS
-48
0dBFS
97
fs=192kHz
BW=40kHz
−60dBFS
-48
BW=80kHz
-45
−60dBFS
Dynamic Range (−60dBFS with A-weighted)
(Note 6)
108
114
S/N (A-weighted)
(Note 7)
108
114
Interchannel Isolation (1kHz)
100
110
DC Accuracy
Interchannel Gain Mismatch
0
0.3
Gain Drift
(Note 8)
20
Output Voltage
(Note 9)
±2.25
±2.4
±2.55
Load Capacitance
25
Load Resistance
(Note 10)
2
-
Unit
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
ppm/°C
Vpp
pF
kΩ
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
AVDD + VDDL/R
30
45
mA
15
mA
DVDD (fs ≤ 96kHz)
24
36
mA
DVDD (fs = 192kHz)
Power down (PDN pin = “L”)
(Note 11)
AVDD+VDDL/R+DVDD
10
100
μA
Note 5. Audio Precision System Two
Note 6. Figure 20 (
2)
100dB at 16bit data.
Note 7. Figure 20 (
2)
S/N
Note 8. (VREFH − VREFL)
+5V
Note 9.
(0dB)
(VREFHL/R − VREFLL/R)
AOUT ([email protected]) = (AOUT+) − (AOUT−) = ±2.4Vpp × (VREFHL/R − VREFLL/R)/5.
Note 10. Load Resistance
AC
(DC
)
2k ohm (min)
Figure 20
DC
4k ohm (min)
Figure 19
Load Resistance
Note 11.
P/S pin = DVDD
VSS4
(MCLK, BICK, LRCK)
MS1146-J-03
2012/01
-7-
[AK4480]
(fs = 44.1kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SLOW bit = “0”,
SD bit=“0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband (Note 12)
PB
0
20.0
kHz
Frequency Response
±0.05dB
0
20.0
kHz
−6.0dB
22.05
kHz
Stopband
(Note 12)
SB
24.1
kHz
Passband Ripple
PR
-0.005
+0.0001
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 13)
GD
27
1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 20.0kHz
-0.2
+0.2
dB
(fs = 96kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SLOW bit = “0”,
SD bit=“0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband (Note 12)
PB
0
43.5
kHz
Frequency Response
±0.05dB
0
43.5
kHz
−6.0dB
48.0
kHz
Stopband
(Note 12)
SB
52.5
kHz
Passband Ripple
PR
-0.005
+0.0001
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 13)
GD
27
1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 40.0kHz
-0.3
+0.3
dB
(fs = 192kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit = “0”, SD
bit=“0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 12)
PB
0
87.0
kHz
Frequency Response
±0.05dB
0
87.0
kHz
−6.0dB
96.0
kHz
Stopband
(Note 12)
SB
105
kHz
Passband Ripple
PR
-0.005
+0.0001
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 13)
GD
27
1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 80.0kHz
-1
+0.1
dB
Note 12.
fs(
)
PB = 0.4535 × fs(@±0.01dB) SB =
0.546 × fs
Note 13.
16/20/24/32
MS1146-J-03
2012/01
-8-
[AK4480]
(fs = 44.1kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SLOW bit=“1”,
SD bit = “0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 14)
PB
0
8.1
kHz
Frequency Response
±0.07dB
0
8.1
kHz
−3.0dB
18.2
kHz
Stopband
(Note 14)
SB
39.2
kHz
Passband Ripple
PR
-0.07
+0.02
dB
Stopband Attenuation
SA
73
dB
Group Delay
(Note 13)
GD
27
1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 20.0kHz
-5
+0.1
dB
(fs = 96kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode DEM=OFF; SLOW bit=“1”, SD
bit = “0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 14)
PB
0
17.7
kHz
Frequency Response
±0.07dB
0
17.7
kHz
−3.0dB
39.6
kHz
Stopband
(Note 14)
SB
85.3
kHz
Passband Ripple
PR
-0.07
+0.02
dB
Stopband Attenuation
SA
73
dB
Group Delay
(Note 13)
GD
27
1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 40.0kHz
-4
+0.1
dB
(fs = 192kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit=“1”, SD
bit = “0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 14)
PB
0
35.5
kHz
Frequency Response
±0.07dB
0
35.5
kHz
−3.0dB
79.1
kHz
Stopband
(Note 14)
SB
171
kHz
Passband Ripple
PR
-0.07
+0.02
dB
Stopband Attenuation
SA
73
dB
Group Delay
(Note 13)
GD
27
1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 80.0kHz
-5
+0.1
dB
Note 14.
fs(
)
PB = 0.185 × fs(@±0.04dB)
SB = 0.888 × fs
MS1146-J-03
2012/01
-9-
[AK4480]
(fs = 44.1kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SLOW bit = “0”,
SD bit=“1”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 14) ±0.01dB
PB
0
20.0
kHz
Frequency Response
±0.06dB
0
20.0
kHz
−6.0dB
22.05
kHz
Stopband
(Note 14)
SB
24.1
kHz
Passband Ripple
PR
-0.0052
+0.0006
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 13)
GD
7
1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 20.0kHz
-0.2
+0.2
dB
(fs = 96kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SLOW bit = “0”,
SD bit=“1”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 14) ±0.01dB
PB
0
43.5
kHz
Frequency Response
±0.06dB
0
43.5
kHz
−6.0dB
48.0
kHz
Stopband
(Note 14)
SB
52.5
kHz
Passband Ripple
PR
-0.0052
+0.0006
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 13)
GD
7
1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 40.0kHz
-0.3
+0.3
dB
(fs = 192kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit = “0”, SD
bit=“1”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 14) ±0.01dB
PB
0
87.0
kHz
Frequency Response
±0.06dB
0
87.0
kHz
−6.0dB
96.0
kHz
Stopband
(Note 14)
SB
105
kHz
Passband Ripple
PR
-0.0052
+0.0006
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 13)
GD
7
1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 80.0kHz
-1
+0.1
dB
MS1146-J-03
2012/01
- 10 -
[AK4480]
DC
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
2.2
Low-Level Input Voltage
VIL
High-Level Output Voltage
(Iout=−100μA)
VOH
DVDD−0.5
Low-Level Output Voltage
(Iout=100μA)
VOL
Input Leakage Current
(Note 15)
Iin
Note 15. TST1/CAD0 pin
, P/S pin
TST1/CAD0 pin, P/S pin
MS1146-J-03
typ
max
0.8
0.5
±10
(typ. 100kΩ)
Unit
V
V
V
V
μA
2012/01
- 11 -
[AK4480]
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)
Parameter
Symbol
min
Master Clock Timing
Frequency
fCLK
7.7
Duty Cycle
dCLK
40
LRCK Frequency
(Note 16)
1152fs, 512fs or 768fs
fsn
30
256fs or 384fs
fsd
54
128fs or 192fs
fsq
108
Duty Cycle
Duty
45
PCM Audio Interface Timing
BICK Period
1/128fsn
tBCK
1152fs, 512fs or 768fs
1/64fsd
tBCK
256fs or 384fs
1/64fsq
tBCK
128fs or 192fs
30
tBCKL
BICK Pulse Width Low
30
tBCKH
BICK Pulse Width High
20
tBLR
BICK “↑” to LRCK Edge
(Note 17)
20
tLRB
LRCK Edge to BICK “↑”
(Note 17)
20
tSDH
SDATA Hold Time
20
tSDS
SDATA Setup Time
External Digital Filter Mode
BICK Period
BCK Pulse Width Low
BCK Pulse Width High
BCK “↑” to WCK Edge
WCK Edge to BCK “↑”
WCK Pulse Width Low
WCK Pulse Width High
DATA Hold Time
DATA Setup Time
DSD Audio Interface Timing
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R
(Note 18)
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Reset Timing
PDN Pulse Width
(Note 19)
typ
max
Unit
41.472
60
MHz
%
54
108
216
55
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tB
tBL
tBH
tBW
tWB
tWCK
tWCH
tDH
tDS
27
10
10
5
5
54
54
5
5
tDCK
tDCKL
tDCKH
tDDD
160
160
−20
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
50
50
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
tPD
150
ns
MS1146-J-03
1/64fs
-
20
ns
ns
ns
ns
2012/01
- 12 -
[AK4480]
Note 16. 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs
Note 17.
Note 18.
Note 19.
LRCK
PDN pin
RSTN bit
BICK “↑”
PDN pin “L”
“H”
■
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
1/fs
VIH
WCK
VIL
tB
VIH
BCK
VIL
tBH
tBL
Clock Timing
MS1146-J-03
2012/01
- 13 -
[AK4480]
VIH
LRCK
VIL
tLRB
tBLR
VIH
BICK
VIL
tSDH
tSDS
VIH
SDATA
VIL
Audio Interface Timing (PCM Mode)
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”)
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)
MS1146-J-03
2012/01
- 14 -
[AK4480]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
C1
CDTI
tCDH
C0
R/W
VIH
A4
VIL
WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
WRITE Data Input Timing
MS1146-J-03
2012/01
- 15 -
[AK4480]
tPD
PDN
VIL
Power Down & Reset Timing
VIH
WCK
VIL
tBW
tWB
VIH
BCK
VIL
tDS
tDH
VIH
DATA
VIL
External Digital Filter I/F mode
MS1146-J-03
2012/01
- 16 -
[AK4480]
■ D/A
AK4480
DSDR
PCM
DSD
D/A
DSD mode
PCM mode
BICK, LRCK, SDATA
D/P bit
D/P bit PCM/DSD mode
2 ~ 3/fs
PCM
DSD
DCLK, DSDL,
PCM
RSTN bit
D/P bit
Interface
0
PCM
1
DSD
Table 1. PCM/DSD Mode Control
I/F
DP bit= “0”
Digital Filter
Digital Filter I/F
(EX DF I/F mode)
MCLK, BCK, WCK, DINL, DINR
EXDF bit
EXDF bit
Digital Filter
Digital Filter I/F
2 ~ 3/fs
Digital Filter
RSTN bit
Ex DF bit
Interface
0
PCM
1
EX DF I/F
Table 2. Digital Filter Control (DP bit = “0”)
■
[1] PCM mode
AK4480
(Table 4)
= “H”)
(Table 6)
AVDD/2
ON
MCLK, BICK, LRCK
MCLK LRCK
MCLK
ΔΣ
MCLK
(Manual Setting Mode)
(Auto Setting Mode)
Manual Setting Mode (ACKS pin = “L”, Normal Speed mode)
MCLK
(RSTN pin = “↑”) Auto Setting Mode
Auto Setting Mode (ACKS pin
MCLK
(Table 5)
MCLK
(typ)
MCLK
LRCK
LRCK
MCLK
(1)
AK4480
MCLK LRCK
Table 3
(P/S pin = “H”)
1. Manual Setting Mode (ACKS pin = “L”)
MCLK
Table 3
DFS1 bit
“0”
4
MS1146-J-03
2012/01
- 17 -
[AK4480]
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
MCLK (MHz)
BICK
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
64fs
N/A
N/A
8.1920
12.2880
16.3840
24.5760
36.8640
2.0480MHz
N/A
N/A
11.2896
16.9344
22.5792
33.8688
N/A
2.8224MHz
N/A
N/A
12.2880
18.4320
24.5760
36.8640
N/A
3.0720MHz
11.2896
16.9344
22.5792
33.8688
N/A
N/A
N/A
5.6448MHz
12.2880
18.4320
24.5760
36.8640
N/A
N/A
N/A
6.1440MHz
Table 3. System Clock Example (Manual Setting Mode @Parallel Mode)(N/A: Not available)
32kHz~96kHz
MCLK= 256fs/384fs
DR, S/N
(Table 4)
MCLK= 512fs/768fs
32kHz~48kHz
3dB
ACKS pin
MCLK
DR,S/N
L
256fs/384fs/512fs/768fs
114dB
H
256fs/384fs
111dB
H
512fs/768fs
114dB
Table 4. MCLK
DR, S/N
(fs = 44.1kHz)
2. Auto Setting Mode (ACKS pin = “H”)
(Table 5)
MCLK
MCLK
Table 6
MCLK
Sampling Speed
1152fs
Normal (fs≤32kHz)
512fs/256fs
768fs/384fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
Table 5. Sampling Speed (Auto Setting Mode @Parallel Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
MCLK (MHz)
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
N/A
N/A
8.1920
12.2880
16.3840
24.5760
36.8640
N/A
N/A
11.2896
16.9344
22.5792
33.8688
N/A
N/A
N/A
12.2880
18.4320
24.5760
36.8640
N/A
N/A
N/A
22.5792
33.8688
N/A
N/A
N/A
N/A
N/A
24.5760
36.8640
N/A
N/A
N/A
22.5792
33.8688
N/A
N/A
N/A
N/A
N/A
24.5760
36.8640
N/A
N/A
N/A
N/A
N/A
Table 6. System Clock Example (Auto Setting Mode @Parallel Mode) (N/A: Not available)
MCLK= 256fs/384fs
32kHz~48kHz
3dB
Auto Setting Mode 32kHz~96kHz
MCLK= 256fs/384fs
DR, S/N
Sampling
Speed
Normal
Double
Quad
(Table 7)
MCLK= 512fs/768fs
ACKS pin
MCLK
DR,S/N
L
256fs/384fs/512fs/768fs
114dB
H
256fs/384fs
111dB
H
512fs/768fs
114dB
Table 7. MCLK
DR, S/N
(fs = 44.1kHz)
MS1146-J-03
2012/01
- 18 -
[AK4480]
(2)
(P/S pin = “L”)
1. Manual Setting Mode (ACKS bit = “0”)
MCLK
MCLK
Table 9
→ “H”) Manual Setting Mode
(Table 8)
(PDN pin = “L”
DFS1-0 bit
DFS1-0 bit
RSTN bit
DFS1 bit DFS0 bit
Sampling Rate (fs)
(default)
0
0
Normal Speed Mode
30kHz ∼ 54kHz
0
1
Double Speed Mode
54kHz ∼ 108kHz
1
0
Quad Speed Mode
120kHz ∼ 216kHz
Table 8. Sampling Speed (Manual Setting Mode @Serial Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
N/A
N/A
N/A
11.2896
12.2880
22.5792
24.5760
MCLK (MHz)
192fs
256fs
384fs
512fs
768fs
1152fs
N/A
8.1920
12.2880
16.3840
24.5760
36.8640
N/A
11.2896
16.9344
22.5792
33.8688
N/A
N/A
12.2880
18.4320
24.5760
36.8640
N/A
16.9344
22.5792
33.8688
N/A
N/A
N/A
18.4320
24.5760
36.8640
N/A
N/A
N/A
33.8688
N/A
N/A
N/A
N/A
N/A
36.8640
N/A
N/A
N/A
N/A
N/A
Table 9. System Clock Example (Manual Setting Mode @Serial Mode)
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
5.6448MHz
6.1440MHz
11.2896MHz
12.2880MHz
2. Auto Setting Mode (ACKS bit = “1”)
(Table 10)
MCLK
MCLK
DFS1-0 bit
Table 11
MCLK
Sampling Speed
1152fs
Normal (fs≤32kHz)
512fs/256fs
768fs/384fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
Table 10. Sampling Speed (Auto Setting Mode @Serial Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
MCLK (MHz)
192fs
256fs
384fs
512fs
768fs
1152fs
N/A
8.1920
12.2880
16.3840
24.5760
36.8640
N/A
11.2896
16.9344
22.5792
33.8688
N/A
N/A
12.2880
18.4320
24.5760
36.8640
N/A
N/A
22.5792
33.8688
N/A
N/A
N/A
N/A
24.5760
36.8640
N/A
N/A
N/A
33.8688
N/A
N/A
N/A
N/A
N/A
36.8640
N/A
N/A
N/A
N/A
N/A
Table 11. System Clock Example (Auto Setting Mode @Serial Mode)
MS1146-J-03
Sampling
Speed
Normal
Double
Quad
2012/01
- 19 -
[AK4480]
MCLK= 256fs/384fs
32kHz~48kHz
3dB
Auto Setting Mode 32kHz~96kHz
MCLK= 256fs/384fs
DR, S/N
(Table 12)
MCLK= 512fs/768fs
ACKS bit
MCLK
DR,S/N
0
256fs/384fs/512fs/768fs
114dB
1
256fs/384fs
111dB
1
512fs/768fs
114dB
Table 12. MCLK
DR, S/N
(fs = 44.1kHz)
[2] DSD mode
MCLK
MCLK, DCLK
DCKS bit
(PDN pin = “H”)
AVDD/2
(typ)
MCLK
DCKS bit
0
1
MCLK
DCLK
AK4480
MCLK Frequency
DCLK Frequency
512fs
64fs
768fs
64fs
Table 13. System Clock (DSD Mode)
MS1146-J-03
(default)
2012/01
- 20 -
[AK4480]
■
[1] PCM mode
BICK LRCK
SDATA
DIF2-0 bit
DIF2-0 pin
2’s
20
BICK
“0”
LSB
Mode
0
1
2
3
4
5
6
7
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
(Table 14)
MSB
Mode 2 16
8
DIF0
Input Format
BICK
0
16bit
≥ 32fs
1
20bit
≥ 48fs
0
24bit
≥ 48fs
1
24bit I2S
≥ 48fs
0
24bit
≥ 48fs
1
32bit
≥ 64fs
0
32bit
≥64fs
2
1
32bit I S
≥ 64fs
Table 14. Audio Interface Format
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
Figure 5
Figure 6
Figure 7
(default)
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDATA
Mode 0
15
0
14
6
1
5
14
4
15
3
2
16
17
1
0
31
15
0
14
6
5
14
1
4
15
3
16
2
17
1
0
31
15
14
0
1
0
1
BICK
(64fs)
SDATA
Mode 0
Don’t care
15
14
15
Don’t care
0
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
BICK
(64fs)
SDATA
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDATA
Mode 4
Don’t care
23
22
21
20
23
22
21
20
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1/4 Timing
MS1146-J-03
2012/01
- 21 -
[AK4480]
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDATA
23 22
1
0
Don’t care
23 22
0
1
Don’t care
23
22
0
1
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
BICK
(64fs)
SDATA
1
23 22
0
Don’t care
23 22
0
1
23
Don’t care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
LRCK
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
BICK(128fs)
SDATA
31
0
1
2
12
13
14
23
1
24
0
31
31
0
1
2
12
13
14
23
1
24
0
31
0
1
BICK(64fs)
SDATA
31 30
20 19 18
9
8
1
0
31 30
Lch Data
20
19 18
9
8
1
0
31
Rch Data
31: MSB, 0:LSB
Figure 5. Mode 5 Timing
MS1146-J-03
2012/01
- 22 -
[AK4480]
LRCK
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
BICK(128fs)
SDATA
31 30
0
1
12 11 10
2
12
13
0
14
31 30
23
24
31
0
1
12
2
11 10
12
13
0
14
31
23
24
31
0
1
BICK(64fs)
SDATA
31 30
20 19 18
8
9
0
1
31 30
20
19 18
Lch Data
8
9
0
1
31
Rch Data
31: MSB, 0:LSB
Figure 6. Mode 6 Timing
LRCK
0
1
2
20
21
22
33
34
63
0
1
2
20
21
22
33
34
63
24
25
31
0
1
BICK(128fs)
SDATA
31
0
1
13 12 11
2
12
0
13
14
31
24
25
31
0
1
13
2
12 11
12
0
13
14
0
1
BICK(64fs)
SDATA
0
31
21 20 19
8
9
1
2
0
31
21
20 19
Lch Data
9
8
2
1
0
Rch Data
31: MSB, 0:LSB
Figure 7. Mode 7 Timing
[2] DSD mode
DSD
DIF2-0 pin
DIF2-0 bit
DCLK
64fs
DCLK
DCKB bit
DCLK (64fs)
DCKB=1
DCLK (64fs)
DCKB=0
DSDL,DSDR
Normal
D0
DSDL,DSDR
Phase Modulation
D0
D1
D1
D2
D1
D2
D3
D2
D3
Figure 8. DSD Mode Timing
MS1146-J-03
2012/01
- 23 -
[AK4480]
[3]
(EX DF I/F mode)
DW WCK1
BCK
MCLK, BCK
WCK
(Table 16) DIF2-0bit
BCK, MCLK
MCLK BCK
Table 17
Sampling
Speed[kHz]
44.1(30~54)
44.1(30~54)
96(54~108)
96(54~108)
192(108~216)
192(108~216)
DINL, DINR
BCK
3
BCK
MCLK&BCK [MHz]
128fs
N/A
384fs
N/A
512fs
768fs
22.5792
33.8688
48
11.2896
32
16.9344
32
N/A
33.8688
N/A
24.576
36.864
N/A
96
N/A
48
12.288
32
18.432
32
N/A
36.864
N/A
N/A
24.576
36.864
N/A
96
N/A
N/A
N/A
32
N/A
48
N/A
N/A
N/A
N/A
N/A
N/A
192fs
N/A
N/A
256fs
N/A
WCK
48
36.864
48
96
Table 15. System Clock Example (EX DF I/F mode)
16fs
DW
8fs
DW
8fs
DW
4fs
DW
4fs
DW
2fs
DW
MCLK
ECS
0
(default)
1
0
1
0
1
Mode
DIF2
DIF1
DIF0
Input Format
0
0
0
0
16bit
1
0
0
1
N/A
2
0
1
0
N/A
3
0
1
1
N/A
4
1
0
0
24bit
5
1
0
1
(default)
32bit
6
1
1
0
N/A
7
1
1
1
N/A
Table 16. Audio Interface Format (EX DF I/F mode) (N/A: Not available)
MS1146-J-03
2012/01
- 24 -
[AK4480]
1/16fs or 1/8fs or 1/4fs or 1/2fs
WCK
0
1
8
9
10
11
16
17
26
27
28
29
30
31
0
1
BCK
DINL or
DINR
31
0
30
1
24 23
5
22
6
21
7
20
8
17
16
47
15
48
14
6
5
65
49
4
3
92
2
93
1
94
0
95
0
1
BCK
DINL or
DINR
Don’t care
0
1
Don’t care
5
6
7
Don’t care
8
23
24
31
17
25
44
1
2
3
45
46
0 Don’t care
47
0
1
BCK
DINL or
DINR
Don’t care
Don’t care
Don’t care
31
3
2
1
0
Don’t care
Figure 9. EX DF I/F Mode Timing
MS1146-J-03
2012/01
- 25 -
[AK4480]
■ D/A
RSTN bit
≥4/fs
D/A Mode
PCM Mode
DSD Mode
≥0
D/A Data
PCM Data
DSD Data
Figure 10. D/A Mode Switching Timing (PCM to DSD)
RSTN bit
D/A Mode
DSD Mode
PCM Mode
≥4/fs
D/A Data
PCM Data
DSD Data
Figure 11. D/A Mode Switching Timing (DSD to PCM)
Note. DSD mode
DSD
25%
75%
SACD
(Scarlet Book)
■
IIR
3
(32kHz, 44.1kHz, 48kHz)
256fs/384fs 128fs/192fs
PCM mode DSD mode
DEM1
0
0
1
1
■
OFF
(50/15μs
DSD mode
)
DEM1-0 bit
DEM0
Mode
0
44.1kHz
1
OFF
(default)
0
48kHz
1
32kHz
Table 17. De-emphasis Control
(PCM, DSD)
AK4480 MUTE
DAC
255
(ATT)
0dB
−48dB
Sampling Speed
1 Level
255 to 0
Normal Speed Mode
4LRCK
1020LRCK
Double Speed Mode
8LRCK
2040LRCK
Quad Speed Mode
16LRCK
4080LRCK
DSD Mode
4LRCK
1020LRCK
Table 18. ATT Transition Time
MS1146-J-03
2012/01
- 26 -
[AK4480]
■
(PCM, DSD)
AK4480
DZF pin
DZF pin “L”
“1”
“L”
pin
DZFM bit
DZF pin “H”
“L”
DZF pin
■
AK4480
“H”
RSTN bit “0”
“0”
“1”
DZFE bit
8192
“0”
“0”
DZF pin “H”
RSTN bit
DZF pin 4 ∼ 5LRCK
8192
“0”
DZF
DZFB bit
(PCM, DSD, Ex DF I/F)
MONO bit SELLR bit
MONO bit
0
0
1
1
SELLR bit
0
1
0
1
Lch Out
Lch In
Rch In
Lch In
Rch In
Rch Out
Rch In
Lch In
Lch In
Rch In
Table 19. MONO Mode Output Select
MS1146-J-03
2012/01
- 27 -
[AK4480]
■
(PCM, DSD)
ATT
× ATT
SMUTE bit “0”
ATT
“L”
SMUTE pin “H”
−∞ (“0”)
−∞
ATT
−∞
SMUTE bit “1”
× ATT
SMUTE pin
ATT
−∞
ATT
S M U T E pin or
S M U T E bit
(1)
(1)
AT T _Level
(3)
A ttenuation
-∞
GD
(2)
GD
(2)
AOUT
(4)
8192/fs
D ZF pin
(1) ATT
× ATT
(2)
(3)
Normal Speed Mode
ATT
“255”
1020LRCK
(GD)
−∞
ATT
(4)
8192
“0”
“0”
DZF pin “H”
DZF pin “L”
Figure 12. Soft Mute Function
■
ON
PDN pin
“L”
MCLK
MCLK 4/fs
MS1146-J-03
2012/01
- 28 -
[AK4480]
■
ON/OFF
AK4480 PDN pin “L”
(Hi-Z)
RSTN bit “0” DAC
VCML/R
PDN
RSTN
Power
PDN pin
(1)
Internal
State
Normal Operation
DAC In
(Digital)
“0”data
“0”data
GD
DAC Out
(Analog)
Reset
(3)
(2)
GD
(4)
(4)
(3)
(5)
Clock In
MCLK,LRCK,BICK
Don’t care
Don’t care
(7)
DZFL/DZFR
External
Mute
Notes:
(1)
(2)
(3)
(4) PDN
(5)
(6)
(7)
(6)
Mute ON
Mute ON
PDN pin
“L”
150ns
PDN pin
“L”
(GD)
Hi-Z
(“↓ ↑”)
“0”
(PDN pin = “L”)
(MCLK, BICK, LRCK)
(3)
(PDN pin = “L”)
DZFL/R pin “L”
Figure 13. Power-down/up Sequence Example
MS1146-J-03
2012/01
- 29 -
[AK4480]
■
(1) RSRN bit
RSTN bit “0”
VCML/R
DAC
DZFL/DZFR pin
“H”
Figure 14
RSTN bit
RSTN bit
3~4/fs (5)
2~3/fs (5)
Internal
RSTN bit
Internal
State
Normal Operation
Normal O peration
D igital Block
P
D/A In
(Digital)
d
“0 ” data
(1)
GD
GD
(3)
D/A Out
(Analog)
(2)
(3)
(1)
2/ fs(4)
DZF
(6)
(1)
(2) RSTN bit = “0”
(3)
RSTN
(GD)
VCOM
(“↓ ↑”)
(4) DZF pin RSTN bit
“L”
(5) RSTN bit
(6)
“0”
“H”
LSI
RSTN bit
2 ~ 3/fs
(3)
Hi-Z
(2)
LSI
RSTN bit
2/fs
3 ~4/fs
Figure 14.
MS1146-J-03
2012/01
- 30 -
[AK4480]
(2) MCLK
LRCK/WCK
PCM mode
(RSTN pin = “H”)
MCLK
MCLK
DSD mode
MCLK WCK
LRCK
(Hi-Z)
LRCK
AK4480
LRCK
MCLK
MCLK
AVDD pin
DVDD pin
(1)
RSTB pin
Internal
State
Power-down
D/A In
(Digital)
Power-down
Normal Operation
Normal Operation
(3)
GD
D/A Out
(Analog)
Digital Circuit Power-down
(2)
GD
(4)
Hi-Z
(2)
(4)
(5)
(4)
(5)
Clock In
MCLK, LRCK Stop
MCLK, LRCK
External
MUTE
Notes:
(1)
(2)
(3)
(6)
PDN pin
(6)
“L”
(6)
150ns
PDN pin
“L”
(GD)
0
MCLK, LRCK
(4) PDN pin
(5)
(“↑”)
“0”
(MCLK
(6)
MCLK
LRCK/WCK
3~4LRCK
)
(MCLK, BICK, LRCK/WCK)
(4)
Figure 15
Figure 15.
MS1146-J-03
2012/01
- 31 -
[AK4480]
■
AK4480
(
)
(
)
PSN pin
PSN pin “L”
3
I/F pin: CSN, CCLK, CDTI
I/F
Chip address (2bit, C1/0), Read/Write (1bit, “1”
, Write only), Register address (MSB
first, 5bit) Control data (MSB first, 8bit)
CCLK “↓”
“↑”
CSN “↑”
CCLK
5MHz (max)
PDN pin AK4480
Function
Parallel Control Mode Serial Control Mode
Audio Format
Y
Y
Auto Setting Mode
Y
De-emphasis
Y
Y
SMUTE
Y
Y
DSD Mode
Y
EX DF I/F
Y
Zero Detection
Y
Sharp Roll off filter
Y
Y
Slow Roll off filter
Y
Minimum delay Filter
Y
Y
Digital Attenuator
Y
Table 20. Function List (Y: Available, -: Not available)
PDN pin “L”
RSTN bit
“0”
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin)
R/W:
READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 16. Control I/F Timing
*AK4480
*PDN pin = “L”
*CSN
“L”
CCLK
“↑” 15
17
MS1146-J-03
2012/01
- 32 -
[AK4480]
PCM
Attenuation Level
0dB
Disable
16fs(fs=44.1kHz)
24bit
Disable
Separated
Sharp roll-off filter
OFF
Normal Operation
PCM mode
512fs
03H
04H
00H
00H
00H
01H
01H
01H
01H
01H
02H
02H
External Digital Filter I/F Mode
Ex DF I/F mode clock setting
Audio Data Interface Modes
Data Zero Detect Enable
Data Zero Detect Mode
Minimum delay Filter Enable
De-emphasis Response
Soft Mute Enable
DSD/PCM Mode Select
Master Clock Frequency Select at
DSD mode
MONO mode Stereo mode select
Inverting Enable of DZF
The data selection of L channel and
R channel
Stereo
“H” active
R channel
02H
02H
02H
ATT7-0
DSD
Ex DF I/F
Y
Y
-
EXDF
ESC
DIF2-0
DZFE
DZFM
SD
DEM1-0
SMUTE
DP
DCKS
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
Y
-
MONO
DZFB
SELLR
Y
Y
Y
Y
Y
-
Y
Y
Y
(Y: Available, -: Not available)
Table 21.
MS1146-J-03
2012/01
- 33 -
[AK4480]
■
Addr
00H
01H
02H
03H
04H
05H
Register Name
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
Control 4
D7
ACKS
DZFE
DP
ATT7
ATT7
INVL
D6
EXDF
DZFM
0
ATT6
ATT6
INVR
D5
ECS
SD
DCKS
ATT5
ATT5
0
D4
0
DFS1
DCKB
ATT4
ATT4
0
D3
DIF2
DFS0
MONO
ATT3
ATT3
0
D2
DIF1
DEM1
DZFB
ATT2
ATT2
0
D1
DIF0
DEM0
SELLR
ATT1
ATT1
0
D0
RSTN
SMUTE
SLOW
ATT0
ATT0
0
Note:
06H ∼ 1FH
PDN pin “L”
RSTN bit “0”
PSN pin
PDN pin AK4480
■
Addr Register Name
00H Control 1
Default
D7
ACKS
0
D6
EXDF
0
D5
ECS
0
D4
0
0
D3
DIF2
0
D2
DIF1
1
D1
DIF0
0
D0
RSTN
1
RSTN: Internal Timing Reset
0: Reset. All registers are not initialized.
1: Normal Operation (default)
“0”
DIF2-0: Audio Data Interface Modes (Table 14)
“010” (Mode2: 24bit
)
ECS: Ex DF I/F mode clock setting (Table 15)
0: BCK 32fs setting. MCLK, BCK are 512fs, 256fs and 128fs (default)
1: No BCK 32fs setting. MCLK, BCK are 768fs, 384fs and 192fs.
EXDF: External Digital Filter I/F Mode (PCM only)
0: Disable: Internal Digital Filter mode (default)
1: Enable: External Digital Filter mode
ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only)
0: Disable: Manual Setting Mode (default)
1: Enable: Auto Setting Mode
ACKS bit “1”
MCLK
MS1146-J-03
2012/01
- 34 -
[AK4480]
Addr Register Name
01H Control 2
Default
D7
DZFE
0
D6
DZFM
0
D5
SD
1
D4
DFS1
0
D3
DFS0
0
D2
DEM1
0
D1
DEM0
1
D0
SMUTE
0
SMUTE: Soft Mute Enable
0: Normal Operation (default)
1: DAC outputs soft-muted.
DEM1-0: De-emphasis Response (Table 17)
“01” (OFF)
SD:
Minimum delay Filter Enable
0: Sharp roll-off filter
1: Minimum delay filter (default)
SD
0
0
1
1
DFS1-0:
DZFM:
DZFE:
SLOW
Mode
0
Sharp roll-off filter
1
Slow roll-off filter
0
Minimum delay filter
1
Reserved
Table 22. Digital Filter setting
Sampling Speed Control (Table 8)
“00” (Normal Speed)
(default)
DFS1-0 bit
Data Zero Detect Mode
0: Channel Separated Mode (default)
1: Channel ANDed Mode
DZFM bit “1”
DZF pin “H”
8192
Data Zero Detect Enable
0: Disable (default)
1: Enable
DZFE bit =“0”
“0”
DZF pin
MS1146-J-03
“L”
2012/01
- 35 -
[AK4480]
Addr Register Name
02H Control 3
Default
SLOW:
D7
DP
0
D6
0
0
D5
DCKS
0
D4
DCKB
0
D3
MONO
0
D2
DZFB
0
D1
SELLR
0
D0
SLOW
0
Slow Roll-off Filter Enable
0: (default)
1: Slow roll-off filter
SELLR: The data selection of L channel and R channel, when MONO mode
0: All channel output R channel data, when MONO mode. (default)
1: All channel output L channel data, when MONO mode.
MONO bit “1”
SELLR bit = “0” R ch
“1” L ch
MONO bit “0”
SELLR bit = “1”
(Table 19)
L R
Lch
Rch
DZFB: Inverting Enable of DZF
0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection
DZFE
DZFB
MONO: MONO mode Stereo mode select
0: Stereo mode (default)
1: MONO mode
MONO bit “1”
Mono mode
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge (default).
1: DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (default)
1: 768fs
DP:
DSD/PCM Mode Select
0: PCM Mode (default)
1: DSD Mode
D/P bit
Addr Register Name
03H Lch ATT
04H Rch ATT
Default
RSTN bit AK4480
D7
ATT7
ATT7
1
D6
ATT6
ATT6
1
D5
ATT5
ATT5
1
D4
ATT4
ATT4
1
D3
ATT3
ATT3
1
D2
ATT2
ATT2
1
D1
ATT1
ATT1
1
D0
ATT0
ATT0
1
ATT7-0: Attenuation Level
ATT = 20 log10 (ATT_DATA / 255) [dB]
FFH: 0dB (default)
00H: Mute
MS1146-J-03
2012/01
- 36 -
[AK4480]
Addr Register Name
05H Control 4
Default
INVR:
AOUTR
0: Disable (default)
1: Enable
INVL:
AOUTL
0: Disable (default)
1: Enable
D7
INVL
0
D6
INVR
0
D5
0
0
MS1146-J-03
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
2012/01
- 37 -
[AK4480]
Figure 17
Figure 19, Figure 20 Figure 21
(AKD4480)
Digital 5.0V
MicroController
Rch Out
Digital
Ground
LRCK
30
CAD0
SDATA
29
3
CCLK
B ICK
28
4
CDTI
PDN
27
5
CAD1
DV DD
26
6
DZFL
VSS 4
25
7
DIF2
MCLK
24
AV DD
23
VS S3
22
10 AOUTRP
AO UTLP
21
11
AOUTRN
AOUTLN
20
12
VSS1
VS S2
19
13
VDDR
VDDL 18
14
VRE FHR
VREFHL 17
15
VRE FLR
V REFLL 16
1
CSN
2
DSP
Rch
Mute
Rch
LPF
10u
+
+
0.1u
10u
0.1u
8
PSN
9
DZFR
AK4480
Top
View
+
0.1u
10u
+
0.1u
10u
Lch
LPF
0.1u
10u
+
+
0.1u
10u
Lch
Mute
Lch Out
Analog 5.0V
Analog
Ground
+
Electrolytic Capacitor
Ceramic Capacitor
Notes:
- AVDD DVDD
- VSS1-4
- AOUT
/
Figure 17. Typical Connection Diagram (AVDD=5V, DVDD=5V, Serial Control Mode)
MS1146-J-03
2012/01
- 38 -
[AK4480]
Analog Ground
Digital Ground
System
Controller
1
SMUTE/CSN
2
SD/CAD0
LRCK
30
SDATA
3
29
DEM0/CCLK
BICK
28
4
DEM1/CDTI
PDN
27
5
DIF0/CAD1
DVDD
26
6
DIF1/DZFL
VSS4
25
7
DIF2
MCLK
24
8
PSN
AVDD
23
9
ACKS/DZFR
VSS3
22
10
AOUTRP
AOUTLP
21
11
AOUTRN
AOUTLN
20
12
VSS1
VSS2
19
13
VDRR
VDDL
18
14
VREFHR
VREFHL
17
15
VREFLR
VREFLL
16
AK4480
Figure 18. Ground Layout
AK4480
AVDD, VDDL/R
AVDD, VDDL/R DVDD
AVDD, VDDL/R
AVDD, VDDL/R
DVDD
DVDD
DVDD
VSS1-4
AK4480
VREFHL/R pin VREFLL/R pin
VREFHL/R pin AVDD
0.1µF
VREFLL/R pin VSS
VCML/R
10µF
VSS
VCML/R pin
VREFHL/R, VREFLL/R pin
0.1µF
AK4480
AVDD/2
2.4Vpp (typ, VREFHL/R −
AOUTL/R +, AOUTL/R −
VAOUT =
5.6Vpp (typ, VREFHL/R − VREFLL/R = 5V)
2’s compliment (2
)
800000H(@24bit)
VREFLL/R = 5V)
(AOUT+)−(AOUT−)
7FFFFFH(@24bit)
000000H(@24bit)
VAOUT
0V
ΔΣ
Figure 19
VREFHL/R pin VREFLL/R pin
(
1
)
(SCF)
LPF
Figure 20
3
LPF
MS1146-J-03
2012/01
- 39 -
[AK4480]
AK4480
3.9k
AOUT-
4.7k
150
470p
+Vop
3.9n
3.9k
AOUT+
4.7k
Analog
Out
150
470p
-Vop
Figure 19. External LPF Circuit Example 1 for PCM (fc = 99.0kHz, Q=0.680)
Frequency Response
Gain
20kHz
−0.036dB
40kHz
−0.225dB
80kHz
−1.855dB
Table 23. Frequency Response of External LPF Circuit Example 1 for PCM
+15
3.3n
+
AOUTL- +
10k
330
180
0.1u
7
3
2 +
4
3.9n
-15
10u
6
NJM5534D
+
10u
0.1u
620
620
3.3n
+
100u
3.9n
100
6
Lch
1.0n NJM5534D
10u
6
NJM5534D
1.2k
330
2 - 4
+
3
7
0.1u
7
3
+
2 4
+
10k
AOUTL+
180
+10u
1.0n
1.2k
680
0.1u
560
560
100u
680
+
0.1u
10u
+
10u
0.1u
Figure 20. External LPF Circuit Example 2 for PCM
1st Stage
2nd Stage
Total
Cut-off Frequency
182kHz
284kHz
Q
0.637
Gain
+3.9dB
-0.88dB
+3.02dB
20kHz
-0.025
-0.021
-0.046dB
Frequency
40kHz
-0.106
-0.085
-0.191dB
Response
80kHz
-0.517
-0.331
-0.848dB
Table 24. Frequency Response of External LPF Circuit Example 2 for PCM
MS1146-J-03
2012/01
- 40 -
[AK4480]
SACD
(Scarlet Book)
SACD
50kHz
−30dB/oct
(Figure 21)
AK4480
(Table 25)
Frequency
Gain
20kHz
−0.4dB
50kHz
−2.8dB
100kHz
−15.5dB
Table 25. Internal Filter Response at DSD Mode
2.0k
AOUT-
1.8k
4.3k
1.0k
270p
2.4Vpp
2200p
2.0k
+Vop
3300p
1.8k
1.0k
AOUT+
+
2.4Vpp
4.3k
270p
Analog
Out
5.42Vp p
-Vop
Figure 21. External 3rd Order LPF Circuit Example for DSD
Frequency
Gain
20kHz
−0.05dB
50kHz
−0.51dB
100kHz
−16.8dB
DC gain = 1.07dB
Table 26. 3rd Order LPF (Figure 21) Response
MS1146-J-03
2012/01
- 41 -
[AK4480]
30pin VSOP (Unit: mm)
1.5MAX
*9.7±0.1
0.3
30
16
15
1
0.22±0.1
7.6±0.2
5.6±0.1
A
0.15 +0.10
-0.05
0.65
0.12 M
0.45±0.2
+0.10
0.08
0.10 -0.05
1.2±0.10
Detail A
NOTE: Dimension "*" does not include mold flash.
■
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy, Halogen (bromine and chlorine) free
Cu
Solder (Pb free) plate
MS1146-J-03
2012/01
- 42 -
[AK4480]
AK4480EF
XXXXXXXXX
1) Pin #1 indication
2) Date Code: XXXXXXXXX(9 digits)
3) Marking Code: AK4480
4) Audio 4 pro Logo
Date (Y/M/D)
10/01/28
10/02/17
Revision
00
01
Reason
Page
Contents
3, 4
9
TST2/DZFR pin → ACKS/DZFR pin
17
■
(1)
/[1] PCM Mode
, 1. Manual Setting Mode
DFS0 pin
Table 3
Table 4
2. Auto Setting Mode
DFS0 pin
(2)
, 2. Auto Setting Mode
Table 12: ACKS pin → ACKS bit
18
20
11/11/01
02
36
■
12/01/12
03
34
■
SELLR
: “05H ~ 1FH” → “06H ∼ 1FH”
MS1146-J-03
2012/01
- 43 -
[AK4480]
z
z
z
z
z
z
MS1146-J-03
2012/01
- 44 -