AK4390

[AK4390]
AK4390
Ultra Low Latency 32-Bit ΔΣ DAC
AK4390
192kHz
216kHz
32
DAC
ΔΣ
(SCF)
PCM
Blu-Ray, DVD-Audio,
(Firewire, USB I/F)
• 128
•
: 30kHz ∼ 216kHz
• 32
8
Ripple: ±0.005dB, Attenuation: 100dB
Low latency option: 7/fs
•
•
• 32, 44.1, 48kHz
•
•
ATT (255 levels and 0.5dB step)
• THD+N: −103dB
• DR, S/N: 120dB
•
I/F
: 24/32
•
:
30kHz ~ 32kHz: 1152fs
30kHz ~ 54kHz: 512fs or 768fs
30kHz ~ 108kHz: 256fs or 384fs
108kHz ~ 216kHz: 128fs or 192fs
•
: 5V ± 5%
•
: TTL
•
: 30pin VSOP
MS1046-J-03
, 16/20/24/32
, I2S
2009/04
-1-
[AK4390]
■
DVDD
VSS3
PDN
AVDD
VSS4
VSS2
VDDL
BICK
LRCK
SDATA
PCM
Data
Interface
8X
Interpolator
SCF
AOUTLP
AOUTLN
VREFHL
DATT
Soft Mute
MCLK
ΔΣ
Modulator
Vref
VREFLL
VREFLR
Clock
Divider
VREFLL
AOUTRP
SCF
CSN/SMUTE
CCLK/DEM0
AOUTRN
Control
Register
CDTI/DEM1
VDDR
VSS1
CAD0 CAD1/DIF0
DZFR
PSN DZFL/DIF1 DIF2
Block Diagram
MS1046-J-03
2009/04
-2-
[AK4390]
■
AK4390EF
AKD4390
−10 ∼ +70°C
30pin VSOP (0.65mm pitch)
Evaluation Board for AK4390
■
SMUTE/CSN
1
30
LRCK
TST1/CAD0
2
29
SDATA
DEM0/CCLK
3
28
BICK
DEM1/CDTI
4
27
PDN
DIF0/CAD1
5
26
DVDD
DIF1/DZFL
6
25
VSS4
DIF2
7
24
MCLK
PSN
8
23
AVDD
TST2/DZFR
9
22
VSS3
AOUTRP
10
21
AOUTLP
AOUTRN
11
20
AOUTLN
VSS1
12
19
VSS2
VDDR
13
18
VDDL
VREFHR
14
17
VREFHL
VREFLR
15
16
VREFLL
AK4390
Top
View
MS1046-J-03
2009/04
-3-
[AK4390]
No.
Pin Name
I/O
SMUTE
I
7
CSN
TST1
CAD0
DEM0
CCLK
DEM1
CDTI
DIF0
CAD1
DIF1
DZFL
DIF2
I
I
I
I
I
I
I
I
I
I
O
I
8
PSN
I
TST2
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DZFR
AOUTRP
AOUTRN
VSS1
VDDR
VREFHR
VREFLR
VREFLL
VREFHL
VDDL
VSS2
AOUTLN
AOUTLP
VSS3
AVDD
MCLK
VSS4
DVDD
O
O
O
I
I
I
I
O
O
I
-
27
PDN
I
1
2
3
4
5
6
9
28 BICK
29 SDATA
30 LRCK
Note:
I
I
I
/
Function
Soft Mute in Parallel Control Mode
When this pin goes to “H”, soft mute cycle is initiated.
When returning to “L”, the output mute releases.
Chip Select in Serial Control Mode
Test Pin in Parallel Control Mode
(Internal pull-down pin)
Chip Address 0 in Serial Control Mode
(Internal pull-down pin)
De-emphasis Enable 0 in Parallel Control Mode
Control Data Clock in Serial Control Mode
De-emphasis Enable 1 in Parallel Control Mode
Control Data Input in Serial Control Mode
Digital Input Format 0 in Parallel Control Mode
Chip Address 1 in Serial Control Mode
Digital Input Format 1 in Parallel Control Mode
Left Channel Zero Input Detect in Serial Control Mode
Digital Input Format 2 in Parallel Control Mode
Parallel/Serial Select
(Internal pull-up pin)
“L”: Serial Control Mode, “H”: Parallel Control Mode
Test pin in Parallel Control Mode.
Connect to GND.
Rch Zero Input Detect in Serial Control Mode
Right Channel Positive Analog Output
Right Channel Negative Analog Output
Connected to VSS2/3/4 Ground
Right Channel Analog Power Supply, 4.75~5.25V
Right Channel High Level Voltage Reference Input
Right Channel Low Level Voltage Reference Input
Left Channel Low Level Voltage Reference Input
Left Channel High Level Voltage Reference Input
Left Channel Analog Power Supply, 4.75~5.25V
Ground (connected to VSS1/3/4 ground)
Left Channel Negative Analog Output
Left Channel Positive Analog Output
Ground (connected to VSS1/2/4 ground)
Analog Power Supply, 4.75 to 5.25V
Master Clock Input
Connected to VSS1/2/3 Ground
Digital Power Supply, 4.75 ∼ 5.25V
Power-Down Mode
When at “L”, the AK4390 is in power-down mode and is held in reset.
The AK4390 should always be reset upon power-up.
Audio Serial Data Clock
Audio Serial Data Input
L/R Clock
MS1046-J-03
2009/04
-4-
[AK4390]
■
(1)
Analog
Digital
AOUTLP, AOUTLN
AOUTRP, AOUTRN
SMUTE
VSS4
(2)
Analog
Digital
AOUTLP, AOUTLN
AOUTRP, AOUTRN
DIF2
DZFL, DZFR
VSS4
MS1046-J-03
2009/04
-5-
[AK4390]
(VSS1 = VSS2 = VSS3 = VSS4 = 0V; Note 1)
Parameter
Power Supplies:
Analog
Analog
Digital
Input Current, Any pin Except Supplies
Digital Input Voltage
Ambient Temperature (Power applied)
Storage Temperature
Symbol
AVDD
VDDL/R
DVDD
IIN
VIND
Ta
Tstg
min
−0.3
−0.3
−0.3
−0.3
−10
−65
Symbol
AVDD
VDDL/R
DVDD
VREFHL/R
VREFLL/R
Δ VREF
min
4.75
4.75
4.75
AVDD-0.5
VSS3
3.0
max
6.0
6.0
6.0
±10
DVDD+0.3
70
150
Units
V
V
V
mA
V
°C
°C
Note 1.
Note 2. VSS1-4
:
(VSS1 = VSS2 = VSS3 = VSS4 =0V; Note 1)
Parameter
Analog
Power Supplies:
Analog
(Note 3)
Digital
“H” voltage reference
Voltage Reference
“L” voltage reference
(Note 4)
VREFH-VREFL
typ
5.0
5.0
5.0
-
max
5.25
5.25
5.25
AVDD
AVDD
Units
V
V
V
V
V
V
Note 1.
Note 3. AVDD, DVDD
Note 4.
(VREFH − VREFL)
AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp× (VREFHL/R − VREFLL/R)/5.
:
MS1046-J-03
2009/04
-6-
[AK4390]
(
Ta=25°C; AVDD=VDDL/R=DVDD=5.0V; VSS1 =VSS2 =VSS3 =VSS4 =0V;
VREFHL/R=AVDD, VREFLL/R= VSS1=VSS2=VSS3; Input data=24bit; RL ≥ 1kΩ; BICK=64fs; Input Signal
Frequency = 1kHz; Sampling Frequency = 44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure
15)
Parameter
min
typ
max
Units
Resolution
24
Bits
Dynamic Characteristics
(Note 5)
0dBFS
−103
93
dB
fs=44.1kHz
THD+N
BW=20kHz
−57
dB
−60dBFS
0dBFS
−100
dB
fs=96kHz
BW=40kHz
−54
dB
−60dBFS
0dBFS
−100
dB
fs=192kHz
BW=40kHz
−60dBFS
−54
dB
BW=80kHz
−51
dB
−60dBFS
Dynamic Range (−60dBFS with A-weighted)
(Note 6)
114
120
dB
S/N (A-weighted)
(Note 7)
114
120
dB
Interchannel Isolation (1kHz)
110
120
dB
DC Accuracy
Interchannel Gain Mismatch
0.15
0.3
dB
Gain Drift
(Note 8)
20
ppm/°C
Output Voltage
(Note 9)
±2.65
±2.8
±2.95
Vpp
Load Capacitance
25
pF
Load Resistance
(Note 10)
1
kΩ
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
AVDD, VDDL/R
DVDD (fs ≤ 96kHz)
DVDD (fs = 192kHz)
Power down (PDN pin = “L”)
AVDD+DVDD
60
43
46
90
70
mA
mA
mA
10
100
μA
(Note 11)
Note 5. Audio Precision System Two
Note 6. Figure 15. (
2)
101dB at 16bit data and 118dB at 20bit data.
Note 7. Figure 15. (
2)
S/N
Note 8. (VREFH − VREFL)
+5V
Note 9.
(0dB)
(VREFHL/R − VREFLL/R)
AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFHL/R − VREFLL/R)/5.
Note 10. AC
DC
1.5kΩ
Note 11.
P/S pin = DVDD
(MCLK, BICK, LRCK)
VSS4
Note 12. VREFHL/R pin +5V
AVDD, DVDD 1kHz, 100mVpp
MS1046-J-03
2009/04
-7-
[AK4390]
(fs = 44.1kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ~ 5.25V, DVDD=4.75 ~ 5.25V; Normal Speed Mode; DEM=OFF; SD bit =“0”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 14) ±0.01dB
PB
0
20.0
kHz
−6.0dB
22.05
kHz
Stopband
(Note 13)
SB
24.1
kHz
Passband Ripple
PR
±0.005
dB
Stopband Attenuation
SA
100
dB
Group Delay
(Note 14)
GD
36
1/fs
Digital Filter + SCF
Frequency Response : 0 ∼ 20.0kHz
±0.2
dB
(fs = 96kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SD bit=“0”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 13) ±0.01dB
PB
0
43.5
kHz
−6.0dB
48.0
kHz
Stopband
(Note 13)
SB
52.5
kHz
Passband Ripple
PR
±0.005
dB
Stopband Attenuation
SA
95
dB
Group Delay
(Note 14)
GD
36
1/fs
Digital Filter + SCF
Frequency Response : 0 ∼ 40.0kHz
±0.3
dB
(fs = 192kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SD bit=“0”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 13) ±0.01dB
PB
0
87.0
kHz
−6.0dB
96.0
kHz
Stopband
(Note 13)
SB
105
kHz
Passband Ripple
PR
±0.005
dB
Stopband Attenuation
SA
90
dB
Group Delay
(Note 14)
GD
36
1/fs
Digital Filter + SCF
Frequency Response : 0 ∼ 80.0kHz
+0/−1
dB
Note 13.
fs(
)
PB = 0.4535 × fs(@±0.01dB)
SB = 0.546 × fs
Note 14.
16/20/24
MS1046-J-03
2009/04
-8-
[AK4390]
(fs = 44.1kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SD bit=“1”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 14) ±0.01dB
PB
0
20.0
kHz
−6.0dB
22.05
kHz
Stopband
(Note 13)
SB
24.1
kHz
Passband Ripple
PR
±0.005
dB
Stopband Attenuation
SA
100
dB
Group Delay
(Note 14)
GD
7
1/fs
Digital Filter + SCF
Frequency Response : 0 ∼ 20.0kHz
±0.2
dB
(fs = 96kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SD bit=“1”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 13) ±0.01dB
PB
0
43.5
kHz
−6.0dB
48.0
kHz
Stopband
(Note 13)
SB
52.5
kHz
Passband Ripple
PR
±0.005
dB
Stopband Attenuation
SA
95
dB
Group Delay
(Note 14)
GD
7
1/fs
Digital Filter + SCF
Frequency Response : 0 ∼ 40.0kHz
±0.3
dB
(fs = 192kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SD bit=“1”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 13) ±0.01dB
PB
0
87.0
kHz
−6.0dB
96.0
kHz
Stopband
(Note 13)
SB
105
kHz
Passband Ripple
PR
±0.005
dB
Stopband Attenuation
SA
90
dB
Group Delay
(Note 14)
GD
7
1/fs
Digital Filter + SCF
Frequency Response : 0 ∼ 80.0kHz
+0/−1
dB
MS1046-J-03
2009/04
-9-
[AK4390]
DC
(Ta=25°C; AVDD=VDDL/R=4.75 ~ 5.25V, DVDD=4.75 ~ 5.25V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
2.4
Low-Level Input Voltage
VIL
High-Level Output Voltage (Iout = −100μA)
VOH
DVDD−0.5
Low-Level Output Voltage (Iout = 100μA)
VOL
Input Leakage Current
(Note 15)
Iin
Note 15. TST1/CAD0 pin
TST1/CAD0 pin, PSN pin
,
PSN pin
MS1046-J-03
typ
-
max
0.8
0.5
±10
Units
V
V
V
V
μA
(typ. 100kΩ)
2009/04
- 10 -
[AK4390]
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)
Parameter
Symbol
min
Master Clock Timing
Frequency
fCLK
7.7
Duty Cycle
dCLK
40
LRCK Frequency
(Note 16)
Normal Speed Mode
fsn
30
Double Speed Mode
fsd
30
Quad Speed Mode
fsq
108
Duty Cycle
Duty
45
PCM Audio Interface Timing
BICK Period
1/128fn
tBCK
Normal Speed Mode
1/64fd
tBCK
Double Speed Mode
1/64fq
tBCK
Quad Speed Mode
30
tBCKL
BICK Pulse Width Low
30
tBCKH
BICK Pulse Width High
20
tBLR
BICK “↑” to LRCK Edge
(Note 17)
20
tLRB
LRCK Edge to BICK “↑”
(Note 17)
20
tSDH
SDATA Hold Time
20
tSDS
SDATA Setup Time
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Reset Timing
PDN Pulse Width
LRCK
PDN pin “L”
Units
41.472
60
MHz
%
54
108
216
55
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
80
80
50
50
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
tPD
150
ns
(Note 18)
BICK
“H”
max
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
Note 16. 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs
Note 17.
Note 18.
typ
PDN pin
RSTN bit
“↑”
MS1046-J-03
2009/04
- 11 -
[AK4390]
■
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDATA
VIL
Audio Interface Timing (PCM Mode)
MS1046-J-03
2009/04
- 12 -
[AK4390]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
C1
CDTI
tCDH
C0
R/W
VIH
A4
VIL
WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
WRITE Data Input Timing
tPD
PDN
VIL
Power Down & Reset Timing
MS1046-J-03
2009/04
- 13 -
[AK4390]
■
AK4390
MCLK, BICK, LRCK
MCLK
MCLK
“L” → “H”)
PDN pin
MCLK
MCLK,
RSTN bit
LRCK
MCLK, LRCK
(typ)
MCLK, LRCK
MCLK
AVDD/2
ON
Table 2
512fs
256fs
128fs
MCLK= 256fs/384fs
(Table 1)
(PDN pin =
ON
AK4390
MCLK
1152fs
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
MCLK LRCK
ΔΣ
(Table 1)
128fs
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
768fs
384fs
192fs
Table 1.
192fs
N/A
N/A
N/A
N/A
N/A
33.8688
36.8640
Table 2.
256fs
8.1920
11.2896
12.2880
22.5792
24.5760
N/A
N/A
Mode
Normal
Normal
Double
Quad
MCLK (MHz)
384fs
512fs
12.2880
16.3840
16.9344
22.5792
18.4320
24.5760
33.8688
N/A
36.8640
N/A
N/A
N/A
N/A
N/A
(N/A: Not available)
30kHz~108kHz
DR, S/N MCLK= 512fs/768fs
MCLK
256fs/384fs
512fs/768fs
Table 3. MCLK
Sampling Rate
30kHz~32kHz
30kHz~54kHz
30kHz~108kHz
108kHz~216kHz
768fs
24.5760
33.8688
36.8640
N/A
N/A
N/A
N/A
(Table 3)
1152fs
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
30kHz~54kHz
3dB
DR,S/N
117dB
120dB
DR, S/N
MS1046-J-03
(fs= 44.1kHz)
2009/04
- 14 -
[AK4390]
■
BICK LRCK
DIF2-0 pin
LSB
“0”
Mode
0
1
2
3
4
5
6
7
DIF2
0
0
0
0
1
1
1
1
SDATA
DIF2-0 bit
BICK
DIF1
0
0
1
1
0
0
1
1
Table 4.
DIF0
0
1
0
1
0
1
0
1
8
(Table 4)
MSB
Mode 2 16
Input Format
16bit LSB justified
20bit LSB justified
24bit MSB justified
24bit I2S Compatible
24bit LSB justified
32bit LSB justified
32bit MSB justified
32bit I2S Compatible
BICK
≥ 32fs
≥ 48fs
≥ 48fs
≥ 48fs
≥ 48fs
≥ 64fs
≥ 64fs
≥ 64fs
2’s
20
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
Figure 5
Figure 5
Figure 6
(default)
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDATA
Mode 0
15
0
14
6
1
5
14
4
15
3
2
16
17
1
0
31
15
0
14
6
5
14
1
4
15
3
16
2
17
1
0
31
15
14
0
1
0
1
BICK
(64fs)
SDATA
Mode 0
Don’t care
15
14
15
Don’t care
0
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
BICK
(64fs)
SDATA
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDATA
Mode 4
Don’t care
23
22
21
20
23
22
21
20
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1/4 Timing
MS1046-J-03
2009/04
- 15 -
[AK4390]
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDATA
23 22
1
0
Don’t care
23 22
0
1
Don’t care
23
22
0
1
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
BICK
(64fs)
SDATA
0
1
23 22
Don’t care
23 22
0
1
23
Don’t care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDATA
32 31
1
0
32 31
1
0
32
31
32:MSB, 0:LSB
Lch Data
Rch Data
Figure 5. Mode 5/6 Timing
LRCK
0
1
2
3
30
31
32
0
1
2
3
30
31
32
0
1
BICK
(≥64fs)
SDATA
31 30
1
0
Don’t care
31 30
1
0
Don’t care
31
31:MSB, 0:LSB
Lch Data
Rch Data
Figure 6. Mode 7 Timing
MS1046-J-03
2009/04
- 16 -
[AK4390]
■
IIR
3
(32kHz, 44.1kHz, 48kHz)
2256fs/384fs 128fs/192fs
DEM1
0
0
1
1
Table 5.
(50/15μs
)
OFF
DEM0
0
1
0
1
Mode
44.1kHz
OFF
48kHz
32kHz
(default)
■
AK4390 MUTE
0.5dB
DAC
256
(ATT)
0dB
MS1046-J-03
−127dB
2009/04
- 17 -
[AK4390]
■
AK4390
DZF pin
DZF pin “L”
8192
“0”
“0”
DZF pin “H”
RSTN bit “1”
DZF pin 4 ∼ 5LRCK
“L”
“0”
DZF pin “H”
DZF pin
“L”
DZF pin
“H”
RSTN bit “0”
“0”
DZFM bit “1”
8192
DZFE bit
DZFB bit
■
ATT
× ATT
SMUTE bit “0”
−∞
(Table 9)
−∞
SMUTE pin “H”
SMUTE bit “1”
−∞ (“0”)
−∞
ATT
× ATT
ATT
SMUTE pin “L”
ATT
ATT
S M U T E pin or
S M U T E bit
(1)
(1)
AT T _Level
(3)
A ttenuation
-∞
GD
(2)
GD
(2)
AOUT
(4)
8192/fs
D ZF pin
(1) ATT
× ATT
(Table 9)
1020LRCK
(2)
(3)
−∞
ATT
(4)
8192
“0”
Normal Speed Mode
ATT
“255”
(GD)
“0”
DZF pin “H”
DZF pin “L”
Figure 7. Soft Mute Function
■
ON
PDN pin
“L”
MCLK
MCLK 4/fs
MS1046-J-03
2009/04
- 18 -
[AK4390]
■
ON/OFF
AK4390 PDN pin “L”
(Hi-Z)
PDN
AK4390 DAC
RSTN bit
AVDD/2(typ)
“0”
RSTN
Power
PDN pin
(1)
Internal
State
Normal Operation
DAC In
(Digital)
“0”data
“0”data
(2)
GD
DAC Out
(Analog)
(3)
Reset
GD
(4)
(4)
(3)
(5)
Clock In
Don’t care
Don’t care
MCLK,LRCK,BICK
(7)
DZFL/DZFR
External
Mute
(1)
(2)
(3)
(4) PDN
(5)
(6)
(7)
(6)
Mute ON
Mute ON
PDN pin
“L”
150ns
PDN pin “L”
(GD)
Hi-Z
(“↓ ↑”)
“0”
(PDN pin = “L”)
(MCLK, BICK, LRCK)
(3)
(PDN pin = “L”)
DZFL/R pin “L”
Figure 8. Power-down/up Sequence Example
MS1046-J-03
2009/04
- 19 -
[AK4390]
■
(1) RSRN bit
RSTN bit “0”
AVDD/2
AK4390
DZFL/DZFR pin “H”
Figure 9 RSTN bit
RSTN bit
3~4/fs (5)
2~3/fs (5)
Internal
RSTN bit
Internal
State
Normal Operation
Normal O peration
D igital Block
P
D/A In
(Digital)
d
“0 ” data
(1)
GD
GD
(3)
D/A Out
(Analog)
(2)
(3)
(1)
2/ fs(4)
DZF
(6)
(1)
(2) RSTN bit = “0”
(3)
RSTN
(GD)
AVDD/2
(“↓ ↑”)
(4) DZF pin RSTN bit
(5) RSTN bit
(6)
“H”
LSI
2 ~ 3/fs
(3)
Hi-Z
“0”
LSI
RSTN bit
RSTN bit
2/fs
“L”
3 ~ 4/fs
(2)
Figure 9. Reset Sequence Example 1
MS1046-J-03
2009/04
- 20 -
[AK4390]
(2) MCLK or LRCK
MCLK
(Hi-Z)
LRCK
MCLK LRCK
AK4390
MCLK
LRCK
AVDD pin
DVDD pin
RSTB pin
(1)
Internal
State
Power-down
D/A In
(Digital)
Power-down
Normal O peration
Normal Operation
(3)
GD
D/A Out
(Analog)
Digital Circuit P ower-down
(2)
GD
(4)
Hi-Z
(2)
(4)
(5)
(4)
(5)
Clock In
MCLK, BICK, LRCK Stop
MCLK, BICK, LRCK
External
MUTE
Notes:
(1)
(2)
(3)
(6)
PDN pin
MCLK LRCK
(4) PDN pin
“0”
(5)
(MCLK
(6)
(4)
(6)
“L”
150ns
(6)
PDN pin “L”
(GD)
0
(“↑”)
MCLK
LRCK
3~4LRCK
)
(MCLK, BICK, LRCK)
Figure 10
Figure 10. Reset Sequence Example 2
MS1046-J-03
2009/04
- 21 -
[AK4390]
■
AK4390
(
)
(
)
PSN pin
PDN pin AK4390
3
I/F
(2bit, CAD0/1), Read/Write (1bit, “1”
CCLK “↓”
“↑”
CCLK
PSN pin “L”
: CSN, CCLK, CDTI
I/F
Chip address
), Register address (MSB first, 5bit) Control data (MSB first, 8bit)
“↑”
CSN
5MHz (max)
Function
Parallel Control Mode Serial Control Mode
Audio Format
Y
Y
De-emphasis
Y
Y
SMUTE
Y
Y
Minimum delay Filter
Y
Digital Attenuator
Y
Table 6. Function List (Y: Available, -: Not available)
PDN pin “L”
RSTN bit “0”
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
Chip Address (C1=CAD1, C0=CAD0)
R/W:
READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 11. Control I/F Timing
* AK4390
* PDN pin = “L”
* CSN “L”
CCLK “↑” 15
17
MS1046-J-03
2009/04
- 22 -
[AK4390]
PCM
Attenuation Level
0dB
03H
ATT7-0
04H
Audio Data Interface Modes
24bit
00H
DIF2-0
Data Zero Detect Enable
Disable
01H
DZFE
Data Zero Detect Mode
Separated
01H
DZFM
Minimum delay Filter Enable
Sharp roll-off filter
01H
SD
De-emphasis Response
OFF
01H
DEM1-0
Soft Mute Enable
Normal Operation
01H
SMUTE
Inverting Enable of DZF
“H” active
02H
DZFB
Table 7. Function List2 (Y: Available, -: Not available)
MS1046-J-03
Y
Y
Y
Y
Y
Y
Y
Y
2009/04
- 23 -
[AK4390]
■
Addr
00H
01H
02H
03H
04H
Register Name
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
D7
0
DZFE
0
ATT7
ATT7
D6
0
DZFM
0
ATT6
ATT6
D5
0
SD
0
ATT5
ATT5
D4
0
DFS1
0
ATT4
ATT4
D3
DIF2
DFS0
0
ATT3
ATT3
D2
DIF1
DEM1
DZFB
ATT2
ATT2
D1
DIF0
DEM0
0
ATT1
ATT1
D0
RSTN
SMUTE
0
ATT0
ATT0
Notes:
05H ∼ 1FH
PDN pin “L”
RSTN bit “0”
PSN pin
PDN pin AK4390
■
Addr Register Name
00H Control 1
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
DIF2
0
D2
DIF1
1
D1
DIF0
0
D0
RSTN
1
RSTN:
0: Reset. All registers are not initialized.
1: Normal Operation (default)
“0”
DIF2-0:
“010” (Mode2 : 24bit
(Table 4)
)
MS1046-J-03
2009/04
- 24 -
[AK4390]
Addr Register Name
01H Control 2
Default
D7
DZFE
0
D6
DZFM
0
D5
SD
0
D4
0
0
D3
0
0
D2
DEM1
0
D1
DEM0
1
D0
SMUTE
0
SMUTE:
0: Normal Operation (default)
1: DAC outputs soft-muted.
DEM1-0:
(Table 5)
“01” (OFF)
SD:
0: Sharp roll-off filter (default)
1: Minimum Delay filter
DZFM:
0: Channel Separated Mode (default)
1: Channel AND’ed Mode
DZFM bit = “1”
DZF pin
H
8192
(LRCK
)
“0
DZFE:
0: Disable (default)
1: Enable
DZFE bit = “0”
DZF pin
MS1046-J-03
“L”
2009/04
- 25 -
[AK4390]
Addr Register Name
02H Control 3
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
DZFB
0
D1
0
0
D0
0
0
D5
ATT5
ATT5
1
D4
ATT4
ATT4
1
D3
ATT3
ATT3
1
D2
ATT2
ATT2
1
D1
ATT1
ATT1
1
D0
ATT0
ATT0
1
DZFB: DZF
0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection
Addr Register Name
03H Lch ATT
04H Rch ATT
Default
D7
ATT7
ATT7
1
D6
ATT6
ATT6
1
ATT7-0:
256 levels, 0.5dB step
Data
FFH
FEH
FDH
:
:
02H
01H
00H
Attenuation
0dB
-0.5dB
-1.0dB
:
:
-126.5dB
-127.0dB
MUTE (-∞)
7424
ATT
FFH
FFH (0dB)
RSTN bit
“1”
00H (MUTE)
FFH
ATT
7424/fs ([email protected]=44.1kHz)
RSTN bit = “0”
ATT
MS1046-J-03
2009/04
- 26 -
[AK4390]
Figure 12
(AKD4390)
Figure 14 Figure 15
Digital 5.0V
LRCK
30
SDATA
29
1
CSN
2
CAD0
3
CCLK
BICK 28
4
CDTI
PDN 27
5
CAD1
DVDD
26
6
DZFL
VSS4
25
7
DIF2
MCLK
24
AVDD
23
MicroController
Rch Out
Digital
Ground
DSP
Rch
Mute
Rch
LPF
10u
+
+
0.1u
10u
0.1u
AK4390
Top
View
8
PSN
9
DZFR
10
AOUTRP
AOUTLP 21
11
AOUTRN
AOUTLN 20
12
VSS1
VSS2 19
13
VDDR
VDDL 18
14
VREFHR
VREFHL 17
15
VREFLR
VREFLL 16
VSS3 22
+
0.1u
10u
+
0.1u
10u
Lch
LPF
0.1u
10u
+
+
0.1u
10u
Lch
Mute
Lch Out
Analog 5.0V
Analog
Ground
+
Electrolytic Capacitor
Ceramic Capacitor
:
- AVDD DVDD
- VSS1-4
- AOUT
/
Figure 12. Typical Connection Diagram (AVDD=5V, DVDD=5V, Serial Control Mode)
MS1046-J-03
2009/04
- 27 -
[AK4390]
Analog Ground
Digital Ground
System
Controller
1
SMUTE/CSN
2
TST1/CAD0
LRCK
30
SDATA
3
29
DEM0/CCLK
BICK
28
4
DEM1/CDTI
PDN
27
5
DIF0/CAD1
DVDD
26
6
DIF1/DZFL
VSS4
25
7
DIF2
MCLK
24
8
PSN
AVDD
23
9
TST2/DZFR
VSS3
22
10
AOUTRP
AOUTLP
21
11
AOUTRN
AOUTLN
20
12
VSS1
VSS2
19
13
VDRR
VDDL
18
14
VREFHR
VREFHL
17
15
VREFLR
VREFLL
16
AK4390
Figure 13. Ground Layout
1.
AK4390
AVDD DVDD
DVDD
AVDD,
AVDD DVDD
AVDD DVDD
VSS1-4
AK4390
2.
VREFHL/R pin VREFLL/R pin
VREFHL/R pin AVDD
0.1µF
VREFHL/R, VREFLL/R pin
VREFLL/R pin VSS1/2/3
VREFHL/R pin VREFLL/R pin
AK4397
3.
5V)
800000H(@24bit)
ΔΣ
Figure 14
(
1
AVDD/2
2.8Vpp (typ, VREFHL/R − VREFLL/R =
AOUTL/R +, AOUTL/R −
VAOUT = (AOUT+)−(AOUT−)
5.6Vpp (typ, VREFHL/R − VREFLL/R = 5V)
2’s compliment (2
) 7FFFFFH(@24bit)
000000H(@24bit)
VAOUT
0V
)
(SCF)
LPF
Figure 15
3
LPF
MS1046-J-03
2009/04
- 28 -
[AK4390]
AK4390
1.5k
AOUT-
1.5k
390
1n
+Vop
2.2n
1.5k
AOUT+
1.5k
Analog
Out
390
1n
-Vop
Figure 14. External LPF Circuit Example 1 for PCM (fc = 99.2kHz, Q=0.704)
Frequency Response
Gain
20kHz
−0.011dB
40kHz
−0.127dB
80kHz
−1.571dB
Table 8. Filter Response of External LPF Circuit Example 1 for PCM
+15
3.3n
+
10k
330
180
0.1u
7
3
2 +
4
3.9n
6
NJM5534D
+
10u
0.1u
620
620
3.3n
+
100u
3.9n
100
6
Lch
1.0n NJM5534D
10u
6
NJM5534D
1.2k
330
2 - 4
+
3
7
0.1u
7
3
+
2 4
+
10k
AOUTL+
180
+10u
1.0n
1.2k
680
0.1u
560
560
100u
AOUTL- +
-15
10u
680
+
0.1u
10u
+
10u
0.1u
Figure 15. External LPF Circuit Example 2 for PCM
1st Stage
2nd Stage
Total
Cut-off Frequency
182kHz
284kHz
Q
0.637
Gain
+3.9dB
-0.88dB
+3.02dB
20kHz
-0.025
-0.021
-0.046dB
Frequency
40kHz
-0.106
-0.085
-0.191dB
Response
80kHz
-0.517
-0.331
-0.848dB
Table 9. Filter Response of External LPF Circuit Example 2 for PCM
MS1046-J-03
2009/04
- 29 -
[AK4390]
30pin VSOP (Unit: mm)
1.5MAX
*9.7±0.1
0.3
30
16
15
1
0.22±0.1
7.6±0.2
5.6±0.1
A
0.15 +0.10
-0.05
0.65
0.12 M
0.45±0.2
+0.10
0.08
0.10 -0.05
1.2±0.10
Detail A
NOTE: Dimension "*" does not include mold flash.
■
Package molding compound: Epoxy, Halogen (bromine and chlorine) free
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
MS1046-J-03
2009/04
- 30 -
[AK4390]
AK4390EF
XXXXXXXXX
XXXXXXXXX
Date (YY/MM/DD)
09/01/09
09/02/05
Revision
00
01
Reason
Date code identifier
Page
Contents
4
/
Pin No.5, 6, 7
“PCM Mode” → “Parallel Control Mode”
Pin No. 28, 29, 30
“PCM Mode”
■
DSD mode
■
Table 6
Table 7
■
“Halogen (bromine and chlorine) free”
Figure 14
Table 8
17
22
23
30
09/02/25
02
09/04/27
03
29
→
MS1046-J-03
2009/04
- 31 -
[AK4390]
•
•
•
•
•
•
MS1046-J-03
2009/04
- 32 -