AK4683 Japanese Datasheet

[AK4683]
AK4683
Asynchronous Multi-Channel Audio CODEC with DIR/T
AK4683
2ch ADC
4ch DAC
1
24bit CODEC
DAC
(DIR)
(AC-3)*
ADC
(DIT)
Non-PCM
μP I/F
ADC
100dB DAC
*
AK4683 192kHz, 24bit
DIR
ADC
AK4683
106dB
64
LQFP
(AC-3)
Dolby Laboratories
† ADC, DAC
† ADC, DAC
† 6:1
† 2ch 24bit ADC
- 64
:
96kHz
- S/(N+D): 90dB
, S/N: 100dB
HPF
(+24/-103dB, 0.5dB
† 4ch 24bit DAC
- 128
:
192kHz
- 24
8
- S/(N+D): 90dB
, S/N: 106dB
(+12/-115dB, 0.5dB
(32kHz, 44.1kHz, 48kHz
)
†
: [email protected]
ON/OFF
†
MS0427-J-03
)
)
2010/09
-1-
[AK4683]
† DIR,DIT
† AES3, IEC60958, S/PDIF, EIAJ CP1201
†
PLL
† PLL
: 32kHz ∼ 192kHz
† PLL/X'tal
†4
1,
3
†
1
(
or
)
†
†
(32kHz, 44.1kHz, 48kHz, 96kHz)
†
- Non-PCM
- DTS-CD
(32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz)
- Unlock & Parity Error
- Validity
† 24
†
40
† Non-PCM
Pc, Pd
† CD Q-subcode
† TTL
I/F
†
: 256fs, 384fs, 512fs (fs=32kHz ∼ 48kHz)
128fs, 192fs, 256fs (fs=64kHz ∼ 96kHz)
128fs (fs=120kHz~ 192kHz)
†
: 128fs, 256fs, 384fs, 512fs
†2
I/F (PORTA, PORTB)
†
/
† I/F
- PORTA:
,
(20bit,24bit), I2S, TDM
- PORTB:
,
(20bit,24bit), I2S
2
†
µP I/F
(I C, 4
)
†
: 4.5 ∼ 5.5V
†
: 2.7 ∼ 5.5V
†
: 64pin LQFP(0.5mm pitch)
MS0427-J-03
2010/09
-2-
[AK4683]
■
RMCLK
RX0
RX1
RX2
RX3
Clock
Recovery
4:2
Input
Selector
XTO
DAIF
Decoder
X’tal
Oscillator
XTI
LISEL
LOPIN
LIN1
LIN2
LIN3
LIN4
LIN5
LIN6
IPS0/1, OPS0/1 bit
MCLK2
HPF
DVOL
ADC
LIN0/1/2, RIN0/1/2 bit
RIN1
RIN2
RIN3
RIN4
RIN5
RIN6
HPF,
DVOL
ADC
MCKO
ADC
Audio
I/F
PORTB
BICKB
LRCKB
DIR
ADC
SDTIA1
SDOUT
off
SDTOB0/1 bit
ROPIN
RISEL
SDTIB
Through
TX
DIT
DIT
DIR
ADC
SDTIB
I2C
SDTIA1
DIT bit
DIT0/1 bit
LOUT1
LPF
DAC
DVOL
ROUT1
LPF
DAC
DVOL
LOUT2
LPF
DAC
DVOL
ROUT2
LPF
DAC
DVOL
DAC1
Audio
I/F
DIR
ADC
SDTIB
SDTIA1
SDTIA2
μP I/F
CSN
CCLK
CDTI
CDTO
SDTIA3
DIR
ADC
SDTIB
SDTIA1
SDTIA2
DAC2
Audio
I/F
SDTIA3
DIR
ADC
SDTIB
off
SDTOA0/1 bit
PORTA
SDTOA
OLRCKA
BICKA
ILRCKA
DAC10/11/12,
HPL
DAC20/21/22 bit
HPR
SDTOB
OPGA
MS0427-J-03
SDTIA1
SDTIA2
SDTIA3
2010/09
-3-
[AK4683]
■
-20 ∼ +85°C
AK4683EQ
AKD4683
64pin LQFP (0.5mm pitch)
AVSS1
AVDD1
LIN1
RIN1
LIN2
RIN2
LIN3
RIN3
LIN4
RIN4
LIN5
RIN5
LIN6
RIN6
PVSS
R
■
PVDD
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
RISEL
RX0
2
47
ROPIN
I2C
3
46
LOPIN
RX1
4
45
LISEL
RX2
5
44
AVSS2
RX3
6
43
AVDD2
INT
7
42
VCOM
VOUT
8
41
ROUT2
40
LOUT2
AK4683EQ
Top View
13
36
HPL
ILRCKA
14
35
HPR
BICKA
15
34
HVSS
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
HVDD
MCKO
SDTOA
SDTIB
OLRCKA
SDTIA3
MUTET
SDTIA2
37
SDTIA1
12
CSN
SDTOB
CCLK
LOUT2
CDTI
38
PDN
11
MCLK2
BICKB
TX
ROUT2
XTO
39
XTI
10
DVDD
LRCKB
DVSS
9
TVDD
CDTO
■ AK4588
Functions
DAC, ADC
DAC
HP-Amp
ADC
AK4588
AK4683
8ch
4ch
2ch
6:1
MS0427-J-03
2010/09
-4-
[AK4683]
No.
1
2
Pin Name
PVDD
RX0
I/O
I
3
I2C
I
4
5
6
7
RX1
RX2
RX3
INT
VOUT
I
I
I
O
O
DZF
O
OVF
O
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CDTO
LRCKB
BICKB
SDTOB
OLRCKA
ILRCKA
BICKA
SDTOA
MCKO
TVDD
DVSS
DVDD
XTI
XTO
O
I/O
I/O
O
I/O
I/O
I/O
O
O
I
O
23
TX
O
24
MCLK2
I
25
PDN
I
29
30
31
32
33
34
35
36
CDTI
SDA
CCLK
SCL
CSN
TEST
SDTIA1
SDTIA2
SDTIA3
SDTIB
HVDD
HVSS
HPR
HPL
I
I/O
I
I
I
I
I
I
I
I
O
O
37
MUTET
-
26
27
28
Function
PLL Power supply Pin, 4.5V∼5.5V
Receiver Channel 0 Pin (Internal biased pin. Internally biased at PVDD/2)
Control Mode Select Pin.
“L”: 4-wire Serial, “H”: I2C Bus
Receiver Channel 1 Pin
Receiver Channel 2 Pin
Receiver Channel 3 Pin
Interrupt Pin
V-bit Output Pin for Receiver Input
Zero Input Detect Pin
When the input data of DAC follow total 8192 LRCK cycles with “0” input data, this
pin goes to “H”. And when RSTN1 bit is “0”, PWDA bit is “0”, this pin goes to “H”.
Analog Input Overflow Detect Pin
This pin goes to “H” if the analog input of Lch or Rch overflows.
Control Data Output Pin in Serial Mode and I2C pin = “L”.
Channel Clock B Pin
Audio Serial Data Clock B Pin
Audio Serial Data Output B Pin
Output Channel Clock A Pin
Input Channel Clock A Pin
Audio Serial Data Clock A Pin
Audio Serial Data Output A Pin
Master Clock Output Pin
Output Buffer Power Supply Pin, 2.7V∼5.5V
Digital Ground Pin, 0V
Digital Power Supply Pin, 4.5V∼5.5V
X'tal Input Pin
X'tal Output Pin
Transmit Channel Output pin
When DIT bit = “0”, RX0~3 Through.
When DIT bit = “1”, Internal DIT Output.
Master Clock Input Pin
Power-Down Mode & Reset Pin
When “L”, the AK4683 is powered-down, all registers are reset. And then all digital
output pins go “L”. The AK4683 must be reset once upon power-up.
Control Data Input Pin in Serial Mode and I2C pin = “L”.
Control Data Pin in Serial Mode and I2C pin = “H”.
Control Data Clock Pin in Serial Mode and I2C pin = “L”
Control Data Clock Pin in Serial Mode and I2C pin = “H”
Chip Select Pin in Serial Mode and I2C pin = “L”.
This pin should be connected to DVSS in Serial Mode and I2C pin = “H”.
Audio Serial Data Input A1 Pin
Audio Serial Data Input A2 Pin
Audio Serial Data Input A3 Pin
Audio Serial Data Input B Pin
HP Power Supply Pin, 4.5V∼5.5V
HP Ground Pin, 0V
HP Rch Output Pin
HP Lch Output Pin
HP Common Voltage Output Pin
1μF capacitor should be connected to HVSS externally.
MS0427-J-03
2010/09
-5-
[AK4683]
No.
38
39
40
41
Pin Name
LOUT2
ROUT2
LOUT1
ROUT1
42
VCOM
-
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
AVDD2
AVSS2
LISEL
LOPIN
ROPIN
RISEL
AVSS1
AVDD1
LIN1
RIN1
LIN2
RIN2
LIN3
RIN3
LIN4
RIN4
LIN5
RIN5
LIN6
RIN6
PVSS
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
-
64
R
-
Notes:
I/O
O
O
O
O
Function
DAC2 Lch Positive Analog Output Pin
DAC2 Rch Positive Analog Output Pin
DAC1 Lch Positive Analog Output Pin
DAC1 Rch Positive Analog Output Pin
DAC/ADC Common Voltage Output Pin
2.2μF capacitor should be connected to AVSS2 externally.
DAC Power Supply Pin, 4.5V∼5.5V
DAC Ground Pin, 0V
Lch Feedback Resistor Output Pin
Lch Feedback Resistor Input Pin, 0.5xAVDD1
Rch Feedback Resistor Input Pin. 0.5xAVDD1
Rch Feedback Resistor Output Pin
ADC Ground Pin, 0V
ADC Power Supply Pin, 4.5V∼5.5V
Lch Input 1 Pin
Rch Input 1 Pin
Lch Input 2 Pin
Rch Input 2 Pin
Lch Input 3 Pin
Rch Input 3 Pin
Lch Input 4 Pin
Rch Input 4 Pin
Lch Input 5 Pin
Rch Input 5 Pin
Lch Input 6 Pin
Rch Input 6 Pin
PLL Ground pin
External Resistor Pin
12kΩ +/-1% resistor should be connected to PVSS externally.
(RX0)
(LIN1-6, RIN1-6)
■
Classification
Analog
Digital
Pin Name
RX0, LOUT1-2, ROUT1-2, LIN1-6, RIN1-6
INT, XTO, MCKO, VOUT/DZF/OVF, SDTOA-B,
CDTO, TX
RX1-3, CSN, CCLK, CDTI, XTI, MCLK2,
OLRCKA, ILRCKA, BICKA, SDTIA1-3,
LRCKB, BICKB, SDTIB
MS0427-J-03
Setting
These pins should be open.
These pins should be open.
These pins should be connected to DVSS.
2010/09
-6-
[AK4683]
(AVSS1, AVSS2, DVSS, PVSS, HVSS =0V; Note 1)
Parameter
Power Supplies ADC Analog
DAC Analog
Headphone Analog
Digital
PLL
Output buffer
|AVSS2-AVSS1| (Note 2)
|AVSS2-DVSS|
(Note 2)
|AVSS2-PVSS|
(Note 2)
|AVSS2-HVSS|
(Note 2)
Input Current (any pins except for supplies)
Analog Input Voltage
(LIN, RIN pins)
Digital Input Voltage
Except for ILRCKA, OLRCKA, LRCKB,
BICKA-B, RX0, I2C pins
ILRCKA, OLRCKA, LRCKB, BICKA-B pins
RX0, I2Cpins
Ambient Temperature (power applied)
Storage Temperature
Note 1.
Note 2. AVSS, DVSS, PVSS
Symbol
AVDD1
AVDD2
HVDD
DVDD
PVDD
TVDD
ΔGND1
ΔGND2
ΔGND3
ΔGND4
IIN
min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-
max
6.0
6.0
6.0
6.0
6.0
6.0
0.3
0.3
0.3
0.3
Units
V
V
V
V
V
V
V
V
V
V
-
±10
mA
VINA
-0.3
AVDD1+0.3
V
VIND1
-0.3
DVDD+0.3
V
VIND2
VIND3
Ta
Tstg
-0.3
-0.3
-20
-65
TVDD+0.3
PVDD+0.3
85
150
V
V
°C
°C
:
(AVSS1, AVSS2, DVSS, PVSS, HVSS =0V; Note 3)
Parameter
ADC Analog
Power Supplies
DAC Analog
(Note 4)
Headphone Analog
Digital
PLL
Output buffer
|DVDD - AVDD1|
|DVDD - AVDD2|
|DVDD - HVDD|
|DVDD - PVDD|
|AVDD1 – AVDD2|
Symbol
AVDD1
AVDD2
HVDD
DVDD
PVDD
TVDD
ΔVDD1
ΔVDD2
ΔVDD3
ΔVDD4
ΔVDD5
min
4.5
4.5
AVDD2
4.5
4.5
2.7
-0.3
-0.3
-0.3
-0.3
-0.1
typ
5.0
5.0
5.0
5.0
5.0
5.0
0
0
0
0
0
max
5.5
5.5
5.5
5.5
5.5
DVDD
+0.3
+0.3
+0.3
+0.3
+0.1
Units
V
V
V
V
V
V
V
V
V
V
V
Note 3.
Note 4. AVDD1, AVDD2, DVDD, PVDD, HVDD, TVDD
:
MS0427-J-03
2010/09
-7-
[AK4683]
(Ta=25°C; AVDD1, AVDD2, HVDD, DVDD, PVDD, TVDD=5V; AVSS1, AVSS2, HVSS, DVSS, PVSS =0V;
fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at fs=48kHz,
20Hz~40kHz at fs=96kHz; 20Hz~40kHz at fs=192kHz, all blocks are synchronized, unless otherwise specified)
Parameter
min
typ
max
Units
Pre-Amp Characteristics:
Feedback Resistance
10
50
kΩ
S/(N+D)
(Note 5)
100
dB
S/N
(A-weighted) (Note 5)
108
dB
Load Capacitance
20
pF
ADC Analog Input Characteristics (Note 6)
Resolution
24
Bits
S/(N+D)
(-0.5dBFS) fs=48kHz
84
92
dB
fs=96kHz
86
dB
DR
(-60dBFS)
fs=48kHz, A-weighted
92
100
dB
fs=96kHz
96
dB
fs=96kHz, A-weighted
100
dB
S/N
(Note 7)
fs=48kHz, A-weighted
92
100
dB
fs=96kHz
96
dB
fs=96kHz, A-weighted
100
dB
Interchannel Isolation
(Note 8)
90
105
dB
Interchannel Gain Mismatch
0.2
0.5
dB
Gain Drift
50
ppm/°C
Input Voltage (Note 6)
AIN=1.22 x AVDD1
5.7
6.1
6.5
Vpp
Power Supply Rejection
(Note 9)
50
dB
DAC Analog Output Characteristics
Resolution
24
Bits
S/(N+D)
fs=48kHz
80
90
dB
fs=96kHz
88
dB
fs=192kHz
88
dB
DR
(-60dBFS) fs=48kHz, A-weighted
95
106
dB
fs=96kHz
100
dB
fs=96kHz, A-weighted
106
dB
fs=192kHz
100
dB
fs=192kHz, A-weighted
106
dB
S/N
(Note 10)
fs=48kHz, A-weighted
95
106
dB
fs=96kHz
100
dB
fs=96kHz, A-weighted
106
dB
fs=192kHz
100
dB
fs=192kHz, A-weighted
106
dB
Interchannel Isolation
90
110
dB
Interchannel Gain Mismatch
0.2
0.5
dB
Gain Drift
50
ppm/°C
Output Voltage
AOUT=0.6xAVDD2
2.75
3.0
3.25
Vpp
Load Resistance
(AC Load)
5
kΩ
Load Capacitance
30
pF
Power Supply Rejection
(Note 9)
50
dB
MS0427-J-03
2010/09
-8-
[AK4683]
Analog Volume Characteristics (OPGA):
0.1
+0dB ∼ -16dB
0.1
-16dB ∼ -38dB
-38dB ∼ -50dB
Headphone-Amp Characteristics: DAC → HPL/HPR pins, RL=16Ω
Output Voltage
(0.506xHVDD)
1.94
S/(N+D)
(−3dBFS)
S/N
(A-weighted)
Interchannel Isolation
Interchannel Gain Mismatch
Load Resistance
16
Figure 1 C1
Load Capacitance
Figure 1 C2
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
(Note 11)
AVDD1+ AVDD2 fs=48kHz,fs=96kHz
fs=192kHz
HVDD
PVDD
DVDD+TVDD
fs=48kHz
(Note 12)
fs=96kHz
fs=192kHz
Power-down mode (PDN pin = “L”)
(Note 13)
Note 5.
47kΩ Feedback
24kΩ
2Vrms
Step Size:
Note 6.
Pre-Amp → ADC
Note 7. CCIR-ARM
Note 8. Pre-Amp
-
dB
dB
dB
2.43
70
90
80
0.1
-
2.92
0.5
30
300
Vpp
dBFS
dB
dB
dB
Ω
pF
pF
37
19
7
8
35
45
55
80
52
mA
27
mA
10
mA
11
mA
49
mA
63
mA
77
mA
200
μA
LOUT/ROUT
47kΩ Feedback
96dB (@fs=48kHz)
(typ. 1Vrms)
IPGA
1
2
4
24kΩ
LIN1-5 RIN1-5
Note 9. AVDD, DVDD, PVDD, TVDD 1kHz, 50mVpp
Note 10. CCIR-ARM
102dB (typ. @fs=48kHz)
Note 11. CL=20pF, X'tal=24.576MHz, CM1-0=“10”, CM1-0=“10”, [email protected],[email protected],
[email protected] Headphone = No output TX
Note 12. TVDD=6mA([email protected]=48kHz), 7mA([email protected]=96kHz), 10mA([email protected]=192kHz).
Note 13.
RX0
RX1-3
DVSS
HP-Amp
HPL, HPR
-
+
+
C1
C2
16Ω
Figure 1.
MS0427-J-03
2010/09
-9-
[AK4683]
(Ta=25°C; AVDD1, AVDD2, DVDD, PVDD, HVDD=4.5∼5.5V; TVDD=2.7∼5.5V; fs=48kHz)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 14)
PB
0
±0.1dB
20.0
-0.2dB
23.0
-3.0dB
Stopband
SB
28.0
Passband Ripple
PR
Stopband Attenuation
SA
68
Group Delay
(Note 15)
GD
19
Group Delay Distortion
0
ΔGD
ADC Digital Filter (HPF):
Frequency Response (Note 14)
-3dB
FR
1.0
-0.1dB
6.5
DAC Digital Filter:
Passband
(Note 14)
-0.1dB
PB
0
-6.0dB
24.0
Stopband
SB
26.2
Passband Ripple
PR
Stopband Attenuation
SA
54
Group Delay
(Note 15)
GD
21
DAC Digital Filter + Analog Filter:
FR
Frequency Response: 0 ∼ 20.0kHz
±0.2
FR
40.0kHz (Note 16)
±0.3
FR
80.0kHz (Note 16)
±1.0
Note 14.
fs
-0.1dB
21.8kHz 0.454 x fs(DAC)
Note 15.
24
PORTA
PORTB
DAC
PORTA
PORTB
max
Units
18.9
-
kHz
kHz
kHz
kHz
dB
dB
1/fs
μs
±0.04
Hz
Hz
21.8
±0.02
kHz
kHz
kHz
dB
dB
1/fs
dB
dB
dB
20/24
Note 16. [email protected]=96kHz, [email protected]=192kHz.
MS0427-J-03
2010/09
- 10 -
[AK4683]
DC
(Ta=25°C; AVDD1, AVDD2, DVDD, PVDD, HVDD =4.5∼5.5V; TVDD=2.7∼5.5V)
Parameter
Symbol
min
typ
2.2
VIH
High-Level Input Voltage
(Except XTI pin)
70%DVDD
VIH
(XTI pin)
VIL
Low-Level Input Voltage
(Except XTI pin)
VIL
(XTI pin)
Input Voltage at AC Coupling (XTI pin) (Note 17)
VAC
40%DVDD
High-Level Output Voltage
TVDD-0.4
VOH
(Except TX pin: Iout=-400μA)
DVDD-0.4
VOH
(TX pin: Iout=-400μA)
VOL
Low-Level Output Voltage
(Iout=400μA)
Iin
Input Leakage Current (Except RX0 pin)
Note 17. XTI pin
(0.1μF)
S/PDIF
(RX0)
(Ta=25°C; AVDD1, AVDD2, DVDD, PVDD, HVDD =4.5~5.5V; TVDD=2.7~5.5V)
Parameter
Symbol
min
typ
Input Resistance
Zin
10
Input Voltage (RX0, Internally biased at PVDD/2)
VTH
200
Input Hysteresis
VHY
50
Input Sample Frequency
fs
32
-
max
0.8
30%DVDD
Units
V
V
V
V
-
Vpp
0.4
±10
V
V
V
μA
max
Units
kΩ
mVpp
mV
kHz
192
PVDD
RX0 pin
20k(typ)
20k(typ)
PVSS
VCOM
Internal biased pin Circuit
S/PDIF
(RX1-3)
(Ta=25°C; AVDD1, AVDD2, DVDD, PVDD, HVDD =4.5~5.5V;TVDD=2.7~5.5V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
2.2
Low-Level Input Voltage
VIL
Input Sample Frequency
fs
32
Iin
Input Leakage Current
-
MS0427-J-03
typ
-
max
0.8
192
±10
Units
V
V
kHz
μA
2010/09
- 11 -
[AK4683]
(Ta=25°C; AVDD1, AVDD2, DVDD, PVDD, HVDD=4.5∼5.5V; TVDD=2.7∼5.5V; CL=20pF; Note 18)
Parameter
Symbol
min
typ
max
Master Clock Timing
Crystal Resonator Frequency
fXTAL
11.2896
24.576
External Clock
Frequency
fECLK
4.096
24.576
Duty
dECLK
40
50
60
MCKO Output
Frequency
fMCK
4.096
24.576
Duty
(Note 19)
dMCLK
40
50
60
(Note 20)
dMCK
33
PLL Clock Recover Frequency (RX0-3)
fpll
32
192
Master Clock
256fsn, 128fsd:
fCLK
8.192
12.288
Pulse Width Low
tCLKL
27
Pulse Width High
tCLKH
27
384fsn, 192fsd:
fCLK
12.288
18.432
Pulse Width Low
tCLKL
20
Pulse Width High
tCLKH
20
512fsn, 256fsd, 128fsq:
fCLK
16.384
24.576
Pulse Width Low
tCLKL
15
Pulse Width High
tCLKH
15
LRCKA (LRCKB) Timing (Slave Mode)
Normal mode
Normal Speed Mode
fsn
32
48
Double Speed Mode
fsd
64
96
Quad Speed Mode
fsq
120
192
Duty Cycle
Duty
45
55
TDM 256 mode
LRCKA frequency
fsd
32
48
“H” time
tLRH
1/256fs
“L” time
tLRL
1/256fs
TDM 128 mode
LRCKA frequency
fsd
64
96
“H” time
tLRH
1/128fs
“L” time
tLRL
1/128fs
LRCKA (LRCKB) Timing (Master Mode)
Normal mode
Normal Speed Mode
fsn
32
48
Double Speed Mode
fsd
64
96
Quad Speed Mode
fsq
120
192
Duty Cycle
Duty
50
TDM 256 mode
LRCKA frequency
fsn
32
48
“H” time
(Note 21)
tLRH
1/8fs
TDM 128 mode
LRCKA frequency
fsd
64
96
“H” time
(Note 21)
tLRH
1/4fs
Power-down & Reset Timing
PDN Pulse Width
(Note 22)
tPD
150
PDN “↑” to SDTO valid
(Note 23)
tPDV
522
Note 18. SDTOA OLRCKA, SDTIA1-3 ILRCKA
Note 19. MCKO1-0= “01”, “10”
MCKO1-0= “00”
CKSDT= “0”
Note 20. MCKO1-0= “00”
CKSDT= “1”
CM1-0 bit
EXTCLK
Duty = “H” /
100
Note 21. I2S
“L” time
Note 22.
PDN pin “L”
“H”
Note 23. PDN pin
LRCKA (LRCKB)
MS0427-J-03
Units
MHz
MHz
%
MHz
%
%
kHz
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
kHz
kHz
kHz
%
kHz
ns
ns
kHz
ns
ns
kHz
kHz
kHz
%
kHz
ns
kHz
ns
ns
1/fs
2010/09
- 12 -
[AK4683]
Parameter
Symbol
Audio Interface Timing (Slave Mode)
Normal mode
BICKA (BICKB) Period
tBCK
BICKA (BICKB) Pulse Width Low
tBCKL
Pulse Width High
tBCKH
LRCKA (LRCKB) Edge to BICKA (BICKB) “↑” (Note 24)
tLRB
BICKA (BICKB) “↑” to LRCKA (LRCKB) Edge (Note 24)
tBLR
LRCKA (LRCKB) to SDTOA, SDTOB (MSB)
tLRS
BICKA (BICKB) “↓” to SDTOA, SDTOB
tBSD
SDTIA1-3, SDTIB Hold Time
tSDH
SDTIA1-3, SDTIB Setup Time
tSDS
TDM 256 mode
BICKA Period
tBCK
BICKA Pulse Width Low
tBCKL
Pulse Width High
tBCKH
LRCKA Edge to BICKA “↑”
(Note 24)
tLRB
BICKA “↑” to LRCKA Edge
(Note 24)
tBLR
BICKA “↓” to SDTOA
tBSD
SDTIA1 Hold Time
tSDH
SDTIA1 Setup Time
tSDS
TDM 128 mode
BICKA Period
tBCK
BICKA Pulse Width Low
tBCKL
Pulse Width High
tBCKH
LRCKA Edge to BICKA “↑”
(Note 24)
tLRB
BICKA “↑” to LRCKA Edge
(Note 24)
tBLR
BICKA “↓” to SDTOA
tBSD
SDTIA1-2 Hold Time
tSDH
SDTIA1-2 Setup Time
tSDS
Audio Interface Timing (Master Mode)
Normal mode
BICKA (BICKB) Frequency
fBCK
BICKA (BICKB) Duty
dBCK
BICKA (BICKB) “↓” to LRCKA (LRCKB) Edge
tMBLR
BICKA (BICKB)“↓” to SDTO
tBSD
SDTIA1-3, B Hold Time
tSDH
SDTIA1-3, B Setup Time
tSDS
TDM 256 mode
BICKA Frequency
fBCK
BICKA Duty
(Note 25)
dBCK
BICKA “↓” to LRCKA Edge
tMBLR
BICKA “↓” to SDTOA
tBSD
SDTIA1 Hold Time
tSDH
SDTIA1 Setup Time
tSDS
TDM 128 mode
BICKA Frequency
fBCK
BICKA Duty
(Note 26)
dBCK
BICKA “↓” to LRCKA Edge
tMBLR
BICKA “↓” to SDTOA
tBSD
SDTIA1-2 Hold Time
tSDH
SDTIA1-2 Setup Time
tSDS
Note 24.
LRCKA (LRCKB)
BICKA (BICKB)
Note 25. MCLK2/XTI pin 512fs
Note 26. MCLK2/XTI pin 256fs
(384fs,256fs
(128fs
MS0427-J-03
min
typ
max
Units
81
32
32
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
20
20
81
32
32
20
20
ns
ns
ns
ns
ns
ns
ns
ns
20
10
10
81
32
32
20
20
ns
ns
ns
ns
ns
ns
ns
ns
20
10
10
64fs
50
-20
20
20
Hz
%
ns
ns
ns
ns
12
20
Hz
%
ns
ns
ns
ns
12
20
Hz
%
ns
ns
ns
ns
20
20
256fs
50
-12
10
10
128fs
50
-12
10
10
Duty
Duty
)
)
2010/09
- 13 -
[AK4683]
Parameter
Control Interface Timing (4-wire serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
Control Interface Timing (I2C Bus mode)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 27)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
Note 27.
300ns (SCL
)
2
Note 28. I C-bus NXP B.V.
MS0427-J-03
Symbol
min
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
50
50
150
50
50
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
4.7
4.0
4.7
4.0
4.7
0
0.25
4.0
0
-
typ
max
Units
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
1.0
0.3
50
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
2010/09
- 14 -
[AK4683]
■
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fsn, 1/fsd, 1/fsq
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
(Normal mode)
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fsn, 1/fsd
VIH
LRCK
VIL
tLRH
tLRL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
(TDM 256 mode, TDM 128 mode)
LRCK= LRCKB, ILRCKA, OLRCKA,
BICK= BICKA, BICKB,
SDTI= SDTIA, SDTIB,
SDTO= SDTOA, SDTOB.
MS0427-J-03
2010/09
- 15 -
[AK4683]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tLRS
tBSD
50%TVDD
SDTO
tSDS
tSDH
VIH
SDTI
VIL
(Normal mode)
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
(TDM 256 mode, TDM 128 mode)
MS0427-J-03
2010/09
- 16 -
[AK4683]
LRCK
50%TVDD
tMBLR
50%TVDD
BICK
tBSD
50%TVDD
SDTO
tDXS
tDXH
VIH
SDTI
VIL
(Master Mode)
tPD
PDN
VIL
MS0427-J-03
2010/09
- 17 -
[AK4683]
VIH
CSN
VIL
tCSS
tCCK
tCCKL tCCKH
VIH
CCLK
VIL
tCDH
tCDS
CDTI
C1
C0
A4
R/W
VIH
VIL
Hi-Z
CDTO
WRITE/READ
ADC/DAC
(4-wire serial mode)
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
VIH
D0
VIL
Hi-Z
CDTO
WRITE
(4-wire serial mode)
VIH
CSN
VIL
VIH
CCLK
VIL
CDTI
A1
VIH
A0
VIL
tDCD
CDTO
Hi-Z
D7
READ
ADC/DAC
D6
D5
50%TVDD
1 (4-wire serial mode)
MS0427-J-03
2010/09
- 18 -
[AK4683]
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
VIL
tCCZ
CDTO
D3
D2
D1
READ
ADC/DAC
D0
Hi-Z
50%TVDD
2 (4-wire serial mode)
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
I2C
ADC/DAC
tPD
VIH
PDN
VIL
tPDV
50%TVDD
SDTO
MS0427-J-03
2010/09
- 19 -
[AK4683]
(
)
■
AK4683
(RMCLK)
ADC
(SAIF) 2 (PORTA, PORTB)
XTI
PORTA/PORTB
4ch DAC DIR DIT
(Figure 2)
(MCLK2) 3
Clock Gen C
DIR
AD/DA
DIR
XTI
MCKO
MCLK2
MCKO0/1 bit
DIR
DIR
PORTA
XTI
DIR
MCLK2
X’tal
Oscillator
(XTI)
CLKB0/1 bit
ADC
MCLK2
DIR
DIR
XTI
MCLK2
MCLK2
XTI
Clock
Gen A
CLKA0/1 bit
XTI
PORTB
DAC
MCLK2
Clock
Gen B
DIR
XTI
DIR
XTI
Clock
MCLK2
Gen C
DIT
MCLK2
CLKL0/1 bit
Note
Note:
ADC,DAC
(RMCLK)
DIR DIT
DIR
CM1-0bit
DIT DIR
X’tal/MCLK2
(Table 1
)
Figure 2 System Clock
MS0427-J-03
2010/09
- 20 -
[AK4683]
■
AK4683 XTI pin
1) X’tal
XTI
C
25kΩ(typ)
C
XTO
AK4683
Note:
(Typ.10-40pF)
Figure 3. X’tal
2)
- Note: DVDD
C
XTI
XTI
External
Clock
External
Clock
25kΩ(typ)
25kΩ(typ)
XTO
XTO
AK4683
AK4683
(Input :CMOS Level)
(Input : 40%DVDD, C=0.1μF)
Figure 4.
Figure 5. AC
3) XTI/XTO
XTI
25kΩ(typ)
XTO
AK4683
Figure 6. OFF
MS0427-J-03
2010/09
- 21 -
[AK4683]
■
AK4683
1
X'tal
CLKDT bit
PLL
(Table 1) DIR
MCLK2
(CM1/0 bit = “10”)
(Table 2) MCLKO
fs
96kHz
CM1 bit
0
0
CM0 bit
0
1
1
0
1
1
512fs
UNLOCK
0
1
-
OCKS1/0 bit
192kHz
256fs,512fs
Clock Source
RMCLK
EXTCLK
RMCLK
EXTCLK
EXTCLK
Table 1. Clock Mode Control
CLKDT bit
0
1
Clock Source
XTI
MCLK2
(default)
Table 2. EXTCLK Control
OCKS1 bit
0
0
1
1
OCKS0 bit
0
1
0
1
MCLKO
256fs
256fs
512fs
128fs
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
Table 3. MCLKO Speed
MCKO1 bit
0
0
1
1
MCKO0 bit
0
1
0
1
MCKO Clock Source
DIR
X’tal(XTI)
MCLK2
Reserved
(default)
Table 4. MCKO Clock Source Control
OCKS1/0 bit
RMCLK
PLL
EXTCLK
CM0/1 bit
x2/3
CKSDT bit
CLKDT bit
DIR
X’tal
Oscillator
(XTI)
XTI
MCLK2
MCKO
MCKO0/1 bit
MCLK2
Figure 7. MCKO Clock
MS0427-J-03
2010/09
- 22 -
[AK4683]
■
PORTA B
MSA, MSB bit
(PDN pin = “L”)
AK4683
MSA, MSB bit “1”
ACKSB bit
“1”
“0”
ACKSAI, ACKSAO,
MSA, MSB bit
“1”
AK4683 ILRCKA, OLRCKA, BICKA,
AK4683 ILRCKA, OLRCKA, BICKA, LRCKB,
LRCKB, BICKB pin
BICKB pin 100kΩ
MSA, MSB bit
Mode
0
Slave Mode
(default)
1
Master Mode
Table 5. Select Master/Salve Mode
: PORTA PORTB
PORTA
PORTB
PORTA, PORTB
■
AK4683 FUNC1/0 bit
Mode
0
1
2
3
VOUT/DZF/OVF pin
FUNC1
0
0
1
1
FUNC0
0
1
0
1
Mode
OFF (“L”)
(default)
V bit
Table 6. VOUT/DZF/OVF pin
1.
AK4683
Lch
(-0.3dBFS
) OVF pin
“H”
(GD = 16/fs = 333μs @fs=48kHz)
(=10.9ms @fs=48kHz)
OVF pin
“L”
HPF
DATT
Rch
OVF
(PDN pin = “L” → “H”) 522/fs
MS0427-J-03
2010/09
- 23 -
[AK4683]
2.
AK4683 1
DZFM1-0 bit
8192
“0”
“0”
DZF pin
(Table 7)
“H”
“L”
DATT
Mode
DZFM1
bit
DZFM0
bit
0
1
2
3
0
0
1
1
0
1
0
1
Table 7.
L1
Enable
Enable
-
AOUT
R1
L2
Enable Enable
Enable
Enable
-
RX
V bit
R2
Enable
Enable
-
(default)
3. Validity
AK4683 Validity
”L”
MS0427-J-03
2010/09
- 24 -
[AK4683]
(ADC/DAC/PORTA/B
)
■
AK4683 2
PORT
PORT
PORT
MSB bit
(PORTA, B)
MCLK, LRCK, BICK
CLKA1-0, CLKB1-0 bit
(Table 8, Table 9)
(Table 16, Table 17) CKSAI2-0 bit, CKSB2-0 bit
PORT
PORT
PORTB
ADC
MCLK
/
(Table 11, Table 14)
LRCK
MSA,
PORT
DAC
ADC
DAC
PORTB
PORTA PORTB
Clock Gen C
CLKL1-0 bit
Clock Gen C
Clock Gen C
(Table 10) CKSL2-0 bit
(Table 15)
CKSIA2-0, OLRA1-0, BICKAF, CKSB2-0 bit
(Table 11, Table 12,
Table 13, Table 14)
ON
(PDN pin = “
PORTA
/
”)
LRCK (ILRCKA / OLRCKA)
BICK
(BICKA)
(PDN pin = “H”)
(RSTN1 bit = “0”)
DIR
ADC DAC
: PORTA PORTB
PORTA
(MCLK, BICK, LRCK)
(PDN pin = “L”)
(PDN pin = “↑”) MCLK, LRCK
ON
RMCLK
PORT
DIR
Clock Gen C
DFSAD, DFSDA1-0 bit
PORTB
PORTA, PORTB
MS0427-J-03
2010/09
- 25 -
[AK4683]
CLKA1 bit
0
0
1
1
CLKA0 bit
0
1
0
1
PORTA Clock Source
DIR
X’tal (XTI)
MCLK2
Reserved
(default)
Table 8. PORTA Clock Source Control
CLKB1 bit
0
0
1
1
CLKB0 bit
0
1
0
1
PORTB Clock Source
DIR
X’tal(XTI)
MCLK2
Reserved
(default)
Table 9. PORTB Clock Source Control
CLKL1 bit
0
0
1
1
CLKL0 bit
0
1
0
1
Clock Gen C Clock Source
DIR
X’tal (XTI)
MCLK2
Reserved
(default)
Table 10. Clock Gen C Clock Source Control
CKSAI2
0
0
0
0
CKSAI1
0
0
1
1
CKSAI0
0
1
0
1
Clock Speed
128fs
192fs
256fs
384fs
1
1
1
1
0
0
1
1
0
1
0
1
512fs
Reserved
Reserved
Reserved
(default)
Table 11. PORTA Input Data Clock Control (Master Mode)
OLRA1 bit
OLRA0 bit
OLRCKA Clock Freq
0
0
ILRCKA x 1
0
1
ILRCKA x 1/2
1
0
ILRCKA x 2
1
1
Reserved
Note: Select OLRA1-0 bits = “00” at TDM mode.
(default)
Table 12. PORTA Output Data Clock Control (Master Mode)
MS0427-J-03
2010/09
- 26 -
[AK4683]
BCAF bit
PORTA BICK Frequency Mode
0
ILRCKA x 64
1
ILRCKA x 128
Note: ILRCKA x 128
MCLK=ILRCKA x 256
BCAF bit is ignored at TDM mode.
(default)
Table 13. PORTA BICK Control (Master Mode)
CKSB2
0
0
0
0
CKSB1
0
0
1
1
CKSB0
0
1
0
1
Clock Speed
128fs
192fs
256fs
384fs
1
1
1
1
0
0
1
1
0
1
0
1
512fs
Reserved
Reserved
Reserved
(default)
Table 14. PORTB Data Clock Control (Master Mode)
CKSL2
0
0
0
0
CKSL1
0
0
1
1
CKSL0
0
1
0
1
Clock Speed
128fs
192fs
256fs
384fs
1
1
1
1
0
0
1
1
0
1
0
1
512fs
Reserved
Reserved
Reserved
(default)
Table 15. Clock Gen C Clock Control
LRCKA (LRCKB) pin, BICKA (BICKB) pin
LRCKA (LRCKB) pin, BICKA (BICKB) pin
LRCKA (LRCKB) pin, BICKA (BICKB) pin
Table 18
MSA bit
0
1
PORTA Master/Slave Mode
Slave
Master
(default)
Table 16. PORTA Master/Slave Control
MSB bit
0
1
PORTB Master/Slave Mode
Slave
Master
(default)
Table 17. PORTB Master/Slave Control
MS0427-J-03
2010/09
- 27 -
[AK4683]
PDN pin
PWPOA (PWPOB) bit
L
-
H
“0”
H
“1”
Master/Slave
Slave
Slave
Master
Slave
Master
LSI
*:
LRCKA
(LRCKB) pin
Input
Input*
“L” Output
Input
Output
BICKA
(BICKB) pin
Input
Input*
L” Output
Input
Output
Table 18. LRCKA (LRCKB) pin, BICKA (BICKB) pin
PORT
SDTOB1-0, SDTOA1-0bit
SDTOA1 bit
0
0
1
1
SDTOA0 bit
0
1
0
1
SDTOA Source
DIR
ADC
SDTIB
Off (“L” Output)
(default)
Table 19. SDTOA Source Control
SDTOB1 bit
0
0
1
1
SDTOB0 bit
0
1
0
1
SDTOB Source
DIR
ADC
Off (“L” Output)
SDTIA1
(default)
Table 20. SDTOB Source Control
MS0427-J-03
2010/09
- 28 -
[AK4683]
■
ADC, DAC
ADC, DAC
Mode)
DFSAD, DFSDA1-0 bit
(Auto Setting Mode) 2
(Manual Setting
PORTA, PORTB
PORTA
1. Manual Setting Mode (ACSKAD/ACSKDA bit = “0”: Default)
ADC, DAC
Setting Mode
Table 22)
BICKA, BICKB)
PORT Manual Setting Mode
Manual Setting Mode
bit
DFSAD
0
1
Clock Gen C
Sampling Speed (fs)
Normal Speed Mode
32kHz~48kHz
Double Speed Mode
64kHz~96kHz
Table 21.ADC
DFSDA1
0
0
1
1
DFSDA0
0
1
0
1
(default)
(Manual Setting Mode)
Sampling Speed (fs)
Normal Speed Mode
32kHz~48kHz
Double Speed Mode
64kHz~96kHz
Quad Speed Mode
120kHz~192kHz
Not Available
-
Table 22.DAC
LRCKA
(LRCKB)
fs
32.0kHz
44.1kHz
48.0kHz
ADC, DAC Manual
DFSAD, DFSDA1-0 bit (Table 21,
(ILRCKA, OLRCKA, LRCKB,
(default)
(Manual Setting Mode)
MCLK (MHz)
256fs
384fs
512fs
8.1920
12.2880
16.3840
11.2896
16.9344
22.5792
12.2880
18.4320
24.5760
(Normal Speed Mode @Manual Setting Mode)
BICKA (BICKB)
(MHz)
64fs
2.0480
2.8224
3.0720
Table 23.
LRCKA
(LRCKB)
fs
88.2kHz
96.0kHz
(
MCLK (MHz)
128fs
192fs
256fs
11.2896
16.9344
22.5792
12.2880
18.4320
24.5760
(Double Speed Mode @Manual Setting Mode)
: ADC Double Speed Mode (DFSAD=“1”) 128fs 192fs
BICKA (BICKB)
(MHz)
64fs
5.6448
6.1440
)
Table 24.
MS0427-J-03
2010/09
- 29 -
[AK4683]
LRCKA
(LRCKB)
fs
176.4kHz
192.0kHz
MCLK (MHz)
BICKA (BICKB)
(MHz)
64fs
11.2896
12.2880
128fs
192fs
256fs
22.5792
24.5760
(Quad Speed Mode @Manual Setting Mode)
( :ADC Quad Speed Mode
)
Table 25.
2. Auto Setting Mode (ACSKAD/ACSKDA bit = “1”)
ADC, DAC
Setting Mode
(Table 27)
PORT Auto Setting Mode
ADC, DAC Auto Setting Mode
MCLK
(Table 26)
DFSAD/DFSDA1-0 bit
MCLK
512fs
256fs
128fs
Sampling Speed
Normal
Double
Quad
Table 26.
LRCKA
(LRCKB)
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
(Auto Setting Mode)
MCLK (MHz)
128fs
22.5792
24.5760
Auto
256fs
22.5792
24.5760
-
Table 27.
512fs
16.3840
22.5792
24.5760
-
Sampling
Speed
Normal
Double
Quad
(Auto Setting Mode)
MS0427-J-03
2010/09
- 30 -
[AK4683]
DAC
DAC12-10, DAC22-20bit
DAC1
DAC2
DAC12 bit
0
0
0
0
DAC11 bit
0
0
1
1
DAC10 bit
0
1
0
1
DAC1 Source
DIR
ADC
SDTIB
SDTIA1
1
1
1
1
0
0
1
1
0
1
0
1
SDTIA2
SDTIA3
Reserved
Reserved
(default)
Table 28. DAC1 Source Control
DAC22 bit
0
0
0
0
DAC21 bit
0
0
1
1
DAC20 bit
0
1
0
1
DAC2 Source
DIR
ADC
SDTIB
SDTIA1
1
1
1
1
0
0
1
1
0
1
0
1
SDTIA2
SDTIA3
Reserved
Reserved
(default)
Table 29. DAC2 Source Control
MS0427-J-03
2010/09
- 31 -
[AK4683]
■
DAC IIR
3
(32kHz, 44.1kHz, 48kHz)
Double Speed Mode Quad Speed Mode
DAC1, DAC2
Mode
0
1
2
3
Sampling Speed
Normal Speed
Normal Speed
Normal Speed
Normal Speed
(50/15μs
)
OFF
DEM21/DEM11
DEM20/DEM10
0
0
1
1
0
1
0
1
DEM
44.1kHz
OFF
48kHz
32kHz
(default)
Table 30.
■
HPF
ADC DC
HPF
HPF
fc
fs=48kHz
1.0Hz
fs
■
PORT
DIFA1-0 bit
DIFB1-0 bit Normal mode
SDTO BICK
LSB
PORTA
Normal mode, TDM256 mode, TDM 128mode
MSB
2’s compliment
SDTI BICK
SDTI
“0”
Table 31 default Mode 2
TDMA1-0 bit,
PORTB
1. PORTA
1-1. Normal mode: TDMA1-0 bit = “00” (default)
TDM1-0 bit = “00”
8
Master/Slave
Mode
Master
/slave
DIFA1
DIFA0
SDTOA
SDTIA1-3
0
1
2
3
4
5
6
7
Slave
Slave
Slave
Slave
Master
Master
Master
Master
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
24bit, L J
24bit, L J
24bit, L J
24bit, I2S
24bit, L J
24bit, L J
24bit, L J
24bit, I2S
20bit, R J
24bit, R J
24bit, L J
24bit, I2S
20bit, R J
24bit, R J
24bit, L J
24bit, I2S
Table 31
DIFA1-0 bit
LRCKA
I/O
H/L
I
H/L
I
H/L
I
L/H
I
H/L
O
H/L
O
H/L
O
L/H
O
BICKA
I/O
I
≥ 48fs
I
≥ 48fs
I
≥ 48fs
I
≥ 48fs
64fs
O
64fs
O
64fs
O
64fs
O
(default)
(Normal mode, L J: Left justified, R J: Right justified.)
MS0427-J-03
2010/09
- 32 -
[AK4683]
1-2. TDM 256 mode: TDMA1-0 bit = “01”
TDMA1-0 bit “01”
SDTIA2-A3
1/256fs(min)
8
Mode
8
9
10
11
12
13
14
15
Master
/slave
Slave
Slave
Slave
Slave
Master
Master
Master
Master
TDM 256 mode
SDTIA1 pin
SDTIA(1,2,3)
BICKA 256fs
LRCKA
“H”
Master/Slave
DIFA1-0 bit
DIFA1
DIFA0
SDTOA
SDTIA1-3
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
24bit, L J
24bit, L J
24bit, L J
24bit, I2S
24bit, L J
24bit, L J
24bit, L J
24bit, I2S
20bit, R J
24bit, R J
24bit, L J
24bit, I2S
20bit, R J
24bit, R J
24bit, L J
24bit, I2S
Table 32.
LRCKA
I/O
I
↑
I
↑
I
↑
I
↓
O
↑
O
↑
O
↑
O
↓
BICKA
I/O
256fs
I
256fs
I
256fs
I
256fs
I
256fs
O
256fs
O
256fs
O
256fs
O
“L”
(default)
TDM 256 mode, L J: Left justified, R J: Right justified.
1-3. TDM 128 mode: TDMA1-0 bit = “11”
TDMA1-0 bit
2ch(SDTIA3)
Mode
16
17
18
19
20
21
22
23
“11”
Master
/slave
Slave
Slave
Slave
Slave
Master
Master
Master
Master
Table 33.
TDM 128 mode
SDTIA1 pin
DIFA1
DIFA0
SDTOA
SDTIA1-3
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
24bit, L J
24bit, L J
24bit, L J
24bit, I2S
24bit, L J
24bit, L J
24bit, L J
24bit, I2S
20bit, R J
24bit, R J
24bit, L J
24bit, I2S
20bit, R J
24bit, R J
24bit, L J
24bit, I2S
4ch(SDTIA1,2)
LRCKA
I/O
I
↑
I
↑
I
↑
I
↓
O
↑
O
↑
O
↑
O
↓
SDTIA2 pin
BICKA
I/O
128fs
I
128fs
I
128fs
I
128fs
I
128fs
O
128fs
O
128fs
O
128fs
O
(default)
TDM 128 mode, L J: Left justified, R J: Right justified.
MS0427-J-03
2010/09
- 33 -
[AK4683]
2. PORTB
2-1: Normal mode:
PORTB Normal mode
(Table 34) Master/Slave
8
Mode
Master
/slave
DIFB1
DIFB0
SDTOB
SDTIB
0
1
2
3
4
5
6
7
Slave
Slave
Slave
Slave
Master
Master
Master
Master
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
24bit, L J
24bit, L J
24bit, L J
24bit, I2S
24bit, L J
24bit, L J
24bit, L J
24bit, I2S
20bit, R J
24bit, R J
24bit, L J
24bit, I2S
20bit, R J
24bit, R J
24bit, L J
24bit, I2S
Table 34.
LRCKB
I/O
H/L
I
H/L
I
H/L
I
L/H
I
H/L
O
H/L
O
H/L
O
L/H
O
DIFB1-0 bit
BICKB
I/O
I
≥ 48fs
I
≥ 48fs
I
≥ 48fs
I
≥ 48fs
64fs
O
64fs
O
64fs
O
64fs
O
(Normal mode, L J: Left justified, R J: Right justified.)
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK (64fs)
SDTO(o)
23 22
12 11 10
Don’t Care
SDTI(i)
0
19 18
23 22
8
7
1
12 11 10
Don’t Care
0
0
19 18
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
23
8
7
1
0
Rch Data
Figure 8. Mode 0, 4
LRCK
0
1
2
8
9
10
24
25
31
0
1
2
8
9
10
24
25
31
0
1
BICK (64fs)
SDTO(o)
23 22
16 15 14
Don’t Care
SDTI(i)
0
23 22
23:MSB, 0:LSB
23 22
8
7
1
16 15 14
Don’t Care
0
0
23 22
Lch Data
23
8
7
1
0
Rch Data
Figure 9. Mode 1, 5
LRCK
0
1
2
21
22
23
24
28
29
30
31
0
1
2
22
23
24
28
29
30
31
0
1
BICK (64fs)
SDTO(o)
SDTI(i)
23 22
2
1
0
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
Lch Data
23 22
2
1
0
23 22
2
1
0
23
Don’t Care
23
Rch Data
Figure 10.Mode 2, 6
MS0427-J-03
2010/09
- 34 -
[AK4683]
LRCK
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
BICK (64fs)
SDTO(o)
23 22
2
1
0
SDTI(i)
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
Don’t Care
Rch Data
Figure 11. Mode 3, 7
256 B ICK
LRCKA
(m ode 8)
LRCKA
(m ode 12)
BICKA(256fs)
SDTOA(o)
23 22
0
23 22
Lch
32 B ICK
SDTIA1(i)
0
23 22
Rch
19 18
32 B ICK
0
19 18
0
19 18
0
19 18
0
19 18
0
19 18
0
L1
R1
L2
R2
L3
R3
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
19
32 B ICK
32 B ICK
Figure 12. Mode 8, 12
256 B ICK
LRCKA
(m ode 9)
LRCKA
(m ode 13)
BICKA(256fs)
SDTOA(o)
23 22
0
23 22
Lch
32 B ICK
SDTIA1(i)
0
23 22
Rch
23 22
32 B ICK
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
L3
R3
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23
32 B ICK
32 B ICK
Figure 13. Mode 9, 13
256 B ICK
LRCKA
(m ode 10)
LRCKA
(m ode 14)
BICKA(256fs)
SDTOA(o)
23 22
0
Lch
SDTIA1(i)
0
23 22
Rch
32 B ICK
23 22
23 22
0
32 B ICK
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
L3
R3
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23 22
32 B ICK
32 B ICK
Figure 14. Mode 10, 14
MS0427-J-03
2010/09
- 35 -
[AK4683]
256 B ICK
LRCKA
(m ode 11)
LRCKA
(m ode 15)
BICKA(256fs)
SDTOA(o)
23
0
23
Lch
32 B ICK
SDTIA1(i)
23
0
23
Rch
32 B ICK
0
23
0
23
0
23
0
23
0
23
0
L1
R1
L2
R2
L3
R3
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23
32 B ICK
32 B ICK
Figure 15. Mode 11, 15
128 B ICK
LRCKA
(m ode 16)
LRCKA
(m ode 20)
BICKA(128fs)
SDTOA(o)
23 22
0
SDTIA2(i)
23 22
Rch
32 B ICK
SDTIA1(i)
0
23 22
Lch
32 BICK
19 18
0
19 18
0
19 18
0
0
19 18
L1
R1
L2
R2
32 B ICK
32 B ICK
32 B ICK
32 B ICK
19 18
0
19 18
0
L3
R3
32 B ICK
32 B ICK
19
19
32 B ICK
32 B ICK
Figure 16. Mode 16, 20
128 B ICK
LRCKA
(m ode 17)
LRCKA
(m ode 21)
BICKA(128fs)
23 22
SDTIA1(i)
SDTIA2(i)
0
0
23 22
Lch
Rch
32 B ICK
32 BICK
23 22
0
23 22
23 22
0
23 22
0
0
23 22
L1
R1
L2
R2
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23 22
0
23 22
0
L3
R3
32 B ICK
32 B ICK
19
19
32 B ICK
32 B ICK
Figure 17. Mode 17, 21
MS0427-J-03
2010/09
- 36 -
[AK4683]
128 B ICK
LRCKA
(m ode 18)
LRCKA
(m ode 22)
BICKA(128fs)
SDTOA(o)
SDTIA1(i)
SDTIA2(i)
23 22
0
0
23 22
Lch
Rch
32 B ICK
32 BICK
23 22
0
23 22
0
23 22
23 22
0
23 22
0
L1
R1
L2
R2
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23 22
0
23 22
0
L3
R3
32 B ICK
32 B ICK
23 22
23 22
32 B ICK
32 B ICK
Figure 18. Mode 18, 22
128 B ICK
LRCKA
(m ode 19)
LRCKA
(m ode 23)
BICKA(128fs)
SDTOA(o)
SDTIA1(i)
SDTIA2(i)
23 22
0
0
23 22
Lch
Rch
32 B ICK
32 BICK
23 22
0
23 22
0
23
0
23 22
23 22
0
L1
R1
L2
R2
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23 22
0
23 22
0
L3
R3
32 B ICK
32 B ICK
23
23
32 B ICK
32 B ICK
Figure 19. Mode 19, 23
MS0427-J-03
2010/09
- 37 -
[AK4683]
■
AK4683
ADC
ADC, DAC
(256
ATTAD7-0 bit (Table 35)
ATTAD7-0
00H
01H
02H
:
2FH
30H
31H
FEH
FFH
, 0.5dB
DAC
Attenuation Level
+24dB
+23.5dB
+22.0dB
:
+0.5dB
0dB
-0.5dB
:
-103dB
MUTE (-∞)
)
ATTDA7-0 bit (Table 36)
(default)
Table 35. ADC
ATTDA7-0
00H
01H
02H
:
17H
18H
19H
FEH
FFH
Attenuation Level
+12dB
+11.5dB
+11.0dB
:
+0.5dB
0dB
-0.5dB
:
-115dB
MUTE (-∞)
(default)
Table 36. DAC
ATTAD7-0(ATTADA7-0)
Mode1
ATSAD(ATSDA) bit
Mode
0
1
ATSAD
0
1
ATT speed
1061/fs
256/fs
Table 37. ADC
Mode
0
1
Mode0
(default)
ATTAD7-0
ATSDA
0
1
ATT speed
1061/fs
256/fs
Table 38. DAC
Mode0
ATT
([email protected]=44.1kHz)
ATTAD7-0
“1”
(Table 37, Table 38)
(default)
ATTDA7-0
1061
PDN pin
“L”
ATTDA7-0 RSTN1 bit
ATTAD7-0
“0”
MS0427-J-03
00H
FFH(MUTE)
1061/fs
ATTDA7-0 30H, 18H
RSTN1 bit
2010/09
- 38 -
[AK4683]
■
ADC, DAC
bit
“1”
-∞ (“0”)
ATT
SMAD/DA
ATT
×ATT
SMAD/DA bit “0”
-∞
ATT
ATT
(Table 37, Table 38)
-∞
ATT
×ATT
SMAD/DA bit
(1)
ATT Level
(1)
(3)
Attenuation
-∞
GD
GD
(2)
AOUT
(4)
8192/fs
DZF
:
(1)ATT
×ATT
(2)
(3)
(Table 37, Table 38)
ATT
Mode 0
00H FFH
(GD)
ATT
“00H”
1061/fs
-∞
ATT
(4)
8192
“0”
“0”
DZF pin
“H”
DZF pin
“L”
Figure 20.
MS0427-J-03
2010/09
- 39 -
[AK4683]
■
AK4683
ATT
6ch
Lch/Rch
AIN2 bit
0
0
0
0
1
1
1
1
(Figure 21)
AIN2-0 bit(Table 39)
AIN1 bit
0
0
1
1
0
0
1
1
AIN0 bit
0
1
0
1
0
1
0
1
Input Selector
LIN1 / RIN1
LIN2 / RIN2
LIN3 / RIN3
LIN4 / RIN4
LIN5 / RIN5
LIN6 / RIN6
None
None
6
1
(default)
Table 39. Input Selector
AK4683
(LIN1-6/RIN1-6)
ATT
2Vrms
(Ri) LOPIN(ROPIN) pin LISEL(RISEL) pin
(Rf)
(Figure 21) LISEL(RISEL) pin
typ. 0.62 x AVDD1 (Vpp)
(LIN1-6/RIN1-6)
Ri
Ri Rf
typ. 0.62 x AVDD1 (Vpp)
Ri Rf
4Vrms
Table 40
Rf
L O P IN
Ri
L IN 1
Ri
L IN 2
Ri
L IN 3
Ri
L IN 4
Ri
L IN 5
Ri
L IN 6
Ri
R IN 1
Ri
R IN 2
Ri
R IN 3
Ri
R IN 4
Ri
R IN 5
Ri
R IN 6
L IS E L
To AD C
P re -A m p
P re -A m p
To AD C
R O P IN
R IS E L
Rf
Figure 21. Input ATT
Input Range
Ri [kΩ]
Rf [kΩ]
4Vrms
47
12
2Vrms
47
24
1Vrms
47
47
Note:
ADC
ATT Gain [dB]
LISEL/R pin
1.02Vrms
−11.86
(2.88Vpp)
1.02Vrms
−5.84
(2.88Vpp)
1Vrms
0
(2.82Vpp)
0.62 x AVDD1 (5V) = 3.1Vpp typ.
Table 40. Input ATT example
MS0427-J-03
2010/09
- 40 -
[AK4683]
[
]
(Figure 22)
1.
2.
3.
SMUTE
(1)
(1)
D AT T Level
A ttenuation
(2)
-∞
C hannel
LIN 1/R IN 1
LIN 2/R IN 2
Figure 22. Input channel switching sequence example
(1)
DATT
DC
DATT
(2)
200ms
+24dB
Mute
1061/fs
(2)
MS0427-J-03
2010/09
- 41 -
[AK4683]
■
AK4683
(PDN pin) “L”
PDN pin = “L”
SDTOA,B, DZF/OVF pin
VCOM
(LRCKB)
“L”
LRCKA
LRCKA (LRCKB)
“↑”
PORTA,B
ADC
522/fs
DAC
VCOM
Figure 23
ADC
DAC
bit = “0”
PWAD bit PWDA bit, PWDA2-1 bit
PWAD bit = “0”
ADC
VCOM
DZF pin “H”
“L”
PWDA, PWDA1-2
Power
PDN pin
522/fs
ADC Internal
State
(1)
Init Cycle
Normal Operation
Power-down
Normal Operation
Power-down
516/fs (2)
DAC Internal
State
Init Cycle
GD (3)
GD
ADC In
(Analog)
ADC Out
(Digital)
“0”data (4)
DAC In
(Digital)
“0”data
(5)
“0”data
“0”data
(3)
GD
(6)
DAC Out
(Analog)
GD
(6)
(7)
Clock In
MCLK,LRCK,BICK
Don’t care
Don’t care
10∼11/fs (10)
(8)
DZF
External
Mute
(1) ADC
(2) DAC
(3)
(4)
(5)
(9)
Mute ON
Mute ON
(GD)
ADC
“0”
ADC
(6) PDN
PDN
(7)
(PDN pin = “L”)
(8)
(9)
(6)
(10) PDN
(PDN pin = “L”)
“↑”
10∼11/fs
512/fs (DAC1), 512/fs + 96ms(DAC2)
(MCLK, BICKA (BICKB), LRCKA (LRCKB))
DZF pin
“L”
DZF pin = “L”
Figure 23.
MS0427-J-03
2010/09
- 42 -
[AK4683]
■
(PDN pin = “L”)
Pin Name
HPL/HPR
LOUT1/ROUT1/LOUT2/ROUT2
LISEL/RISEL
HVSS
VCOM
Hi-Z
■
RSTN1 bit = “0”
VCOM
ADC DAC
DZF pin
“H”
SDTOA/B pin
“L”
Figure 24 RSTN1 bit
RSTN1 bit
4~5/fs (9)
1~2/fs (9)
Internal
RSTN1 bit
516/fs (1)
ADC Internal
State
Normal Operation
Digital Block Power-down
DAC Internal
State
Normal Operation
Digital Block Power-down
Normal Operation
Init Cycle
Normal Operation
GD (2)
GD
ADC In
(Analog)
(3)
ADC Out
(Digital)
(4)
“0”data
DAC In
(Digital)
“0”data
(2)
GD
GD
(6)
DAC Out
(Analog)
(6)
(5)
(7)
Clock In
Don’t care
MCLK,LRCK,BICK
4∼5/fs (8)
DZF
(1) ADC
(2)
(3)
(4)
(GD)
ADC
“0”
ADC
(5) RSTN1 bit = “0”
(6) RSTN1 bit
(7)
VCOM
“0”
4∼5/fs
RSTN1 bit
(RSTN1 bit = “0”)
“1”
1∼2/fs
(MCLK, BICKA (BICKB), LRCKA (LRCKB))
(MCLK, BICKA (BICKB), LRCKA (LRCKB))
= “1”
(8) DZF1-2 pin
(9) RSTN1 bit
RSTN1 bit
“0”
“0”
“H”
LSI
RSTN1 bit
RSTN
“1”
6~7/fs
RSTN1 bit
“L”
4~5/fs
Figure 24.
MS0427-J-03
2010/09
- 43 -
[AK4683]
■
HVDD
HVSS
MUTET pin
HVDD
HVDD/2
“1”
MUTEN bit
MUTEN bit “0”
HVDD/2
MUTET pin
: MUTET pin
C=1μF, HVDD=5V
: 120ms(typ)
PWHP bit “0”
“L” (HVSS)
HPL, HPR pin
PWHP bit
MUTEN bit
HPL pin,
HPR pin
(1) (2)
(3)
( )
( )
Figure 25.
(1)
(2)
(PWHP bit = “1”)
HVSS
(MUTEN bit = “1”) OPGA
(3)
(4)
(5)
(MUTEN bit = “0”)
(PWHP bit = “0”)
HVSS
(fc)
Table 41
(fc)
RL
16Ω
HVDD=5V
HP-AMP
R
C
Headphone
16Ω
AK4683
Figure 26.
R [Ω]
0
6.8
16
C [μF]
220
100
100
47
100
47
Table 41.
fc [Hz]
45
100
70
149
50
106
Output Power [mW]@0dBFS
50
25
12.5
,
f
MS0427-J-03
2010/09
- 44 -
[AK4683]
■
(OPGA)
0dB ∼ -50dB & MUTE
OPGA
L/R
DAC
L/R
ZCE = “0”
OPGA
OPGA4-0
1FH
1EH
1DH
:
10H
0FH
0EH
0DH
:
05H
04H
03H
02H
01H
00H
GAIN(dB)
+0
-1
-2
:
-15
-16
-18
-20
:
-36
-38
-42
-46
-50
MUTE
STEP
LEVEL
1dB
17
2dB
11
4dB
3
1
Table 42.
(default)
ATT
L/R
Table 43
DAC2 Sampling Speed
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
768/fs (16ms @fs=48kHz)
1536/fs (16ms @fs=96kHz)
3072/fs (16ms @fs=192kHz)
Table 43. Zero crossing timeout
PWDAbit
Mute
1
PDNpin
DAC2 Sampling Speed
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
PWDA2 bit
“1”
Enable
96ms (@fs=48kHz)
(Table 44)
512/fs + 96ms (@fs=48kHz)
DAC
OPGA
4608/fs (96ms @fs=48kHz)
9216/fs (96ms @fs=96kHz)
18432/fs (96ms @fs=192kHz)
Table 44. OPGA Initialize Time
MS0427-J-03
2010/09
- 45 -
[AK4683]
(DIR/DIT
)
■ 192kHz
PLL 32kHz
192kHz
20ms
(32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz)
■
(DIR)
DIR
RX
Mode 2
PLL
(XTI/MCLK2)
RX
Unlock
Mode 3
Mode 2, 3
Mode
0
1
CM1
0
0
CM0
0
1
2
1
0
3
1
1
DIT
PORT
CM1-0 bit
PLL
UNLOCK
PLL
Clock source
ON
PLL
OFF
EXTCLK
0
ON
PLL
1
ON
EXTCLK
ON
EXTCLK
ON: Power-up, OFF: Power-Down
SDTO
RX
DIT
RX
DIT
DIT
(default)
Table 45.
XTI
MCLK2 DIR/DIT
CKSDT bit
CKSDT bit
0
1
Clock Speed
x1
x2/3
(default)
Table 46. XTI/MCLK2 Speed
MS0427-J-03
2010/09
- 46 -
[AK4683]
■
AK4683
2
XTL1-0 bit
FS0, FS1, FS2, FS3 bit
X’tal/MCLK2
XTL1-0 bit = ”1,1”
FS0, FS1, FS2, FS3 bit
XTL1
0
0
1
1
XTL0
0
1
0
1
X’tal/MCLK2 Frequency
11.2896MHz
12.288MHz
24.576MHz
(default)
Table 47.
XTL1,0= “1,1”
XTL1,0= “1,1”
Register output
fs
Clock comparison
(Note 1)
FS3
FS2
FS1
FS0
0
0
0
0
1
1
1
1
Note 1:
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
44.1kHz
Reserved
48kHz
32kHz
88.2kHz
96kHz
176.4kHz
192kHz
±3%
44.1kHz
Reserved
48kHz
32kHz
88.2kHz
96kHz
176.4kHz
192kHz
Consumer
mode
(Note 2)
Byte3
Bit3,2,1,0
0000
0001
0010
0011
(1000)
(1010)
(1100)
(1110)
Table
32kHz∼192kHz
Professional mode
Byte0
Bit7,6
01
10
11
00
00
00
00
Byte4
Bit6,5,4,3
0000
(Others)
0000
0000
1010
0010
1011
0011
FS3-0 bit =
“0001”
Note 2:
Byte3 Bit3-0 FS3-0 bit
Table 48.
PEM bit
(CS12=0
)
1
CS12 bit = “1”
2
PEM
Pre-emphasis
0
1
OFF
ON
Byte 0
Bits 3-5
≠ 0X100
0X100
Table 49.
PEM
Pre-emphasis
0
1
OFF
ON
Byte 0
Bits 2-4
≠110
110
Table 50.
MS0427-J-03
2010/09
- 47 -
[AK4683]
■
IIR
4
(32kHz, 44.1kHz, 48kHz, 96kHz)
DEAU bit = “1”
FS3-0 bit
(50/15μs
)
DEAU bit = “0”
OFF
PEM bit =
DEM0/1, DFS bit
“0”
PEM
1
1
1
1
1
0
FS3
0
0
0
1
FS2
0
0
0
0
x
x
FS1
0
1
1
1
FS0
0
0
1
0
x
x
Mode
44.1kHz
48kHz
32kHz
96kHz
OFF
OFF
(Others)
Table 51.
PEM
1
1
1
1
1
1
1
1
0
(DEAU bit = “1”: Default)
DFS
0
0
0
0
1
1
1
1
x
DEM1
0
0
1
1
0
0
1
1
x
DEM0
0
1
0
1
0
1
0
1
x
Mode
44.1kHz
OFF
48kHz
32kHz
OFF
OFF
96kHz
OFF
OFF
Table 52.
(default)
(DEAU bit = “0”)
■
AK4683
PDN pin
PWN bit
PDN pin
RSTN2 bit
“L”
PDN pin:
“L”
RSTN2 bit:
“0”
PWN bit
“0”
RSTN bit
SDTO pin
“L”
PWN bit RSTN2 bit
PWN bit:
“0”
PLL
X’tal
MS0427-J-03
2010/09
- 48 -
[AK4683]
■
4
(RX0-3)
IPS1-0 bit
RX0
RX1-3 TTL
200mVpp
IPS1 bit
0
0
1
1
IPS0 bit
0
1
0
1
DIR Source
RX0
RX1
RX2
RX3
V bit
(default)
Table 53. DIR Source Control
(B)
1/4fs
VOUT
SDTO
C(R191)
V(L0)
R190
V(R0)
L191
V(L1)
R191
L0
V(L39)
L38
V(R39) V(L40)
R38
L39
LRCK
2
(except I S)
LRCK
(I2S)
Figure 27. V
MS0427-J-03
2010/09
- 49 -
[AK4683]
■
TX pin
DIT bit
VIN bit
mode)
Sub frame 1
bit
“0”
RX
DIT
OPS0, 1 bit 4
C bit
5Byte
bit20-23(Audio channel)
“1000”
, Sub frame 2 “0100”
“0000”
TX
DIT
CT20 bit
V bit
bit0= “0”(consumer
“1”
CT20
DIT bit
0
0
0
0
OPS1 bit
0
0
1
1
OPS0 bit
0
1
0
1
TX Source
RX0
RX1
RX2
RX3
1
*
*
DIT
(default)
Table 54. TX Source Control
DIT
CM1-0 bit, CLKDT bit, CKSDT bit, OCKS1-0 bit
CM1 bit
0
0
CM0 bit
0
1
1
0
1
1
UNLOCK
0
1
-
Clock Source
RMCLK
EXTCLK
RMCLK
EXTCLK
EXTCLK
PORT
(default)
Table 55. Clock Mode Control
CLKDT bit
0
1
Clock Source
XTI
MCLK2
Table 56. EXTCLK Control
CKSDT bit
0
0
0
0
1
1
1
1
OCKS1bit
0
0
1
1
0
0
1
1
OCKS0 bit
0
1
0
1
0
1
0
1
EXTCLK
256fs
256fs
512fs
128fs
384fs
384fs
768fs
192fs
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
48 kHz
48 kHz
32 kHz
96 kHz
Table 57. MCLKO Speed
MS0427-J-03
2010/09
- 50 -
[AK4683]
DIT
DITD1-0 bit
DITD1 bit
0
0
1
1
DITD0 bit
0
1
0
1
DIT Source
DIR
ADC
SDTIB
SDTIA1
(default)
Table 58. DIT Source Control
■ RX0
0.1uF
RX0
75Ω
Coax
75Ω
AK4683
Figure 28.
Note: Coaxial
50mV
(Coaxial
)
RX
Optical Receiver
Optical
Fiber
470
RX0-3
O/E
AK4683
Figure 29.
Coaxial
(
)
RX
RX
“H”
“L”
AK4683 TX
0.5V+/-20%
330
Figure 30
T1 1:1
2%
TX
100
75Ω cable
2%
DVSS
T1
Figure 30. TX
MS0427-J-03
2010/09
- 51 -
[AK4683]
■ Q-subcode
U bit
CD Q-subcode
1. Subcode sync word (S0,S1)
2. Start bit
“1”
3. Q-W 7 bit
start bit
4. Start bit
8-16 bit
Q-subcode
S0
S1
S2
S3
:
S97
S0
S1
S2
S3
:
1
0
0
1
1
:
1
0
0
1
1
:
16
QINT
2
3
0
0
0
0
Q2
R2
Q3
R3
:
:
Q97 R97
0
0
0
0
Q2
R2
Q3
R3
:
:
Q
Q2
Q3 Q4
CTRL
Q5
Q6
Q7 Q8
ADRS
“0” bit
Q9
QINT bit
4
0
0
S2
S3
:
S97
0
0
S2
S3
:
5
0
0
T2
T3
:
T97
0
0
T2
T3
:
6
0
0
U2
U3
:
U97
0
0
U2
U3
:
“0”
7
8
0
0
0
0
V2 W2
V3 W3
:
:
V97 W97
0
0
0
0
V2 W2
V3 W3
:
:
*
0…
0…
0…
0…
:
0…
0…
0…
0…
0…
:
(*) number of "0": min=0; max=8.
Figure 31. U(CD)
Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25
TRACK NUMBER
INDEX
Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49
MINUTE
SECOND
FRAME
Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73
ZERO
ABSOLUTE MINUTE
ABSOLUTE SECOND
Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97
ABSOLUTE FRAME
CRC
G(x)=x16+x12+x5+1
Figure 32.
Addr
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Register Name
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
D7
Q9
Q17
D6
Q8
Q16
Q81
Q80
Q
D5
D4
D3
D2
D1
Q3
Q11
D0
Q2
Q10
Q75
Q74
Figure 33. Q-subcode register
MS0427-J-03
2010/09
- 52 -
[AK4683]
■
INT pin
“H”
1. UNLOCK : PLL
2. PAR
8
“1”
:
“1”
“1”
3. AUTO
5. AUDION
: Non-Linear PCM
4096
: DTS-CD
DTS-CD
sync
: AUDIO
6. PEM
:
7. QINT
:Q-subcode bit Sync
Sync
4. DTSCD
8. CINT
:
U-
“1”
Sync
“1”
PLL OFF
(Clock Operation Mode 1) INT pin
“L”
(EFH0/1 bit
)
“H”
INT pin
PAR, QINT, CINT bit
“1”
1
8
OR
INT pin
INT pin
(
1024/fs (EFH0/1 bit
“1”
INT pin
06H
)
06H
1024/fs
) INT pin
PAR, QINT, CINT bit
“H”
UNLOCK, PAR bit
UNLOCK
1
0
0
0
0
0
0
0
PAR
x
1
0
0
0
0
0
0
AUTO
x
x
1
x
x
x
x
x
Event
DTSCD AUDION
x
x
x
x
x
x
1
x
x
1
x
x
x
x
x
x
Pin
PEM
x
x
x
x
x
1
x
x
QINT
x
x
x
x
x
x
1
x
CINT
x
x
x
x
x
x
x
1
SDTO*
“L”
Previous Data
Output
Output
Output
Output
Output
Output
V*
“L”
Output
Output
Output
Output
Output
Output
Output
*:
TX*
Output
Output
Output
Output
Output
Output
Output
Output
Table 59.
MS0427-J-03
2010/09
- 53 -
[AK4683]
Error
(UNLOCK, PAR,..)
(Error)
INT pin
Hold Time (max: 4096/fs)
Register
(PAR,CINT,QINT)
Hold ”1”
Reset
Register
(others)
Command
MCKO, BICK, LRCK
(UNLOCK) note
MCKO, BICK, LRCK
(except UNLOCK)
note
SDTO (UNLOCK)
note
SDTO
(PAR error) note
READ 06H
Free Run
(fs: around 20kHz)
Previous Data
SDTO
(others) note
Vpin
(UNLOCK) note
Vpin
(except UNLOCK)
note
Normal Operation
note: When DIR is selected as source.
Figure 34. INT pin
MS0427-J-03
2010/09
- 54 -
[AK4683]
PDN pin ="L" to "H"
Initialize
Read 06H
INT pin ="H"
No
Yes
Release
Muting
Mute DAC output
Read 06H
(Each Error Handling)
Read 06H
(Resets registers)
No
INT pin ="H"
Yes
Figure 35.
1
MS0427-J-03
2010/09
- 55 -
[AK4683]
PDN pin ="L" to "H"
Initialize
Read 06H
No
INT pin ="H"
Yes
Read 06H
and
Detect QSUB= “1”
(Read Q-buffer)
QCRC = “0”
No
New data
is invalid
Yes
INT pin ="L"
No
Yes
New data
is valid
Figure 36.
2 (Q/CINT)
MS0427-J-03
2010/09
- 56 -
[AK4683]
■ Non-PCM/DTS-CD
AK4683 Non-PCM
Dolby “AC-3 Data Stream in IEC60958 Interface”
32
Mode Non-PCM
AUTO bit
“1”
96
sync code 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F
4096
sync code
sync code
AUTO bit
“0”
sync code
2
(Pc, Pd)
DTS-CD
DTSCD bit “1”
4096
sync code
sync code
DTSCD bit
“0”
■ Non-PCM
sub-frame of IEC60958
0
3 4
preamble
7 8
11 12
Aux.
27 28 29 30 31
LSB
MSB V U C P
16 bits of bitstream
0
Pa Pb Pc Pd
15
Burst_payload
stuffing
repetition time of the burst
Figure 37. IEC60958
Preamble word
Pa
Pb
Pc
Pd
Length of field
16 bits
16 bits
16 bits
16 bits
Contents
sync word 1
sync word 2
Burst info
Length code
Value
0xF872
0x4E1F
See Table 61
Numbers of bits
Table 60.
MS0427-J-03
2010/09
- 57 -
[AK4683]
Bits of Pc Value
Contents
0-4
data type
NULL data
Dolby AC-3 data
reserved
PAUSE
MPEG-1 Layer1 data
MPEG-1 Layer2 or 3 data or MPEG-2 without extension
MPEG-2 data with extension
MPEG-2 AAC ADTS
MPEG-2, Layer1 Low sample rate
MPEG-2, Layer2 or 3 Low sample rate
reserved
DTS type I
DTS type II
DTS type III
ATRAC
ATRAC2/3
reserved
reserved, shall be set to “0”
error-flag indicating a valid burst_payload
error-flag indicating that the burst_payload may contain
errors
data type dependent info
bit stream number, shall be set to “0”
5, 6
7
8-12
13-15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-31
0
0
1
0
Repetition time of burst
in IEC60958 frames
≤4096
1536
384
1152
1152
1024
384
1152
512
1024
2048
512
1024
(Refer the IEC standards.)
Table 61.
Pc
MS0427-J-03
2010/09
- 58 -
[AK4683]
■ Non-PCM
1) Non-PCM
4096
PDN pin
Bit stream
Pa Pb Pc1 Pd1
Pa Pb Pc2 Pd2
Repetition time
Pa Pb Pc3 Pd3
>4096 frames
AUTO bit
Pc Register
“0”
Pd Register
“0”
Pc1
Pc2
Pd1
Pd2
Figure 38.
2) Non-PCM
Pc3
Pd3
1
(MULK0=0
)
INT0 hold time
INT0 pin
<20mS (Lock time)
Bit stream
Pa Pb Pc1 Pd1
Stop
Pa Pb Pcn Pdn
2~3 Syncs (B,M or W)
<Repetition time
AUTO bit
Pc Register
Pd Register
Pc0
Pc1
Pd0
Pcn
Pd1
Figure 39.
Pdn
2
MS0427-J-03
2010/09
- 59 -
[AK4683]
(ADC/DAC
, DIR/DIT
)
■
AK4683
ADC/DAC
DIR/DIT
(1) 4
(I2C pin = “L”)
4
I/F (CSN, CCLK, CDTI, CDTO)
I/F
Chip address (2bits, AK4683
ADC/DAC
”10”
DIR/DIT
”00”
), Read/Write (1bit), Register address (MSB first, 5bits) Control Data
(MSB first, 8bits)
CCLK “↓”
“↑”
CSN
“↑”
CSN
“↑”
Hi-Z
CCLK
5MHz (max)
PDN pin= “L”
ADC/DAC
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
WRITE
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
CDTO
CDTI
READ
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
CDTO
C1,C0:
R/W:
A4-A0:
D7-D0:
D7 D6 D5 D4 D3 D2 D1 D0
Chip Address: (ADC/DAC
“10”, DIR/DIT
READ/WRITE (0:READ, 1:WRITE)
Register Address
Control Data
Figure 40. 4
“00”
Hi-Z
)
I/F
MS0427-J-03
2010/09
- 60 -
[AK4683]
(2) I2C
AK4683
(I2C pin = “H”)
I 2C
(max:100kHz)
(max:400kHz)
ADC/DAC
(2)-1
·
1
·
READ
WRITE
·
(2)-1-1.
SDA
SCL
“L”
“L”
“H”
“H”
“H”
SCL
“L”
SDA
SDA
SCL
·
·
SCL
SDA
CHANGE
OF DATA
ALLOWED
DATA LINE
STABLE :
DATA VALID
Figure 41.
(2)-1-2.
SCL
“H”
SDA
“H”
·
“L”
SCL
·
·
“H”
·
SDA
“L”
“H”
SCL
SDA
START CONDITION
Figure 42.
STOP CONDITION
·
·
MS0427-J-03
2010/09
- 61 -
[AK4683]
(2)-1-3.
IC
1
SDA
IC
SDA
(HIGH
)
“L”
AK4683
WRITE
AK4683
·
READ
SDA
·
SDA
AK4683
·
AK4683
(
)ADC,DAC
READ
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
START
CONDITION
acknowledge
Figure 43.
(2)-1-4.
1
1
·
·
5
“00100”
“10”, DIR/DIT
“00”
IC
R/W bit
R/W bit= “1”
0
2
7
IC
ADC/DAC
·
1
R/W bit= “0”
READ
0
1
(ADC,DAC
0
0
CAD1
CAD1,CAD0=“10”
Figure 44.
8
WRITE
CAD0
DIR
(
)
R/W
”00”
)
1
MS0427-J-03
2010/09
- 62 -
[AK4683]
(2)-2. WRITE
R/W bit
“0”
AK4683 WRITE
2
Don’t care
3
*
*
WRITE
2
MSB first
*
A4
A3
A2
A1
A0
(*: Don’t care)
Figure 45.
2
3
8
D7
D6
D5
D4
Figure 46.
D3
MSB first
D2
D1
D0
3
AK4683
1
1FH
S
T
A
R
T
SDA
·
Register
Address(n)
Slave
Address
·
Data(n)
00H
S
T
Data(n+x) O
P
Data(n+1)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 47. WRITE
MS0427-J-03
2010/09
- 63 -
[AK4683]
(2)-3. READ
R/W bit
“1”
·
AK4683
READ
1FH
00H
ADC/DAC
AK4683
·
·
·
READ
(2)-3-1.
AK4683
·
·
·
AK4683 READ
·
·
·
(READ
WRITE
n+1
(R/W bit = “1”)
·
)
n
·
·
1
1
READ
·
S
T
A
R
T
SDA
·
Slave
Address
Data(n)
Data(n+1)
S
Data(n+x) T
O
P
Data(n+2)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 48. CURRENT ADDRESS READ
(2)-3-2.
·
·
·
(R/W bit = “1”)
·
·
WRITE
WRITE
·
READ
(R/W bit = “0”)
AK4683
·
READ
·
(R/W bit = “1”)
AK4683
·
1
·
READ
S
T
A
R
T
SDA
Slave
Address
S
T
A
R
T
Word
Address(n)
S
Slave
Address
Data(n)
S
Data(n+x) T
O
P
Data(n+1)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 49. RANDOM READ
MS0427-J-03
2010/09
- 64 -
[AK4683]
■
(ADC/DAC
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
:
Register Name
Powerdown 1
Powerdown 2
Clock Select 1
Clock Select 2
Clock Select 3
Clock Select 4
Sampling Speed
Data Source Select 1
Data Source Select 2
Analog Input Control
Audio Data Format
De-emphasis/ ATT speed
LIN Volume Control
RIN Volume Control
LOUT1 Volume Control
ROUT1 Volume Control
LOUT2 Volume Control
ROUT2 Volume Control
HPL Volume Control
OVF/DZF/V Control
)
D7
PWXTL
PWPOB
0
CKSL2
CKSAI2
0
0
0
0
0
0
DEM11
D6
MUTEN
PWPOA
0
CKSL1
CKSAI1
XTL1
D5
PWVR
PWDA
0
CKSL0
CKSAI0
XTL0
ACKSAI
ACKSAO
0
DAC22
0
0
DEM10
ATTAD7
ATTAD7
ATTDA7
ATTDA7
ATTDA7
ATTDA7
0
0
DITD1
DAC21
0
DIFB1
DEM21
D4
PWHP
PWAD
0
CLKL1
SELAO
CKSDT
ACKSB
DITD0
DAC20
0
DIFB0
DEM20
ATTAD6
ATTAD6
ATTDA6
ATTDA6
ATTDA6
ATTDA6
ATTAD5
ATTAD5
ATTDA5
ATTDA5
ATTDA5
ATTDA5
0
0
0
ZCE
14H∼1FH
PDN pin
“L”
RSTN1 bit “0”
D3
0
0
CLKB1
CLKL0
OLRA1
CKSB2
0
D2
SMAD
0
CLKB0
MCKO1
OLRA0
CKSB1
DFSAD
D1
SMDA
PWDA2
CLKA1
MCKO0
BCAF
CKSB0
D0
RSTN1
PWDA1
CLKA0
CLKDT
MSA
MSB
SDTOB1
SDTOB0
DFSDA1
SDTOA1
DFSDA0
SDTOA0
0
0
TDMA1
0
DAC12
AIN2
TDMA0
ATSAD
DAC11
AIN1
DIFA1
0
DAC10
AIN0
DIFA0
ATSDA
ATTAD4
ATTAD4
ATTDA4
ATTDA4
ATTDA4
ATTDA4
ATTAD3
ATTAD3
ATTDA3
ATTDA3
ATTDA3
ATTDA3
ATTAD2
ATTAD2
ATTDA2
ATTDA2
ATTDA2
ATTDA2
ATTAD1
ATTAD1
ATTDA1
ATTDA1
ATTDA1
ATTDA1
ATTAD0
ATTAD0
ATTDA0
ATTDA0
ATTDA0
ATTDA0
OPGA4
VIN
OPGA3
FUNC1
OPGA2
FUNC0
OPGA1
DZFM1
OPGA0
DZFM0
DZF pin
“0” bit
“H”
“0”
MS0427-J-03
2010/09
- 65 -
[AK4683]
■
Addr
00H
Register Name
Powerdown 1
Default
RSTN1: Codec
0:
1:
SMDA: DAC
0:
1:
D7
PWXTL
1
D6
MUTEN
0
D5
PWVR
1
D4
PWHP
0
D3
0
0
D2
SMAD
0
D1
SMDA
0
D0
RSTN1
1
DZF pin “H”
(default)
(default)
DAC
SMAD: ADC
0:
1: ADC
(default)
PWHP:
0: Power OFF (default)
1: Power ON
PWVR: Codec
0: Power-down
1: Normal operation (default)
MUTEN:
0:
1:
(default)
DC
VSS(0V)
0.5 x HVDD
PWXTL:
0: Power OFF
1: Power ON (default)
MS0427-J-03
2010/09
- 66 -
[AK4683]
Addr
01H
Register Name
Powerdown 2
Default
D7
PWPOB
1
D6
PWPOA
1
D5
PWDA
1
D4
PWAD
1
D3
0
0
D2
0
D1
PWDA2
1
D0
PWDA1
1
D5
0
0
D4
0
0
D3
CLKB1
0
D2
CLKB0
1
D1
CLKA1
0
D0
CLKA0
1
0
PWDA1: Power-down control of DAC1 Analog
0: Power-down
1: Normal operation (default)
PWDA2: Power-down control of DAC2 Analog
0: Power-down
1: Normal operation (default)
PWAD: Power-down control of ADC
0: Power-down
1: Normal operation (default)
PWDA: Full-Power-down control of DAC1-2
0: Power-down
1: Normal operation (default)
PWPOA: Power-down control of PORTA
0: Power-down
1: Normal operation (default)
PWPOB: Power-down control of PORTB
0: Power-down
1: Normal operation (default)
Addr
02H
Register Name
Clock Select 1
Default
D7
0
0
D6
0
0
CLKA1-0: PORTA
00: DIR
01: X’tal(XTI) (default)
10: MCLK2
11: (Reserved)
CLKB1-0: PORTB
00: DIR
01: X’tal(XTI) (default)
10: MCLK2
11: (Reserved)
MS0427-J-03
2010/09
- 67 -
[AK4683]
Addr
03H
Register Name
Clock Select 2
Default
D7
D6
D5
D4
D3
D2
D1
D0
CKSL2
0
CKSL1
1
CKSL0
0
CLKL1
0
CLKL0
1
MCKO1
0
MCKO0
1
CLKDT
0
CLKDT: Clock source control for DIT
Refer Table 56.
MCLKO1-0: Clock source control for MCLKO
Refer Table 4.
CLKL1-0: Clock source control for Clock Gen C
00: DIR
01: X’tal(XTI) (default)
10: MCLK2
11: (Reserved)
CLSL2-0: Clock control for Clock Gen C
Refer Table 15.
Addr
04H
Register Name
Clock Select 3
Default
D7
D6
D5
D4
D3
D2
D1
D0
CKSAI2
0
CKSAI1
1
CKSAI0
0
SELAO
0
OLRA1
0
OLRA0
0
BCAF
0
MSA
0
MSA: Master/Slave control for input data of PORTA.
Refer Table 16.
BCAF: Bit clock control for PORTA
Refer Table 13.
OLRA1-0: Clock control for PORTA OLRCKA.
Refer Table 12.
SELAO: Clock control for DIR/DIT
0: Except for the case at “1”. (default)
1: Selects when the frequency of ILRCKA and OLRCKA are different, DITD[1:0] = “00” or “01” and
both SDTOA[1:0] and DITD[1:0] select same data source.
CKSAI2-0: Clock control for PORTA Input Data.
Refer Table 11.
MS0427-J-03
2010/09
- 68 -
[AK4683]
Addr
05H
Register Name
Clock Select 4
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
XTL1
0
XTL0
0
CKSDT
0
CKSB2
0
CKSB1
CKSB0
0
MSB
0
MSB: Master/Slave control for input data of PORTB.
Refer Table 17.
CKSB2-0: Clock control for PORTB.
Refer Table 9.
CKSDT: Clock control for DIT.
Refer Table 57.
XTL1-0: X’tal Frequency control
00: 11.2896MHz (default)
01: 12.288MHz
10: 24.576MHz
11: (channel status)
Addr
06H
Register Name
Sampling Speed
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
ACKSAI
ACKSAO
0
0
ACKSB
0
0
0
DFSAD
0
DFSDA1
0
DFSDA0
0
DFSDA1-0: DAC
PORT Auto Setting Mode
DFSAD, DFSDA1-0 bits
Table 22
DFSAD: ADC
PORT Auto Setting Mode
DFSAD, DFSDA1-0 bits
Table 21
ACKSB: Auto Setting Mode of PORTB
0:
, Manual Setting Mode (default)
1:
, Auto Setting Mode
ACKSB bit = “1”
MCLK
DFSAD, DFSDA1-0 bits
DFSAD, DFSDA1-0 bits
PORT
ACKSB bit = “0”
MCLK
ACKSAO: Auto Setting Mode of PORTA Output
0:
, Manual Setting Mode (default)
1:
, Auto Setting Mode
ACKSAO bit = “1”
MCLK
DFSAD, DFSDA1-0 bits
DFSAD, DFSDA1-0 bits
PORT
ACKSAO bit = “0”
MCLK
ACKSAI: Auto Setting Mode of PORTA Input
0:
, Manual Setting Mode (default)
1:
, Auto Setting Mode
ACKSAI bit = “1”
MCLK
DFSAD, DFSDA1-0 bits
DFSAD, DFSDA1-0 bits
PORT
ACKSAI bit = “0”
MCLK
MS0427-J-03
2010/09
- 69 -
[AK4683]
Addr
07H
Register Name
Data Source Select 1
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
DITD1
1
DITD0
1
SDTOB1
SDTOB0
SDTOA1
0
1
0
SDTOA0
1
SDTOA1-0: PORTA
00: DIR
01: ADC (default)
10: SDTIB
11: off (“L”
)
SDTOB1-0: PORTB
00: DIR
01: ADC (default)
10: off (“L”
)
11: SDTIA1
DITD1-0: DIT
00: DIR
01: ADC
10: SDTIB
11: SDTIA1 (default)
MS0427-J-03
2010/09
- 70 -
[AK4683]
Addr
08H
Register Name
Data Source Select 2
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
DAC22
1
DAC21
0
DAC20
0
0
0
DAC12
0
DAC11
1
DAC10
1
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
AIN2
0
AIN1
0
AIN0
0
DAC12-10: DAC1
000: DIR
001: ADC
010: SDTIB
011: SDTIA1 (default)
100: SDTIA2
101: SDTIA3
DAC22-20: DAC2
000: DIR
001: ADC
010: SDTIB
011: SDTIA1
100: SDTIA2 (default)
101: SDTIA3
Addr
09H
Register Name
Analog Input Control
Default
AIN2-0: ADC
000: LIN1/RIN1 (default)
001: LIN2/RIN2
010: LIN3/RIN3
011: LIN4/RIN4
100: LIN5/RIN5
101: LIN6/RIN6
110: None
111: None
Addr
0AH
Register Name
Audio Data Format
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
DIFB1
1
DIFB0
0
TDMA1
0
TDMA0
0
DIFA1
DIFA0
0
DIFA1-0, TDMA1-0: PORTA
Table 31, Table 32, Table 33
DIFB1-0: PORTB
Table 34
Addr
0BH
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
De-emphasis/ ATT speed
DEM11
0
DEM10
1
DEM21
0
DEM20
1
0
0
ATSAD
0
0
0
ATSDA
0
Default
ATSDA: DAC
ATSAD: ADC
Table 37, Table 38
DEM11-10: DAC1
DEM21-20: DAC2
Table 30
Default: “01”, OFF
MS0427-J-03
2010/09
- 71 -
[AK4683]
Addr
0CH
0DH
Register Name
LIN Volume Control
RIN Volume Control
Default
ATTAD7-0: ADC
Table 35
Addr
0EH
0FH
10H
11H
D7
D6
D5
D4
D3
D2
D1
D0
ATTAD7
ATTAD7
ATTAD6
ATTAD6
ATTAD5
ATTAD5
ATTAD4
ATTAD4
ATTAD3
ATTAD3
ATTAD2
ATTAD2
ATTAD1
ATTAD1
ATTAD0
0
0
1
1
0
0
0
0
Default: “30H”, 0dB
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
LOUT1 Volume Control
ROUT1 Volume Control
LOUT2 Volume Control
ROUT2 Volume Control
ATTDA7
ATTDA6
ATTDA5
ATTDA4
ATTDA3
ATTDA2
ATTDA1
ATTDA0
ATTDA7
ATTDA6
ATTDA5
ATTDA4
ATTDA3
ATTDA2
ATTDA1
ATTDA0
ATTDA7
ATTDA6
ATTDA5
ATTDA4
ATTDA3
ATTDA2
ATTDA1
ATTDA0
ATTDA7
ATTDA6
ATTDA5
ATTDA4
ATTDA3
ATTDA2
ATTDA1
ATTDA0
0
0
0
1
1
0
0
0
D5
0
D4
D3
D2
D1
D0
OPGA4
OPGA3
OPGA2
OPGA1
OPGA0
0
0
0
0
0
0
Default
ATTDA7-0: DAC
Table 36
Addr
12H
Default: “18H”, 0dB
Register Name
HPL Volume Control
Default
OPGA4-0: HP OPGA
Table 42
Addr
13H
ATTAD0
D7
D6
0
0
0
0
Default: “00H”, Mute
Register Name
OVF/DZF/V Control
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
ZCE
1
VIN
0
FUNC1
0
FUNC0
0
DZFM1
0
DZFM0
0
DZFM1-0: DZF
Table 7
FUNC1-0: OVF/DZF/V
00: off (“L”
01:
10:
11: V
default)
VIN: DIT V bit
0: V bit = “0” (default)
1: V bit = “1”
ZCE: OPGA
0:
1:
(default)
MS0427-J-03
2010/09
- 72 -
[AK4683]
■
(DIR/T
)
Addr
Register Name
00H CLK & Power Down Control
01H Format & De-em Control
02H Input/ Output Control 0
03H Input/ Output Control 1
04H INT MASK
05H TEST
06H Receiver status 0
07H Receiver status 1
08H RX Channel Status Byte 0
09H RX Channel Status Byte 1
0AH RX Channel Status Byte 2
0BH RX Channel Status Byte 3
0CH RX Channel Status Byte 4
0DH TX Channel Status Byte 0
0EH TX Channel Status Byte 1
0FH TX Channel Status Byte 2
10H TX Channel Status Byte 3
11H TX Channel Status Byte 4
12H Burst Preamble Pc Byte 0
13H Burst Preamble Pc Byte 1
14H Burst Preamble Pd Byte 0
15H Burst Preamble Pd Byte 1
16H Q-subcode Address / Control
17H Q-subcode Track
18H Q-subcode Index
19H Q-subcode Minute
1AH Q-subcode Second
1BH Q-subcode Frame
1CH Q-subcode Zero
1DH Q-subcode ABS Minute
1EH Q-subcode ABS Second
1FH Q-subcode ABS Frame
: PDN pin
“L”
RSTN2 bit “0”
PWN bit “0”
“0” bit
D7
D6
CS12
1
0
1
TXE
0
EFH1
EFH0
MQIT0 MAUT0
1
0
QINT AUTO
FS3
FS2
CR7
CR6
CR15
CR14
CR23
CR22
CR31
CR30
CR39
CR38
CT7
CT6
CT15
CT14
CT23
CT22
CT31
CT30
CT39
CT39
PC7
PC6
PC15
PC14
PD7
PD6
PD15
PD14
Q9
Q8
Q17
Q16
Q25
Q24
Q33
Q32
Q41
Q40
Q49
Q48
Q57
Q56
Q65
Q64
Q73
Q72
Q81
Q80
“0” “1” bit
D5
CM1
1
OPS1
0
MCIT0
1
CINT
FS1
CR5
CR13
CR21
CR29
CR37
CT5
CT13
CT21
CT29
CT39
PC5
PC13
PD5
PD13
Q7
Q15
Q23
Q31
Q39
Q47
Q55
Q63
Q71
Q79
D4
D3
CM0
OCKS1
0
DEAU
OPS0
0
0
DIT
MULK0 MDTS0
1
0
UNLCK DTSCD
FS0
0
CR4
CR3
CR12
CR11
CR20
CR19
CR28
CR27
CR36
CR35
CT4
CT3
CT12
CT11
CT20
CT19
CT28
CT27
CT39
CT39
PC4
PC3
PC12
PC11
PD4
PD3
PD12
PD11
Q6
Q5
Q14
Q13
Q22
Q21
Q30
Q29
Q38
Q37
Q46
Q45
Q54
Q53
Q62
Q61
Q70
Q69
Q78
Q77
D2
OCKS0
DEM1
0
0
MPE0
1
PEM
V
CR2
CR10
CR18
CR26
CR34
CT2
CT10
CT18
CT26
CT39
PC2
PC10
PD2
PD10
Q4
Q12
Q20
Q28
Q36
Q44
Q52
Q60
Q68
Q76
D1
PWN
DEM0
0
IPS1
MAUD0
0
AUDION
QCRC
CR1
CR9
CR17
CR25
CR33
CT1
CT9
CT17
CT25
CT39
PC1
PC9
PD1
PD9
Q3
Q11
Q19
Q27
Q35
Q43
Q51
Q59
Q67
Q75
D0
RSTN2
DFS
0
IPS0
MPAR0
1
PAR
CCRC
CR0
CR8
CR16
CR24
CR32
CT0
CT8
CT16
CT24
CT32
PC0
PC8
PD0
PD8
Q2
Q10
Q18
Q26
Q34
Q42
Q50
Q58
Q66
Q74
“1”
MS0427-J-03
2010/09
- 73 -
[AK4683]
■
Reset & Initialize
Addr
Register Name
00H CLK & Power Down Control
R/W
Default
D7
CS12
R/W
0
D6
1
R/W
1
D5
CM1
R/W
0
D4
CM0
R/W
0
D3
D2
OCKS1 OCKS0
R/W
R/W
0
0
D1
PWN
R/W
1
D0
RSTN2
R/W
1
RSTN2:
0:
1:
&
(default)
0:
1:
(default)
PWN:
OCKS1-0:
Refer Table 3, Table 57.
CM1-0:
Refer Table 1, Table 45, Table 55.
CS12:
0: Channel 1 (default)
1: Channel 2
C bit, AUDION, PEM, FS3-0, Pc, Pd
Format & De-emphasis Control
Addr
Register Name
01H Format & De-em Control
R/W
Default
D7
0
R/W
0
D6
1
R/W
1
D5
1
R/W
1
D4
0
R/W
0
D3
DEAU
R/W
1
D2
DEM1
R/W
0
D1
DEM0
R/W
1
D0
DFS
R/W
0
DFS: 96kHz
Refer Table 52.
DEM1-0: 32, 44.1, 48kHz
Refer Table 52.
DEAU:
0:
1:
(default)
MS0427-J-03
2010/09
- 74 -
[AK4683]
Input/Output Control
Addr
Register Name
02H Input/ Output Control 0
R/W
Default
D7
TXE
R/W
1
D6
0
R/W
0
D5
OPS1
R/W
0
D4
OPS0
R/W
0
D3
0
R/W
0
D2
0
R/W
0
D1
0
R/W
0
D0
0
R/W
0
D7
EFH1
R/W
0
D6
EFH0
R/W
1
D5
0
R/W
0
D4
0
R/W
0
D3
DIT
R/W
1
D2
0
R/W
0
D1
IPS1
R/W
0
D0
IPS0
R/W
0
D1
MAN0
R/W
1
D0
MPR0
R/W
0
OPS1-0:
Refer Table 54.
TXE: TX
0:
1:
TX pin
(default)
“L”
Addr
Register Name
03H Input/ Output Control 1
R/W
Default
IPS1-0:
Refer Table 53.
DIT: TX pin
0:
1:
(DIT U bit
(RX
“0”
)
(default)
)
EFH1-0: INT pin
00: 512 LRCK
01: 1024 LRCK (default)
10: 2048 LRCK
11: 4096 LRCK
Mask Control for INT
Addr
Register Name
04H INT MASK
R/W
Default
MPR0:
MAN0:
MPE0:
MDTS0:
MUL0:
MCI0:
MAT0:
MQI0:
D7
MQI0
R/W
1
D6
MAT0
R/W
1
D5
MCI0
R/W
1
D4
MUL0
R/W
0
D3
MDTS0
R/W
1
D2
MPE0
R/W
1
PAR bit
AUDN bit
PEM bit
DTSCD bit
UNLOCK bit
CINT bit
AUTO bit
QINT bit
0:
1:
MS0427-J-03
2010/09
- 75 -
[AK4683]
Receiver Status 0
Addr
Register Name
06H Receiver status 0
R/W
Default
D7
QINT
RD
0
D6
AUTO
RD
0
D5
CINT
RD
0
D4
D3
UNLCK DTSCD
RD
RD
0
0
D2
PEM
RD
0
D1
AUDION
RD
0
D0
PAR
RD
0
PAR:
0:No Error
1:Error
PAR bit
“1”
AUDION: Audio bit
0: Audio
1: Non Audio
PEM:
0: OFF
1: ON
DTSCD: DTS-CD
0:
1:
UNLCK: PLL
0:
1:
CINT:
0:
1:
AUTO: Non-PCM
0:
1:
QINT: Q
0:
1:
QINT, CINT, PAR bit 06H
READ
MS0427-J-03
2010/09
- 76 -
[AK4683]
Receiver Status 1
Addr
Register Name
07H Receiver status 1
R/W
Default
CCRC:
D7
FS3
RD
0
D6
FS2
RD
0
D5
FS1
RD
0
D4
FS0
RD
1
D3
0
RD
0
D2
V
RD
0
D1
QCRC
RD
0
D0
CCRC
RD
0
D2
CR2
CR10
CR18
CR26
CR34
D1
CR1
CR9
CR17
CR25
CR33
D0
CR0
CR8
CR16
CR24
CR32
D2
CT2
CT10
CT18
CT26
CT34
D1
CT1
CT9
CT17
CT25
CT335
D0
CT0
CT8
CT16
CT24
CT32
CRC
0:
1:
QCRC: Q
CRC
0:
1:
V:
0: Valid
1: Invalid
FS3-0:
(Table 48)
Receiver Channel Status
Addr
08H
09H
0AH
0BH
0CH
Register Name
RX Channel Status Byte 0
RX Channel Status Byte 1
RX Channel Status Byte 2
RX Channel Status Byte 3
RX Channel Status Byte 4
R/W
Default
CR39-0:
D7
CR7
CR15
CR23
CR31
CR39
D6
CR6
CR14
CR22
CR30
CR38
D5
CR5
CR13
CR21
CR29
CR37
D4
CR4
CR12
CR20
CR28
CR36
D3
CR3
CR11
CR19
CR27
CR35
RD
Not Initialized
Byte 4-0
Transmitter Channel Status
Addr
0DH
0EH
0FH
10H
11H
Register Name
TX Channel Status Byte 0
TX Channel Status Byte 1
TX Channel Status Byte 2
TX Channel Status Byte 3
TX Channel Status Byte 3
R/W
Default
CT39-0:
D7
CT7
CT15
CT23
CT31
CT39
D6
CT6
CT14
CT22
CT30
CT38
D5
CT5
CT13
CT21
CT29
CT37
D4
D3
CT4
CT3
CT12
CT11
CT20
CT19
CT28
CT27
CT36
CT35
R/W
0
Byte 4-0
MS0427-J-03
2010/09
- 77 -
[AK4683]
Burst Preamble Pc/Pd in non-PCM encoded Audio Bitstreams
Addr
12H
13H
14H
15H
Register Name
Burst Preamble Pc Byte 0
Burst Preamble Pc Byte 1
Burst Preamble Pd Byte 0
Burst Preamble Pd Byte 1
R/W
Default
PC15-0:
PD15-0:
D7
PC7
PC15
PD7
PD15
D6
PC6
PC14
PD6
PD14
D5
PC5
PC13
PD5
PD13
D4
PC4
PC12
PD4
PD12
D3
PC3
PC11
PD3
PD11
D2
PC2
PC10
PD2
PD10
D1
PC1
PC9
PD1
PD9
D0
PC0
PC8
PD0
PD8
D2
Q4
Q12
Q20
Q28
Q36
Q44
Q52
Q60
Q68
Q76
D1
Q3
Q11
Q19
Q27
Q35
Q43
Q51
Q59
Q67
Q75
D0
Q2
Q10
Q18
Q26
Q34
Q42
Q50
Q58
Q66
Q74
RD
Not Initialized
Pc Byte 0, 1
Pd Byte 0, 1
Q-subcode Buffer
Addr
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Register Name
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
R/W
Default
D7
Q9
Q17
Q25
Q33
Q41
Q49
Q57
Q65
Q73
Q81
D6
Q8
Q16
Q24
Q32
Q40
Q48
Q56
Q64
Q72
Q80
D5
Q7
Q15
Q23
Q31
Q39
Q47
Q55
Q63
Q71
Q79
D4
Q6
Q14
Q22
Q30
Q38
Q46
Q54
Q62
Q70
Q78
D3
Q5
Q13
Q21
Q29
Q37
Q45
Q53
Q61
Q69
Q77
RD
Not Initialized
MS0427-J-03
2010/09
- 78 -
[AK4683]
Figure 50
(AKD4683)
5
Analog in
+ 10u
12k
+
10u
0.1u
AVSS1 49
LIN1 51
AVDD1 50
LIN2 53
RIN1 52
LIN3 55
RIN2 54
LIN4 57
RIN3 56
LIN5 59
RIN4 58
LIN6 61
RIN5 60
RIN6 62
PVSS 63
R 64
0.1u
S/PDIF sources
1 PVDD
RISEL 48
2 RX0
ROPIN 47
3 I2C
LOPIN 46
4 RX1
LISEL 45
5 RX2
AVSS2 44
6 RX3
AVDD2 43
7 INT
+
0.1u
VCOM 42
8 DZF
+
2.2u
ROUT2 41
MUTE
LOUT2 40
MUTE
10 LRCKB
ROUT2 39
MUTE
11 BICKB
LOUT2 38
MUTE
12 SDTOB
MUTET 37
AK4683
9 CDTO/TEST
Audio DSP2
0.1u 10u
1u
HPL 36
14 ILRCKA
HPR 35
+
32 SDTIB
31 SDTIA3
30 SDTIA
29 SDTIA
27 SCL
26 SDA
25 PDN
23 TX
22 XTO
21 XTI
20 DVDD
47u
6.8
47u
Headphone
0.1u 10u
+
Analog 5V
X’tal
0.1u
C
C
3.3V to 5V
Digital
Audio DSP1
HVSS 34
HVDD 33
6.8
Analog out
10u
19 DVSS
18 TVDD
+
0.1u
10u
17 MCKO
16 SDTOA
24 MCLK2
15 BICKA
28 CSN/TEST
13 OLRCKA
Analog 5V
Micro
Controller
5V Digital
S/PDIF out
Digital Ground
Figure 50
Analog Ground
I2C
Note
-C
- AVSS, DVSS, PVSS, HVSS
-
R pin
RCA
AK4683
MS0427-J-03
PVSS
2010/09
- 79 -
[AK4683]
1.
AVDD1, AVDD2, DVDD, PVDD, HVDD
AVDD1, AVDD2, DVDD, PVDD, HVDD
AVSS1, AVSS2, DVSS, PVSS, HVSS
PC
2.
AVDD1 pin
AVDD2 pin
AVSS pin
0.1μF
2.2μF
VCOM pin
0.1μF
(AVDD1)/2
AVSS
VCOM pin
AVDD1 pin,
AVDD2 pin, VCOM pin
3.
ADC
VCOM
)
AK4683
AVSS1
2’s complement(2
)
AK4683
1.22 x AVDD1 Vpp (typ. fs=48kHz,
AVDD1
DC
HPF
=47kΩ,
64fs
=24kΩ
64fs
AK4683
(RC
64fs
)
4.
DAC
2’s compliment(2
800000H(@24bit)
(
VCOM
)
7FFFFFH(@24bit)
000000H(@24bit)
)
0.6x AVDD2 Vpp(typ)
VCOM
(SCF)
(CTF)
LSI
DC
VCOM
mV
5.
LIN1-6, RIN1-6 pin
Feedback
Pre-Amp
LOPIN, ROPIN pin
LIN1-6, RIN1-6 pin
MS0427-J-03
2010/09
- 80 -
[AK4683]
64pin LQFP(Unit: mm)
12.0
Max 1.85
10.0
1.40
0.00~0.25
33
32
48
12.0
49
64
17
16
1
0.5
0.2±0.1
0.09~0.25
0.10 M
0°~10°
0.50±0.25
0.10
■
(
)
MS0427-J-03
2010/09
- 81 -
[AK4683]
AKM
AK4683EQ
XXXXXXX
1
1)
2)
3)
4)
Date (YY/MM/DD)
05/09/30
05/11/15
Revision
00
01
Reason
Pin #1 indication
Asahi Kasei Logo
Marking Code: AK4683EQ
Date Code: XXXXXXX (7 digits)
Page
Contents
24
24
24
27
28
“CKSAO2-0 bit”
“CLKL1-0 bit
07/04/01
02
30
39
43
50
67
67
70
73
23,25
10/09/17
03
81
MS0427-J-03
(Table7)”… -> “(Table10)”
“DFSAD, DFSDA1-0 bit (Table 20, Table21)”… ->
(Table 21, Table 22)
Table 28, 29: “off” -> “SDTIB”
“Table 39 Ri
Rf …” -> “Table 40 …”
“Table 40
…” -> “Table 41 …”
CLKDT: “Table 54” -> “…Table 56”
SELAO: “DIT[1:0]” -> “DITD[1:0]”
DEM21-20: “Table 29” -> “Table 30”
DEM1-0: “Table 51” -> “Table 52”
PORTA
PORTB
2010/09
- 82 -
[AK4683]
z
z
z
z
z
z
MS0427-J-03
2010/09
- 83 -