Data Sheet

[AK7782]
AK7782
Dual Audio DSP with 24bit 5ch ADC & SRC
GENERAL DESCRIPTION
The AK7782 is an audio digital signal processor with integrated 24bit 5ch ADCs, an 8:2 stereo input
selector and sample rate converters that support 2ch inputs and the frequency up to 96kHz. The ADC
supports wide range of sampling frequency from 7.35kHz to 96kHz. Two integrated audio DSPs have
high performance processing speed of 2560step/fs (at 48kHz sampling), and two 6k-word delay RAMs
allow surround processing, time alignment adjusting and FIR filtering. As the AK7782 is a RAM based
DSP, it is programmable for various user requirements. It is housed in a 100pin LQFP package.
FEATURES
[DSP1/DSP2]
□ Word Length: 28-bits
□ Instruction Cycle Time: 8.1ns (2560fs, fs=48kHz)
□ Processing Step: 2560 steps (max) /fs= 48kHz, 44.1kHz (Normal Speed)
15360 steps (max) /fs= 8kHz, 7.35kHz
1280 steps (max) fs= 96kHz, 88.2kHz (Double Speed)
□ Multiplier: 24 x 16 → 40-bits (double precision available)
□ Divider: 24 ÷ 24 → 24-bits (floating point normalization function)
□ ALU: 44-bit arithmetic operation (with 4-bit overflow margin)
□
24-bit arithmetic and logic operation
Data Shift: Right shift after multiplication 1, 2, 4, 5, 8, 14, 15-bits
Right shift BUS 1, 2, 3, 4, 8, 14, 15-bits
Left shift after multiplication 1, 2, 3, 4, 8, 15-bits
Left shift BUS 1, 2, 3, 4, 6, 8, 15-bits
Indirect shifting function
Program RAM (PRAM): 2048word x 36-bits
□
□ Coefficient RAM (CRAM): 2048word x 16-bits
□ Data RAM (DRAM): 2048word x 28-bits
□ Offset Register (OFREG): 64word x 13-bits
□ Delay RAM (DLRAM): 168kbit (four types)
● 6kword 28-bits
● 4kword 28-bits + 4kword 14-bits
● 3kword 28-bits + 6kword 14-bits
● 3kword 28-bits + 3kword 28-bits (Linear)
□ Register: 44-bits x 4 (ACC) [for ALU]
28-bits x 12 (TMP) [DBUS connection]
28-bits x 6 steps stack (PTMP) [DBUS connection]
MS1337-E-00
2011/11
- 1-
[AK7782]
[Stereo ADC, Common for ADC1 and ADC2]
□ 24-bit 2ch x 2
□ S/(N+D): 90dB (fs=48kHz)
□ D-range: 96dBA (fs=48kHz)
□ S/N: 96dBA (fs=48kHz)
□ 8ch bidirectional analog input selector
□ High-pass filter (HPF) for DC offset cancellation
□ fs=7.35kHz ~ 96kHz
[Mono ADC]
□ 24bit 1ch
□ S/(N+D) 88dB (fs=48kHz)
□ D-range 95dBA (fs=48kHz)
□ S/N 95dBA (fs=48kHz)
□ High-pass filter (HPF) for DC offset cancellation
□ fs=7.35kHz ~ 96kHz
□ Digital volume control
[DSP1/DSP2 In/Output Digital Interface]
□ Serial Data Input: 14ch (including ADC block)
□ Serial Data Output: 16ch (each DSP outputs are 14ch)
□ Microcomputer Interface: 1ch In/Out or I2C-bus
[SRC, Common for SRC1 and SRC2]
□ 2ch x 2
□ fs=7.35kHz ~ 96kHz
[General]
□ PLL
□ 3.3V±0.3V, 1.8V ±0.1V
□ Operational Temperature: -40°C ~ 85°C
□ 100pin LQFP
MS1337-E-00
2011/11
- 2-
[AK7782]
AINL8, AINR8
2
2
2
2
AINM
AINL5, AINR5
2
AINL6 AINR6
2
AINL7, AINR7
AINL3, AINR3
2
AINL4, AINR4
AINL+,AINR+
AINL+,AINR+
4
AINL2, AINR2
■ Block Diagram
pull down
Hi-z
3 VSS3
8
3
6 DVDD
ASEL2[2:0]
ASEL1[2:0]
ctrl reg sw
ADC1
ADC2
ADCM
VOL
3 AVDD
3 VREFH
VREF
MUX
VCOM
VREFL
3 VSS1
OUTASEL1
0
1
2
3
SDIN7/JX2
JX2
SDIN6 / JX1
P1IN6SEL
JX1
SDIN5
P1IN5SEL
P1SDIN7
0 1
P2IN7SEL
P1SDOUT7
0
1
2
3
0
1
2
3
P1SDIN6
P2SDIN7
0
1
2
3
0
1
2
3
P1SDIN5
P1SDOUT5
IRPT1
P1SDOUT3
GPO10
SDIN2(32bit)
P1SDIN2
P1SDOUT2
P2IN5SEL
0
1
2
3
0
OUTAEN
0
1
2
3
P2SDOUT7
P2SDIN3
P1SDIN1
P1SDOUT1
JX12
SRC1I SRC1O
SRC1LRCKO
SRC1BICKO
JX11
JX10
SRC1
DSP1
SRC1LRCKI
SRC1BICKI
JX12E
JX11E
OUT5EN
P2SDIN1
SDOUT5
OUT4SEL
0
1
2
3
P2SDOUT4
GPO21
OUT4EN
P2SDOUT3
GPO20
SDOUT4(32bit)
OUT3SEL
0
1
2
3
OUT3EN
SDOUT3(32bit)
OUT2SEL
0
1
2
3
OUT2EN
SDOUT2(32bit)
OUT1SEL1
0
1
2
3
0
1
2
3
SDOUT6
OUT5SEL1
P2SDOUT5
IRPT2
P2SDIN2
1
P2IN2SEL
OUT6SEL
P2SDOUT6
P2SDOUT2
0
0
1
2
3
P2SDIN5
SDOUT7
OUT7EN
OUT6EN
0
1
2
3
P2SDIN4
1
P2IN4SEL
0
SRCLRCK
SRCBICK
SDOUTA
3
0
1
2
3
P2SDIN6
1
P2IN3SEL
RSRC1RSTN
1
MSEL
P2IN6SEL
P1SDIN3
PSRCRSTN
2 3
P1SDOUT6
SDIN3(32bit)
PSRCSMUTE
0
OUT7SEL
P1SDOUT4
GPO11
RSRC1SMUTE
OUTASEL2
1
2
2
P1SDIN4
P1IN1SEL
0
3
P1IN7SEL
SDIN4(32bit)
SDIN1
2 VSS2
7 DVDD18
I/O
OUT1EN
SDOUT1
P2SDOUT1
JX22E
JX22
P2IN1SEL
JX21E
JX21
JX10E
JX20E
JX20
JX2
JX1
JX0
WDT1EN
WDT1
CRCE
SRC1UNLOCK
DSP2
SRC2LRCK
SRC2BICK
NC
STO
WDT2EN
WDT2
LOCK1E
LOCK2E
0
1
2
3
RSRC2SMUTE
SRC2I SRC2O
SRC2LRCKO
SRC2BICKO
CRC
RSRCRST2N
0
1
SRC2
MICIF
SRC2CKO
SRC2LRCKI
1
SRC2CKI
I2CSEL
SDA
2
0
2
SCLK/SCL
SO
0
2
SI/CAD0
RQN/CAD1
2
0
1
1
TESTO
SRC2ISEL
RDY
SRC2BICKI
SRC2UNLOCK
LRCLKO
BITCLKO
TESTI2
TESTI1
CKM[2:0] 3
XTI
XTO
CONTROLLER
CKRSTN
PCKRSTN
RCKRSTN
PDSPRSTN
RDSPRSTN
(Master="H",Slave="L")
SMODE
DSPRSTN
SRESETN
PADRSTN
RADRSTN
ADRSTN
LFLT
CLKO1
LRCLKI
BITCLKI
INITRSTN
Figure 1. Block Diagram
MS1337-E-00
2011/11
- 3-
[AK7782]
■ DSP Block Diagram (Common for DSP1 and DSP2)
DLP0, DLP1
DP0, DP1
CP0, CP1
DLRAM
6kw x 28bit
DRAM
2048w x 28bit
CRAM
2048w x 16bit
etc
OFREG
64w x 13bit
CBUS(16bit)
DBUS(28bit)
MPX16
Micon I/F
MPX24
X
Control
DEC
Y
PRAM
2048w x 36bit
Multiply
16bit x 24bit → 40bit
PC
Stack: 5level(max)
TMP
28bit
40bit
12 x 28bit
PTMP(LIFO) 6 x 28bit
MUL
44bit
A
DBUS
2 x 24/24.4bit
SDIN7
SHIFT
2 x 24/24.4bit
SDIN6
44bit
2 x 24/24.4bit
SDIN5
2 x 24/20/16/32/24.4bit
SDIN4
2 x 24/20/16/32/24.4bit
SDIN3
2 x 24/20/16/32/24.4bit
SDIN2
2 x 24/24.4bit
SDIN1
B
ALU
44bit
Overflow Margin: 4bit
44bit
DR0-3
44bit
Over Flow Data
Generator
Division 24÷24→24
Serial I/F
2 x 24/24.4bit
SDOUT7
2 x 24/24.4bit
SDOUT6
2 x 24/24.4bit
SDOUT5
2 x 24/16/32/24.4bit
SDOUT4
2 x 24/16/32/24.4bit
SDOUT3
2 x 24/16/32/24.4bit
SDOUT2
2 x 24/24.4bit
SDOUT1
Peak Detector
MS1337-E-00
2011/11
- 4-
[AK7782]
■ Ordering Guide
-40 ∼ +85°C
100pin LQFP (0.5mm pitch)
Evaluation Board for AK7782
AK7782VQ
AKD7782
RDY
STO
SDOUTA1
SDOUT6
SDOUT7
DVDD
DVDD18
VSS3
SDIN6/JX1
SDIN7/JX2
JX0
SDIN1
SRCBICK
SRCLRCK
PSRCRSTN
SDA
DVDD18
VSS3
DVDD
PSRCSMUTE
VSS2
VSS1
AVDD
TESTI2
NC
■ Pin Layout
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC
AINM
76
77
50
49
AINR4
78
48
VSS3
AINL4
79
47
DVDD18
AINR3
80
81
46
45
SCLK/SCL
AINL3
AINR2
82
44
RQN/CAD1
AINL2
43
42
PDSPRSTN
AVDD
83
84
VREFH
85
41
PCKRSTN
VCOM
86
40
INITRSTN
VREFL
39
38
VSS3
VSS1
87
88
AINR-
89
37
LRCLKI
AINR+
36
35
BITCLKI
AINL-
90
91
AINR+
92
34
SDIN4
AINR5
93
94
33
32
SDIN3
AINL5
AINR6
95
31
DVDD18
AINL6
96
30
VSS3
AINR7
97
98
29
28
DVDD
AINL7
AINR8
99
27
SDOUT5
AINL8
100
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
SDOUT4
100 pin LQFP
SDOUT3
SDOUT2
SDOUT1
BITCLKO
LRCLKO
VSS3
DVDD
DVDD18
CKM[2]
CKM[0]
DVDD18
CKM[1]
XTO
VSS3
XTI
DVDD
VSS3
VSS2
SRC2BICK
SRC2LRCK
TESTI1
I2CSEL
AVDD
LFLT
VSS1
(TOP VIEW)
SO
DVDD
SI/CAD0
PADRSTN
DVDD18
SDIN5
SDIN2
CLKO1
pin
Input
Output
I/O
Power
Figure 2. Pin Layout
MS1337-E-00
2011/11
- 5-
[AK7782]
PIN/FUNCTION
No. Pin Name
I/O
Function
Filter Connection Pin for AK7782 Core PLL
When using the PLL function, connect with R (1.5kΩ) and C (47nF) in
series and connected to analog ground (VSS1)
Ground Pin 0V (silicon board potential)
Power Supply Pin for Analog Block 3.3V (typ)
Test Pin (Internal pull-down)
Connect to VSS3
I2C-bus Select Pin
“L”: Normal Microcomputer Interface
“H”: I2C-bus selected mode. SCL and SDA are active.
I2CSEL must be fixed to “L” (VSS3) or “H” (DVDD).
LR Clock Input Pin for SRC2
BIT Clock Input Pin for SRC2
Ground Pin (silicon board potential)
Connect to VSS1
Classification
1
LFLT
O
Analog Output
2
3
VSS1
AVDD
-
4
TESTI1
I
5
I2CSEL
I
6
7
SRC2LRCK
SRC2BICK
I
I
8
VSS2
-
9
DVDD
-
Power Supply Pin for Digital Block 3.3V (typ)
Digital Power
Supply
10
VSS3
-
Ground Pin 0V
Power Supply
11
XTI
I
12
XTO
O
13
14
15
16
17
VSS3
DVDD18
CKM [1]
CKM [0]
CKM [2]
I
I
I
18
DVDD18
-
19
20
VSS3
DVDD
-
Power Supply
Test
I2C Select
SRC2
Power Supply
Crystal Oscillator Input Pin
Connect a crystal oscillator between the XTI pin and XTO pin or input
an external clock into the XTI pin when not using a crystal oscillator.
System Clock
Crystal Oscillator Output Pin
Connect a crystal oscillator between the XTI pin and XTO pin or leave
open when using an external clock source.
Ground Pin 0V
Power Supply
Power Supply Pin for Digital Block 1.8V (typ)
Clock Mode Select Pin
Mode Select
Clock Mode Select Pin
Clock Mode Select Pin
Digital Power
Power Supply Pin for Digital Block 1.8V (typ)
Supply
Ground Pin 0V
Power Supply
Power Supply Pin for Digital Block 3.3V (typ)
MS1337-E-00
2011/11
- 6-
[AK7782]
No. Pin Name
21
LRCLKO
I/O
O
Function
LR Channel Select Pin
Master mode: Outputs 1fs clock.
Slave mode: Outputs LRCLKI clock.
Serial bit Clock Output Pin
Master mode: Outputs 64fs clock.
Slave mode: Outputs BITCLKI clock
DSP Serial Data Output Pin
Outputs “L” during initial reset.
The output data is selected by CONT7 D3, D2.
DSP Serial Data Output Pin
Outputs “L” during initial reset.
The output data is selected by CONT7 D5, D4.
DSP Serial Data Output Pin
Outputs “L” during initial reset.
The output data is selected by CONT7 D7, D6.
DSP Serial Data Output Pin
Outputs “L” during initial reset.
The output data is selected by CONT6 D1, D0.
DSP Serial Data Output Pin
Outputs “L” during initial reset.
The output data is selected by CONT6 D3, D2.
Clock Output Pin 1
Output frequency can be set by control registers.
Outputs “L” during initial reset.
22
BITCLKO
O
23
SDOUT1
O
24
SDOUT2
O
25
SDOUT3
O
26
SDOUT4
O
27
SDOUT5
O
28
CLKO1
O
29
DVDD
-
Power Supply Pin for Digital Block 3.3V (typ)
30
31
VSS3
DVDD18
-
32
SDIN2
I
33
SDIN3
I
34
SDIN4
I
35
SDIN5
I
Ground Pin 0V
Power Supply Pin for Digital Block 1.8V (typ)
DSP Serial Data Input Pin
Supports floating point input F24.4:
MSB 32-bit and 24-bit / LSB 24-bit, 20-bit and 16-bit.
Connect to VSS3 when this pin is not used.
DSP Serial Data Input Pin
Supports floating point input F24.4:
MSB 32-bit and 24-bit / LSB 24-bit, 20-bit and 16-bit.
Connect to VSS3 when this pin is not used.
DSP Serial Data Input Pin
Supports floating point input F24.4:
MSB 32-bit and 24-bit / LSB 24-bit, 20-bit and 16-bit.
Connect to VSS3 when this pin is not used.
DSP Serial Data Input Pin
Supports floating point input F24.4:
MSB 24-bit / LSB 24-bit, 20-bit and 16-bit.
Connect to VSS3 when this pin is not used.
MS1337-E-00
Classification
System Clock
Digital Block
Serial Data Output
Clock Output
Digital Power
Supply
Power Supply
Digital Block
Serial Data Input
Digital Block
Serial Data Input
2011/11
- 7-
[AK7782]
No.
36
37
Pin Name
BITCLKI
LRCLKI
I/O
I
Serial bit Clock input Pin
I
LR channel select Input Pin
Function
38
DVDD18
-
Power Supply Pin for Digital Block 1.8V (typ)
39
VSS3
-
40
INITRSTN
I
41
PCKRSTN
I
System Clock
42
PADRSTN
I
43
PDSPRSTN
I
RQN
I
CAD1
I
SI
I
CAD0
I
SCLK
I
SCL
I
Ground Pin 0V
Initial Reset N Pin (for device initialization)
The AK7782 is initialized by the INITRSTN pin = “L”.
This pin must be “L” upon power-up the AK7782.
CKM[2:0] Pin settings can be change when the INITRSTN pin = “L”.
Clock Reset N Pin
The internal clock is reset by the PCKRSTN pin = “L”.
Setting of CKM[2:0] can be changed by the PCKRSTN pin = “L”,
even if the INITRSTN pin is “H”.
ADC Reset N Pin
ADC1, ADC2 and ADCM are reset by the PADRSTN pin = “L”.
Control register RADRSTN bit= “0” can also reset these blocks.
The AK7782 is in system reset state when PADRSTN and PDSPRSTN
pins = “L”.
DSP Reset N Pin
DSP1 and DSP2 are reset by the PDSPRSTN= “L”. Control Register
RDSRE bit = “0” can also reset these blocks .
The AK7782 is in system reset state when PADRSTN and PDSPRSTN
pins = “L”.
Microcomputer Interface Request N Pin (I2CSEL= “L”)
Set this pin to “H” during initial reset or when not interfacing to a
microcomputer.
I2C-bus Address Pin 1 (I2CSEL= “H”)
Serial Data Input Pin for Microcomputer Interface (I2CSEL= “L”)
Set this pin to “L” when not used.
I2C-bus address Pin 0 (I2CSEL= “H”)
Serial Data Clock Pin for Microcomputer Interface (I2CSEL= “L”)
Set this pin to “H” when there is no clock input.
SCL I2C-bus Interface Pin (I2CSEL= “H”)
47
DVDD18
-
Power Supply Pin for Digital Block 1.8V (typ)
48
VSS3
-
Ground Pin 0V
49
DVDD
-
Power Supply Pin for Digital Block 3.3V (typ)
50
SO
O
Serial Data Output Pin for Microcomputer Interface
Outputs “Hi-z” when the RQN pin = “H”.
Outputs “Hi-z” during initial reset.
44
45
46
Classification
MS1337-E-00
Digital Power
Supply
Power Supply
Reset
Microcomputer
I/F
I2C
Microcomputer
I/F
I2C
Microcomputer
I/F
I2C
Digital Power
Supply
Power Supply
Digital Power
Supply
Microcomputer
I/F
2011/11
- 8-
[AK7782]
No. Pin Name
I/O
51
O
RDY
Function
Data write ready Pin for Microcomputer Interface
Status Output Pin
“H”: Normal operation
“L”: WDT, CRC error or SRCUNLOCK status (Figure 1)
Outputs “H” during initial reset.
Serial Data Output Pin
Supports MSB 24-bit.
Outputs “L” during initial reset.
Serial Data Output Pin
Supports MSB 24-bit.
Outputs “L” during initial reset.
Serial Data Output Pin
Supports MSB 24-bit.
Outputs “L” during initial reset.
52
STO
O
53
SDOUTA1
O
54
SDOUT6
O
55
SDOUT7
O
56
DVDD
-
Power Supply Pin for Digital Block 3.3V (typ)
57
VSS3
-
Ground Pin 0V
58
DVDD18
-
Power Supply Pin for Digital Block 1.8V (typ)
SDIN7
I
JX2
I
SDIN6
I
JX1
I
61
JX0
I
62
SDIN1
I
63
SRCBICK
I
SRCLRCK
I
59
60
64
65
66
67
68
69
70
71
Classification
Microcomputer
I/F
Status
Digital Block
Serial Data Output
Digital Power
Supply
Power Supply
Digital Power
Supply
DSP Serial Data Input Pin
Digital Block
Connect to VSS3 when this pin is not used. This pin supports 24-bit
Serial Data Input
MSB justified, floating point F24.4.
Conditional Jump Pin
Condition
Connect to VSS3 when this pin is not used.
DSP Serial Data Input Pin
Digital Block
Connect to VSS3 when this pin is not used. This pin supports 24-bit
Serial Data Input
MSB justified, floating point F24.4.
Conditional Jump Pin
Connect to VSS3 when this pin is not used.
Condition
Conditional Jump Pin
Connect to VSS3 when this pin is not used.
DSP/SRC Serial Data Input Pin
Digital Block
Connect to VSS3 when this pin is not used. This pin supports 24-bit
Serial Data Input
MSB justified, floating point F24.4.
SRC Serial bit Clock Input Pin
SRC1
SRC LR channel Select Input Pin
I2CSEL Pin = “L”
O
Outputs “L”.
SDA
I2C
I2CSEL Pin= “H”
I/O
SDA I2C-bus Interface
SRC Reset N Pin
SRC1 and SRC2 blocks are reset by the PSRCRSTN pin = “L”. Reset
PSRCRSTN I
Control register RSRCRSTN bit = “0” can also reset these blocks.
Digital Power
DVDD18
- Power Supply Pin for Digital Block 1.8V (typ)
Supply
VSS3
- Ground Pin 0V
Power Supply
Digital Power
DVDD
- Power Supply Pin for Digital Block 3.3V (typ)
Supply
Ground Pin 0V (silicon board potential)
Power Supply
VSS2
Connect to VSS1.
SRC Soft Mute Pin
PSRC
SRC1 and SRC2 blocks are soft muted by the PSRCSMUTE pin =
SRC
I
SMUTE
“H”. Control register RSRCSMUTE bit = “1” can also soft mutes
these blocks.
MS1337-E-00
2011/11
- 9-
[AK7782]
No. Pin Name
I/O
Function
Classification
72
TESTI2
I
Test Pin (Internal pull-down)
Connect to VSS3.
Test
73
AVDD
-
Power Supply Pin for Analog Block 3.3V (typ)
Analog Power
Supply
74
VSS1
-
Ground Pin 0V (silicon board potential)
Power Supply
75
NC
-
76
NC
-
77
78
79
80
81
82
83
AINM
AINR4
AINL4
AINR3
AINL3
AINR2
AINL2
I
I
I
I
I
I
I
NC Pin
Connect to VSS1.
NC Pin
Connect to VSS1.
ADCM Mono Single-ended Input Pin
Rch Single-ended Input Pin for ADC1 or ADC2
Lch Single-ended Input Pin for ADC1 or ADC2
Rch Single-ended Input Pin for ADC1 or ADC2
Lch Single-ended Input Pin for ADC1 or ADC2
Rch Single-ended Input Pin for ADC1 or ADC2
Lch Single-ended Input Pin for ADC1 or ADC2
84
AVDD
-
Power Supply Pin for analog Block 3.3V (typ)
NC
NC
Analog Input
Analog Power
Supply
Reference voltage Input Pin for analog Block
Connect this pin to AVDD, and connect a 0.1μF and 10μF capacitors Analog Input
between this pin and VSS1.
Common voltage Output Pin for analog Block
86
VCOM
O
Analog Output
Connect a 0.1μF and 10μF capacitors between this pin and VSS1.
Do not connect to external circuits.
Reference voltage input Pin for analog Block
87
VREFL
I
Analog Input
Normally, this pin is connected to VSS1.
88
VSS1
- Ground Pin 0V (silicon board potential)
Power Supply
89
AINRI Rch Differential Input Pin for ADC1 or ADC2
90
AINR+
I Rch Differential Input Pin for ADC1 or ADC2
91
AINLI Lch Differential Input Pin for ADC1 or ADC2
92
AINL+
I Lch Differential Input Pin for ADC1 or ADC2
93
AINR5
I Rch Single-ended Input Pin for ADC1 or ADC2
94
AINL5
I Lch Single-ended Input Pin for ADC1 or ADC2
Analog Input
95
AINR6
I Rch Single-ended Input Pin for ADC1 or ADC2
96
AINL6
I Lch Single-ended Input Pin for ADC1 or ADC2
97
AINR7
I Rch Single-ended Input Pin for ADC1 or ADC2
98
AINL7
I Lch Single-ended Input Pin for ADC1 or ADC2
99
AINR8
I Rch Single-ended Input Pin for ADC1 or ADC2
100
AINL8
I Lch Single-ended Input Pin for ADC1 or ADC2
Note 1. All digital input pins must not be allowed to float.
Note 2. If analog input pins (AINR-, AINR+, AINL-, AINL+, AINL2~8, AINR2~8, AINM) are not used, leave them
open.
Note 3. The I2CSEL pin should be fixed to “L” (VSS3) or “H” (DVDD).
85
VREFH
I
MS1337-E-00
2011/11
- 10-
[AK7782]
■ Handling of Unused Pins
Unused I/O pins must be connected appropriately.
Pin Name
AINL+, AINL-, AINR+, AINR-, AINL2, AINR2, AINL3, AINR3, AINL4, AINR4,
Analog
AINL5, AINR5, AINL6, AINR6, AINL7, AINR7, AINL8, AINR8, AINM
XTO, LRCLKO, BITCLKO, SDOUT1, SDOUT2, SDOUT3, SDOUT4, SDOUT5,
CLKO1, SO, RDY, STO, SDOTUA1, SDOUT6, SDOUT7, SDA (I2CSEL= “L”)
Digital
TESTI1, SRC2LRCK, SRC2BICK, XTI, SDIN2, SDIN3, SDIN4, SDIN5,
PCKRSTN, PADRSTN, SDIN7/JX2, SDIN6/JX1, JX0, SDIN1, SRCBICK,
SRCLRCK, PSRCRSTN, PSRCSMUTE, TESTI2
Relationship between the I2CSEL pin and the SDA
I2CSEL
Normal Microcomputer
L
Interface
L
I2C-bus
H
H
MS1337-E-00
INITRSTN
L
H
L
H
Setting
Leave Open
Leave Open
Connect to VSS3
SDA
L
L
“Hi-Z” → pull-up
function
2011/11
- 11-
[AK7782]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=VSS3=0V; Note 4)
Parameter
Symbol
min
Power Supply Voltage
Analog (AVDD)
VA
-0.3
Digital (DVDD)
VD
-0.3
Digital (DVDD18)
VD18
-0.3
|VSS1(VSS2) – VSS3| (Note 5)
ΔGND
-0.3
Input Current (except for power supply pin)
IIN
–
Analog Input Voltage
AINL+, AINL-, AINR+, AINR-,
VINA
-0.3
AINL2~8, AINR2~8, AINM
VREFH, VREFL
Digital Input Voltage
VIND
-0.3
Operational Ambient Temperature
Ta
-40
Storage Temperature
Tstg
-65
Note 4. All voltages with respect to ground.
Note 5. VSS1, VSS2 and VSS3 must be connected to the same ground plane.
max
Unit
4.3
4.3
2.5
+0.3
±10
V
V
V
V
mA
(VA+0.3) ≤ 4.3
V
(VD+0.3) ≤ 4.3
85
150
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATION CONDITION
(VSS1=VSS2=VSS3=0V; Note 4)
Parameter
Symbol
min
typ
max
Unit
Power Supply Voltage
AVDD
VA
3.0
3.3
3.6
V
DVDD
VD
3.0
3.3
3.6
V
DVDD18
VD18
1.7
1.8
1.9
V
AVDD-DVDD
ΔVDD
-0.3
0
+0.3
V
Reference Voltage (VREF)
VREFH
(Note 6)
VRH
VA
V
VREFL
(Note 7)
VRL
0.0
V
Note 4. All voltages with respect to ground.
Note 6. The VREFH pin is normally connected to AVDD.
Note 7. The VREFL pin is normally connected to VSS1.
Note 8. The analog input voltage is proportional to the (VREFH-VREFL) voltage.
Note 9. The power-up sequence between AVDD, DVDD and DVDD18 is not critical. The INITRSTN pin should be held
“L” when power is supplied. The INITRSTN pin is allowed to be “H” after all power supplies are applied and
settled.
Note 10. Do not turn off the power supply of the AK7782 when the power supplies of the surrounding device are turned
on in I2C-bus mode (I2CSEL pin = “H”). Pull-up resistors at SDA and SCL pins must be connected to the DVDD
voltage or less. (A diode exists for DVDD in the SDA and SCL pins.)
WARNING: AKM assumes no responsibility for the usage beyond the conditions in the datasheet.
MS1337-E-00
2011/11
- 12-
[AK7782]
ANALOG CHARACTERISTICS
(1) Analog Characteristics
1-1) ADC
(Ta=25°C; AVDD=DVDD=3.3V; DVDD18=1.8V, VREFH=AVDD, VREFL=VSS1, BITCLK=64fs; Signal frequency
1kHz; Measurement [email protected], [email protected]; ADC full differential input (ADC1,
ADC2); CKM Mode 0 (CKM[2:0]=000), during SRC reset, unless otherwise specified.)
Parameter
min
typ
max
Unit
Resolution
24
Bits
Stereo
ADC
Dynamic Characteristics
S/(N+D)
fs = 48kHz (-1dBFS) Note 11)
82
90
dB
ADC1
fs = 96kHz (-1dBFS)
87
dB
ADC2
Dynamic Range
fs = 48kHz (A-filter) Note 11, Note 12)
88
96
dB
fs = 96kHz
93
dB
S/N
fs = 48kHz (A-filter) Note 11)
88
96
dB
fs = 96kHz
93
dB
Inter-channel Isolation (f=1kHz) Note 13)
90
115
dB
DC Accuracy
Channel Gain Mismatch
0.0
0.3
dB
Analog Input
Input Voltage (Differential Input)
Note 14)
±1.85
±2.00
±2.15
Vp-p
Input Voltage (Single-ended Input)
Note 15)
1.85
2.00
2.15
Vp-p
Input Impedance
Note 16)
22
33
kΩ
Resolution
24
Bits
Mono
ADC
Dynamic Characteristics
S/(N+D)
fs = 48kHz (-1dBFS)
78
88
dB
ADCM
fs = 96kHz (-1dBFS)
87
dB
Dynamic Range
fs = 48kHz (A-filter) Note 12)
87
95
dB
fs = 96kHz
92
dB
dB
S/N
fs = 48kHz (A-filter)
87
95
dB
fs = 96kHz
92
Analog Input
Input Voltage
Note 17)
1.85
2.00
2.15
Vp-p
Input Impedance
Note 18)
22
33
kΩ
Note 11. Values are not guaranteed with single-ended inputs.
Note 12. S/(N+D) when -60dB signal is applied.
Note 13. Inter-channel isolation between L-channel and R-channel at –1dBFS signal input.
Note 14. AINL+, AINL-, AINR+, and AINR- pins.
The full scale for differential input voltage is (± FS= ± (VREFH-VREFL) x (2.0/3.3)).
Note 15. AINL2~L8, and AINR2~R8 pins.
The full scale of single-ended input voltage (FS=(VREFH-VREFL) x (2.0/3.3)).
Note 16. AINL+, AINL-, AINR+, AINR-, AINL2~L8, and AINR2~R8 pins.
Note 17. AINM pin. The full scale of input voltage is (FS=(VREFH-VREFL) x (2.0/3.3)).
Note 18. AINM pin.
MS1337-E-00
2011/11
- 13-
[AK7782]
1-2) SRC
(Ta=25°C; AVDD = 3.3V; DVDD=3.3V; DVDD18=1.8V; data = 24bit; measurement bandwidth = 20Hz∼ FSO/2, unless
otherwise specified.)
Parameter
Symbol
min
typ
max
Unit
Resolution
24
Bits
Input Sample Rate
FSI
7.35
96
kHz
Output Sample Rate
FSO
7.35
96
kHz
THD+N
(Input= 1kHz, 0dBFS)
FSO/FSI=44.1kHz/48kHz
-112
dB
FSO/FSI=44.1kHz/96kHz
-112
dB
FSO/FSI=48kHz/44.1kHz
-112
dB
FSO/FSI=48kHz/96kHz
-112
dB
FSO/FSI=48kHz/8kHz
-111
-103
dB
FSO/FSI=8kHz/48kHz
-112
dB
FSO/FSI=8kHz/44.1kHz
-100
dB
Dynamic Range (Input= 1kHz, -60dBFS)
FSO/FSI=44.1kHz/48kHz
113
dB
FSO/FSI=44.1kHz/96kHz
113
dB
FSO/FSI=48kHz/44.1kHz
113
dB
FSO/FSI=48kHz/96kHz
113
dB
FSO/FSI=48kHz/8kHz
109
112
dB
FSO/FSI=8kHz/48kHz
113
dB
FSO/FSI=8kHz/44.1kHz
113
dB
Dynamic Range (Input= 1kHz, -60dBFS, A-weighted
FSO/FSI=44.1kHz/48kHz
115
dB
Ratio between Input and Output Sample Rate
FSO/FSI
0.167
6
MS1337-E-00
2011/11
- 14-
[AK7782]
DC CHARACTERISTICS
(Ta=-40°C~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
min
High Level Input Voltage
Note 19)
VIH
80%DVDD
Low Level Input Voltage
Note 19)
VIL
SCL, SDA High Level Input Voltage
VIH
70%DVDD
SCL, SDA Low Level Input Voltage
VIL
VOH
DVDD-0.5
High Level Output Voltage Iout=-100μA
VOL
Low Level Output Voltage Iout=100μA Note 20)
SDA Low Level Output Voltage Iout=3mA
VOL
Input Leak Current
Note 21)
Iin
Input Leak Current (pull-down pin)
Note 22)
Iid
Input Leak Current (XTI pin)
Iix
typ
max
Unit
V
20%DVDD
V
V
30%DVDD
V
V
0.5
V
0.4
V
±10
μA
22
μA
26
μA
Note 19. Except for the SDA pin and the SCL pin (when I2CSEL= “1”). The SCLK pin is included when I2CSEL = “0”.
Note 20. Except for the SDA pin.
Note 21. Except for the XTI pin and pull-down pins.
Note 22. Pull-down pins (typ. 150kΩ) are the TESTI1 and TESTI2 pins.
POWER CONSUMPTION
(Ta=25°C, AVDD=DVDD=3.0~3.6V(typ=3.3V, max=3.6V), DVDD18=1.7~1.9V(typ=1.8V, max=1.9V))
Parameter
min
typ
max
Unit
Power Supply Current (Note 23)
1) a) AVDD
52
70
mA
b) DVDD
8
15
mA
c) DVDD18
140
210
mA
Note 23. The current of DVDD18 changes depending on the system frequency and contents of the DSP program.
MS1337-E-00
2011/11
- 15-
[AK7782]
DIGITAL FILTER CHARACTERISTICS
1) ADC1, ADC2
(Ta=-40°C~85°C; AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; fs=48kHz (Note 24))
Parameter
Symbol
min
typ
max
Unit
Passband (±0.005dB) (Note 25)
PB
0
21.5
kHz
(-0.02dB)
21.768
kHz
(-6.0dB)
23.99
kHz
Stopband
SB
26.54
kHz
Passband Ripple
(Note 25)
PR
±0.005
dB
Stopband Attenuation
(Note 26, Note 27)
SA
80
dB
Group Delay Distortion
0
ΔGD
μs
Group Delay
(Ts=1/fs)
GD
29
Ts
Digital Delay Filter + Analog Filter
Amplitude Characteristics 20Hz~20.0kHz
±0.01
dB
Note 24. Frequency of each amplitude characteristic is in proportion to fs (sampling rate). The characteristic of the high
pass filter is not included.
Note 25. The passband is from DC to 21.5kHz when fs=48kHz.
Note 26. The stopband is from 26.5kHz to 3.0455MHz when fs = 48kHz.
Note 27. When fs = 48 kHz, the analog modulator samples the analog input at 3.072MHz. There is no attenuation of an
input signal in band of integer times (n x 3.072MHz ± 21.99kHz; n=0, 1, 2, 3…) of the sampling frequency by
the digital filter.
2) ADCM
(Ta=-40°C ~85°C; AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V fs=48kHz; (Note 24))
Parameter
Symbol
min
typ
max
Unit
Passband (±0.005dB) (Note 25)
PB
0
21.5
kHz
(-0.02dB)
21.768
kHz
(-6.0dB)
23.99
kHz
Stopband
SB
26.54
kHz
Passband Ripple
(Note 25)
PR
±0.005
dB
Stopband Attenuation
(Note 26, Note 27)
SA
80
dB
Group Delay Distortion
0
ΔGD
μs
Group Delay (Ts=1/fs) (Note 28)
GD
29
Ts
Digital Delay Filter + Analog Filter
Amplitude Characteristics 20Hz~20.0kHz
±0.1
dB
Note 24. Frequency of each amplitude characteristic is in proportion to fs (sampling rate). The characteristic of the high
pass filter is not included.
Note 25. The passband is from DC to 21.5kHz when fs=48kHz.
Note 26. The stopband is from 26.5kHz to 3.0455MHz when fs = 48kHz.
Note 27. When fs = 48 kHz, the analog modulator samples the analog input at 3.072MHz. There is no attenuation of an
input signal in band of integer times (n x 3.072MHz ± 21.99kHz; n=0, 1, 2, 3…) of the sampling frequency by the digital
filter.
Note 28. 1Ts additional delay occurs in VOL + MUX path.
MS1337-E-00
2011/11
- 16-
[AK7782]
3) SRC (Common for SRC1 and SRC2)
(Ta=-40°C ~85°C; AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
min
typ
max
Passband -0.01dB
0.980≤FSO/FSI≤6.000
PB
0
0.4583FSI
0.900≤FSO/FSI<0.990
PB
0
0.4167FSI
0.533≤FSO/FSI<0.909
PB
0
0.2182FSI
0.490≤FSO/FSI<0.539
PB
0
0.2177FSI
0.450≤FSO/FSI<0.495
PB
0
0.1948FSI
0.225≤FSO/FSI<0.455
PB
0
0.0917FSI
0.167≤FSO/FSI<0.227
PB
0
0.0917FSI
Stopband
0.980≤FSO/FSI≤6.000
SB
0.5417FSI
0.900≤FSO/FSI<0.990
SB
0.5021FSI
0.533≤FSO/FSI<0.909
SB
0.2974FSI
0.490≤FSO/FSI<0.539
SB
0.2812FSI
0.450≤FSO/FSI<0.495
SB
0.2604FSI
0.225≤FSO/FSI<0.455
SB
0.1573FSI
0.167≤FSO/FSI<0.227
SB
0.1354FSI
Passband Ripple
0.225≤FSO/FSI≤6.000
PR
±0.01
0.167≤FSO/FSI<0.227
PR
±0.0612
Stopband Attenuation
0.450≤FSO/FSI≤6.000
SA
95.2
0.167≤FSO/FSI<0.455
SA
92.3
Group Delay (Ts=1/fs) (Note 29)
GD
56
Note 29. SRC delay time is calculated from the rising edge of SRCLRCK just after data input to the rising edge of
LRCLKO just after data output, when there is no phase difference between SRCLRCK and LRCLKO.
MS1337-E-00
Unit
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
dB
Ts
2011/11
- 17-
[AK7782]
SWITCHING CHARACTERISTICS
[#h indicates hexadecimal numbers. (#=0, 1, 2 ~ 9, A, B, C, D, E, F)]
1) System Clock
(Ta=-40°C~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
min
XTI
CKM[2:0] 0h, 1h, 2h, 3h
a) with a Crystal Oscillator
CKM[2:0]=0h, 2h
fXTI
CKM[2:0]=1h, 3h
fXTI
b) with an External Clock
Duty Cycle
CKM[2:0]=0h, 2h
CKM[2:0]=1h, 3h
LRCLKI Frequency
(Note 30)
fXTI
fXTI
fs
40
11.0
16.5
7.35
typ
11.2896
12.288
16.9344
18.432
50
48
BITCLKI Frequency
High Level Width
tBCLKH
64
Low Level Width
tBCLKL
64
fBCLK
64
a) CKM[2:0]=2h, 3h
Duty Cycle
40
50
CKM[2:0]=2h, 3h
0.23
b) CKM[2:0]=4h, 5h
(Note 31)
64
fBCLK
Duty Cycle
40
50
CKM[2:0]=4h
fBCLK
2.75
CKM[2:0]=5h
fBCLK
5.5
Note 30. LRCLK frequency and sampling rate (fs) should be the same.
Note 31. BITCLKI is a source of master clock. It should be 64 times fs correctly.
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
min
SRCLRCK Frequency
(Note 30) fs
7.35
SRCBICK Frequency
High Level Width
Low Level Width
(Note 32)
Duty Cycle
64
64
32
40
0.23
Note 30. LRCLK frequency and sampling rate (fs) should be the same.
Note 32. The maximum value 128fs is achieved when fs ≤ 48kHz.
typ
48
tBCLKH
tBCLKL
fBCLK
MS1337-E-00
max
50
Unit
MHz
MHz
60
12.4
18.6
96
%
MHz
MHz
kHz
60
3.1
6.2
ns
ns
fs
%
MHz
fs
%
MHz
MHz
max
96
Unit
kHz
128
60
6.2
ns
ns
fs
%
MHz
60
6.2
2011/11
- 18-
[AK7782]
2) Reset
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V)
Parameter
Symbol
min
INITRSTN
(Note 33) tRST
600
PCKRSTN
tRST
600
PADRSTN
tRST
600
PDSPRSTN
tRST
600
PSRCRSTN
tRST
600
Note 33. The INITRSTN pin must be “L” when power-up the AK7782.
typ
max
Unit
ns
ns
ns
ns
ns
3) Audio Interface
3-1) SDIN1~ SDIN7, SDOUT1~ SDOUT7 and SDOUTA1 (supports up to fs=96kHz)
MSB, LSB justified and I2S Compatible Format
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V, CL=20pF)
Parameter
Symbol
Slave Mode CKM[2:0]=2h, 3h, 4h, 5h
Delay Time from BITCLKI “↑” to LRCLKI
(Note 34) tBLRD
Delay Time from LRCLKI to BITCLKI “↑”
(Note 34) tLRBD
Delay Time from LRCLKI/O to Serial Data Output
tLRD
Delay Time from BITCLKI/O to Serial Data Output
tBSOD
Serial Data Input Latch Setup Time
tBSIDS
Serial Data Input Latch Hold Time
tBSIDH
Master Mode CKM[2:0]=0h, 1h
BITCLKO Frequency
fBCLK
BITCLKO Duty Cycle
Delay Time from BITCLKI “↓” to LRCLKO
tMBL
Delay Time from LRCLKO to Serial Data Output
tLRD
Delay Time from BITCLKO to Serial Data Output
tBSOD
Serial Data Input Latch Setup Time
tBSIDS
Serial Data Input Latch Hold Time
tBSIDH
Note 34. BITCLKI edge must not occur at the same time as LRCLKI edge.
min
typ
max
Unit
40
40
ns
ns
ns
ns
ns
ns
20
20
40
40
64
50
-20
40
40
40
40
40
fs
%
ns
ns
ns
ns
ns
3-2) SDIN1 and SDIN5 (SRC1I and SRC2I Inputs) (supports up to fs=96kHz)
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
min
Slave Mode
Delay Time from SRCBICK1 “↑” to SRCLRCK1 (Note 35) tBLRD
20
Delay Time from SRCLRCK1 to SRCBICK1 “↑” (Note 35) tLRBD
20
Serial Data Input Latch Setup Time
tBSIDS
40
Serial Data Input Latch Hold Time
tBSIDH
40
Note 35. SRCBICK1 edge must not occur at the same time as SRCLRCK1 edge.
MS1337-E-00
typ
max
Unit
ns
ns
ns
ns
2011/11
- 19-
[AK7782]
4) Microprocessor Interface
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V, CL=20pF)
Parameter
Symbol
min
Microprocessor Interface Signal
SCLK Frequency
fSCLK
SCLK Low Level Width
tSCLKL
200
SCLK High Level Width
tSCLKH
200
Microprocessor → AK7782
Time from PDSPRSTN, PADRSTN“↓” to RQN“↓”
tREW
500
Time from RQN“↑” to PDSPRSTN, PADRSTN“↑”
tWRE
500
RQN High Level Width
tWRQH
500
Time from RQN“↓” to SCLK“↓”
tWSC
500
Time from SCLK“↑” to RQN“↑”
tSCW
800
SI Latch Setup Time
tSIS
200
SI Latch Hold Time
tSIH
200
AK7782 ← Microprocessor
Delay Time from SCLK “↓” to SO Output
tSOS
Delay Time from SCLK “↑” to SO Output
tSOH
200
Time from RQN “↓” to SO Hi-Z Release
tRQHR
(Iout=±360μA)
Time from RQN “↑” to SO Hi-Z set (Iout=±360μA)
tRQHS
MS1337-E-00
typ
max
Unit
2.1
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
ns
ns
600
ns
600
ns
2011/11
- 20-
[AK7782]
5) I2C-BUS Interface
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
I2C Timing
SCL clock frequency
fSCL
Bus Free Time Between Transmissions
tBUF
Start Condition Hold Time (prior to first Clock pulse)
tHD:STA
Clock Low Time
tLOW
Clock High Time
tHIGH
Setup Time for Repeated Start Condition
tSU:STA
min
max
tHD:DAT
0
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
tSU:DAT
tR
0.1
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed
By Input Filter
Capacitive load on bus
tSU:STO
tSP
0.6
0
Unit
400
kHz
μs
μs
μs
μs
μs
0.9
μs
0.3
μs
μs
0.3
μs
50
μs
ns
400
pF
1.3
0.6
1.3
0.6
0.6
SDA Hold Time from SCL Falling
Cb
typ
2
Note 36. I C-bus is a trademark of NXP B.V.
MS1337-E-00
2011/11
- 21-
[AK7782]
■ Timing Diagram
1) System Clock
1/fXTI
1/fXTI
tXTI=1/fXTI
VIH
XTI
VIL
1/fs
ts=1/fs
1/fs
VIH
LRCLKI
SRCLRCK
VIL
1/fBCLK
1/fBCLK
tBCLK=1/fBCLK
VIH
BITCLKI
SRCBICK
VIL
tBCLKH
tBCLKL
Figure 3. System Clock
2) Reset
INITRSTN
PCKRSTN
tRST
PADRSTN
VIL
PDSPRSTN
PSRCRSTN
Figure 4. Reset
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[AK7782]
3) Audio Interface
LRCLKI
50%DVDD
LRCLKO
tBLRD
tMB tMBL
tLRBD
BITCLKI
50%DVDD
BITCLKO
tLRD
tBSOD
SDOUT *
50%DVDD
tBSIDS
tBSIDH
SDIN *
50%DVDD
SDIN * =SDIN1, SDIN2, SDIN3, SDIN4, SDIN5, SDIN6, SDIN7
SDOUT * =SDOUT1, SDOUT2, SDOUT3, SDOUT4, SDOUT5, SDOUT6, SDOUT7, SDOUTA1
Figure 5. Standard / I2C Compatible Format
SRCLRCK
SRCLRCK2
50%DVDD
tBLRD
tLRBD
50%DVDD
SRCBICK
SRCBICK2
tBSIDS
SRCI=
SDIN1,SDIN5
tBSIDH
50%DVDD
Figure 6. SRC
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[AK7782]
4) Microprocessor Interface
VIH
VIL
RQN
VIH
VIL
SCLK
tSCLKL
tSCLKH
1/fSCLK
1/fSCLK
Figure 7. Microprocessor Interface Signal
tWRE
tREW
PDSPRSTN
VIL
PADRSTN
VIH
VIL
tWRQH
RQN
tWSC
VIH
SI
VIL
tSIS
tSIH
VIH
VIL
SCLK
tSCW
tWSC
tSCW
Figure 8. Microprocessor → AK7782
VIH
VIL
SCLK
VIH
SO
VIL
tSOS
tSOH
Figure 9. AK7782 → Microprocessor
Note 37. The timing diagram during RUN state is identical except PDSPRSTN and PASRSTN are “H”.
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- 24-
[AK7782]
VIH
VIL
RQN
tRQHS
tRQHR
Hi-Z
SO
Figure 10. SO Output Timing
5) I2C-bus Interface
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
Figure 11. I2C-bus Interface
MS1337-E-00
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- 25-
[AK7782]
OPERATION OVERVIEW
■ Pin Settings
1. CKM[2:0] Clock Mode Select Pin
Master/Slave mode switching, MCLK/ICLK (internal master clock/generating clock) clock source pin select, and
ICLK frequency change are controlled by CKM [2:0] clock mode select pins. CKM[2:0] pins can only be set during
initial reset or clock reset.
CKM
CKM Master
MCLK
Input frequency for MCLK Input pin(s) required for
Use of crystal
Mode
[2:0] Slave
source
generating clock (ICLK)
system clock
oscillator
0
000 Master
XTI
12.288MHz (Note 38)
XTI
Available
1
001 Master
XTI
18.432MHz (Note 38)
XTI
Available
2
010 Slave
XTI
12.288MHz (Note 38)
XTI, BITCLKI, LRCLKI
Available
3
011 Slave
XTI
18.432MHz (Note 38)
XTI, BITCLKI, LRCLKI
Available
4
100 Slave
BITCLKI
64fs(fs=48,44.1kHz)
BITCLKI, LRCLKI
5
101 Slave
BITCLKI
64fs(fs=96,88.2kHz)
BITCLKI, LRCLKI
6
110 TEST
N/A
N/A
N/A
7
111 TEST
N/A
N/A
N/A
Note 38. On operating fs=44.1kHz series, multiply 44.1/48. (11.2896MHz in Mode 0 or 2, 16.9344MHZ in Mode 1 or 3)
Note 39. CKM modes 6 and 7 are for testing purpose only. These modes cannot be used.
Note 40. Sampling Frequency (fs) for CKM Mode 0~3 are set by control register CONT00.
Note 41. In CKM Mode is 2 or 3, XTI and LRCLKI must be synchronized, but the phase between these clocks is not
important.
Note 42. fs is fixed in CKM Modes 4 and 5. Control register settings are ignored.
Note 43. In CKM mode 4 or 5, 64-times clock of LRCLKI frequency must be input to BITCLKI. BITCLKI and LRCLKI
must be synchronized.
[Description rule]
Regarding the input / output levels in this datasheet, the low level is represented as “L” and the high level is
represented as “H”. The registers or bus pins (such as CKM[2:0] is represented “0” and “1”.
##h indicates hexadecimal numbers. (# = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F)
MS1337-E-00
2011/11
- 26-
[AK7782]
CKM Mode 0/1/2/3
ICLK
XTI pin
Divider
REFCLK
MCLK
PLL
(MCLK source)
ICLK
BITCLKI pin
CKM Mode 4/5
Divider
REFCLK
MCLK
PLL
(MCLK source)
MCLK 122.88MHz or 112.896MHz
Figure 12. Relationship between MCLK Generating Clock (ICLK) MCLK
1-1. Master Mode (CKM Mode 0/1)
CKM
Mode
0
1
CKM
[2:0]
000
001
XTI
fs: 48kHz
12.288MHz
18.432MHz
fs: 44.1kHz
11.2896MHz
16.9344MHz
fs: sampling frequency
Input frequency range Use of crystal
(MHz)
oscillator
11.0~12.4
Available
16.7~18.6
Available
Input system clock to the XTI pin. The internal counter which is synchronized to XTI generates LRCLKO (1fs) and
BITCLKO (64fs). LRCLKO and BITCLKO are not output during initial reset state (INITRSTN pin= “L”) and system
reset state. When the LRCLKI and BITCLKI pins are not used, input “L” level (VSS3) to these pins. The system clock
for the AK7782 can be supplied to the XTI pin by following methods.
In CKM mode 0~3, connect a crystal oscillator between XTI and XTO pins, or supply appropriate system clock to the
XTI pin.
XTI
XTI
External Clock
XTO
XTO
AK7782
Use of Crystal Oscillator: CKM Mode 0-3
AK7782
Use of External Clock: CKM Mode 0-3
* Sampling rate for CKM Mode 0~3 are set by control register CONT00.
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[AK7782]
1-2. Slave Mode (using XTI) (CKM Mode 2/3)
CKM
Mode
2
3
CKM
[2:0]
010
011
XTI
fs: 48kHz
12.288MHz
18.432MHz
fs: 44.1kHz
11.2896MHz
16.9344MHz
fs: sampling frequency
Input frequency range
Use of crystal
(MHz)
oscillator
11.0~12.4
Available
16.7~18.6
Available
Required system clocks are XTI, LRCLKI and BITCLKI. XTI and LRCLKI must be synchronized, but the phase
between these clocks is no important.
LRCLKI and BITCLKI are directly output to the LRCLKO and BITCLKO pins, respectively.
DVD etc.
(Master device)
XTI
LRCLKI
BITCLKI
Clk Gen.
CKM2, 3
LRCLKO
BITCLKO
DAC etc.
(Slave device)
AK7782
CLKO
MS1337-E-00
2011/11
- 28-
[AK7782]
1-3. Slave Mode (BITCLKI Input) (CKM Mode 4/5)
In CKM mode 4 or 5, BITCLKI is the master clock source instead of XTI. The master clock (MCLK) is generated from
the clock input to BITCLKI by an internal PLL. This clock is multiplied by the internal PLL, therefore 64-times clock
(64fs) of LRCLKI frequency must be input to the BITCLKI pin. BITCLKI must be synchronized with LRCLKI.
CKM
Mode
4
5
CKM
[2:0]
100
101
BITCLKI
BITCLKI
64fs(fs=48,44.1kHz)
64fs(fs=96,88.2kHz)
fs: 48kHz
3.072MHz
6.144MHz
fs: sampling frequency
Input frequency
fs: 44.1kHz
range
2.8224MHz
2.75~3.1MHz
5.6448MHz
5.5~6.2MHz
XTI
0
1
Divider
PLL
XTO
BITCLKI
External
Clock
MCLK
CKM[2:0]
“1”: when
CKM[2:0]=4h or 5h
BITCLK
AK7782
Figure 13. Internal Connection Block Diagram
• The sampling rate is determined by the CKM [2:0] pin settings. Control Register DFS mode settings (CONT00) are
ignored.
• In system applications where the AK7782 is used in CKM Modes 4, or 5 only (when XTI is not used), set the XTI
pin = “L” (VSS3)
1-4. CKM[2:0] Pin Setting
Changing the CKM [2:0] pin setting after power-on must be made during Initial Reset (INITRSTN pin= “L”) or during
Clock Reset (INITRSTN pin= “L” → “H”, PCKRSTN pin = “L”, RCKRSTN bit = “0”).
MS1337-E-00
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[AK7782]
1-5. CKM[2:0] Pin Setting and Input-Output Interface
Slave/
Master
M
M
M
M
M
M
M
M
S
S
S
S
S
S
S
S
S
S
CKM
Mode
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2,3
4
5
CKM
[2:0]
00X
00X
00X
00X
00X
00X
00X
00X
01X
01X
01X
01X
01X
01X
01X
01X
100
101
DFS
Mode
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
-
DFS
[2:0]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
-
fs(kHz)
Normal 48, 44.1
Double 96, 88.2
N/A
32, 29.4
12, 11.025
24, 22.05
16, 14.7
8, 7.35
Normal 48,44.1
Double 96,88.2
N/A
32, 29.4
12, 11.025
24, 22.05
16, 14.7
8, 7.35
Normal 48,44.1
Double 96,88.2
BITCLK
MSB, LSB justified
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
I2S Compatible
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
(X: Don’t care)
Note 44. DFS mode is set by CONT00 DFS[2:0] (D7, D6, D5) bits.
MS1337-E-00
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- 30-
[AK7782]
■ Control Register Setting
The AK7782 Control Register is set through a microprocessor interface. All registers are initialized by initial reset
(INITRSTN pin = “L”). When power-up the AK7782, initial reset must always be made to determine register settings.
W
R
C0h
40h
Name
CONT00
C1h
41h
CONT01
C2h
42h
CONT02
C3h
43h
CONT03
C4h
44h
CONT04
C5h
45h
CONT05
C6h
46h
CONT06
C7h
47h
CONT07
C8h
48h
CONT08
C9h
CAh
49h
4Ah
CONT09
CONT0A
CBh
4Bh
CONT0B
CCh
4Ch
CONT0C
CDh
4Dh
CONT0D
CEh
4Eh
CONT0E
CFh
4Fh
CONT0F
D0h
D1h
50h
51h
CONT10
CONT11
D2h
52h
CONT12
D3h
53h
CONT13
D4h
54h
CONT14
D5h
55h
CONT15
D6h
56h
CONT16
D7
D6
D5
D4
D3
D2
D1
CLK1S[0]
RCK
RSTN
00h
Reserved
Reserved
00h
Reserved
Reserved
00h
P1
WAVP[0]
P1
IN1SEL[1]
P2
IN1SEL[1]
OUT4
SEL[1]
P1
EFEN
P1
IN1SEL[0]
P2
IN1SEL[0]
OUT4
SEL[0]
MSEL[1]
MSEL[0]
00h
CLKO1EN
00h
OUT1EN
BICKOEN
00h
00h
TEST
00h
TEST
00h
TEST
00h
TEST
00h
TEST
00h
TEST
MUX[0]
00h
00h
Reserved
Reserved
00h
SRC1
SEMIAUTO
SRC2
SEMIAUTO
PSADCM
SRC1
AUTOSEL
SRC2
AUTOSEL
Reserved
Reserved
Reserved
DFS[2]
DFS[1]
DFS[0]
DIFI2S
CLK1S[2]
CLK1S[1]
P1
DATARAM
P2
DATARAM
P2
WAVM
P1
IN7SEL[1]
P2
IN7SEL[1]
OUT7
SEL[1]
OUT3
SEL[1]
OUTA
SEL2[1]
OUTAEN
P2JX2E
P2
WDTEN
P1
DIF7
P2
DIF7
P1
DOF7
P2
DOF7
VOL[5]
ASEL2[2]
SRC2
ISEL[1]
SRC1
BIEDGE
SRC2
BIEDGE
PSDSP2
RSRC2
SMUTE
P1
BANK[1]
P2
BANK[1]
P2
WAVP[1]
P1
IN7SEL[0]
P2
IN7SEL[0]
OUT7
SEL[0]
OUT3
SEL[0]
OUTA
SEL2[0]
OUT7EN
P2JX1E
P1
WDTEN
P1
DIF6
P2
DIF6
P1
DOF6
P2
DOF6
VOL[4]
ASEL2[1]
SRC2
ISEL[0]
SRC1
IDIF[2]
SRC2
IDIF[2]
PSDSP1
RSRC1
SMUTE
P1
BANK[0]
P2
BANK[0]
P2
WAVP[0]
P1
IN6SEL[1]
P2
IN6SEL[1]
OUT6
SEL[1]
OUT2
SEL[1]
OUTA
SEL1[1]
OUT6EN
P2JX0E
P1
POMODE
P2
POMODE
P2
EFEN
P1
IN6SEL[0]
P2
IN6SEL[0]
OUT6
SEL[0]
OUT2
SEL[0]
OUTA
SEL1[0]
OUT5EN
P1JX2E
SRC2
LOCKE
P1
DIFD[2]
P2
DIFD[2]
P1
DOFD[2]
P2
DOFD[2]
VOL[2]
ASEL1[2]
SRC2
CKI[0]
SRC1
IDIF[0]
SRC2
IDIF[0]
PSSRC1
RDSP
RSTN
P1
SS[1]
P2
SS[1]
P1
WAVM
P1
IN5SEL[1]
P2
IN5SEL[1]
OUT5
SEL[1]
OUT1
SEL[1]
P2
IN4SEL
OUT4EN
P1JX1E
SRC1
LOCKE
P1
DIFD[1]
P2
DIFD[1]
P1
DOFD[1]
P2
DOFD[1]
VOL[1]
ASEL1[1]
SRC2
CKO[1]
SRC1
BIFS[1]
SRC2
BIFS[1]
PSADC2
RAD
RSTN
P1
SS[0]
P2
SS[0]
P1
WAVP[1]
P1
IN5SEL[0]
P2
IN5SEL[0]
OUT5
SEL[0]
OUT1
SEL[0]
P2
IN3SEL
OUT3EN
P1JX0E
P2
IN2SEL
OUT2EN
LRCKOEN
TEST
TEST
P1
DIFD[0]
P2
DIFD[0]
P1
DOFD[0]
P2
DOFD[0]
VOL[0]
ASEL1[0]
SRC2
CKO[0]
SRC1
BIFS[0]
SRC2
BIFS[0]
PSADC1
P1
DIF1
P2
DIF1
P1
DOF1
P2
DOF1
TEST
MUX[1]
Reserved
CRCE
P1
DIF5
P2
DIF5
P1
DOF5
P2
DOF5
VOL[3]
ASEL2[0]
SRC2
CKI[1]
SRC1
IDIF[1]
SRC2
IDIF[1]
PSSRC2
RSRC
RSTN
Default
D0
Note 45. Command codes and register settings other than those specified above should not be executed.
Note 46. Writing to CONT00 may only be executed during System Reset.
Note 47. “0” must be written into Test bits.
MS1337-E-00
2011/11
- 31-
00h
00h
00h
00h
00h
00h
00h
00h
[AK7782]
1) CONT00: Sampling Rate and Input Interface Select
Write during system reset.
W
R
Name
D7
C0h 40h CONT00
DFS[2]
D6
DFS[1]
D5
DFS[0]
D4
DIFI2S
D3
CLK1S
[2]
D2
CLK1S
[1]
D1
CLK1S
[0]
D0
RCK
RSTN
Default
00h
D7, D6, D5: DFS[2:0] Sampling Rate Setting
fs: sampling frequency
DFS
DFS
CKM
fs(kHz)
fs(kHz)
DSP maximum ADC
Mode
[2:0]
Mode
48kHz family 44.1kHz family STEP
Operation
0
000
0-3
48
44.1
2560
○
(default)
1
001
0-3
96
88.2
1280
○
2
010
0-3
N/A
N/A
3
011
0-3
32
29.4
3840
○
4
100
0-3
12
11.025
10240
○
5
101
0-3
24
22.05
5120
○
6
110
0-3
16
14.7
7680
○
7
111
0-3
8
7.35
15360
○
4
48
44.1
2560
○
5
96
88.2
1280
○
Note 48. DFS mode is available in CKM mode 0~3.
Note 49. Sampling frequencies shown in DFS mode 0~7 can only be selected.
Note 50. DFS mode2 is not available.
D4: DIFI2S Audio Interface Select
0: MSB, LSB justified (default)
1: I2S Compatible
When I2S Compatible mode is selected, all audio interface input and output pins should be set to I2S compatible
mode. The AK7782 audio interface setting should be MSB-justified.
D3, D2, D1: CLK1S[2:0] CLKO1 Output Clock Select
The CLKO1 output is stopped during initial reset and clock reset. During system reset, the CLKO1 output is not
stopped, so that a click noise occurs by changing CLK1S mode.
CLK1S Mode
CLK1S[2:0]
fs=48kHz family
fs=44.1kHz family
0
000
12.288MHz
11.2896MHz
(default)
1
001
6.144MHz
5.6448MHz
2
010
3.072MHz
2.8224MHz
3
011
8.192MHz
7.5264MHz
4
100
4.092MHz
3.7632MHz
5
101
2.048MHz
1.8816MHz
6
110
24.576MHz
22.5792MHz
7
111
XTI
XTI
XTI signal is output in CLK1S mode 7.
D0: RCKRSTN Clock Reset N Register
0: Clock Reset (default)
1: Clock Reset Release
Set the PCKRSTN pin to “L” (VSS3) when changing RCKRSTN bit.
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[AK7782]
2) CONT01: DSP1 RAM Control
Write during system reset or DSP reset.
W
R
Name
D7
D6
P1
P1
C1h 41h CONT01
DATARAM BANK[1]
D5
P1
BANK[0]
D7: P1DATARAM DSP1 DATARAM Addressing Select
DSP1 DATARAM
A(000h-3FFh)
1024word
Mode
0
Ring Addressing
1
Ring Addressing
Pointer
DP0
D6, D5: P1BANK[1:0] DSP1 DLRAM Mode Setting
DSP1 DLRAM Mode P1BANK[1:0] Ring 28bit
0
00
6144word
1
01
4096word
2
10
3072word
3
11
3072word
D4
P1
POMODE
B(400h-7FFh)
1024word
Ring Addressing
Linear Addressing
DP1
Ring 14bit
D3
D2
P1
P1
SS[1] SS[0]
D1
D0
Default
0
0
00h
(default)
Linear 28bit
(default)
4096word
6144word
3072word
D4: P1POMODE DSP1 DLRAM Pointer 0 Select
0: OFRAM
(default)
1: DBUS direct
D3, D2: P1SS[1:0] DSP1 DLRAM Sampling Setting
DSP1 SS Mode
P1SS[1:0] Sampling Setting
0
00
Address is updated at every sampling
(default)
1
01
Address is updated at every 2 samplings
2
10
Address is updated at every 4 samplings
3
11
Address is updated at every 8 samplings
Note 51. When mode 1/2/3 is selected, aliasing noise may be generated.
Note 52. Ring 14bit is supported in DSP1 DLRAM mode 1 and 2. (Ring 28bit is supported in DSP1 DLRAM mode 0
and 3)
D1: Reserved
0: Normal Operation (default)
Write “0” into this bit.
D0: Reserved
0: Normal Operation (default)
Write “0” into this bit.
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[AK7782]
3) CONT02: DSP2 RAM Control
Write during system reset or DSP reset.
W
R
Name
D7
D6
D5
D4
D3
P2
P2
P2
P2
P2
C2h
42h CONT02
DATARAM BANK[1] BANK[0] POMODE SS[1]
D7: P2DATARAM DSP2 DATARAM Addressing Select
DSP2 DATARAM Mode
A(000h-3FFh)
1024word
0
Ring Addressing
1
Ring Addressing
Pointer
DP0
D6, D5: P2BANK[1:0] DSP2 DLRAM Mode Setting
DSP2 DLRAM Mode P2BANK[1:0] Ring 28bit
0
00
6144word
1
01
4096word
2
10
3072word
3
11
3072word
D2
P2
SS[0]
B(400h-7FFh)
1024word
Ring Addressing
Linear Addressing
DP1
Ring 14bit
D1
D0
Default
0
0
00h
(default)
Linear 28bit
(default)
4096word
6144word
3072word
D4: P2POMODE DSP2 DLRAM Pointer 0 Select
0: OFRAM
(default)
1: DBUS direct
D3, D2: P2SS[1:0] DSP2 DLRAM Sampling Setting
DSP2 SS Mode
P2SS[1:0]
Sampling Setting
0
00
Address is updated at every sampling
(default)
1
01
Address is updated at every 2 samplings
2
10
Address is updated at every 4 samplings
3
11
Address is updated at every 8 samplings
Note 53. When mode 1/2/3 is selected, aliasing noise may be generated.
Note 54. Ring 14bit is supported in DSP2 DLRAM mode 1 and 2. (Ring 28bit is supported in DSP2 DLRAM mode 0
and 3)
D1: Reserved
0: Normal Operation (default)
Write “0” into this bit.
D0: Reserved
0: Normal Operation (default)
Write “0” into this bit.
MS1337-E-00
2011/11
- 34-
[AK7782]
4) CONT03 DSP2 & DSP1 RAM Control
Write during system reset or DSP reset.
W
C3h
R
Name
43h
CONT03
D7
P2
WAVM
D6
P2
WAVP[1]
D5
P2
WAVP[0]
D4
P2
EFEN
D3
P1
WAVM
D2
P1
WAVP[1]
D1
P1
WAVP[0]
D0
P1
EFEN
Default
00h
D7: P2WAVM DSP2 CRAM WAV Mode Select
0: 1/4 Mode (default)
1: 1/2 Mode
1/4 mode has an advantage of CRAM memory size but calculation precision drops down.
D6, D5: P2WAVP[1:0] DSP2 CRAM Memory Assignment
DSP2 WAVP Mode P2WAVP[1:0] P2WAVM bit = “0”
0
00
33word
1
01
65word
2
10
129word
3
11
257word
P2WAVM bit = “1”
65word
129word
257word
513word
Number of FFT Point
128
256
512
1024
(default)
D4: P2EFEN DSP2 Instruction EF, SJ and IN Enable
0: EF, SJ, IN Disable (default)
1: EF, SJ, IN Enable
D3: P1WAVM DSP1 CRAM WAV Mode Select
0: 1/4 Mode (default)
1: 1/2 Mode
1/4 mode has an advantage of CRAM memory size but calculation precision drops down.
D2, D1: P1WAVP[1:0] DSP1 CRAM Memory Assignment
DSP1 WAVP Mode P1WAVP[1:0] P1WAVM bit = “0”
0
00
33word
1
01
65word
2
10
129word
3
11
257word
P1WAVM bit = “1”
65word
129word
257word
513word
Number of FFT Point
128
256
512
1024
(default)
D0: P1EFEN DSP1 Instruction EF, SJ and IN Enable
0: EF, SJ, IN Disable (default)
1: EF, SJ, IN Enable
MS1337-E-00
2011/11
- 35-
[AK7782]
5) CONT04 DSP1 Input Select
Write during system reset or DSP reset.
W
R
Name
D7
D6
P1IN7
P1IN7
C4h
44h CONT04
SEL[1] SEL[0]
D5
P1IN6
SEL[1]
D4
P1IN6
SEL[0]
D7, D6: P1IN7SEL[1:0] DSP1 SDIN7 Input Select
DSP1 IN7SEL Mode
P1IN7SEL[1:0]
DSP1 SDIN7
0
00
ADC2
1
01
SDIN7/JX2 pin
2
10
SRC1O
3
11
ADCM
D5, D4: P1IN6SEL[1:0] DSP1 SDIN6 Input Select
DSP1 IN6SEL Mode
P1IN6SEL[1:0]
DSP1 SDIN6
0
00
ADC1
1
01
SDIN6/JX1 pin
2
10
ADCM
3
11
SRC1O
D3, D2: P1IN5SEL[1:0] DSP1 SDIN5 Input Select
DSP1 IN5SEL Mode
P1IN5SEL[1:0]
DSP1 SDIN5
0
00
SDIN5 pin
1
01
SRC2O
2
10
ADC1
3
11
ADCM
D1, D0: P1IN1SEL[1:0] DSP1 SDIN1 Input Select
DSP1 IN1SEL Mode
P1IN1SEL[1:0]
DSP1 SDIN1
0
00
SDIN1 pin
1
01
SRC1O
2
10
SRC2O
3
11
ADC2
MS1337-E-00
D3
P1IN5
SEL[1]
D2
P1IN5
SEL[0]
D1
P1IN1
SEL[1]
D0
P1IN1
SEL[0]
Default
00h
(default)
(default)
(default)
(default)
2011/11
- 36-
[AK7782]
6) CONT05 DSP2 Input Select
Write during system reset or DSP reset.
W
R
Name
D7
D6
P2IN7 P2IN7
C5h
45h CONT05
SEL[1] SEL[0]
D5
P2IN6
SEL[1]
D7, D6: P2IN7SEL[1:0] DSP2 SDIN7 Input Select
DSP2 IN7SEL Mode P2IN7SEL[1:0] DSP2 SDIN7
0
00
ADC2
1
01
SDIN7/JX2 pin
2
10
SRC1O
3
11
DSP1 SDOUT7
D5, D4: P2IN6SEL[1:0] DSP2 SDIN6 Input Select
DSP2 IN6SEL Mode P2IN6SEL[1:0] DSP2 SDIN6
0
00
ADC1
1
01
SDIN6/JX1 pin
2
10
ADCM
3
11
DSP1 SDOUT6
D3, D2: P2IN5SEL[1:0] DSP2 SDIN5 Input Select
DSP2 IN5SEL Mode P2IN5SEL[1:0] DSP2 SDIN5
0
00
SDIN5 pin
1
01
SRC2O
2
10
ADC1
3
11
DSP1 SDOUT5
D1, D0: P2IN1SEL[1:0] DSP2 SDIN1 Input Select
DSP2 IN1SEL Mode P1IN2SEL[1:0] DSP2 SDIN1
0
00
SDIN1 pin
1
01
SRC1O
2
10
SRC2O
3
11
DSP1 SDOUT1
MS1337-E-00
D4
P2IN6
SEL[0]
D3
P2IN5
SEL[1]
D2
P2IN5
SEL[0]
D1
P2IN1
SEL[1]
D0
P2IN1
SEL[0]
Default
00h
(default)
(default)
(default)
(default)
2011/11
- 37-
[AK7782]
7) CONT06 Output Pin Select
Write during system reset or DSP reset.
W
R
Name
D7
D6
OUT7 OUT7
C6h 46h CONT06
SEL[1] SEL[0]
D5
OUT6
SEL[1]
D4
OUT6
SEL[0]
D7, D6: OUT7SEL[1:0] SDOUT7 pin Output Select
OUT7SEL Mode
OUT7SEL[1:0]
SDOUT7 pin
0
00
DSP1 SDOUT7
1
01
DSP2 SDOUT7
2
10
ADCM
3
11
SRC2O
D5, D4: OUT6SEL[1:0] SDOUT6 pin Output Select
OUT6SEL Mode
OUT6SEL[1:0]
SDOUT6 pin
0
00
DSP1 SDOUT6
1
01
DSP2 SDOUT6
2
10
ADC1
3
11
ADC2
D3, D2: OUT5SEL[1:0] SDOUT5 pin Output Select
OUT5SEL Mode
OUT5SEL[1:0]
OUT5SEL Output
0
00
DSP1 SDOUT5
1
01
DSP2 SDOUT5
2
10
DSP1 IRPT
3
11
DSP2 IRPT
D1, D0: OUT4SEL[1:0] SDOUT4 pin Output Select
OUT4SEL Mode
OUT4SEL[1:0]
OUT4SEL Output
0
00
DSP1 SDOUT4
1
01
DSP2 SDOUT4
2
10
DSP1 GPO1
3
11
DSP2 GPO1
MS1337-E-00
D3
OUT5
SEL[1]
D2
OUT5
SEL[0]
D1
OUT4
SEL [1]
D0
OUT4
SEL[0]
Default
00h
(default)
(default)
(default)
(default)
2011/11
- 38-
[AK7782]
8) CONT07 Output Pin Select
Write during system reset or DSP reset.
W
R
Name
D7
D6
OUT3 OUT3
C7h 47h CONT07
SEL[1] SEL[0]
D5
OUT2
SEL[1]
D4
OUT2
SEL[0]
D7, D6: OUT3SEL[1:0] SDOUT3 pin Output Select
OUT3SEL Mode
OUT3SEL[1:0]
SDOUT3 pin
0
00
DSP1 SDOUT3
1
01
DSP2 SDOUT3
2
10
DSP1 GPO0
3
11
DSP2 GPO0
D5, D4: OUT2SEL[1:0] SDOUT2 pin Output Select
OUT2SEL Mode
OUT2SEL[1:0]
SDOUT2 pin
0
00
DSP1 SDOUT2
1
01
DSP2 SDOUT2
2
10
MUXOUT
3
11
SRC2O
D3, D2: OUT1SEL[1:0] SDOUT1 pin Output Select
OUT1SEL Mode
OUT1SEL[1:0]
OUT1SEL Output
0
00
DSP1 SDOUT1
1
01
DSP2 SDOUT1
2
10
MUXOUT
3
11
SRC1O
D1, D0: MSEL[1:0] MUX Source Select
MSEL Mode
MSEL[1:0]
0
00
1
01
2
10
3
11
MSELOUT
DSP1 SDOUT1
DSP1 SDOUT5
DSP2 SDOUT1
DSP2 SDOUT5
MS1337-E-00
D3
OUT1
SEL[1]
D2
OUT1
SEL[0]
D1
MSEL
[1]
D0
Default
MSEL[0]
00h
(default)
(default)
(default)
(default)
2011/11
- 39-
[AK7782]
9) CONT08 SDOUTA Output Select, DSP2 Input Select
Write during system reset or DSP reset.
W
R
Name
D7
D6
OUTA
OUTA
C8h 48h CONT08
SEL2[1] SEL2[0]
D5
OUTA
SEL1[1]
D4
D3
D2
D1
OUTA
P2
P2
P2
SEL1[0] IN4SEL IN3SEL IN2SEL
D7, D6: OUTASEL2[1:0] SDOUTA pin Output Select 2
OUTASEL2 Mode
OUTASEL2[1:0] SDOUTA pin
0
00
OUTASEL1 Output
1
01
SRC2O
2
10
DSP1 SDOUT7
3
11
DSP1 SDOUT7
D5, D4: OUTASEL1[1:0] SDOUTA pin Output Select 1
OUTASEL1 Mode
OUTASEL1[1:0] OUTASEL1 Output
0
00
MUXOUT
1
01
ADC1
2
10
ADC2
3
11
SRC1O
D0
CLKO1
EN
Default
00h
(default)
(default)
D3: P2IN4SEL DSP2 SDIN4 Input Select
0: SDIN4 pin
(default)
1: DSP1 SDOUT4
D2: P2IN3SEL DSP2 SDIN3 Input Select
0: SDIN3 pin
(default)
1: DSP1 SDOUT3
D1: P2IN2SEL DSP2 SDIN2 Input Select
0: SDIN2 pin
(default)
1: DSP1 SDOUT2
D0: CLKO1EN
0: CLKO1 Output Enable (default)
1: CLKO1 pin= “L”
MS1337-E-00
2011/11
- 40-
[AK7782]
10) CONT09: Output Enable Setting
Write during system reset or DSP reset.
W
R
Name
D7
D6
C9h 49h CONT09 OUTAEN OUT7EN
D5
OUT6EN
D4
D3
OUT5EN OUT4EN
D2
D1
D0
OUT3EN
OUT2EN
OUT1EN
Default
00h
D7: OUTAEN
0: SDOUTA Output Enable (default)
1: SDOUTA pin= “L”
D6: OUT7EN
0: SDOUT7 Output Enable (default)
1: SDOUT7 pin= “L”
D5: OUT6EN
0: SDOUT6 Output Enable (default)
1: SDOUT6 pin= “L”
D4: OUT5EN
0: SDOUT5 Output Enable (default)
1: SDOUT5 pin= “L”
D3: OUT4EN
0: SDOUT4 Output Enable (default)
1: SDOUT4 pin= “L”
D2: OUT3EN
0: SDOUT3 Output Enable (default)
1: SDOUT3 pin= “L”
D1: OUT2EN
0: SDOUT2 Output Enable (default)
1: SDOUT2 pin= “L”
D0: OUT1EN
0: SDOUT1 Output Enable (default)
1: SDOUT1 pin= “L”
MS1337-E-00
2011/11
- 41-
[AK7782]
11) CONT0A: JX Enable Setting, LRCLKO and BITCLKO Output Enable Setting
Write during system reset or DSP reset.
W
R
Name
D7
D6
P2
P2
CAh 4Ah CONT0A
JX2E
JX1E
D7: P2JX2E DSP2 JX2 Select
0: DSP2 JX2 Setting Disable
1: DSP2 JX2 Setting Enable
(default)
D6: P2JX1E DSP2 JX1 Select
0: DSP2 JX1 Setting Disable
1: DSP2 JX1 Setting Enable
(default)
D5: P2JX0E DSP2 JX0 Select
0: DSP2 JX0 Setting Disable
1: DSP2 JX0 Setting Enable
(default)
D4: P1JX2E DSP1 JX2 Select
0: DSP1 JX2 Setting Disable
1: DSP1 JX2 Setting Enable
(default)
D3: P1JX1E DSP1 JX1 Select
0: DSP1 JX1 Setting Disable
1: DSP1 JX1 Setting Enable
(default)
D2: P1JX0E DSP1 JX0 Select
0: SP1 JX0 Setting Disable
1: DSP1 JX0 Setting Enable
(default)
D5
P2
JX0E
D4
P1
JX2E
D3
P1
JX1E
D2
D1
D0
Default
P1
LRCKOEN BICKOEN
00h
JX0E
D1: LRCKOEN
0: LRCLKO Output Enable (default)
1: LRCLKO pin= “L”
D0: BICKOEN
0: BITCLKO Output Enable (default)
1: BITCLKO pin= “L”
MS1337-E-00
2011/11
- 42-
[AK7782]
12) CONT0B: DSP Block Setting
Write during system reset or DSP reset.
W
R
Name
CBh
4Bh
CONT0B
D7
P2
WDTEN
D6
P1
WDTEN
D5
CRCE
D4
SRC2
LOCKE
D3
SRC1
LOCKE
D2
D1
D0
TEST
TEST
TEST
Default
00h
D7: P2WDTEN
0: DSP2 WDT Enable (default)
1: DSP2 WDT Disable
WDT: Watch dog timer
D6: P1WDTEN
0: DSP1 WDT Enable (default)
1: DSP1 WDT Disable
D5: CRCE
0: CRC Disable (default)
1: CRC Enable
D4: SRC2LOCKE
0: SRC2LOCK Disable
1: SRC2LOCK Enable
(default)
D3: SRC1LOCKE
0: SRC1LOCK Disable
1: SRC1LOCK Enable
(default)
D3, D2, D1: TEST
000: Normal Operation
001-111: Not Available
(default)
MS1337-E-00
2011/11
- 43-
[AK7782]
13) CONT0C: DSP1 Input Interface Select
Write during system reset or DSP reset.
W
R
Name
D7
D6
P1
P1
CCh 4Ch CONT0C
DIF7 DIF6
D5
P1
DIF5
D4
P1
DIFD[2]
D3
P1
DIFD[1]
D2
P1
DIFD[0]
D1
P1
DIF1
D0
Default
TEST
00h
D7: P1DIF7 DSP1 SDIN7 Input Format Select
P1DIF7 Mode
P1DIF7
Input Format
0
0
MSB (24bit)
(default)
1
1
MSB F24.4 floating point
Note 55. Set P1DIF7 mode to 0 when DSP1 SDIN7 is connected to ADC2, ADCM or SRC1O.
D6: P1DIF6 DSP1 SDIN6 Input Format Select
P1DIF6 Mode
P1DIF6
Input Format
0
0
MSB (24bit)
(default)
1
1
MSB F24.4 floating point
Note 56. Set P1DIF6 mode to 0 when DSP1 SDIN6 is connected to ADC1, ADCM or SRC1O.
D5: P1DIF5 DSP1 SDIN5 Input Format Select
P1DIF5 Mode
P1DIF5
Input Format
0
0
MSB (24bit)
(default)
1
1
MSB F24.4 floating point
Note 57. Set P1DIF5 mode to 0 when DSP1 SDIN5 is connected to ADC1, ADCM or SRC2O.
D4, D3, D2: P1DIFD[2:0] DSP1 SDIN4, DSP1 SDIN3, DSP1 SDIN2 Input Format Select
P1DIFD Mode
P1DIFD
Input Format
0
000
MSB (24bit)
(default)
1
001
LSB 24bit
2
010
LSB 20bit
3
011
LSB 16bit
4
100
MSB F24.4 floating point
5
101
MSB 32bit
6
110
N/A
7
111
N/A
Note 58. Set P1DIFD mode to 0 in I2S compatible mode (DIFI2S bit = “1”).
D1: P1DIF1 DSP1 SDIN1 Input Format Select
P1DIF1 Mode
P1DIF1
Input Format
0
0
MSB (24bit)
(default)
1
1
MSB F24.4 floating point
Note 59. Set P1DIF1 mode to 0 when DSP1 SDIN1 is connected to ADC2, SRC1O or SRC2O.
D0: TEST
0: Normal Operation
1: Not Available
MS1337-E-00
2011/11
- 44-
[AK7782]
14) CONT0D: DSP2 Input Interface Select
Write during system reset or DSP reset.
W
R
Name
D7
D6
P2
P2
CDh
4Dh
CONT0D
DIF7 DIF6
D5
P2
DIF5
D4
D3
D2
P2
P2
P2
DIFD[2] DIFD[1] DIFD[0]
D1
P2
DIF1
D0
TEST
Default
00h
D7: P2DIF7 DSP2 SDIN7 Input Format Select
P2DIF7 Mode
P2DIF7
Input Format
0
0
MSB (24bit)
(default)
1
1
MSB F24.4 floating point
Note 60. Set P2DIF7 mode to 0 when DSP2 SDIN7 is connected to ADC2 or SRC1O.
D6: P2DIF6 DSP2 SDIN6 Input Format Select
P2DIF6 Mode
P2DIF6
Input Format
0
0
MSB (24bit)
(default)
1
1
MSB F24.4 floating point
Note 61. Set P2DIF6 mode to 0 when DSP2 SDIN6 is connected to ADC1 or ADCM.
D5: P2DIF5 DSP2 SDIN5 Input Format Select
P2DIF5 Mode
P2DIF5
Input Format
0
0
MSB (24bit)
(default)
1
1
MSB F24.4 floating point
Note 62. Set P2DIF5 mode to 0 when DSP2 SDIN5 is connected to ADC1 or SRC2O.
D4, D3, D2: P2DIFD[2:0] DSP2 SDIN4, DSP2 SDIN3, DSP2 SDIN2 Input Format Select
P2DIFD Mode
P2DIFD
Input Format
0
000
MSB (24bit)
(default)
1
001
LSB 24bit
2
010
LSB 20bit
3
011
LSB 16bit
4
100
MSB F24.4 floating point
5
101
MSB 32bit
6
110
N/A
7
111
N/A
Note 63. Set P2DIFD mode to 0 in I2S compatible mode (DIFI2S bit = “1”).
D1: P2DIF1 DSP2 SDIN1 Input Format Select
P2DIF1 Mode
P2DIF1
Input Format
0
0
MSB (24bit)
(default)
1
1
MSB F24.4 floating point
Note 64. Set P2DIF1 mode to 0 when DSP2 SDIN1 is connected to SRC1O or SRC2O.
D0: TEST
0: Normal Operation
1: Not Available
(default)
MS1337-E-00
2011/11
- 45-
[AK7782]
15) CONT0E: DSP1 Output Interface Select
Write during system reset or DSP reset.
W
R
Name
D7
D6
P1
P1
CEh 4Eh CONT0E
DOF7 DOF6
D5
P1
DOF5
D4
P1
DOFD[2]
D3
P1
DOFD[1]
D2
P1
DOFD[0]
D1
P1
DOF1
D0
Default
TEST
00h
D7: P1DOF7 DSP1 SDOUT7 Output Format Select
P1DOF7 Mode
P1DOF7
Output Format
0
0
MSB (24bit)
(default)
1
1
MSB F24.4 floating point
D6: P1DOF6 DSP1 SDOUT6 Output Format Select
P1DOF6 Mode
P1DOF6
Output Format
0
0
MSB (24bit)
(default)
1
1
MSB F24.4 floating point
D5: P1DOF5 DSP1 SDOUT5 Output Format Select
P1DOF5 Mode
P1DOF5
Output Format
0
0
MSB (24bit)
(default)
1
1
MSB F24.4 floating point
D4, D3, D2: P1DOFD[2:0] DSP1 SDOUT4,DSP1 SDOUT3,DSP1 SDOUT2 Output Format Select
P1DOFD Mode
P1DOFD
Output Format
0
000
MSB (24bit)
(default)
1
001
LSB 24bit
2
010
LSB 20bit
3
011
LSB 16bit
4
100
MSB F24.4 floating point
5
101
MSB 32bit
6
110
N/A
7
111
N/A
Note 65. Set P1DOFD mode to 0 in I2S compatible mode (DIFI2S bit= “1”).
D1: P1DOF1 DSP1 SDOUT1 Output Format Select
P1DOF1 Mode
P1DOF1
Output Format
0
0
MSB (24bit)
(default)
1
1
MSB F24.4 floating point
D0: TEST
0: Normal Operation
1: Not Available
(default)
MS1337-E-00
2011/11
- 46-
[AK7782]
16) CONT0F: DSP2 Output Interface Select
Write during system reset or DSP reset.
W
R
Name
D7
D6
P2
P2
CFh 4Fh CONT0F
DOF7 DOF6
D5
P2
DOF5
D4
P2
DOFD[2]
D7: P2DOF7 DSP2 SDOUT7 Output Format Select
P2DOF7 Mode
P2DOF7 Output Format
0
0
MSB (24bit)
1
1
MSB F24.4 floating point
D6: P2DOF6 DSP2 SDOUT6 Output Format Select
P2DOF6 Mode
P2DOF6 Output Format
0
0
MSB (24bit)
1
1
MSB F24.4 floating point
D5: P2DOF5 DSP2 SDOUT5 Output Format Select
P2DOF5 Mode
P2DOF5 Output Format
0
0
MSB (24bit)
1
1
MSB F24.4 floating point
D3
P2
DOFD[1]
D2
P2
DOFD[0]
D1
P2
DOF1
D0
Default
TEST
00h
(default)
(default)
(default)
D4, D3, D2: P2DOFD[2:0] DSP2 SDOUT4, DSP2 SDOUT3, DSP2 SDOUT2 Output Format Select
P2DOFD Mode
P2DOFD Output Format
0
000
MSB (24bit)
(default)
1
001
LSB 24bit
2
010
LSB 20bit
3
011
LSB 16bit
4
100
MSB F24.4 floating point
5
101
MSB 32bit
6
110
N/A
7
111
N/A
Note 66. Set P2DOFD mode to 0 in I2S compatible mode (DIFI2S bit= “1”).
D1: P2DOF1 DSP2 SDOUT1 Output Format Select
P2DOF1 Mode
P2DOF1 Output Format
0
0
MSB (24bit)
1
1
MSB F24.4 floating point
D0: TEST
0: Normal Operation
1: Not Available
(default)
(default)
MS1337-E-00
2011/11
- 47-
[AK7782]
17) CONT10: ADCM Volume Setting
W
D0h
R
50h
Name
D7
CONT10 VOL[5]
D6
VOL[4]
D5
VOL[3]
D4
D3
D2
D1
VOL[2] VOL[1] VOL[0] TEST
D0
TEST
Default
00h
D7, D6, D5, D4, D3, D2: VOL[5:0] ADCM Volume Setting
VOL[5] VOL[4] VOL[3] VOL[2] VOL[1] VOL[0] Volume (dB)
0
0
0
0
0
0
0
(default)
0
0
0
0
0
1
-2
0
0
0
0
1
1
-4
0
0
0
1
0
0
-6
0
0
0
1
0
1
-8
0
0
0
1
1
1
-10
0
0
1
0
0
0
-12
0
0
1
0
0
1
-14
0
0
1
0
1
1
-16
0
0
1
1
0
0
-18
0
0
1
1
0
1
-20
0
0
1
1
1
1
-22
0
1
0
0
0
0
-24
0
1
0
0
0
1
-26
0
1
0
0
1
1
-28
0
1
0
1
0
0
-30
0
1
0
1
0
1
-32
0
1
0
1
1
1
-34
0
1
1
0
0
0
-36
0
1
1
0
0
1
-38
0
1
1
0
1
1
-40
0
1
1
1
0
0
-42
0
1
1
1
0
1
-44
0
1
1
1
1
1
-46
1
0
0
0
0
0
-48
1
0
0
0
0
1
-50
1
0
0
0
1
1
-52
1
0
0
1
0
0
-54
1
0
0
1
0
1
-56
1
0
0
1
1
1
-58
1
0
1
0
0
0
-60
1
1
1
1
-∞
D1: TEST
0: Normal Operation
1: Not Available
(default)
D0: TEST
0: Normal Operation
1: Not Available
(default)
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[AK7782]
18) CONT11: ADC2 and ADC1 Analog Switch Select
W
D1h
R
51h
Name
CONT11
D7
ASEL2[2]
D6
ASEL2[1]
D5
ASEL2[0]
D7, D6, D5: ASEL2[2:0] ADC2 Input Selector Setting
ASEL2[2:0]
Selected Analog Input Pin
000
AINL-, AINL+, AINR-, AINR+
001
AINL2, AINR2
010
AINL3, AINR3
011
AINL4, AINR4
100
AINL5, AINR5
101
AINL6, AINR6
110
AINL7, AINR7
111
AINL8, AINR8
D4, D3, D2: ASEL1[2:0] ADC1 Input Selector Setting
ASEL1[2:0]
Selected Analog Input Pin
000
AINL-, AINL+, AINR-, AINR+
001
AINL2, AINR2
010
AINL3, AINR3
011
AINL4, AINR4
100
AINL5, AINR5
101
AINL6, AINR6
110
AINL7, AINR7
111
AINL8, AINR8
D4
ASEL1[2]
D3
D2
D1
ASEL1[1] ASEL1[0] MUX[1]
Default
00h
(default)
(default)
D1, D0: MUX[1:0] MUX Input Select
MUX Mode
MUX[1:0]
MUXOUT Lch Output
MUXOUT Rch Output
0
00
MSELOUT Lch
MSELOUT Rch
1
01
MSELOUT Lch
ADCM
2
10
ADCM
MSELOUT Rch
3
11
ADCM
ADCM
Note 67. L channel and R channel output the same data in MUX Mode 3.
MS1337-E-00
D0
MUX[0]
(default)
2011/11
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[AK7782]
19) CONT12: SRC2 Data, Clock Setting
Write during system reset or DSP reset.
W
R
Name
D7
SRC2
D2h 52h
CONT12
ISEL[1]
D7, D6: SRC2ISEL[1:0] SRC2I Select
SRC2ISEL Mode SRC2ISEL[1:0]
0
00
1
01
2
10
3
11
D6
SRC2
ISEL[0]
D5
SRC2
CKI[1]
SRC2I
SDIN5 pin
SDIN1 pin
DSP1 SDOUT1
DSP2 SDOUT1
D4
SRC2
CKI[0]
D3
SRC2
CKO[1]
D2
SRC2
CKO[0]
D1
D0
Default
0
0
00h
(default)
D5, D4: SRC2CKI[1:0] SRC2 Input Clock Select
SRC2CKI Mode SRC2CKI[1:0]
SRC2LRCKI
0
00
SRC2LRCK pin
1
01
SRCLRCK pin
2
10
LRCLKO
3
11
N/A
SRC2BICKI
SRC2BICK pin
SRCBICK pin
BITCLKO
N/A
D3, D2: SRC2CKO[1:0] SRC2 Output Clock Select
SRC2CKO Mode SRC2CKO[1:0]
SRC2LRCKO
0
00
LRCLKO
1
01
SRCLRCK pin
2
10
SRC2LRCK pin
3
11
N/A
SRC2BICKO
BITCLKO
SRCBICK pin
SRC2BICK pin
N/A
(default)
(default)
D1: Reserved
0: Normal Operation (default)
Write “0” into this bit.
D0: Reserved
0: Normal Operation (default)
Write “0” into this bit.
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[AK7782]
20) CONT13: SRC1 Setting
Write during system reset or DSP reset.
W
R
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
SRC1
00h
D3h 53h CONT13
BIEDGE IDIF[2] IDIF[1] IDIF[0] BIFS[1] BIFS[0] SEMIAUTO AUTOSEL
D7: SRC1BIEDGE SRC1BICKI Edge Select
0: Rising Edge of SRC1LRCKI
1: Falling Edge of SRC1LRCKI
This setting is valid only when the SRC1 input interface setting is in PCM mode (SRC1IDIF mode 6 or 7).
D6, D5, D4: SRC1IDIF[2:0] SRC1I Input Interface Select
SRC1IDIF Mode
0
1
2
3
4
5
6
7
SRC1IDIF[2:0]
000
001
010
011
100
101
110
111
fsi: SRC1 Input Sampling Rate
Input Format
SRC1BICKI
LSB 16bit
≥ 32fsi
(default)
LSB 20bit
≥ 40fsi
MSB 24/20bit
≥ 48fsi
I2S Compatible 24/16bit ≥ 48fsi or 32fsi
LSB 24bit
≥ 48fsi
N/A
PCM SHORT
SRC1BIFS[1:0] Setting
PCM LONG
SRC1BIFS[1:0] Setting
D3, D2: SRC1BIFS[1:0] SRC1BICKI fs Select
SRC1BIFS Mode
0
1
2
3
SRC1BIFS[1:0]
00
01
10
11
SRC1BICKI
32fsi
64fsi
128fsi
48fs
(default)
D1: SRC1SEMIAUTO SRC1 Soft Mute SEMIAUTO Function Switch
0: SRC1 SEMIAUTO OFF
1: SRC1 SEMIAUTO ON
D0: SRC1AUTOSEL SRC1 Soft Mute SEMIAUTO mode Release Time Setting
0: 2205/fso (default)
1: 8820/fso
Note 68. The output format of SRC1 is fixed to 24-bit MSB justified.
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[AK7782]
21) CONT14: SRC2 Setting
Write during system reset or DSP reset.
W
R
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
SRC2
00h
D4h 54h CONT14
BIEDGE IDIF[2] IDIF[1] IDIF[0] BIFS[1] BIFS[0] SEMIAUTO AUTOSEL
D7: SRC2BIEDGE SRC2BICKI Edge Select
0: Rising Edge of SRC2LRCKI (default)
1: Falling Edge of SRC2LRCKI
This setting is valid only when the SRC2 input interface setting is in PCM mode (SRC2IDIF mode 6 or 7).
D6, D5, D4: SRC2IDIF[2:0] SRC2I Input Interface Select
SRC2IDIF Mode
0
1
2
3
4
5
6
7
SRC2IDIF[2:0]
000
001
010
011
100
101
110
111
fsi: SRC2 Input Sampling Rate
Input Format
SRC2BICKI
LSB 16bit
≥ 32fsi
(default)
LSB 20bit
≥ 40fsi
MSB24/20bit
≥ 48fsi
I2S Compatible 24/16bit ≥ 48fsi or 32fsi
LSB 24bit
≥ 48fsi
N/A
PCM SHORT
SRC2BIFS[1:0] Setting
PCM LONG
SRC2BIFS[1:0] Setting
D3, D2: SRC2BIFS[1:0] SRC2BICKI fs Select
SRC2BIFS Mode
0
1
2
3
SRC2BIFS[1:0]
00
01
10
11
SRC2BICKI
32fsi
64fsi
128fsi
48fs
(default)
D1: SRC2SEMIAUTO SRC2 Soft Mute SEMIAUTO Function Switch
0: SRC2 SEMIAUTO OFF (default)
1: SRC2 SEMIAUTO ON
D0: SRC2AUTOSEL SRC2 Soft Mute SEMIAUTO Mode Release Time Setting
0: 2205/fso (default)
1: 8820/fso
Note 69. The output format of SRC2 is fixed to 24-bit MSB justified.
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[AK7782]
22) CONT15: Power Save Setting
W
D5h
R
55h
Name
CONT15
D7
PSDSP2
D6
PSDSP1
D5
PSSRC2
D4
PSSRC1
D3
PSADC2
D2
PSADC1
D1
PSADCM
D0
0
Default
00h
D7: PSDSP2 DSP2 Power Save
0: Normal Operation (default)
1: DSP2 Power Save
When not using DSP2, DSP2 block can be set to power-save mode by setting this bit to “1”.
Write “0” to return to the normal Operation.
D6: PSDSP1 DSP1 Power Save
0: Normal Operation (default)
1: DSP1 Power Save
When not using DSP1, DSP1 block can be set to power-save mode by setting this bit to “1”.
Write “0” to return to the normal Operation.
D5: PSSRC2 SRC2 Power Save
0: Normal Operation (default)
1: SRC2 Power Save
When not using SRC2, SRC2 block can be set to power-save mode by setting this bit to “1”.
Write “0” to return to the normal Operation.
D4: PSSRC1 SRC1 Power Save
0: Normal Operation (default)
1: SRC1 Power Save
When not using SRC1, SRC1 block can be set to power-save mode by setting this bit to “1”.
Write “0” to return to the normal Operation.
D3: PSADC2 ADC2 Power Save
0: Normal Operation (default)
1: ADC2 Power Save
When not using ADC2, ADC2 block can be set to power-save mode by setting this bit to “1”.
Write “0” to return to the normal Operation.
D2: PSADC1 ADC1 Power Save
0: Normal Operation (default)
1: ADC1 Power Save
When not using ADC1, ADC1 block can be set to power-save mode by setting this bit to “1”.
Write “0” to return to the normal Operation.
D1: PSADCM ADCM Power Save
0: Normal Operation (default)
1: ADCM Power Save
When not using ADCM, ADCM block can be set to power-save mode by setting this bit to “1”.
Write “0” to return to the normal Operation.
D0: Reserved
0: Normal Operation (default)
Write “0” into this bit.
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[AK7782]
23) CONT16: Reset Control
W
R
Name
D6h
56h
CONT16
D7
RSRC2
SMUTE
D6
RSRC1
SMUTE
D5
RSRC
RSTN
D4
RDSP
RSTN
D3
RADC
RSTN
D2
D1
D0
Default
0
0
0
00h
D7: RSRC2SMUTE
0: SRC2 SOFT MUTE OFF (default)
1: SRC2 SOFT MUTE ON
When RSRC2SMUTE register is used to control soft mute, the PSRCSMUTE pin should be tied “L”.
D6: RSRC1SMUTE
0: SRC1 SOFT MUTE OFF (default)
1: SRC1 SOFT MUTE ON
When RSRC1SMUTE register is used to control soft mute, the PSRCSMUTE pin should be tied “L”.
D5: RSRCRSTN SRC Reset N Register
0: SRC1, SRC2 Reset (default)
1: SRC1, SRC2 Reset Release
When RSRCRSTN register is used to control soft mute, the PSRCRSTN pin should be tied “L”.
D4: RDSPRSTN DSP Reset N Register
DSP1, DSP2 Reset (default)
1: DSP1, DSP2 Reset Release
When RDSPRSTN register is used to control soft mute, the PDSPRSTN pin should be tied “L”.
D3: RADCRSTN ADC Reset N Register
0: ADC1, ADC2, ADCM Reset (default)
1: ADC1, ADC2, ADCM Reset Release
When RADCRSTN register is used to control soft mute, the PADRSTN pin should be tied “L”.
D2: Reserved
0: Normal Operation (default)
Write “0” into this bit.
D1: Reserved
0: Normal Operation (default)
Write “0” into this bit.
D0: Reserved
0: Normal Operation (default)
Write “0” into this bit.
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[AK7782]
■ Reset
1. Hardware Reset and Software Reset
The AK7782 has six Reset functions: Initial Reset, System Reset, Clock Reset, ADC Reset, DSP Reset and SRC reset.
Initial Reset is controlled by INITRSETN pin Hardware Reset only. Other resets are controlled by a pin (hardware reset)
or register (software reset). The difference between Hardware Reset and Software Reset is only the method of pin setting
or register setting. When using Hardware Reset, the R*RSTN bit should be “0”. When using Software Reset, the P*RSTN
pin should be connected to VSS3. The relationship between Hardware Reset and Software Reset is shown below.
P*RSTN (Hard)
*RSTN
R*RSTN(Soft)
*=CK, AD, DSP, SRC
Figure 14. Logical Relationship between Hardware and Software Resets
*: CK, AD, DSP, SRC
P*RSTN (Hard)
L (0)
L (0)
H (1)
H (1)
R*RSTN (Soft)
0
1
0
1
*RSTN
0
1
1
1
Reset
Reset Release (Soft)
Reset Release (Hard)
Not Used (Release Reset)
The software reset register is configured with an 8-bit command code and 8-bit data and it becomes valid on the rising
edge of SCLK where data D0 written (refer to section ■ Microcontroller Interface). The default condition after initial reset
is set to 0 (reset condition)
P*RSTN (Hard) “L”
RQN
1
8 9
SCLK
SI (Soft)
16
D7
Command
D0
Data
*RSTN (Internal)
Figure 15. Soft Reset
The sequence of Hardware reset and software reset are the same. In the following description, reset pins and registers are
described as *RSTN. Figure 15 shows a software reset example.
2. Initial Reset
Initial reset is required to initialize all blocks of the AK7782. As INITRSTN pin= “L”, all control registers are initialized,
and internal counters; ADC, SRC, DSP, PLL, and etc. are stopped. When changing the INITRSTN pin to “H”, VREF
circuit (Analog reference voltage) and PLL for master clock starts operating and control register writing become valid.
CKM[2:0] pin setting, that is to change the clock frequency of the XTI pin input clock (CKM mode 0/1/2/3) or the
BITCLKI pin input clock (CKM mode 4/5), must be executed during initial reset or clock reset. CKM[2:0] pins are
related to main PLL circuit and internal counter control. Therefore, changing these pin sates must be executed during
initial reset or clock reset, otherwise it may cause erroneous operation.
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[AK7782]
Pin State during Initial Reset (Output pins, Input/Output pins)
Pin Pin
I/O Pin State
Pin
No. Name
during Initial Reset
No.
1
LFLT
O
H
50
12
XTO
O
Hi-Z
51
21
LRCLKO O
L
52
22
BITCLKO O
L
53
23
SDOUT1
O
L
54
24
SDOUT2
O
L
55
25
SDOUT3
O
L
65
26
27
28
SDOUT4
SDOUT5
CLKO1
O
O
O
L
L
L
76
86
Pin
Name
SO
RDY
STO
SDOUTA1
SDOUT6
SDOUT7
SDA
I/O
O
O
O
O
O
O
IO
TESTO
VCOM
O
O
Pin State
during Initial Reset
Hi-Z
H
H
L
L
L
L (I2CSEL=L)
Hi-Z (I2CSEL=H)
Hi-Z
L
3. Clock Reset
After initial reset is released (INITRSTN pin = “H”), the AK7782 enters clock reset condition with the PCKRSTN pin =
“L” and RCKRSTN bit = “0”. Release clock reset when system clocks (XTI in CKM mode 0 or 1) (XTI, LRCLKI and
BITCLKI in CKM mode 2 or 3) (LRCLKI and BITCLKI in CKM mode 4 or 5) are stabled. After clock reset is released,
PLL starts operation and generates a master clock. DSP programs, coefficient data and other data can not be sent to the
AK7782 until the PLL reaches stable oscillation (18ms). The ADC or DSP block of the AK7782 will start operation by
ADRSTN bit = “1” or DSPRSTN bit = “1”, respectively after DSP programs, coefficients and data are input.
The setting of CKM[2:0] pins and input clock frequency can be changed during clock reset (PCKRSTN pin = “L”,
RCKRSTN bit = “0” and INITRSTN pin = “H”). The AK7782 also becomes clock reset state by changing the PCKRSTN
pin to “L” from “H” or RCKRSTN bit to “0” from “1”, during system reset.
INITRSTN
PCKRSTN
SRESETN(Intenal)
ICLK
(XTI or BITCLKI)
Stabilization of new
Changes of pin setting
input clock
PLL oscillation
Transferable time
stabilized (18ms)
of DSP program
and input clock
Figure 16. PCKRSTN pin Clock Reset (Hardware Rest) Timing during Initial Rest
PCKRSTN= “L”
600ns(min)
RQN
SCLK (Simplified)
SI
SRESETN (Internal)
Stabilization of new
input clock
D6h
00h
C0h
00h
C0h
RCKRSTN=0
02h
D6h
18h
CKRSTN=1
CKRSTN (Internal)
Changes of pin setting
PLL Oscillation
Transferable time of command
and input clock
Stabilized (18ms)
code and DSP program
Figure 17. RCKRSTN bit Clock Reset (Soft Reset) Timing during Normal Operation
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[AK7782]
4. System Reset
System reset is defined as when ADC reset (ADRSTN bit = “0”) and DSP reset (DSPRSTN bit = “0”) are on after Clock
reset release (PCKRSTN pin = “H” or RCKRSTN bit = “1”).
PADRSTN (Hard)
RADRSTN(Soft)
ADRSTN
Internal SRESETN
PDSPRSTN (Hard)
DSPRSTN
RDSPRSTN(Soft)
Figure 18. System Reset Diagram
ADRSTN
DSPRSTN
0
0
1
1
0
1
0
1
Internal
SRESETN
0
1
1
1
Status
System reset
DSP in operation, ADC reset (System reset release)
DSP reset, ADC in operation (System reset release)
DSP, ADC operation (System reset release)
Writing to programs is executed during this System reset condition (except writing during RUN or when changing DSP
program during ADC operation). The ADC and DSP blocks are in Reset condition during System Reset, and SRC block is
not available. LRCLKO and BITCLKO in Master mode are stopped. System Reset is released when either ADRSTN bit
or DSPRSTN bit is changed to “1” from “0”, then the internal counters start operation. ADC block outputs data in
130LRCK (max) after System reset is released. ([email protected]=48kHz, [email protected]=8kHz)
In Slave mode, internal clocks start operation on the rising edge of LRCLK (on the falling edge in I2S mode) when the
System reset is released (ADRSTN bit = “1” or DSPRSTN bit = “1”). Timing adjustment between external clock
(LRCLKI, BITCLKI) and internal clock operation may only be made at this time. Therefore, do not stop LRCLKI and
BITCLKI or do not change frequency of these clocks after releasing System reset. However, if the phase difference
between LRCLKI and internal timing during operation is within 16fs, internal timing maintains operation. When the
phase difference becomes larger than this range, phase adjustment synchronized with the rising edge of LRCLKI (falling
edge in I2S mode) is made. This function avoids the loss of synchronization between the AK7782 and external circuitry
due to noise, but normal data is not output momentarily. It takes 4LRCLK (max) for phase adjustment between external
clocks (LRCLKI and BITCLKI) and internal timing. This function cannot be used for phase adjustment of clocks and
clock frequency changes in normal operation.
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[AK7782]
5. Relationship between Resets and Internal Operation
(1) Conditions on Hardware Reset (pin: Pin Name, ctreg: Control Register Name)
INITRSTN (pin)
PCKRSTN (pin)
PDSPRSTN (pin)
PADRSTN (pin)
RCKRSTN (ctreg)
RDSPRSTN (ctreg)
RADRSTN (ctreg)
SRESETN (Internal)
REF Circuit
Main PLL
Except CLKO1 XTI Outputs
CLKO1 XTI Outputs
LRCLKO (Slave)
(Master)
BITCLKO (Slave)
(Master)
DSP Block
ADC Block
Initial
Reset
Clock
Reset
System
Reset
DSP
Reset Release
ADC
Reset Release
DSP+ADC
Reset Release
L
L
L
L
0
0
0
0
Stop
Stop
Stop
Stop
Stop
Stop
Stop
Stop
Stop
Stop
H
L
L
L
0
0
0
0
Active
Stop
Stop
Active
LRCLKI
Stop
BITCLKI
Stop
Stop
Stop
H
H
L
L
0
0
0
0
Active
Active
Active
Active
LRCLKI
Stop
BITCLKI
Stop
Stop
Stop
H
H
H
L
0
0
0
1
Active
Active
Active
Active
LRCLKI
Active
BITCLKI
Active
Active
Stop
H
H
L
H
0
0
0
1
Active
Active
Active
Active
LRCLKI
Active
BITCLKI
Active
Stop
Active
H
H
H
H
0
0
0
1
Active
Active
Active
Active
LRCLKI
Active
BITCLKI
Active
Active
Active
(2) Conditions on Software Reset (pin: Pin Name, ctreg: Control Register Name)
Initial
Reset
INITRSTN (pin)
L
PCKRSTN (pin)
L
PDSPRSTN (pin)
L
PADRSTN (pin)
L
RCKRSTN (ctreg)
0
RDSPRSTN (ctreg)
0
RADRSTN (ctreg)
0
SRESETN (Internal)
0
REF Circuit
Stop
Main PLL
Stop
Except CLKO1 XTI Outputs
Stop
CLKO1 XTI Outputs
Stop
LRCLKO (Slave)
Stop
(Master)
Stop
BITCLKO (Slave)
Stop
(Master)
Stop
DSP Block
Stop
ADC Block
Stop
Conditions of (1) and (2) can be mixed.
Clock
Reset
System
Reset
DSP
Reset Release
ADC
Reset Release
DSP+ADC
Reset Release
H
L
L
L
0
0
0
0
Active
Stop
Stop
Active
LRCLKI
Stop
BITCLKI
Stop
Stop
Stop
H
L
L
L
1
0
0
0
Active
Active
Active
Active
LRCLKI
Stop
BITCLKI
Stop
Stop
Stop
H
L
L
L
1
1
0
1
Active
Active
Active
Active
LRCLKI
Active
BITCLKI
Active
Active
Stop
H
L
L
L
1
0
1
1
Active
Active
Active
Active
LRCLKI
Active
BITCLKI
Active
Stop
Active
H
L
L
L
1
1
1
1
Active
Active
Active
Active
LRCLKI
Active
BITCLKI
Active
Active
Active
MS1337-E-00
2011/11
- 58-
[AK7782]
■ Power-up Sequence
The AK7782 should be powered up on the INITRSTN pin= “L”, PCKRSTN pin = “L”, PDSPRSTN pin = “L” and
PADRSTN pin = “L”. This INITRSTN pin = “L” initializes control resisters and internal circuits (Note 70). After all
powers are supplied, REF circuit (analog reference voltage) starts operation by setting the INITRSTN pin = “H”. Then,
main PLL starts operation by setting PCKRSTN pin = “H” after stabilized system clock is input (Note 71). The main PLL
generates master clock (MCLK). Downloading DSP program by external clocks is prohibited until the PLL oscillation is
stabilized.
Note 70. To assure initialization, power must be supplied.
Note 71. When the PCKRSTN pin is fixed “L” and clock reset operation is controlled only by the Control Register
(Software reset), release Clock Reset by setting CONT00 D0 (RCKRSTN) = “1”.
Note System clocks (CKM mode0/1: XTI; CKM mode 2/3: XTI, LRCLKI, BITCLKI; CKM mode 4/5: LRCLKI,
BITCLKI) should not be stopped except during Initial reset (INITRSTN pin = “L”) or Clock reset (INITRSTN pin
= “H” & RCKRSTN bit = “0”).
AVDD
DVDD
DVDD18
INITRSTN
CKRSTN
SRESETN (Internal)
XTI(CKM Mode 0-3)
BITCLKI(CKM Mode 4,5)
(Internal PLLCLK)
CLKO1
Power OFF
INITRSTN Release
Bring CKRST “H”
Transmission of command codes
Transfer time of command codes and
after Power-up
after crystal
is prohibited until PLL reached
DSP program (no time limitation)
oscillation stabilizes stable oscillation (18ms)
Pin settings should be completed
CLKO1 Output Start (18ms max)
Figure 19. Power-up Sequence
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[AK7782]
■ RAM Clear
The AK7782 has a RAM clear function. After the DSP reset release, DRAM and DLRAM are cleared by “0”. The
required time to clear RAM is about 7*LRCLK (max) + 4096*MCLK (internal master clock) in slave mode, and
3*LRCK (max) + 4096*MCLK in master mode. For example, in slave mode, it is (7/48kHz)+(4096/122.88MHz)=179μs
when fs=48kHz, and (7/8kHz)+(4096/122.88MHz)=908μs when fs=8kHz.
In a RAM clear sequence, it is possible to send data to DSP. (DSP is stopped during RAM clear sequence. Data is
accepted automatically after this sequence is completed.)
INITRSTN
PDSPRSTN
RAM Clear (Internal)
DSP Start (Internal)
RAM Clear Period
DSP Program Start
Figure 20. RAM Clear Sequence
■ Audio Data Interface
Serial Audio Data pins SDIN1, SDIN2, SDIN3, SDIN4, SDIN5, SDIN6, SDIN7, SDOUT1, SDOUT2, SDOUT1,
SDOUT2, SDOUT3, SDOUT4, SDOUT5, SDOUT6, SDOUT7 and SDOUTA1 pins are interfaced with external systems
using LRCLKI, BITCLKI, LRCLKO and BITCLKO clocks. The data format is 2's complement MSB first. Input/Output
format supports I2S compatible, MSB justified and LSB justified. When settings are in I2S mode, all Input/Output audio
data and DSP signal are limited to I2S format. BITCLKI only corresponds to 64fs.
The input format of SDIN2, SDIN3 and SDIN4 is corresponds to 24-bit MSB, 24/20/16-bit LSB, F24.4 floating point
MSB and 32-bit MSB justified. The data format setting for SDIN2-4 is in common. The input formats of SDIN1, SDIN5,
SDIN6 and SDIN7 correspond to 24-bit MSB and F24.4 floating point MSB justified. The data format settings of SDIN1,
SDIN5, SDIN 6 and SDIN7 can be set individually by control register settings. The data format setting of SDIN2, SDIN3
and SDIN4 are in common. When connecting ADC1, ADC2, ADCM, SRC1O and SRC2O to SDIN1, SDIN5, SDIN6 and
SDIN7, set control registers to MSB justified. (same as I2S mode).
The output format of SDOUT2, SDOUT3 and SDOUT4 corresponds to 24-bit MSB, 24/20/16bit LSB, F24.4 floating
point MSB, 32-bit MSB justified. The data format setting for SDOUT2, SDOUT3, and SDOUT4 are in common. The
output format of DSOUT1, SDOUT5, SDOUT6 and SDOUT7 corresponds to 24-bit MSB and F24.4 floating point MSB
justified. The data format setting of SDIN1, SDIN5, SDIN 6 and SDIN7 can be set individually by control register
settings. ADCM outputs are the same for both L and R channels.
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[AK7782]
1) MSB/LSB Justified: DIFI2S bit= “0” (CONT00 D4)
Left ch
LRCLKO
Right ch
BITCLKO
31 30 29 28 27
SDIN1~7
DIF Mode 0
SDOUT1~7
DOF Mode 0
SDOUTA1
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M 22 2120 19
2 1 L
M 22 21 20 19
2 1 L
M:MSB,L:LSB
M 22 2120 19
2 1 L
M 22 21 20 19
2 1 L
M:MSB,L:LSB
Figure 21. Master Mode (CKM Mode 0, 1) MSB Justified (24-bit), BITCLK64fs
Left ch
LRCLKO
Right ch
BITCLKO
31 30
SDIN2~4
DIFD Mode 1
SDIN2~4
DIFD Mode 2
SDIN2~4
DIFD Mode 3
SDOUT2~4
DOFD Mode 1
SDOUT2~4
DOFD Mode 2
SDOUT2~4
DOFD Mode 3
23 22 21 20 19 18 17 16 15 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
Don’t care M 22 21 20 19 18 17 16 15 14
1 L Don’t care M 22 21 20 19 18 17 16 15 14
1 L
Don’t care
M 18 17 16 15 14
1 L Don’t care
1 L
Don’t care
M 14
M 18 17 16 15 14
1 L Don’t care
M:MSB,L:LSB
M 14
1 L
MSB
22 21 20 19 18 17 16 15 14
1 L
MSB
22 21 20 19 18 17 16 15 14
1 L
MSB
18 17 16 15 14
1 L
MSB
18 17 16 15 14
1 L
MSB
14
1 L
MSB
14
1 L
Figure 22. Master Mode (CKM Mode 0, 1) LSB Justified, BITCLK64fs
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[AK7782]
Left ch
LRCLKI
Right ch
BITCLKI
31 30 29 28 27
SDIN1~7
DIF Mode 0
SDOUT1~7
DOF Mode 0
SDOUTA1
LRCLKO
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M 22 2120 19
2 1 L
M 22 21 20 19
2 1 L
M:MSB,L:LSB
M 22 2120 19
2 1 L
M 22 21 20 19
2 1 L
M:MSB,L:LSB
Left ch
Right ch
BITCLKO
Figure 23. Slave Mode (CKM Mode 2~5) MSB Justified (24bit), BITCLK64fs
Left ch
LRCLKI
Right ch
BITCLKI
31 30
SDIN2~4
DIFD Mode 1
SDIN2~4
DIFD Mode 2
SDIN2~4
DIFD Mode 3
SDOUT2~4
DOFD Mode 1
SDOUT2~4
DOFD Mode 2
SDOUT2~4
DOFD Mode 3
LRCLKO
23 22 21 20 19 18 17 16 15 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
Don’t care M 22 21 20 19 18 17 16 15 14
1 L Don’t care M 22 21 20 19 18 17 16 15 14
1 L
Don’t care
M 18 17 16 15 14
1 L Don’t care
M 18 17 16 15 14
1 L
Don’t care
M 14
1 L Don’t care
M 14
1 L
M:MSB,L:LSB
MSB
22 21 20 19 18 17 16 15 14
1 L
MSB
22 21 20 19 18 17 16 15 14
1 L
MSB
18 17 16 15 14
1 L
MSB
18 17 16 15 14
1 L
MSB
14
1 L
MSB
14
1 L
Left ch
Right ch
BITCLKO
Figure 24. Slave Mode (CKM Mode 2~5) LSB Justified, BITCLK64fs
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[AK7782]
Left ch
LRCLKO
Right ch
BITCLKO
31 30 29 28 27
SDIN1, 5~7
DIF Mode 1
SDIN2, 3, 4
DIF Mode 4
SDOUT1, 5~7
DOF Mode 1
SDOUT2, 3, 4
DOF Mode 4
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M 22 2120 19
2 1 L S3S2S1S0
M 22 21 20 19
2 1 L S3 S2 S1 S0
M 22 2120 19
2 1 L S3S2S1S0
M 22 21 20 19
2 1 L S3 S2 S1 S0
M 22 2120 19
2 1 L S3S2S1S0
M 22 21 20 19
2 1 L S3 S2 S1 S0
M 22 2120 19
2 1 L S3S2S1S0
M 22 21 20 19
2 1 L S3 S2 S1 S0
Figure 25. Master Mode (CKM Mode 0, 1) MSB Justified (24-bit), BITCLK64fs,
DIF7/6/5/1 Mode 1, DIFD Mode 4, DOF7/6/5/1 Mode 1, DOFD Mode 4
Left ch
LRCLKO
Right ch
BITCLKO
31 30 29 28 27
SDIN1, 5~7
DIF Mode 0
SDIN2, 3, 4
DIF Mode 5
SDOUT1, 5~7
DOF Mode 0
SDOUT2, 3, 4
DOF Mode 5
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
M 22 2120 19
2 1 L
M 30 2928 27
10 9 8 7 6 5 4 3 2 1 L M 30 2928 27
10 9 8 7 6 5 4 3 2 1 L
M 22 2120 19
2 1 L
2 1 L
M 30 2928 27
10 9 8 7 6 5 4 3 2 1 L M 30 2928 27
M 22 21 20 19
2 1 L
10 9 8 7 6 5 4 3 2 1 L
Figure 26. Master Mode (CKM Mode 0, 1) MSB Justified (24-bit), BITCLK64fs,
DIF7/6/5/1 Mode 0, DIFD Mode 5, DOF7/6/5/1 Mode 0, DOFD Mode 5
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[AK7782]
Left ch
LRCLKI
Right ch
BITCLKI
31 30 29 28 27
SDIN1, 5~7
DIF Mode 1
SDIN2, 3, 4
DIF Mode 4
SDOUT1, 5~7
DOF Mode 1
SDOUT2, 3, 4
DOF Mode 4
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M 22 2120 19
2 1 L S3S2S1S0
M 22 21 20 19
2 1 L S3 S2 S1 S0
M 22 2120 19
2 1 L S3S2S1S0
M 22 21 20 19
2 1 L S3 S2 S1 S0
M 22 2120 19
2 1 L S3S2S1S0
M 22 21 20 19
2 1 L S3 S2 S1 S0
M 22 2120 19
2 1 L S3S2S1S0
M 22 21 20 19
2 1 L S3 S2 S1 S0
Left ch
LRCLKO
Right ch
BITCLKO
Figure 27. Slave Mode (CKM Mode 0, 1) MSB Justified (24-bit), BITCLK64fs,
DIF7/6/5/1 Mode 1, DIFD Mode 4, DOF7/6/5/1 Mode 1, DOFD Mode 4
Left ch
LRCLKI
Right ch
BITCLKI
31 30 29 28 27
SDIN1, 5~7
DIF Mode 0
SDIN2, 3, 4
DIF Mode 5
SDOUT1, 5~7
DOF Mode 0
SDOUT2, 3, 4
DOF Mode 5
LRCLKO
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
M 22 2120 19
2 1 L
M 30 2928 27
10 9 8 7 6 5 4 3 2 1 L M 30 2928 27
10 9 8 7 6 5 4 3 2 1 L
M 22 2120 19
2 1 L
2 1 L
M 30 2928 27
10 9 8 7 6 5 4 3 2 1 L M 30 2928 27
M 22 21 20 19
Left ch
2 1 L
10 9 8 7 6 5 4 3 2 1 L
Right ch
BITCLKO
Figure 28. Slave Mode (CKM Mode 0, 1) MSB Justified (24-bit), BITCLK64fs,
DIF7/6/5/1 Mode 0, DIFD Mode 5, DOF7/6/5/1 Mode 0, DOFD Mode 5
MS1337-E-00
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[AK7782]
2) I2S Compatible Format: DIFI2S bit= “1” (CONT00 D4)
Left ch
LRCLKO
Right ch
BITCLKO
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1~7
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
SDOUT1~7
SDOUTA1
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
M:MSB,L:LSB
M:MSB,L:LSB
When using this mode, set all input and output formats to MSB-justified 24-bit.
Figure 29. Master Mode (CKM Mode 0~1)
Left ch
LRCLKI
Right ch
BITCLKI
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1~7
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
SDOUT1~7
SDOUTA1
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
LRCLKO
Left ch
M:MSB,L:LSB
M:MSB,L:LSB
Right ch
BITCLKO
When using this mode, set all input and output formats to MSB-justified 24-bit.
Figure 30. Slave Mode (CKM Mode 2~5)
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[AK7782]
■ Microcontroller Interface (I2CSEL pin= “L”)
1. Configuration
The access format is Command code (8-bit) + Address + Data (MSB first).
Bit
Length
Command
8
MSB bit is R/W flag. Remaining 7-bits are for access area such as PRAM/CRAM
registers.
Address
16 / 0
Valid only for those cases where accessed areas have addresses such as
PRAM/CRAM/OFREG. When no address is assigned, there is no data.
Data
See the
Write or Read data.
following
section
Note 72. The address of PRAM is fixed to “0”.
RQN
SCLK
don’tcare
(L/H )
SI
Command (8bit)
SO
Hi-Z
Address (16bit or 0bit )
d on’tcare
(L/H)
Data ( write )
Data ( read )
Low or Echo back
Hi-Z
SO is in Hi-Z condition while RQN=High
2. Command Codes
BIT7
BIT6
BIT5
Area to be Accessed
Access area and accompanying data
BIT7
BIT6
BIT5
BIT4
BIT4
BIT3
BIT2
BIT1
BIT0
Accompanying Data to the Accessed Area
BIT3~0
0
0
1
0
0100
0
0
1
0
0110
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0100
0010
1000
0110
1100
1010
0000
0001
0110
1000
0111
1001
Register Address
Register Address
0010
0000
Confirmation of write preparation to CRAM/OFRAM
during RUN
Confirmation of write preparation to CRAM2/OFRAM
during RUN
CRAM Read during DSP reset.
OFRAM Read during DSP reset
PRAM Read during DSP reset
CRAM2 Read during DSP reset
OFRAM2 Read during DSP reset
PRAM2 Read during DSP reset
DSP1 Error Status Read
DSP2 Error Status Read
MICR Read @DSP1
MIR2 Read @DSP1
MICR Read @DSP2
MIR2 Read @DSP2
Registers 00~0F Read
Registers 10~16 Read
CRC result Read
Device Identification
MS1337-E-00
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[AK7782]
3. Address
All address notations are LSB-justified.
When accessing Command codes, BIT [6:4] = 000 ~ 011, 16-bit address assignment must be followed.
When accessing Command codes, BIT [6:4] = 100 ~ 111, no address assignment is required.
4. Data
Length of write data is variable depending on the write area size. When accessing RAM, write data to sequential address
locations by writing data continuously.
Write
Command
Code
Address
Data
Length
80h~8Fh
16bit Assignment
16bit × n
A2h
A4h
B2h
B4h
B8h
F4h
16bit Assignment
16bit Assignment
16bit Assignment
16bit Assignment
16bit Assignment
None
None
None
16bit × n
16bit × n
40bit × n
8bit
90h~9Fh
16bit Assignment
16bit × n
ACh
A6h
BCh
B6h
BAh
F5h
16bit Assignment
16bit Assignment
16bit Assignment
16bit Assignment
16bit Assignment
None
None
None
16bit × n
16bit × n
40bit × n
8bit
10h~1Fh
16bit Assignment
16bit × n
AEh
16bit Assignment
None
ADh
16bit Assignment
None
BEh
BDh
BFh
F6h
C0h~CFh
D0h~D6h
F2h
16bit Assignment
16bit Assignment
16bit Assignment
None
None
None
None
16bit × n
16bit × n
40bit × n
8bit
8bit
8bit
16bit
Content
CRAM/OFRAM Write preparation during RUN.
BIT3:BIT0 of the command code determines the amount of write
operations (80h # of write: 1, 81h # of write: 2, ----, 8Fh # of write: 16).
If the actual amount of write operations exceeds the defined amount,
that data will be ignored.
Execution of OFRAM Write during RUN: address is ignored.
Execution of CRAM Write during RUN: address is ignored.
OFRAM Write during DSP reset.
CRAM Write during DSP reset.
PRAM Write during DSP reset.
DSP1 JX writing
CRAM2/OFRAM2 Write preparation during RUN.
BIT3:BIT0 of the command code determines the amount of write
operations (90h # of write: 1, 91h # of write: 2, ----, 9Fh # of write: 16).
If the actual amount of write operations exceeds the defined amount,
that data will be ignored.
Execution of OFRAM2 Write during RUN: address is ignored.
Execution of CRAM2 Write during RUN: address is ignored.
OFRAM2 Write during DSP reset.
CRAM2 Write during DSP reset.
PRAM2 Write during DSP reset.
DSP2 JX Writing
CRAM&CRAM2, OFRAM&OFRAM2 Write preparation during
RUN.
BIT3:BIT0 of the command code determines the amount of write
operations (10h # of write: 1, 11h # of write: 2, ----, 1Fh # of write: 16).
If the actual amount of write operations exceeds the defined amount,
that data will be ignored.
Execution of OFRAM & OFRAM2 Write during RUN: address is
ignored.
Execution of CRAM & CRAM2 Write during RUN: address is
ignored.
OFRAM & OFRAM2 Write during DSP reset.
CRAM & CRAM2 Write during DSP reset.
PRAM & PRAM2 Write during DSP reset.
DSP1 & DSP2 JX code Write
Registers 00h~0Fh Write
Registers 10h~17h Write
CRC Write
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[AK7782]
Read
Length of the read data is variable depending on the read area size. When accessing the RAM, data may be read from
sequential address locations by reading data continuously.
Command Address
Data
Content
Code
Length
24h
None
16bit × n
Confirmation of CRAM, OFRAM Write preparation during RUN
32h
16bit Assignment
16bit × n
OFRAM Read during DSP reset.
34h
16bit Assignment
16bit × n
CRAM Read during DSP reset.
16bit
PRAM Read during DSP reset.
38h
40bit × n
ALL0
70h
None
8bit
DSP1 Error Status Read.
MIR1 Read @DSP1
28-bit data is upper-bit-justified. Lower 4-bits are validity flags.
76h
None
32bit
Valid at 0000.
MIR2 Read @DSP1
28-bit data is upper-bit-justified. Lower 4-bits are validity flags.
78h
None
32bit
Valid at 0000.
26h
3Ch
36h
16bit × n
16bit × n
16bit × n
71h
None
16bit Assignment
16bit Assignment
16bit
ALL0
None
77h
None
32bit
79h
None
32bit
40h~4Fh
50h~56h
72h
60h
None
None
None
None
8bit
8bit
16bit
8bit
3Ah
40bit × n
8bit
Confirmation of CRAM2, OFRAM2 Write during RUN.
OFRAM2 Read during DSP reset
CRAM2 Read during DSP reset
PRAM2 Read during DSP reset
DSP2 Error Status Read
MIR1 Read @DSP2
28-bit data is upper-bit-justified. Lower 4-bits are validity flags.
Valid at 0000.
MIR2 Read @DSP2
28-bit data is upper-bit-justified. Lower 4-bits are validity flags.
Valid at 0000.
Registers 00h~0Fh Read
Registers 10h~17h Read
CRC result Read
Device identification
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[AK7782]
5. Echo Back Mode
The AK7782 has an Echo-back mode where written-data is output on the SO pin one after another.
(1) Write
RQN
SI
COMMAND
SO
IN VALID
ADDRESS1
ADDRESS2
COMMAND
ADDRESS1
DATA1
DATA2
ADDRESS2
don’ tcare
(L/H)
DATA1
COMMAND
Hi-Z
IN VALID
ADDRESS1
COMMAND
Data is output on the SO pin delaying the time for 8bit from SI input.
Figure 31. Echo-back Mode Writing 1
RQN
SI
0xB4
SO
INVALID
0x00
COMMAND
0x00
ADDRESS1
BIT15~8
ADDRESS2
BIT7~0
Dummy 8bit
DATA1
DATA2
Hi-Z
It is possible to write 8bit dummy data in order to verify the written data. During PRAM or PRAM2 writing, if the dummy
data is more than 40bit, this dummy data is accepted. (more than 16bit when CRAM, CRAM2, OFRAM or OFRAM2
writing)
Figure 32. Echo-back Mode Writing 2
(2) Read
RQN
SI
COMMAND
SO
IN VALID
ADDRESS1
ADDRESS2
COMMAND
ADDRESS1
d on’tcare
(L/ H)
COMMAND
READ DATA
READ DATA
Hi-Z
IN VALID
ADDRESS1
COMMAND
Echo-back mode is not completely performed when reading, and read data output is prioritized. The figure above is when
reading PRAM or PRAM2.
Figure 33. Echo-back Mode Reading
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[AK7782]
6. Format
6-1. Write Operation during DSP Reset
Program RAM (PRAM, PRAM2) Writing (during DSP)
(1) COMMAND
B8h, BAh, BFh
(2) ADDRESS1
0 0 0 0 0 A10 A9 A8
(3) ADDRESS2
A7 ~ A0
(4) DATA1
0 0 0 0 D35 D34 D33 D32
(5) DATA2
D31~D24
(6) DATA3
D23~D16
(7) DATA4
D15~D8
(8) DATA5
D7~D0
Five bytes of data may be written continuously for each address.
Coefficient RAM (CRAM, CRAM2) Writing (during DSP)
(1) COMMAND
B4h, B6h, BDh
(2) ADDRESS1
0 0 0 0 0 A10 A9 A8
(3) ADDRESS2
A7~A0
(4) DATA2
D15~D8
(5) DATA3
D7~D0
Two bytes of data may be written continuously for each address.
Offset RAM(OFRAM, OFRAM2) Writing (during DSP Reset)
(1) COMMAND
B2h, BCh, BEh
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 A5 A4 A3 A2 A1 A0
(4) DATA1
0 0 0 D12 D11 D10 D9 D8
(5) DATA2
D7~D0
Two bytes of data may be written continuously for each address.
6-2. Write Operation during DSP Reset and RUN
Control Register Writing (during DSP Reset and RUN)
SI
(1) COMMAND
C0h~CFh, D0h~D6h
(2) DATA
D7~D0
Note 73. Write operation may be limited depending on register settings during RUN.
External Conditional Jump Code Writing (during DSP Reset and RUN)
SI
(1) COMMAND
F4h, F5h, F6h
(2) DATA
D7~D0
CRC code Writing (during DSP Reset and RUN)
SI
(1) COMMAND
F2h
(2) DATA
D15~D8
(3) DATA
D7~D0
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[AK7782]
6-3. Write Operation during RUN
Coefficient RAM (CRAM, CRAM2, and CRAM&CRAM2 together), Offset RAM (OFRAM, OFRAM2, and
OFRAM & OFRAM2 together)
Write Preparation (during RUN): The preparation sequence is the same for both coefficient and offset RAM.
SI
(1) COMMAND
80h~8Fh (one data at 80h, sixteen data at 8Fh)
90h~9Fh (one data at 90h, sixteen data at 9Fh)
10h~1Fh (one data at 10h, sixteen data at 1Fh)
(2) ADDRESS1
0 0 0 0 0 A10 A9 A8
(3) ADDRESS2
A7~A0
(4) DATA1
D15~D8
(5) DATA2
D7~D0
Two bytes of data may be written continuously for each address.
Note 74. The COMMAND determines the length of the data.
Coefficient RAM (CRAM, CRAM2, and CRAM & CRAM2 together)
Execute
SI
(1) COMMAND
A4h, A6h, ADh
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
Offset RAM (OFRAM, OFRAM2, and OFRAM & OFRAM2 together)
Execute
SI
(1) COMMAND
A2h, ACh, AEh
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
Note 75. The COMMAND determines the length of the data. If the written data exceeds the allotted amount, the
excess data is ignored.
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6-4. Read Operation during DSP Reset
Program RAM (PRAM, PRAM2) Read (during DSP Reset)
SI
SO
(1) COMMAND
38h, 3Ah
(2) ADDRESS1
0 0 0 0 0 A10 A9 A8
(3) ADDRESS2
A7 ~ A0
(4) DATA1
0 0 0 0 D35 D34 D33 D32
(5) DATA2
D31~D24
(6) DATA3
D23~D16
(7) DATA4
D15~D8
(8) DATA5
D7~D0
Five bytes of data may be read continuously for each address.
Coefficient RAM (CRAM, CRAM2) Read (during DSP Reset)
SI
SO
(1) COMMAND
34h, 36h
(2) ADDRESS1
0 0 0 0 0 A10 A9 A8
(3) ADDRESS2
A7~A0
(4) DATA1
D15~D8
(5) DATA2
D7~D0
Two bytes of data may be read continuously for each address.
Offset RAM (OFRAM, OFRAM2) Read (during DSP Reset)
SI
SO
(1) COMMAND
32h, 3Ch
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 A5 A4 A3 A2 A1 A0
(4) DATA1
0 0 0 D12 D11 D10 D9 D8
(5) DATA2
D7~D0
Two bytes of data may be read continuously for each address.
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6-5. Read Operation during DSP Reset and RUN
Control Register Reading (during DSP Reset and RUN)
SI
(1) COMMAND
40h~4Fh, 50h~56h
(2) DATA
Device Identification (during DSP Reset and RUN)
SI
(1) COMMAND
60h
(2) DATA
CRC Result Reading (during DSP Reset and RUN)
SI
(1) COMMAND
72h
(2) DATA
(3) DATA
SO
D7~D0
SO
D7
1
D5
0
8
D4
0
D3
0
D2
0
2
D1
1
D0
0
SO
D15~D8
D7~D0
Error Status Reading (during DSP Reset and RUN)
SI
SO
(1) COMMAND
70h, 71h
(2) DATA
D7
CRCERRN
D6
0
D6
D5
D4
WDTERRN
GPO0
GPO1
D3
0
D2
0
D1
0
D0
0
6-6. Read Operation during RUN
CRAM, CRAM2 / OFRAM, OFRAM2 Write Preparation Reading (during RUN)
SI
SO
(1) COMMAND
24h, 26h
(2) ADDRESS1
A15~A8
(3) ADDRESS2
A8~A0
(4) DATA1
D15~D8
(5) DATA2
D7~D0
MIR1/2 Reading (during RUN)
SI
SO
(1) COMMAND
76h (DSP1 MICR Read)
78h (DSP1 MIR2 Read)
77h (DSP2 MICR Read)
79h (DSP2 MIR2 Read)
(2) DATA1
D27~D20
(3) DATA2
D19~D12
(4) DATA3
D11~D4
(5) DATA4
D3 D2 D1 D0 (flag) (flag) (flag) (flag)
Note 76. Data is valid only when all flags are zero. The data is ignored when all flag bit is “1”.
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7. Timing
7-1. RAM Writing Timing during Reset
Write to Program RAM (PRAM, PRAM2), Coefficient RAM (CRAM, CRAM2) and Offset RAM (OFRAM,
OFRAM2) during System Reset in the order of Command code, Address and Data. When writing Data to consecutive
address locations, continue to input data only. When writing data at separated address locations, set RQN pin to “L” from
“H” and then input command code, address and data in this order. Writing to PRAM at separated address locations is not
possible.
PDSPRSTN
(Control Register Setting is omitted)
RQN
SCLK
SI
don’tcare
(L/H)
Command
Address
DATA
DATA
DATA
DATA
DATA
don’tcare
(L/H)
DATA
don’tcare
(L/H)
RDY = “H”
Figure 34. Writing to RAM at Consecutive Address Locations
PDSPRSTN
(Control Register Setting is Omitted)
RQN
SCLK
SI
don’tcare
(L/H)
Command
Address DATA
don’tcare
(L/H)
Command
Address
RDY = “H”
Figure 35. Writing to RAM at Separated Address Location
7-2. RAM Writing Timing during RUN
Use this operation to rewrite Coefficient RAM (CRAM, CRAM2) and Offset RAM (OFRAM, OFRAM2) during
RUN.
1) Write Preparation
After inputting the assigned command code (8-bit) to select the number of data from 1 to 16, input the start address of
data writing (16-bit) and the data in this order.
2) Write Preparation Data Confirmation
After write preparation, the write data can be confirmed. Address and Data are read in this order by write preparation
data confirmation command “24h” or “26h”. The data will be “0001h” when reading more than write preparation
data. Execute write preparation again when the address and data are garbled by external noise.
3) Write Execution
Upon completion of this operation, execute RAM write during RUN by inputting the corresponding command code
and address (16-bit all 0) in this order.
Note 77. Execute Write preparation before a write execution. When writing to RAM without write preparation
sequence, a malfunction occurs. Access operation by microcontroller is prohibited until RDY changes to
“H”.
Write modification of RAM contents is executed whenever the RAM address for modification is assigned. For
example, when 5 Data are written, from RAM address “10”, it is executed as shown below.
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RAM execution address
7
8
9
Write execution position
10
↓
○
11
↓
○
13
16
11
12
↓
○
↑
13
↓
○
14
↓
○
15
Note: Address “13” is not executed until rewriting address “12”.
PDSPRSTN= “H”
RQN
E.g. when # of DATA is 4
SCLK
SI
CRAM,OFRAM Command 83h
CRAM2,OFRAM2 Command 93h
don’tcare
(L/H)
Command
RDY = “H”
Address
DATA
DATA
DATA
don’tcare
(L/H)
DATA
CRAM,OFRAM 80h(# of DATA: 1) ~ 8Fh(# of DATA: 16)
CRAM2,OFRAM2
90h(# of DATA: 1) ~ 9Fh(# of DATA: 16)
Figure 36. CRAM, OFAM Write Preparation
PDSPRSTN=H
RQN
SCLK
SI
don’tcare
(L/H)
24h, 26h
INVALID
SO
don’tcare
(L/H)
Address DATA
DATA
DATA
DATA
Hi-Z
RDY=H
Figure 37. CRAM, OFRAM Write Preparation
PDSPRSTN= “H”
RQN
SCLK
SI
don’tcare
(L/H)
RDY
Command
00000000
00000000
don’tcare
(L/H)
max 400ns
CRAM A4h, OFRAM A2h
CRAM2 A6h, OFRAM2 ACh
RDYLG (Note 78)
Note 78. When internal write is finished, RDY changes to high, and it cannot be accessed from the microcontroller. While
the RQN pin is “L” level, the RDY signal remains at a “L” level.
Figure 38. CRAM, OFRAM Write
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7-3. External Conditional Jump
External Conditional Jump Code Writing (during DSP and RUN)
(1) COMMAND
F4h, F5h, F6h
(2) DATA
D7~D0
External Conditional Jump code can be input during both DSP Reset and RUN. Input data is set to the designated
register on the rising edge of LRCLK (LRCLKI, LRCLKO). The RDY pin changes to “L” when the command code is
transferred, and it changes to “H” when write operations are completed. When any single bit of “1” data in 8-bit
External Jump code matches an “1” bit data in the IFCON field, a Jump instruction is executed. Then, the RDY pin
changes to “H” when the rise of LRCLKO is captured. Access operation by microcontroller is prohibited until the
RDY pin changes to “H”. IFCON field is the area where the external conditions are written. This Jump code is reset to
00h by setting the INITRSTN pin to “L”, but it is not reset by System Reset.
(F4h: DSP1, F5h: DSP2, F6h: Both DSP1 and 2)
7
■
4
3
2
1
0
■ ■ ■
■
■
↑
Check if “1” of IFCON field corresponds with External Condition Jump Code including Jump pins by at least
one at the same location.
16
↓
9
IFCON Field
♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦
External Conditional Jump Code
6
■
5
■
PDSPRSTN (Control Register Setting is Omitted)
SCLK
don’tcare
(L/H)
SI
F4h
D7… D0
don’tcare
(L/H)
Lch
RQN
Rch
LRCLK
RDY
Figure 39. External Conditional Jump Code Writing Timing (in DSP Reset, JX write example of DSP1)
PDSPRSTN = “H”
SCLK
SI
don’tcare
(L/H)
F4h
D7 …. D0
don’tcare
(L/H)
RQN
L ch
R ch
LRCLK
RDY
Figure 40. External Conditional Jump Code Writing Timing (RUN, JX wrote example of DSP1)
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7-4. RAM Reading Timing during DSP Reset
Read Program RAM (PRAM), Coefficient RAM (CRAM) and Offset REG (OFREG) during DSP reset in the order
of input Command code and Address. PRAM address is fixed to 0h. After writing the Command, the data comes out
from the SO pin synchronous with falling edge of SCLK. (The SI pin input data is “Don’t care”) When reading Data
at consecutive address locations, continue to input SCLK as is.
PDSPRSTN
RQN
SCLK
don’tcare
(L/H)
SI
SO
HI-Z
Command
don’tcare
(L/H)
Address
DATA
Echo-back Output
DATA
DATA
DATA
DATA
HI-Z
RDY
Figure 41. RAM Reading at Consecutive Address
7-5. RAM Reading during DSP Reset and RUN
Read control registers, device identification codes, error statuses and CRC results during RUN or DSP Reset state.
These codes are input in the order of Command and Address.
After completing Command code write, the data comes out from the SO pin synchronous with falling edge of
SCLK. (The SI pin input data is “Don’t care”)
PDSPRSTN
RQN
SCLK
SI
don’tcare
(L/H)
SO
HI-Z
Command
Address
don’tcare
(L/H)
Echo-back Output
DATA
HI-Z
RDY
Figure 42. RAM Reading during DSP Reset
PDSPRSTN=H
RQN
SCLK
SI
SO
don’tcare
(L/H)
HI-Z
Command
Address
don’tcare
(L/H)
DATA
Echo-back Output
HI-Z
RDY
Figure 43. RAM Reading during RUN
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■ I2C Bus Interface (I2CSEL pin= “H”)
I2C BUS mode (including 400kHz FAST mode) is enabled when the I2CSEL pin = “H”. (3.4MHz Hs-mode is not
supported)
1. Data Transfer
In order to access any IC devices on the I2C BUS, input a start condition first, followed by a single slave address that
includes the device address. IC devices on the BUS compare this slave address with their own addresses and the IC device
that has an identical address with the slave-address generates an acknowledgement. An IC device with the identical
address then executes either a read or write operation. After the command execution, input a Stop condition.
1-1. Data Change
Change the data on the SDA line while the SCL line is “L”. SDA line condition must be stable and fixed while the clock
is “H”. Change the Data line condition between “H” and “L” only when the clock signal on the SCL line is “L”. Change
the SDA line condition while SCL line is “H” only when the start condition or stop condition is input.
SCL
SDA
DATA LINE
STABLE:
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 44. Data Change
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1-2. Start Condition and Stop Condition
A start condition is generated by the transition of “H” to “L” on the SDA line while the SCL line is “H”. All instructions
are initiated by a Start condition. A stop condition is generated by the transition of “L” to “H” on the SDA line while the
SCL line is “H”. All instructions end by a Stop condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 45. Start Condition and Stop Condition
1-3. Repeated Start Condition
When a Start condition is received again instead of a Stop condition, the bus changes to a Repeated Start condition. A
Repeated Start condition is functionally the same as a Start condition.
SCL
SDA
START CONDITION
Repeated Start CONDITION
Figure 46. Repeated Start Condition
1-4. Acknowledge
An external device that is sending data to the AK7782 releases the SDA line (“H”) after receiving one byte of data. An
external device that receives data from the AK7782 then sets the SDA line to “L” at the next clock. This operation is
called “acknowledgement”, and it enables verification that the data transfer has been properly executed. The AK7782
generates an acknowledgement upon receipt of a Start condition and a Slave address. For a write instruction, an
acknowledgement is generated whenever receipt of each byte is completed. For a read instruction, succeeded by
generation of an acknowledgement, the AK7782 releases the SDA line after outputting data at the designated address, and
it monitors the SDA line condition. When the Master side generates an acknowledgement without sending a Stop
condition, the AK7782 outputs data at the next address location. When no acknowledgement is generated, the AK7782
ends data output (not acknowledged).
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Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
not acknowledge
acknowledge
START
CONDITION
Figure 47. Generation of Acknowledgement
1-5. The First Byte
The First Byte, which includes the Slave-address, is input after the Start condition is set, and a target IC device that will be
accessed on the bus is selected by the Slave-address. The Slave-address is configured with the upper 7-bits. Data of the
upper 5-bits is “00110”. The next 2 bits are the address bits that select the desired IC, which are set by the CAD1 and
CAD0 pins. When the Slave-address is inputted, an external device that has the identical device address generates an
acknowledgement and instructions are then executed. The 8th bit of the First Byte (lowest bit) is allocated as the R/W Bit.
When the R/W Bit is “1”, the read instruction is executed, and when it is “0”, the write instruction is executed.
Note 79. In this document, there is a case that describes a “Write Slave-address assignment” when both address bits match
and a Slave-address at R/W Bit = “0” is received. There is a case that describes a “Read Slave-address
assignment” when both address bits match and a Slave-address at R/W Bit = “1” is received.
0
0
1
1
0
CAD1
CAD0
R/W
(CAD1, CAD0 are set by pins)
Figure 48. First Byte Configuration
1-6. The Second and Succeeding Bytes
The data format of the second and succeeding bytes of the AK7782 Transfer / Receive Serial data (command code,
address and data in microcontroller interface format) on the I2C BUS are all configured with a multiple of 8-bits. When
transferring or receiving those data on the I2C BUS, they are divided into an 8-bit data stream segment and they are
transferred / received with the MSB side data first with an acknowledgement in-between.
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Example)
When transferring / receiving A1B2C3 (hex) 24-bit serial data in microprocessor interface format:
2
(1) Microcomputer interface Format
A1
B2
(1)I C Format
C3
A1
B2
A
24BIT
8BIT
C3
A
8BIT
8BIT
A …Acknowledge
Figure 49. Division of Data
Note 80. In this document, there is a case that describes a write instruction command code, which is received at the second
byte as “Write Command”. There is a case that describes a read instruction command code, which is received at
the second byte as “Read Command”.
2. Write Sequence
In the AK7782, when a “Write-Slave-address assignment” is received at the first byte, the write command at the second
byte and data at the third and succeeding bytes are received. At the data block, address and write data are received in a
single-byte unit each in accordance with a command code. The number of write data bytes (*1 in Figure 50) is fixed by the
received command code.
Usable command codes in write sequence are listed below as “(Table 1) List of Usable Command Codes in Write
Sequence”.
S
SLAD
W
A
Cmd
A
Data
A
Stp
repeat N times (*1)
Figure 50. Write Sequence
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Command
Code
80h~8Fh
Address
Data Length
2byte
2byte × n
A2h
A4h
B2h
B4h
B8h
F4h
90h~9Fh
2byte
2byte
2byte
2byte
2byte
None
2byte
None
None
2byte × n
2byte × n
5byte × n
1byte
2byte × n
ACh
A6h
BCh
B6h
BAh
F5h
10h~1Fh
2byte
2byte
2byte
2byte
2byte
None
2byte
None
None
2byte × n
2byte × n
5byte × n
1byte
2byte × n
AEh
2byte
None
ADh
BEh
BDh
BFh
F6h
C0h~CFh
2byte
2byte
2byte
2byte
None
None
None
2byte × n
2byte × n
5byte × n
1byte
1byte
Content
Write preparation while CRAM/OFRAM is running.
BIT3 ~ BIT0 of the command code assign # of write operation (0x80:1,
0x81:2,…, 0x8F: 16).
Write operation exceeding the assigned # of write, abandons the data.
Write execution while OFRAM is running; Address is ignored
Write execution while CRAM is running; Address is ignored
OFRAM Write (during DSP Reset)
CRAM Write (during DSP Reset)
PRAM Write (during DSP Reset)
DSP1 JX Write
Write preparation while CRAM2/OFRAM2 is running.
BIT3 ~ BIT0 of the command code assign # of write operation (0x90:1,
0x91:2,…, 0x9F: 16).
Write operation exceeding the assigned # of write, abandons the data.
Write execution while OFRAM2 is running; Address is ignored
Write execution while CRAM2 is running; Address is ignored
OFRAM2 Write (during DSP Reset)
CRAM2 Write (during DSP Reset)
PRAM2 Write (during DSP Reset)
DSP2 JX Writing
Write preparation while CRAM&CRAM2/OFRAM&OFRAM2 is running.
BIT3 ~ BIT0 of the command code assign # of write operation (0x10:1,
0x11:2,…, 0x1F: 16).
Write operation exceeding the assigned # of write, abandons the data.
Write execution while OFRAM & OFRAM2 are running; Address is
ignored.
Write execution while CRAM & CRAM2 are running; Address is ignored.
OFRAM & OFRAM2 Write (during DSP Reset)
CRAM & CRAM2 Write (during DSP Reset)
PRAM & PRAM2 Write (during DSP Reset)
DSP1 & DSP2 JX Write
Registers 00h~0Fh Write
(Write operation may be limited depending on register settings during RUN)
D0h~D6h
None
1byte
Registers 10h~16h Write
F2h
None
1byte
CRC Write
Note 81. Length of write data is variable with the areas to be written. When accessing RAM for writing, it is possible to
write data at sequential address locations by writing data continuously. Do not write a command code other than
shown above.
Table 1. List of Usable Command Codes in Write Sequence
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3. Read Sequence
In the AK7782, when a “write- slave-address assignment” is received at the first byte, the read command at the second
byte and the data at the third and succeeding bytes are received. At the data block, the address is received in a single byte
unit in accordance with a read command code. In a command code without address assignment, the sequence does not
have to be repeated (*2 in Figure 51).
When the last address byte (or command code if no address assignment is specified) is received and an acknowledgement
is transferred, the read command waits for the next restart condition. When a “read slave-address assignment” is received
at the first byte, data is transferred at the second and succeeding bytes. The number of readable data bytes (*3 in Figure
51) is fixed by the received read command.
After reading the last byte, assure that a “not acknowledged” signal is received. If this “not acknowledged” signal is not
received, the AK7782 continues to send data regardless whether data is present or not, and since it did not release the
BUS, the stop condition cannot be properly received.
Usable command codes in read sequence are listed in Table 2: List of Usable Read Command Codes in Read Sequence.
S
SLAD
W A
Cmd
A
Data
A
rS
SLAD
Repeat N times (*2)
R A
Data
A
Data
Na Stp
Repeat N-1 times (*3)
Figure 51. Read Sequence
Command
Code
Address
24h
32h
34h
38h
70h
76h
None
2byte
2byte
2byte
None
None
Data Length
Content
2byte × n
2byte × n
2byte × n
5byte × n
1byte
4byte
CRAM/OFRAM Write Preparation Data Read (during RUN)
OFRAM Read (during DSP Reset)
CRAM Read (during DSP Reset)
PRAM Read (during DSP Reset)
DSP1 Error Status Read
MIR1 Read @DSP1
28-bit data is upper-bit-justified. Lower 4-bits are for validity flags.
Valid at 0000.
78h
None
4byte
MIR2 Read @DSP1
28-bit data is upper-bit-justified. Lower 4-bits are for validity flags.
Valid at 0000.
26h
None
2byte × n
CRAM2/OFRAM2 Write Preparation Data Read (during RUN)
3Ch
2byte
2byte × n
OFRAM2 Read (during DSP Reset)
36h
2byte
2byte × n
CRAM2 Read (during DSP Reset)
3Ah
2byte
5byte × n
PRAM2 Read (during DSP Reset)
71h
None
1byte
DSP2 Error Status Read
77h
None
4byte
MIR1 Read @DSP2
28-bit data is upper-bit-justified. Lower 4-bits are for validity flags.
Valid at 0000.
79h
None
4byte
MIR2 Read @DSP2
28-bit data is upper-bit-justified. Lower 4-bits are for validity flags.
Valid at 0000.
40h~4Fh
None
1byte
Registers 00h~0Fh Read
50h~56h
None
1byte
Registers 10h~16h Read
60h
None
1byte
Device Identification
72h
None
2byte
CRC result Read
Note 82. Length of read data is variable with the areas to be read. When accessing RAM for reading, it is possible to read
data at sequential address locations by reading data continuously.
Note 83. Do not read a command code other than shown above.
Table 2. List of Usable Read Command Codes in Read Sequence
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4. Not Acknowledged
4-1. Slave address receiving when the RDY pin is Low
The AK7782 does not accept command codes until the RDY pin is set to a high level, when a command is
received to set the RDY pin to a low level. In order to confirm the RDY pin condition, a “Write Slave-Address
assignment” should be sent after the Start condition. If the RDY pin is then at a low level, “Acknowledgement”
is not generated at the succeeding clock (generation of “Not Acknowledged”). After sending “Not
Acknowledged”, the BUS is released and all receiving data are ignored until the next start condition (behaves as
if it received a Slave address of other device).
Refer to (3) and (4) of Figure 52 “RDY Pin Condition and Acknowledgement”.
(1) After Slave-address
(2) While RDY is Low, “Not
(3) “Not Acknowledged” is
(4) “Acknowledgement” is
matching is confirmed, RDY
Acknowledged” is generated
generated as RDY is already
generated as RDY is already
condition is ignored
after receiving Slave-address
“L” at the Receive Start point
“H” at the Receive Start point
of Slave-address
of Slave-address
…
Data
A
Stp
S
SLAD
W Na …
S
SLAD
W Na …
S
SLAD
W
A
…
RDY
Figure 52. RDY pin Condition and Acknowledgement
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4-2. When Read Slave-address assignment is received without receiving Read command code
Data read in the AK7782 can be made only in the previously documented Read sequence. Data cannot be read out
without receiving a read command code. In the AK7782, a “Not Acknowledged” is generated when a “Read
Slave-address Assignment” without proper receipt of read command is received. Under this condition, which
occurs when RDY pin shifts from low level to high level after a “Write Slave-address assignment” in the read
sequence and before a “Read Slave-address assignment” (Note 84), “Not Acknowledged” is generated in return.
Note 84. This condition may be avoided by assigning a read Slave-address only when the acknowledgement is
confirmed, by utilizing the acknowledge-polling feature.
Slave-address writing assignment
I2C bus
S
SLAD
W Na
Cmd
Slave-address reading assignment
Na
xxx
Na
rS
SLAD
R Na
Read command code is not
received
Repeated N times
RDY
Without receiving read command and code, “Not
Acknowledged” is transmitted even when “Read
Slave-address assignment” is received at RDY= “H”
Figure 53. Read Slave-Address Assignment without Receiving Read Command Code
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[AK7782]
Limitation in use of I2C Interface
The I2C Interface does not support the following features:
(1) No operation in Hs mode (max: 3.4MHz)
(Supports FAST mode (max: 400kHz)
(2) Echo-Back function in Microcontroller Interface Format
(3) Error Status Read
Note 85. Do not turn off the power of the AK7782 during the power supplies of surrounding devices are turned on. The
pull-up of SDA and SCL of I2C BUS must not exceed DVDD. (The diode exists for DVDD in the SDA and SCL
pins.)
Note 86. The meaning of symbols in I2C format in Figure 50 ~ Figure 53.
SLAD
…Slave Address (7 bits)
Cmd
…Command Code (8 bits)
S
…Start Condition
rS
…Repeated Start Condition
Stp
…Stop Condition
W
…R / W bit, the lowest bit of the first byte is at write (= 0) condition, Write (1 bit)
R
…R / W bit, the lowest bit of the first byte is at read (= 1) condition, Read (1 bit)
A
…Acknowledge (1 bit)
Na
…Not Acknowledge (1 bit)
(Gray)
… (Gray) where it is controlled by Master device.
(White)
… (White) where it is controlled by Slave device. It is done by the AK7782
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[AK7782]
■ ADC Block
1. ADC High-pass Filter
The AK7782 ADC has digital High Pass Filter (HPF) for DC offset cancellation. The cut-off frequency of the HPF is
approximately 1Hz (at fs=48kHz). This cut-off frequency is shown below.
Sampling frequency (fs)
96kHz
48kHz
44.1kHz
32kHz
8kHz
Cut-off frequency
1.86Hz
0.93Hz
0.86Hz
0.62Hz
0.16Hz
2. ADCM Digital Volume (VOL)
The ADCM output port has a digital volume control. After setting the control register, the output level changes in
2LRCLK cycle (max) after the rising edge of the RQN. This function does not have neither soft transition nor zero
crossing detection. Click noise must be muted externally when changing the volume during an operation.
When writing to theVOL5-0 bits continuously, the control register should be written with an interval more than 2LRCLK
cycles from the rising edge of RQN. This volume setting is initialized by initial reset but it is not initialized by system
reset.
VOL mode VOL[5] VOL[4] VOL[3] VOL[2] VOL[1] VOL[0] Volume (dB)
00
0
0
0
0
0
0
0
(default)
01
0
0
0
0
0
1
-2
03
0
0
0
0
1
1
-4
04
0
0
0
1
0
0
-6
05
0
0
0
1
0
1
-8
07
0
0
0
1
1
1
-10
08
0
0
1
0
0
0
-12
09
0
0
1
0
0
1
-14
0B
0
0
1
0
1
1
-16
0C
0
0
1
1
0
0
-18
0D
0
0
1
1
0
1
-20
0F
0
0
1
1
1
1
-22
10
0
1
0
0
0
0
-24
11
0
1
0
0
0
1
-26
13
0
1
0
0
1
1
-28
14
0
1
0
1
0
0
-30
15
0
1
0
1
0
1
-32
17
0
1
0
1
1
1
-34
18
0
1
1
0
0
0
-36
19
0
1
1
0
0
1
-38
1B
0
1
1
0
1
1
-40
1C
0
1
1
1
0
0
-42
1D
0
1
1
1
0
1
-44
1F
0
1
1
1
1
1
-46
20
1
0
0
0
0
0
-48
21
1
0
0
0
0
1
-50
23
1
0
0
0
1
1
-52
24
1
0
0
1
0
0
-54
25
1
0
0
1
0
1
-56
27
1
0
0
1
1
1
-58
28
1
0
1
0
0
0
-60
3C-3F
1
1
1
1
-∞
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[AK7782]
3. ADCM MUX
The ADCM volume setting output and DSP serial data output can be mixed by the MUX circuit. MSEL[1:0] bits select
the DSP serial data from DSP1 SDOUT1, DSP1 SDOUT5, DSP2 SDOUT1 and DSP2 SDOUT5. L or R channel can be
selected by MUX[1:0] bits. The path is changed in 2LRCLK cycles (max) after the rising edge of RQN when control
register settings are changed. Click noise should be muted externally or 00000h Data should be output for 4LRCLK cycles
when changing the MUX mode during an operation. The MUX mode setting is initialized by initial reset but it is not
initialized by system reset.
MUX Mode
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MSEL[1:0]
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
MUX[1:0]
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
L channel Output
DSP1 SDOUT1 Lch
DSP1 SDOUT1 Lch
ADCM
ADCM
DSP1 SDOUT5 Lch
DSP1 SDOUT5 Lch
ADCM
ADCM
DSP2 SDOUT1 Lch
DSP2 SDOUT1 Lch
ADCM
ADCM
DSP2 SDOUT5 Lch
DSP2 SDOUT5 Lch
ADCM
ADCM
R channel Output
DSP1 SDOUT1 Rch
ADCM
DSP1 SDOUT1 Rch
ADCM
DSP1 SDOUT5 Rch
ADCM
DSP1 SDOUT5 Rch
ADCM
DSP2 SDOUT1 Rch
ADCM
DSP2 SDOUT1 Rch
ADCM
DSP2 SDOUT5 Rch
ADCM
DSP2 SDOUT5 Rch
ADCM
4. ADCM VOL + MUX Delay Time
The delay time from ADCM serial output to SDOUT1, SDOUT2 and SDOUTA1 pins through VOL + MUX is 1Ts (1/fs).
The delay time from DSP1 SDOUT1, DSP1 SDOUT5, DSP2 SDOUT1 or DSP2 SDOUT5 serial output to SDOUT1,
SDOUT2 and SDOUTA1 pins through MUX is also 1Ts (1/fs). Set an 1Ts (1/fs) delay to the output timing of DSP
SDOUT by a program when synchronizing the output of SDOUT1, SDOUT2 and SDOUTA1 pins with the output of
other SDOUT pins.
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[AK7782]
■ SRC
1. General Description
1-1. Sampling Rate
The AK7782 includes a stereo digital sampling rate converter (SRC). The input sampling rate is supported from
7.35kHz to 96kHz (FSI). The output sampling frequency (FSO) is 7.35kHz ~ 96kHz. When sampling rate ratio
FSO/FSI is more than 1, the output sampling rate is converted to 7.35kHz ~ 96kHz. Available sampling rate ratio
FSO/FSI = 0.167~6.0.
(1) Up Sampling (0.98 ≤ FSO/FSI ≤ 6.00)
Following sampling rates are supported.
FSO
FSI
FSO/FSI
Pass Band
96kHz
96kHz
1.00
44.00kHz
96kHz
88.2kHz
1.09
40.42kHz
96kHz
48kHz
2.00
22.00kHz
96kHz
44.1kHz
2.18
20.21kHz
88.2kHz
88.2kHz
1.00
40.42kHz
88.2kHz
48kHz
1.84
22.00kHz
88.2kHz
44.1kHz
2.00
20.21kHz
48kHz
48kHz
1.00
22.00kHz
48kHz
44.1kHz
1.09
20.21kHz
48kHz
32kHz
1.50
14.67kHz
48kHz
24kHz
2.00
11.00kHz
48kHz
16kHz
3.00
7.33kHz
48kHz
12kHz
4.00
5.50kHz
48kHz
8kHz
6.00
3.67kHz
44.1kHz
44.1kHz
1.00
20.21kHz
44.1kHz
32kHz
1.38
14.67kHz
44.1kHz
24kHz
1.84
11.00kHz
44.1kHz
16kHz
2.76
7.33kHz
44.1kHz
12kHz
3.68
5.50kHz
44.1kHz
8kHz
5.51
3.67kHz
Stop Band
52.00kHz
47.78kHz
26.00kHz
23.89kHz
47.78kHz
26.00kHz
23.89kHz
26.00kHz
23.89kHz
17.33kHz
13.00kHz
8.67kHz
6.50kHz
4.33kHz
23.89kHz
17.33kHz
13.00kHz
8.67kHz
6.50kHz
4.33kHz
(2) Down Sampling (0.167 ≤ FSO/FSI < 0.99)
Supported sampling ratios (FSO/FSI) are 0.92, 0.54, 0.50, 0.46, 0.25, 0.181 and 0.167.
FSO
FSI
FSO/FSI
Pass Band
Stop Band
44.1kHz 48kHz
0.92
20.00kHz
24.10kHz
48kHz 88.2kHz
0.54
19.25kHz
26.23kHz
48kHz
96kHz
0.50
20.90kHz
27.00kHz
44.1kHz 88.2kHz
0.50
19.20kHz
24.81kHz
16kHz
32kHz
0.50
6.97kHz
9.00kHz
8kHz
16kHz
0.50
2.48kHz
4.50kHz
44.1kHz 96kHz
0.46
18.70kHz
25.00kHz
8kHz
32kHz
0.25
2.93kHz
3.98kHz
8kHz
48kHz
0.167
4.40kHz
6.50kHz
8kHz
44.1KHz
0.181
4.04kHz
5.97kHz
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[AK7782]
1-2. SRC Input/Output Interfaces
(1) Input Interface Format
The SDIN1 pin is for SRC1 input (SRC1I). The SDIN5 pin, SDIN1 pin, internal node P1SDOUT1, and
P2SDOUT1 are for SRC2 input (SRC2I) (Figure 1). The input interface format is set by control registers
CONT13 and CONT14. These registers should be set during system reset. This audio interface supports MSB
first, 2’s complement data format.
CONT13, CONT14
1. D7: BIEDGE SRC BICK Select
0: Falling edged of SRCLRCKI
SRCLRCKI
tBCLK
SF
SRCBICKI
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
1: Rising edged of SRCLRCKI
SRCLRCKI
tBCLK
SF
SRCBICKI
63 62 61 60 59
2.
3.
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
D6, D5, D4: IDIF[2:0] SRC Input Interface Select
fsi: SRC input sampling rate
IDIF Mode
IDIF[2]
IDIF[1] IDIF[0] Input Format
0
0
0
0
LSB 16bit
1
0
0
1
LSB 20bit
2
0
1
0
MSB 24/20bit
3
0
1
1
I2S Compatible 24/16bit
4
1
0
0
LSB 24bit
5
1
0
1
N/A
6
1
1
0
PCM SHORT(24bit)
7
1
1
1
PCM LONG(24bit)
10 9 8 7 6 5 4 3 2 1 0
SRC BICK
≥ 32fsi
≥ 40fsi
≥ 48fsi
≥ 48fsi or 32fsi
≥ 48fsi
BIFS[1:0] Setting
BIFS[1:0] Setting
D3, D2: BIFS[1:0] SRCBICKI Select
BIFS Mode
BIFS[1]
BIFS[0]
SRCBICKI
0
0
0
32fsi
1
0
1
64fsi
2
1
0
128fsi
3
1
1
48fsi
Note 87. This setting is necessary when operating in IDIF mode 6 or 7.
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[AK7782]
Left ch
SRCLRCKI
Right ch
SRCBICKI
31 30
SRC1I,SRC2I
IDIF Mode 4
SRC1I,SRC2I
IDIF Mode 1
SRC1I,SRC2I
IDIF Mode 0
23 22 21 20 19 18 17 16 15 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
Don’t care M 22 21 20 19 18 17 16 15 14
1 L Don’t care M 22 21 20 19 18 17 16 15 14
1 L
Don’t care
M 18 17 16 15 14
1 L Don’t care
M 18 17 16 15 14
1 L
Don’t care
M 14
1 L Don’t care
M 14
1 L
M:MSB,L:LSB
Figure 54. IDIF Mode 0, 1, 4 @BIEDGE=0, SRCBICKI 64fs
Left ch
SRCLRCKI
Right ch
SRCBICKI
SRC1I,SRC2I
IDIF Mode 2
31 30 29 28 27
M 22 2120 19
10 9 8 7 6 5 4 3 2 1
2 1 L
0 31 30 29 28 27
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
2 1 L
M:MSB,L:LSB
Figure 55. IDIF Mode 2 @BIEDGE=0, SRCBICKI 64fs
Left ch
SRCLRCKI
Right ch
SRCBICKI
SRC1I,SRC2I
IDIF Mode 2
23 22 21 20 19 18 17 16 23 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0
M 22 21 20 19 18 17 16 7 6 5 4 3 2 1 L M 22 21 20 19 18 17 16 7 6 5 4 3 2 1 L
M:MSB
L:LSB
Figure 56. IDIF Mode 2 @BIEDGE=0, SRCBICKI 48fs
Left ch
SRCLRCKI
Right ch
SRCBICKI
SRC1I,SRC2I
IDIF Mode 3
31 30 29 28 27
M 22 21 20
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
3 2 1 L
M 22 21 20
10 9 8 7 6 5 4 3 2 1 0
3 2 1 L
M:MSB,L:LSB
Figure 57. IDIF Mode 3 @BIEDGE=0, SRCBICI 64fs
SRCLRCKI
tBCLK
SF
SRCBICKI
SRC1I,SRC2I
IDIF Mode 6
63 62 61 60 59
M 22 21 20 19
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
2 1 L L ch
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
2 1 L
R ch
tBCLK x 32
Figure 58. IDIF Mode 6 @BIEDGE=1, BIFS[1:0]=1h
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[AK7782]
tBCLK
SF
SRCLRCKI
SRCBICKI
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRC1I,SRC2I
IDIF Mode 6
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L
Lch
tBCLK x 16
M:MSB
L:LSB
R ch
Figure 59. IDIF Mode 6 @BIEDGE=1, BIFS[1:0]=0h
1 ≤ tBCLK ≤ 60
LF
SRCLRCKI
SRCBICKI
SRC1I,SRC2I
IDIF Mode 7
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
M 22 21 20 19
2 1 L
L ch
tBCLK
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
2 1 L
M:MSB,L:LSB
R ch
tBCLK x 32
Figure 60. IDIF Mode 7 @BIEDGE=1, BIFS[1:0]=1h
1 ≤ tBCLK ≤ 28
LF
tBCLK
SRCLRCKI
SRCBICKI
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRIN1-3
IDIF Mode 7
M:MSB
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L L:LSB
L ch
R ch
tBCLK x 16
Figure 61. IDIF Mode 7 @BIEDGE=1, BIFS[1:0]=0h
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[AK7782]
(2) Output Interface Format
The SRC output format is fixed to MSB justified 24-bit 2’s complement. The output data is synchronized with
internal clock LRCLKO and BITCLKO. I²S compatible format is available by setting a control register
CONT00 DIFI2S bit = “1”. Set DSP input format MSB justified when connecting the SRC output to the DSP.
Left ch
LRCKO
Right ch
BICKO
31 30 29 28 27
SRC1O,SRC2O
M 22 2120 19
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
2 1 L
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
2 1 L
M:MSB,L:LSB
Figure 62. CONT00 DIFI2S (D4) bit= “0”
Left ch
LRCKO
Right ch
BICKO
31 30 29 28 27
SRC1O,SRC2O
M 22 21 20
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
3 2 1 L
M 22 21 20
10 9 8 7 6 5 4 3 2 1 0
3 2 1 L
M:MSB,L:LSB
Figure 63. CONT00 DIFI2S (D4) bit= “1”
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[AK7782]
2. Soft Mute
2-1. Manual Mode
The soft mute operation is performed in the digital domain of the SRC output. When PSRCSMUTE pin is set to “H”, the
SRC output data are attenuated by −∞ in 1024 LRCLKO cycles. When the PSRCSMUTE pin is set to “L”, the mute is
cancelled and the output attenuation gradually changes to 0dB in 1024 LRCLKO cycles. If the soft mute is cancelled
before mute state, the attenuation is discontinued and returned to 0dB by the same cycles. The soft mute is effective for
changing the signal source. (SRC1 and SRC2 can be soft muted independently by RSRC1SMUTE and RSRC2SMUTE
bits)
SRCSMUTE
(PSRCSMUTE pin)
(RSRC*SMUTE bit)
0dB
Attenuation Level
at SRCOUT
-∞dB
(2)
(1)
(1)
Figure 64. Soft Mute Manual Mode
(1) The output data is attenuated to −∞ in 1024 LRCLKO cycles (1024/fso).
(2) If the soft mute is cancelled before attenuating to −∞, the attenuation is discontinued and returned to 0dB by the same
number of clock cycles.
2-2. Semi-Auto Mode
Soft mute semi-auto mode is enabled by setting SRC1SEMIAUTO or SRC2SEMIAUTO bit to “1”. The soft mute is
cancelled automatically after keeping the mute for 50ms or 200ms (@FSO=44.1kHz) by setting RSRCRSTN bit “0” →
“1” or PSRCRSTN pin “L” → “H”. If the PSRCSMUTE pin is “H”, soft mute is still ON even SRC reset is released. The
mute time varies according to SRC1AUTOSEL bit, SRC2AUTOSEL bit setting and FSO as shown below.
AUTOSEL register
0
1
Period
2205/fso×1
8820/fso×1
P S R C R S T N pin
R S R C R S T N b it
P S R C S M U T E p in
R S R C 1S M U T E b it
R S R C 2S M U T E b it
FSO=44.1kHz
50ms
200ms
FSO=48kHz
46ms
184ms
FSO=88.2kHz
25ms
100ms
FSO=96kHz
23ms
92ms
“L ” or “0 ”
D on ’t C ar e
“L ” o r “0 ”
(1 )
0d B
A tte n u ation
220 5/fso
-∞
(2 )
GD
SRCO
(S R C 1 O , S R C 2O )
Figure 65. Soft Mute Semi-Auto Mode
(1) The output attenuation level returns to 0dB in 1024LRCKO cycles (1024/fso).
(2) The digital output corresponding to the digital input has group delay (GD).
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[AK7782]
3. SRC System Reset
Bringing the PSRCRSTN pin = “L” resets both SRC1 and SRC2, and initializes the digital filters. When the PSRCRSTN
pin = “L”, output of the SRCOUT pin is “L”. The PSRCRSTN pin must be “L” upon power-up the AK7782. The SRC
outputs the data within 50ms by releasing the SRC reset after the clock is input. Until then, the SRCO outputs “L”. Before
releasing the SRC system reset, the SRC setting should be completed.
Case 1
External clocks
(Input port)
Don’t care
Input Clocks 1
Input Clocks 2
Don’t care
SRCnI (n=1, 2)
Don’t care
Input Data 1
Input Data 2
Don’t care
LRCKO
BICKO
(Output port)
Don’t care
Output Clocks 1
Output Clocks 2
Don’t care
SRCRST
< 50ms
(Internal state) Power-down
SRCnO (n=1, 2)
< 50ms
Normal
operation
PLL lock &
fs detection
“0” data
PLL lock &
fs detection
PD
Normal data
“0” data
Normal
operation
Power-down
Normal data
“0” data
SRCUNLOCK
Figure 66. System Reset 1
Case 2
External clocks
(Input port)
(No Clock)
SRCnI (n=1, 2)
External clocks
(Output port)
Input Clocks
Don’t care
(Don’t care)
Input Data
Don’t care
(Don’t care)
Output Clocks
Don’t care
SRCRST
(Internal state) Power-down
SRCnO (n=1, 2)
< 50ms
PLL Unlock
“0” data
PLL lock &
fs detection
Normal
operation
Power-down
Normal data
“0” data
SRCUNLOCK
Figure 67. System Reset 2
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[AK7782]
4. Clock Change
4-1. Internal Reset Function for Clock Change
The SRC block of the AK7782 executes an internal reset automatically when the in/output clock is stopped. Normal
data will be output within 50ms after the clock is restarted.
4-2. Clock Change Sequence
Clock change sequence is shown in Figure 68.
clocks
(input or output)
state 1
(unknown)
SRCRST
< 50ms(SETSRC=”L”)
(interlal state)
SRCnO (n=1, 2)
normal operation
Power
down
PLL locktime
& fs detection
normal operation
Note 86
normal data
SRCSMUTE
(Note87,recommended)
Att.Level
state 2
normal data
1024/fso
1024/fso
0dB
-∞dB
Figure 68. Clock Change Sequence
Note 88. The data on SRCO may cause a clicking noise. This click noise can be prevented by inputting “0” data to the
SRCI from GD before a SRC system reset. It makes the data on SRCO remain as “0”. (p55 )
Note 89. The click noise (Note 88) can be removed by SRC soft mute. Refer to p54 “CONT16: D7, D6”.
5. UNLOCK
SRC states are output from the STO pin when SRC1LOCKE and SRC2LOCKE bits = “1”. The STO pin outputs “H” if
the Ratio detection of the SRC is finished. If not, the STO pin outputs “L”. The STO pin also outputs “L” during SRC
reset (SRCRSTN bit = “0”) and when a clock over 96kHz is input to the SRCLRCK pin. SRC output is “L” when the STO
pin is “L”.
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[AK7782]
SYSTEM DESIGN
1. Typical Connection Diagrams
Digital +3.3V
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
10μ
9
CLOCK
CONTROL
15,16,17
Rd
12
20
29
49
56
DVDD x 6
69
I2CSEL
SDA
CKM[2:0]
STO
51
50
RQN
44
SI
45
SCLK
46
INITRSTN
40
PCKRSTN
41
PADRSTN
42
PDSPRSTN
43
AK7782
XTI
37
LRCLKI
36
BITCLKI
28
CLKO1
22
BITCLKO
21
LRCLKO
CLOCK
61
PSRCRSTN
TESTI1,2
NC
JX0
JUMP
NC
Analog Lch+
92
AINL+
Analog Lch-
91
AINL-
Analog Rch+
90
AINR+
89
AINR-
Analog RchAnalog Lch
83,81,79,94,96,98,100
Analog Rch
82,80,78,93,95,97,99
77
Analog Mono
C
R
1
73
10μ
3
PSRCSMUTE
SRCLRCK
SRCBICK
I/F
RESET
CONTROL
66
4,72
76
75
6
7
SRC
71
64
63
AINR2~AINR8
AINM
SDIN1
SDIN2~7
LFLT
SDOUTA1
AVDD
SDOUT1~7
62
32-35,59,60
53
23-27,54,55
Audio
I/F
VCOM
86
AVDD
0.1μ
10μ
0.1μ
84
10μ
SRC2BICK
Micom
0.1μ
Analog +3.3V
10μ
SRC2LRCK
AINL2~AINL8
52
SO
CL
11
“L”
65
RDY
XTO
CL
5
0.1μ
85
10,13,19,30,39,48,57,68
VSS1
AVDD
VREFL
VREFH
VSS2
VSS3
14
2,74,88
87
8,70
DVDD18 x 7
18
31
38
47
58
67
Digital +1.8V
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
10μ
Figure 69. Hardware Reset (I2CSEL pin= “L”)
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[AK7782]
Digital +3.3V
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
10μ
9
CLOCK
CONTROL
15,16,17
Rd
12
20
29
49
56
DVDD x 6
69
I2CSEL
STO
CKM[2:0]
11
51
SO
SDA
50
65
CAD1
44
CAD0
45
SCL
46
INITRSTN
40
PCKRSTN
41
PADRSTN
42
XTO
AK7782
XTI
37
LRCLKI
36
BITCLKI
28
CLKO1
22
BITCLKO
21
LRCLKO
CLOCK
61
PDSPRSTN
PSRCRSTN
TESTI1,2
JX0
JUMP
Analog Lch+
92
AINL+
Analog Lch-
91
AINL-
Analog Rch+
90
AINR+
Analog Rch-
89
AINR-
Analog Lch
83,81,79,94,96,98,100
Analog Rch
82,80,78,93,95,97,99
77
Analog Mono
C
R
1
73
10μ
3
CONTROL
6
7
SRC
71
64
63
AINR2~AINR8
AINM
SDIN1
SDIN2~7
LFLT
SDOUTA1
SDOUT1~7
AVDD
62
32-35,59,60
53
23-27,54,55
Audio
I/F
VCOM
86
AVDD
0.1μ
10μ
0.1μ
84
10μ
SRCBICK
RESET
0.1μ
Analog +3.3V
10μ
75
SRCLRCK
I/F
4,72
NC
PSRCSMUTE
Micom
43
76
SRC2BICK
I2C
66
NC
SRC2LRCK
AINL2~AINL8
“H”
RDY
CL
CL
5
52
0.1μ
85
10,13,19,30,39,48,57,68
VSS1
AVDD
VREFL
VREFH
VSS2
VSS3
14
2,74,88
87
8,70
DVDD18 x 7
18
31
38
47
58
67
Digital +1.8V
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
0.1μ
10μ
Figure 70. Software Reset (I2CSEL pin= “H”)
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[AK7782]
2. Peripheral Circuits
2-1. Ground and Power Supply
To minimize digital noise coupling, AVDD, DVDD and DVDD18 should be individually de-coupled at the AK7782.
System analog power is supplied to AVDD. Power supply should be wired separately and connected as close as possible
to where the supplies are brought onto the printed circuit board. Decoupling capacitors, particularly small capacity
capacitors, should be connected as close as possible to the AK7782.
2-2. Reference Voltage
The input voltage difference between the VREFH pin and the VREFL pin determines the full scale of analog input.
Normally, connect AVDD to VREFH, and connect VSS1 to VREFL pins. Connect a 0.1μF ceramic capacitor to the
VREF pin to eliminate the effects of high frequency noise in parallel with an appropriate 10μF electrolytic capacitor
between this pin and VSS1. The ceramic capacitor in particular should be connected as close as possible to the pin. To
avoid coupling to the AK7782, digital signals and clock signals should be kept away as far as possible from the VREFH
and VREFL pins.
VCOM is used as the common voltage of the analog signal. A 10μF electrolytic capacitor in parallel with a 0.1μF ceramic
capacitor attached between VCOM pin and VSS1 pin eliminates the effects of high frequency noise. The ceramic
capacitor should be connected as close as possible to the pin. Do not draw current from the VCOM pin.
2-3. Analog Input
Analog input signals are applied to the modulator through the input pin of each channel. The input voltage is ±FS=±
(VREFH-VREFL)×2.0/3.3. When VREFH = 3.3V and VREFL = 0.0V, the input range is within ±2.00Vpp (typ). The
output code format is given in terms of 2's complements.
The AK7782 samples the analog inputs at 3.072MHz when fs=48kHz. The digital filter rejects noise from 30kHz to
3.042MHz. The AK7782 includes an anti-aliasing filter (RC filter) to attenuate a noise around 3.042MHz~3.072MHz. No
external low-pass filter is needed in front of the ADC for normal audio signal. However, an external low-pass filter should
be connected before the ADC for the signal which has large out-of-band noise such as D/A converted signals.
The analog source voltage to the AK7782 is +3.3V typical. Voltage of AVDD + 0.3V or more, voltage of VSS1 - 0.3V or
less, and current of 10mA or more must not be applied to analog input pins. Excessive current will damage the internal
protection circuit and will cause latch-up, damaging the IC. Accordingly, if the external analog circuit voltage is ±15V,
the analog input pins must be protected from signals with the absolute maximum rating or more.
10k
Signal
22μ
+
10k
10k
68p
+
+12V
10k
2.0Vpp
68p
+
+
LME49720MA
AIN+
2.2μ
+
2.2μ
AIN2.0Vpp
Figure 71. Input Buffer Circuit Example (Differential Input)
After initial reset is released, the internal operating point level AVDD/2 occurs on analog input pins (AINL+,
AINL-, AINR+, AINR-, AINL2~L8, AINR2~R8, AINM) of the AK7782.
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[AK7782]
2-4. Connection to Digital Circuit
Connect CMOS logic or low voltage logic circuits to digital output pins of the AK7782 to minimize digital noise
coupling. Adequate CMOS logics are 74HC and 74AC series, and low-voltage logics are 74LV, 74LV-A, 74ALVC and
74AVC series.
2-5. Cristal Oscillator
The resistor and capacitor values for the oscillator RC circuit are shown in the table below.
CKM Mode
0, 2
1, 3
R1 max
70Ω
50Ω
C0 max
5pF
5pF
XTI, XTO pin Capacity
10pF or 15pF or 22pF
10pF or 15pF
2-6. LFLT pin External Connection
A resistor and a capacitor with a following specification should be connected to the LFLT pin (pin #1).
R [kΩ]
1.5±5%
C [nF]
47± 30%
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[AK7782]
PACKAGE
100-pin LQFP
(Unit: mm)
1.60 Max.
16.0
14.0
76
50
100
26
14.0
16.0
0.10±0.05
51
75
25
1
0.5
0.22±0.05
0.09~0.20
0.10
M
1.0
S
0°~10°
0.60±0.15
0.10 S
■ Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
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[AK7782]
MARKING
AK7782VQ
XXXXXXX
1) Pin #1 indication
2) Date Code: XXXXXXX(7 digits)
3) Marking Code: AK7782VQ
REVISION HISTORY
Date (YY/MM/DD)
11/11/02
Revision
00
Reason
First Edition
Page
MS1337-E-00
Contents
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[AK7782]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
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