データシート

[AK4629]
AK4629
High Performance Multi-channel Audio CODEC
AK4629
4ch ADC
DAC
8ch DAC
24bit CODEC
ADC
AK4629
48
ADC
LQFP
† 4ch 24bit ADC
- 64
:
96kHz
/
- S/(N+D): 92dB (
)
, S/N: 102dB (
) 103dB (
HPF
- I/F
:
, I2S, TDM
† 8ch 24bit DAC
- 128
:
192kHz
- 24
8
- S/(N+D): 90dB
, S/N: 106dB
- I/F
:
,
(20bit,24bit), I2S, TDM
(128
, 0.5dB
(32kHz, 44.1kHz, 48kHz
)
†
† TTL
I/F
†
µP I/F: 3
, I2C
†
: 256fs, 384fs, 512fs (fs=32kHz ∼ 48kHz)
128fs, 192fs, 256fs (fs=64kHz ∼ 96kHz)
128fs (fs=120kHz~ 192kHz)
†
: 4.5 ∼ 5.5V
†
: 2.7 ∼ 5.5V
†
: 48
LQFP
MS1277-J-02
)
)
2012/03
-1-
[AK4629]
■
LIN1+/LIN1
LIN1-
ADC
HPF
RIN1+/RIN1
RIN1-
ADC
HPF
LIN2+/LIN2
LIN2-
ADC
HPF
RIN2+/RIN2
RIN2-
ADC
HPF
Audio
I/F
SDTO1
SDTO1
SDTO2
SDTO2
MCLK
MCLK
LRCK
BICK
LOUT1
LPF
DAC
DATT
ROUT1
LPF
DAC
DATT
LOUT2
LPF
DAC
DATT
ROUT2
LPF
DAC
DATT
LOUT3
LPF
DAC
DATT
ROUT3
LPF
DAC
DATT
LOUT4
LPF
DAC
DATT
ROUT4
LPF
DAC
DATT
SDIN1
SDIN2
SDIN3
SDIN4
LRCK
BICK
SDTI1
SDTI2
SDTI3
SDTI4
AK4629
MS1277-J-02
2012/03
-2-
[AK4629]
■
AK4629VQ
AKD4629
-40 ∼ +105°C
AK4629
48pin LQFP(0.5mm pitch)
LOUT2
ROUT3
LOUT3
27
26
25
LOUT1
ROUT2
28
VCOM
31
ROUT1
VREFH
32
29
AVDD
33
30
VSS2
34
DZF1
35
36
DZF2
■
RIN2-
37
24
R OUT4
RIN2+/RIN2
38
23
LOUT4
LIN 2-
39
22
TST2
LIN 2+/LIN2
40
21
I2C/TST6
RIN1-
41
20
D FS0
RIN 1+/RIN1
42
19
SDTI4
LIN1-
43
18
SDTI3
17
SD TI2
AK4629
Top V iew
8
9
10
11
12
VSS1
TDM0/SDA/CDTI
DIF1/SCL/CCLK
DIF0/CSN
PDN
MC LK
7
13
DVDD
48
6
SMUTE
TVDD
B ICK
5
14
SDTO2
47
4
DZFE
SDTO1
LRCK
3
SD TI1
15
PS
16
46
2
45
SGL
CAD1
TST1
1
44
CAD0
LIN1+/LIN1
MS1277-J-02
2012/03
-3-
[AK4629]
No.
1
2
3
4
5
6
7
8
9
Pin Name
CAD0
CAD1
PS
SDTO1
SDTO2
TVDD
DVDD
VSS1
TDM0
I/O
I
I
I
O
O
I
SDA/CDTI
I/O
10
DIF1
SCL/CCLK
I
I
11
DIF0
CSN
I
I
PDN
I
MCLK
BICK
LRCK
SDTI1
SDTI2
SDTI3
SDTI4
DFS0
I
I
I
I
I
I
I
I
I2C
I
TST6
I
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TST2
LOUT4
ROUT4
LOUT3
ROUT3
LOUT2
ROUT2
LOUT1
ROUT1
O
O
O
O
O
O
O
O
Function
Chip Address 0 Pin
Chip Address 1 Pin
Parallel/Serial Select Pin
“L”: Serial control mode, “H”: Parallel control mode
ADC1 Audio Serial Data Output Pin
ADC2 Audio Serial Data Output Pin
Output Buffer Power Supply Pin, 2.7V∼5.5V
Digital Power Supply Pin, 4.5V∼5.5V
Digital Ground Pin, 0V
TDM I/F Format Mode Pin in parallel control mode
“L”: Normal mode, “H”: TDM mode
Control Data Input Pin in serial control mode
I2C pin= “L”: CDTI (3-wire Serial), I2C pin= “H”: SDA (I2C Bus)
Audio Data Interface Format 1 Pin in parallel control mode
Control Data Clock Pin in serial control mode
I2C pin= “L”: CCLK (3-wire Serial), I2C pin= “H”: SCL (I2C Bus)
Audio Data Interface Format 0 Pin in parallel control mode
Chip Select Pin in 3-wire serial control mode
This pin should be connected to DVDD at I2C bus control mode
Power-Down & Reset Pin
When “L”, the AK4629 is powered-down and the control registers are reset to default
state. If the state of the PS pin or CAD1-0 changes, then the AK4629 must be reset by the
PDN pin.
Master Clock Input Pin
Audio Serial Data Clock Pin
Input Channel Clock Pin
DAC1 Audio Serial Data Input Pin
DAC2 Audio Serial Data Input Pin
DAC3 Audio Serial Data Input Pin
DAC4 Audio Serial Data Input Pin
Double Speed Sampling Mode Pin (Note 1)
“L”: Normal Speed, “H”: Double Speed
Control Mode Select Pin (PS pin = “L”)
“L”: 3-wire Serial, “H”: I2C Bus
Test Pin (PS pin = “H”)
This pin should be connected to VSS1
Test Pin
This pin should be connected to VSS1.
DAC4 Lch Analog Output Pin
DAC4 Rch Analog Output Pin
DAC3 Lch Analog Output Pin
DAC3 Rch Analog Output Pin
DAC2 Lch Analog Output Pin
DAC2 Rch Analog Output Pin
DAC1 Lch Analog Output Pin
DAC1 Rch Analog Output Pin
MS1277-J-02
2012/03
-4-
[AK4629]
No.
31
Pin Name
VCOM
32
33
34
35
VREFH
AVDD
VSS2
DZF1
36
DZF2
37
38
45
RIN2RIN2+
RIN2
LIN2LIN2+
LIN2
RIN1RIN1+
RIN1
LIN1LIN1+
LIN1
TST1
46
SGL
47
DZFE
48
SMUTE
39
40
41
42
43
44
Note 1. PS pin= “L”
Note 2. PS pin= “L”
DZFM3-0 bit
Note 3.
I/O
O
Function
Common Voltage Output Pin, AVDD/2
Large external capacitor around 2.2µF is used to reduce power-supply noise.
I
Positive Voltage Reference Input Pin, AVDD
Analog Power Supply Pin, 4.5V∼5.5V
Analog Ground Pin, 0V
O
Zero Input Detect 1 Pin
(Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “L”, this pin goes to
“H”. It always is in “L” when the PS pin is “H”.
O
Zero Input Detect 2 Pin
(Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “L”, this pin goes to
“H”. It always is in “L” when the PS pin is “H”.
I
ADC2 Rch Analog Negative Input Pin (SGL pin = “L”)
I
ADC2 Rch Analog Positive Input Pin (SGL pin = “L”)
I
ADC2 Rch Analog Input Pin (SGL pin = “H”)
I
ADC2 Lch Analog Negative Input Pin (SGL pin = “L”)
ADC2 Lch Analog Positive Input Pin (SGL pin = “L”)
I
ADC2 Lch Analog Input Pin (SGL pin = “H”)
I
ADC1 Rch Analog Negative Input Pin (SGL pin = “L”)
I
ADC1 Rch Analog Positive Input Pin (SGL pin = “L”)
I
ADC1 Rch Analog Input Pin (SGL pin = “H”)
I
ADC1 Lch Analog Negative Input Pin (SGL pin = “L”)
I
ADC1 Lch Analog Positive Input Pin (SGL pin = “L”)
I
ADC1 Lch Analog Input Pin (SGL pin = “H”)
I
Test Pin
This pin should be connected to VSS1.
I
Single-ended Input Mode Select Pin.
“L”: ADC Differential Input Mode
“H”: ADC Single-ended Input Mode
I
Zero Input Detect Enable Pin
“L”: mode 7 (disable) at parallel mode,
zero detect mode is selectable by DZFM3-0 bits at serial mode
“H”: mode 0 (DZF1 is AND of all six channels)
I
Soft Mute Pin (Note 1)
When this pin goes to “H”, soft mute cycle is initialized.
When returning to “L”, the output mute releases.
SMUTE, DFS0 pin
OR
DZFE = “L”
(DZF1/2 pin)
(Table 11)
MS1277-J-02
2012/03
-5-
[AK4629]
(VSS1=VSS2=0V; Note 4)
Parameter
Power Supplies
Analog
Digital
Output buffer
Input Current (any pins except for supplies)
Analog Input Voltage
Digital Input Voltage
Ambient Temperature (power applied) (Note 6)
Storage Temperature
Note 4.
Note 5. VSS1 VSS2
Note 6.
100%
Symbol
AVDD
DVDD
TVDD
IIN
VINA
VIND
Ta
Tstg
min
-0.3
-0.3
-0.3
-0.3
-0.3
-40
-65
max
6.0
6.0
6.0
±10
AVDD+0.3
DVDD+0.3
105
150
Unit
V
V
V
mA
V
V
°C
°C
max
5.5
5.5
5.5
Unit
V
V
V
:
(VSS1=VSS2=0V; Note 4)
Parameter
Analog
Power Supplies
Digital
(Note 7)
Output buffer
Note 4.
Note 7. AVDD, DVDD, TVDD
ON
Symbol
AVDD
DVDD
TVDD
min
4.5
4.5
2.7
typ
5.0
5.0
5.0
I2C
AK4629
OFF
:
MS1277-J-02
2012/03
-6-
[AK4629]
(Ta=25°C; AVDD=DVDD=TVDD=5V; VSS1=VSS2=0V; VREFH=AVDD; fs=48kHz; BICK=64fs;
Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at 48kHz, 20Hz~40kHz at fs=96kHz,
20Hz~40kHz at fs=192kHz; unless otherwise specified)
Parameter
min
typ
max
Unit
ADC Analog Input Characteristics (Single-ended Inputs)
Resolution
24
Bits
S/(N+D)
(-0.5dBFS)
fs=48kHz
84
96
dB
fs=96kHz
92
dB
DR
(-60dBFS)
fs=48kHz, A-weighted
94
102
dB
fs=96kHz
88
99
dB
fs=96kHz, A-weighted
93
105
dB
S/N
(Note 11)
fs=48kHz, A-weighted
94
102
dB
fs=96kHz
88
99
dB
fs=96kHz, A-weighted
93
105
dB
Interchannel Isolation
90
110
dB
DC Accuracy (Single-ended Inputs)
Interchannel Gain Mismatch
0.2
0.3
dB
Gain Drift
20
ppm/°C
Input Voltage
AIN=0.68xVREFH
3.2
3.4
3.6
Vpp
fs=48kHz
12
14
kΩ
Input Resistance
fs=96kHz
11
kΩ
Power Supply Rejection
(Note 9)
50
dB
ADC Analog Input Characteristics (Differential inputs)
S/(N+D)
(-0.5dBFS)
fs=48kHz
84
96
dB
fs=96kHz
94
dB
DR
(-60dBFS)
fs=48kHz, A-weighted
95
103
dB
fs=96kHz
89
100
dB
fs=96kHz, A-weighted
94
106
dB
S/N
(Note 11)
fs=48kHz, A-weighted
95
103
dB
fs=96kHz
89
100
dB
fs=96kHz, A-weighted
94
106
dB
Interchannel Isolation
90
110
dB
DC Accuracy (Differential inputs)
Interchannel Gain Mismatch
0.2
0.3
dB
Gain Drift
20
ppm/°C
Input Voltage
AIN=0.68xVREFH (Note 8)
±3.2
±3.4
±3.6
Vpp
fs=48kHz
22
32
kΩ
Input Resistance
fs=96kHz
19
kΩ
Power Supply Rejection
(Note 9)
50
dB
Common Mode Rejection Ratio (CMRR)
(Note 10)
60
dB
MS1277-J-02
2012/03
-7-
[AK4629]
DAC Analog Output Characteristics
Resolution
S/(N+D)
(0dBFS)
fs=48kHz
80
98
fs=96kHz
78
98
fs=192kHz
98
DR
(-60dBFS)
fs=48kHz, A-weighted
95
106
fs=96kHz
88
100
fs=96kHz, A-weighted
94
106
fs=192kHz
100
fs=192kHz, A-weighted
106
S/N
(Note 12)
fs=48kHz, A-weighted
95
106
fs=96kHz
88
100
fs=96kHz, A-weighted
94
106
fs=192kHz
100
fs=192kHz, A-weighted
106
Interchannel Isolation
90
110
DC Accuracy
Interchannel Gain Mismatch
0.2
Gain Drift
20
Output Voltage
AOUT=0.6xVREFH
2.75
3.0
Load Resistance
5
Load Capacitance
Power Supply Rejection
(Note 10)
50
Note 8. (LIN+) – (LIN-)
(RIN+) – (RIN-)
VREFH
Note 9. VREFH +5V
AVDD, DVDD, TVDD 1kHz, 50mVpp
Note 10. VREFH +5V
LIN+(RIN+) LIN-(RIN-)
AVDD1,2x1/2
CMRR
1.52Vpp=-7dBFS
Note 11. CCIR-ARM
98dB(@fs=48kHz)
Note 12. CCIR-ARM
102dB(@fs=48kHz)
Parameter
Power Supplies
Power Supply Current (AVDD+DVDD+TVDD)
Normal Operation (PDN = “H”)
AVDD
fs=48kHz, 96kHz
fs=192kHz
DVDD+TVDD fs=48kHz
fs=96kHz
fs=192kHz
Power-down mode (PDN = “L”)
Note 13. TVDD=0.1mA(typ).
Note 14.
min
(Note 13)
(Note 14)
24
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
0.5
3.25
dB
ppm/°C
Vpp
kΩ
pF
dB
25
1.52Vpp, 1kHz
typ
max
Unit
57
34
19
27
27
80
86
51
29
40
40
200
mA
mA
mA
mA
mA
μA
VSS1
MS1277-J-02
2012/03
-8-
[AK4629]
(Ta=25°C; AVDD=DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; fs=48kHz)
Parameter
Symbol
min
ADC Digital Filter (Decimation LPF):
Passband
(Note 15)
PB
0
±0.1dB
-0.2dB
-3.0dB
Stopband
SB
28
Passband Ripple
PR
Stopband Attenuation
SA
68
Group Delay
(Note 16)
GD
Group Delay Distortion
ΔGD
ADC Digital Filter (HPF):
Frequency Response
(Note 15) -3dB
FR
-0.1dB
DAC Digital Filter:
Passband
(Note 15) -0.1dB
PB
0
-6.0dB
Stopband
SB
26.2
Passband Ripple
PR
Stopband Attenuation
SA
54
Group Delay
(Note 16)
GD
DAC Digital Filter + Analog Filter:
FR
Frequency Response: 0 ∼ 20.0kHz
FR
40.0kHz (Note 17)
FR
80.0kHz (Note 17)
Note 15.
Note 16.
fs
-0.1dB
typ
max
Unit
20.0
23.0
18.9
-
16
0
kHz
kHz
kHz
kHz
dB
dB
1/fs
μs
1.0
6.5
Hz
Hz
±0.04
21.8
-
24.0
±0.02
19.2
±0.2
±0.3
±1.0
21.8kHz 0.454 x fs
kHz
kHz
kHz
dB
dB
1/fs
dB
dB
dB
24
ADC
DAC
20/24
DAC
Note 17. 40.0kHz; fs=96kHz , 80.0kHz; fs=192kHz.
DC
(Ta=25°C; AVDD=DVDD=4.5∼5.5V; TVDD=2.7∼5.5V)
Parameter
Symbol
High-Level Input Voltage
VIH
Low-Level Input Voltage
VIL
High-Level Output Voltage
(SDTO1-2 pin:
Iout=-100μA)
VOH
(DZF1, DZF2 pins: Iout=-100μA)
VOH
Low-Level Output Voltage
(SDTO1-2, DZF1, DZF2 pins: Iout= 100μA)
VOL
(SDA pin:
Iout= 3mA)
VOL
Input Leakage Current
Iin
MS1277-J-02
min
2.2
-
typ
-
max
0.8
Unit
V
V
TVDD-0.5
AVDD-0.5
-
-
V
V
-
-
0.5
0.4
±10
V
V
μA
2012/03
-9-
[AK4629]
(Ta=25 ; AVDD= DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
256fsn, 128fsd:
fCLK
8.192
Pulse Width Low
tCLKL
27
Pulse Width High
tCLKH
27
384fsn, 192fsd:
fCLK
12.288
Pulse Width Low
tCLKL
20
Pulse Width High
tCLKH
20
512fsn, 256fsd, 128fsq:
fCLK
16.384
Pulse Width Low
tCLKL
15
Pulse Width High
tCLKH
15
LRCK Timing
Normal mode (TDM0= “0”, TDM1= “0”)
Normal Speed Mode
fsn
32
Double Speed Mode
fsd
64
Quad Speed Mode
fsq
128
Duty Cycle
Duty
45
TDM256 mode (TDM0= “1”, TDM1= “0”)
LRCK frequency
fsn
32
“H” time
tLRH
1/256fs
“L” time
tLRL
1/256fs
TDM128 mode (TDM0= “1”, TDM1= “1”)
LRCK frequency
fsd
64
“H” time
tLRH
1/128fs
“L” time
tLRL
1/128fs
Audio Interface Timing
Normal mode (TDM0= “0”, TDM1= “0”)
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
32
Pulse Width High
tBCKH
32
LRCK Edge to BICK “↑”
(Note 18)
tLRB
20
BICK “↑” to LRCK Edge
(Note 18)
tBLR
20
LRCK to SDTO1-2 (MSB)
tLRS
BICK “↓” to SDTO1-2
tBSD
SDTI1-4 Hold Time
tSDH
20
SDTI1-4 Setup Time
tSDS
20
TDM256 mode (TDM0= “1”, TDM1= “0”)
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
32
Pulse Width High
tBCKH
32
LRCK Edge to BICK “↑”
(Note 18)
tLRB
20
BICK “↑” to LRCK Edge
(Note 18)
tBLR
20
BICK “↓” to SDTO1
tBSD
SDTI1 Hold Time
tSDH
10
SDTI1 Setup Time
tSDS
10
TDM128 mode (TDM0= “1”, TDM1= “1”)
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
32
Pulse Width High
tBCKH
32
LRCK Edge to BICK “↑”
(Note 18)
tLRB
20
BICK “↑” to LRCK Edge
(Note 18)
tBLR
20
BICK “↓” to SDTO1
tBSD
SDTI1-2 Hold Time
tSDH
10
SDTI1-2 Setup Time
tSDS
10
Note 18.
LRCK
BICK
MS1277-J-02
typ
max
Unit
12.288
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
18.432
24.576
48
96
192
55
kHz
kHz
kHz
%
48
kHz
ns
ns
96
kHz
ns
ns
40
40
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2012/03
- 10 -
[AK4629]
Parameter
Control Interface Timing (3-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 19)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
Power-down & Reset Timing
PDN Pulse Width
(Note 20)
PDN “↑” to SDTO1-2 valid
(Note 21)
Note 19.
300ns(SCL
)
Note 20.
PDN pin “L”
“H”
Note 21. PDN pin
LRCK
Note 22. I2C-bus NXP B.V.
MS1277-J-02
Symbol
min
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
tPD
tPDV
150
typ
max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
400
1.0
0.3
50
400
522
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
ns
1/fs
2012/03
- 11 -
[AK4629]
■
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fsn, 1/fsd
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
(TDM0 bit= “0”)
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRH
tLRL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
(TDM0 bit= “1”)
MS1277-J-02
2012/03
- 12 -
[AK4629]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tLRS
tBSD
50%TVDD
SDTO
tSDS
tSDH
VIH
SDTI
VIL
(TDM0 bit= “0”)
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
(TDM0 bit= “1”)
MS1277-J-02
2012/03
- 13 -
[AK4629]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
WRITE
VIH
A4
VIL
(3
)
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
D3
CDTI
D2
D1
WRITE
(3
VIH
D0
VIL
)
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
Start
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
I2C
tPD
VIH
PDN
VIL
tPDV
50%TVDD
SDTO
MS1277-J-02
2012/03
- 14 -
[AK4629]
■
MCLK, LRCK, BICK
MCLK
MCLK LRCK
DFS0 pin
DFS0, DFS1 bit
(Manual
Setting Mode)
(Auto Setting Mode) 2
Manual Setting Mode
(ACKS bit= “0”: Default)
DFS0, DFS1 bit
(Table 1)
MCLK
(Table 2, Table 3, Table 4)
Auto Setting Mode (ACKS bit= “1”)
MCLK
(Table 5)
(Table 6)
DFS bit
MCLK
VCOM
(typ)
ON
MCLK
LRCK
AK4629
MCLK LRCK
LRCK
DFS1
0
0
1
DFS0
0
1
0
Sampling Speed (fs)
Normal Speed Mode
32kHz~48kHz
Double Speed Mode
64kHz~96kHz
Quad Speed Mode
120kHz~192kHz
Table 1.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920
11.2896
12.2880
Table 2.
LRCK
fs
88.2kHz
96.0kHz
(
(default)
(Manual Setting Mode)
MCLK (MHz)
384fs
12.2880
16.9344
18.4320
512fs
16.3840
22.5792
24.5760
BICK (MHz)
64fs
2.0480
2.8224
3.0720
(Normal Speed Mode @Manual Setting Mode)
128fs
11.2896
12.2880
MCLK (MHz)
192fs
16.9344
18.4320
256fs
22.5792
24.5760
BICK (MHz)
64fs
5.6448
6.1440
Table 3.
(Double Speed Mode @Manual Setting Mode)
:Double Speed Mode (DFS1bit= “0”, DFS0 bit= “1”) 128fs 192fs
ADC
LRCK
fs
176.4kHz
192.0kHz
(
Table 4.
:Quad Speed Mode
128fs
22.5792
24.5760
MCLK (MHz)
192fs
-
256fs
-
BICK (MHz)
64fs
11.2896
12.2880
(Quad Speed Mode @Manual Setting Mode)
(DFS1 bit= “1”, DFS0 bit= “0”)
ADC
MS1277-J-02
)
)
2012/03
- 15 -
[AK4629]
MCLK
512fs
256fs
128fs
Sampling Speed
Normal
Double
Quad
Table 5.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
(Auto Setting Mode)
128fs
22.5792
24.5760
MCLK (MHz)
256fs
22.5792
24.5760
-
Table 6.
■
Sampling
Speed
512fs
16.3840
22.5792
24.5760
-
Normal
Double
Quad
(Auto Setting Mode)
/
AK4629 SGL pin = “L”
(Figure 1) “H”
L/RIN1-2 pin
L/RIN1-2 pin
L/RIN1-2 pin Open
AK4629
L/RIN+
(Figure 2)
AK4629
AK4629
L/RIN
LPF
LPF
SCF
L/RIN-
SCF
LPF
L/RIN(Open)
Figure 1.
Figure 2.
(SGL pin = “L”)
(SGL pin = “H”)
MS1277-J-02
2012/03
- 16 -
[AK4629]
■
IIR
3
(32kHz, 44.1kHz, 48kHz)
Double Speed Mode Quad Speed Mode
DAC1(SDTI1), DAC2(SDTI2), DAC3(SDTI3), DAC4(SDTI4)
Mode
0
1
2
3
Sampling Speed
Normal Speed
Normal Speed
Normal Speed
Normal Speed
DEM1
0
0
1
1
(50/15µs
)
OFF
DEM0
0
1
0
1
DEM
44.1kHz
OFF
48kHz
32kHz
(default)
Table 7.
■
HPF
ADC DC
HPF
HPF
fc
fs=48kHz
1.0Hz
fs
MS1277-J-02
2012/03
- 17 -
[AK4629]
■
TDM1 bit = “0” TDM0 pin = “L”
DIF1-0 bit
SDTO1-2 BICK
TDM1-0 bits = “00”
MSB
2’s
SDTI1-4 BICK
4
(Table 8)
mode2, 3, 6, 7,10,11 16 ∼ 20
SDTI
Mode
TDM 1
TDM0
DIF1
DIF0
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
LSB
SDTI1- 4
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I2S
Table 8.
TDM0 pin
LRCK
SDTO1-2
BICK
H/L
I
≥ 48fs
I
H/L
I
≥ 48fs
I
H/L
I
≥ 48fs
I
L/H
I
≥ 48fs
I
(
(default)
)
“H”
SDTO2 pin = “L”
TDM I/F
SDTO1 pin
ADC(4ch)
TDM256 Mode
SDTI1 pin
DAC(8ch)
4
BICK 256fs
LRCK “H”
“L”
1/256fs(min)
(Table 9) DIF1-0
MSB
2’s
SDTO1 BICK
SDTI1 BICK
TDM
LOOP1-0 bit “0”
TDM128 Mode (96kHz) TDM1
(Table 10) SDTI1 pin DAC(4ch; L1,R1,L2,R2) SDTI2 pin DAC(4ch;L3,R3,L4,R4)
8ch
TDM256
TDM0 pin
TDM0
“H”
2
TDM0
TDM1
“1”
Mode
TDM 1
TDM0
DIF1
DIF0
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
SDTO1
SDTI1
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I2S
Table 9.
LRCK
TDM 1
TDM0
DIF1
DIF0
8
1
1
0
0
9
1
1
0
1
10
1
1
1
0
11
1
1
1
1
SDTO1
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
Table 10.
SDTI1,
SDTI2
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I2S
↑
I
256fs
I
↑
I
256fs
I
↑
I
256fs
I
↓
I
256fs
I
MS1277-J-02
4
)
LRCK
BICK
↑
I
128fs
I
↑
I
128fs
I
↑
I
128fs
I
↓
I
128fs
I
(TDM128
SDTI2-
BICK
(TDM256
Mode
“0”
)
2012/03
- 18 -
[AK4629]
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
12 11 10
0
19 18
8
Don’t Care
23 22
7
1
12
11 10
Don’t Care
0
0
19 18
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
23
8
7
1
0
Rch Data
Figure 3. Mode 0
LRCK
0
1
2
8
9
10
24
25
31
0
1
2
8
9
10
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
16 15 14
Don’t Care
0
23 22
23:MSB, 0:LSB
23 22
8
7
1
16 15 14
Don’t Care
0
0
23 22
Lch Data
23
8
7
1
0
Rch Data
Figure 4. Mode 1
LRCK
0
1
2
21
22
23
24
28
29
30
31
0
1
2
22
23
24
28
29
30
31
0
1
BICK(64fs)
SDTO(o)
23 22
2
1
0
SDTI(i)
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
23
Don’t Care
23
Rch Data
Figure 5. Mode 2
LRCK
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
BICK(64fs)
SDTO(o)
23 22
2
1
0
SDTI(i)
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
Lch Data
23 22
2
1
0
23 22
2
1
0
Don’t Care
Rch Data
Figure 6. Mode 3
MS1277-J-02
2012/03
- 19 -
[AK4629]
256 BICK
LRCK
BICK(256fs)
SDTO1(o)
SDTI1(i)
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
19 18
0
19 18
0
19 18
0
19 18
23 22
0
19 18
0
19 18
0
19 18
0
19 18
0
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
19
Figure 7. Mode 4
256 BICK
LRCK
BICK(256fs)
SDTO1(o)
23 22
0
23 22
L1
R1
32 BICK
SDTI1(i)
23 22
0
23 22
23 22
L2
32 BICK
0
0
23 22
23 22
R2
32 BICK
0
0
23 22
32 BICK
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
Figure 8. Mode 5
256 BICK
LRCK
BICK(256fs)
SDTO1(o)
23 22
0
23 22
L1
R1
32 BICK
SDTI1(i)
23 22
23 22
0
0
23 22
L2
32 BICK
23 22
0
0
23 22
R2
32 BICK
23 22
0
0
32 BICK
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23 22
Figure 9. Mode 6
256 BICK
LRCK
BICK(256fs)
SDTO1(o)
SDTI1(i)
23
0
23
0
23
0
23
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23
23
23
0
23
0
0
0
23
23
0
23
0
23
0
23
0
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
Figure 10. Mode 7
MS1277-J-02
2012/03
- 20 -
[AK4629]
128 BICK
LRCK
BICK(128fs)
SDTO1(o)
SDTI1(i)
SDTI2(i)
23 22
0
0
23 22
23 22
0
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
19 18
0
19 18
0
19 18
0
19 18
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
19 18
0
19 18
0
L3
R3
32 BICK
32 BICK
19 18
0
19 18
L4
23 22
0
19
0
19
R4
Figure 11. Mode 8
128 BICK
LRCK
BICK(128fs)
SDTO1(o)
SDTI1(i)
SDTI2(i)
23 22
0
0
23 22
23 22
0
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
19
0
19
Figure 12. Mode 9
128 BICK
LRCK
BICK(128fs)
SDTO1(o)
SDTI1(i)
SDTI2(i)
23 22
0
0
23 22
23 22
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
0
23 22
0
23 22
0
23 22
Figure 13. Mode 10
MS1277-J-02
2012/03
- 21 -
[AK4629]
128 BICK
LRCK
BICK(128fs)
SDTO1(o)
SDTI1(i)
SDTI2(i)
23 22
0
23 22
0
L1
R1
32 BICK
32 BICK
23 22
0
23 22
0
23 22
L2
23 22
0
23 22
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
0
23 22
0
23 22
23
0
23
0
23
R2
32 BICK
23 22
0
0
23 22
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
Figure 14. Mode 11
MS1277-J-02
2012/03
- 22 -
[AK4629]
■
AK4629 2
DZFE pin
PS pin= “L”
(DZF1/2 pin) DZFM3-0 bit
mode 0
mode 0
“H”
DZF1 pin (DZF2 pin)
“H”
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DZFM
2 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
DZFE pin= “L”
(Table 11) PS pin
DZF1
8ch AND
8192
DZF1 pin (DZF2 pin)
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
L1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
R1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF1
DZF1
DZF1
DZF1
“0”
“0”
AOUT
L2
R2
L3
R3
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF1
DZF1
DZF2
DZF2
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
disable (DZF1=DZF2 = “L”)
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
(“L”)
DZF1(DZF2) pin
“L”
L4
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
R4
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF1
DZF2
DZF2
DZF2
(default)
disable (DZF1=DZF2 = “L”)
Table 11.
MS1277-J-02
2012/03
- 23 -
[AK4629]
■
AK4629
ATT7-0 bit
(128
(Table 12)
ATT7-0
00H
01H
02H
:
7DH
7EH
7FH
FEH
FFH
, 0.5dB
Attenuation Level
0dB
-0.5dB
-1.0dB
:
-62.5dB
-63dB
MUTE (-∞)
:
MUTE (-∞)
MUTE (-∞)
)
(default)
Table 12.
ATT7-0
ATS1-0 bit
Mode
0
1
2
3
ATS1
0
0
1
1
(Table 13) Mode0
ATS0
0
1
0
1
Table 13.
Mode0
ATT
(37.3ms@fs=48kHz)
“0”
00H
Note: ATT Level
Mode1
ATT speed
1792/fs
896/fs
256/fs
256/fs
(default)
ATT7-0
1742
PDN pin “L”
RSTN bit “1”
00H(0dB)
ATT7-0 00H
7FH(MUTE)
ATT7-0
1792/fs
RSTN bit
11bit
MS1277-J-02
2012/03
- 24 -
[AK4629]
■
×ATT
-∞
ATT
SMUTE pin
-∞ (“0”)
(Table 13)
×ATT
“H”
ATT
SMUTE pin
-∞
ATT
ATT
“L”
ATT
SMUTE bit
(1)
ATT Level
(1)
(3)
Attenuation
-∞
GD
(2)
GD
AOUT
(4)
8192/fs
DZF1,2
:
(1) ATT
×ATT
(2)
(3)
(Table 13)
ATT
Mode 0
00H 7FH
(GD)
ATT
“00H”
1792/fs
-∞
ATT
(4)
8192
“0”
“0”
DZF1-2 pin “H”
DZF1-2 pin “L”
Figure 15.
■
ON
PDN pin
LRCK “↑”
“L”
MCLK
LRCK
MS1277-J-02
2012/03
- 25 -
[AK4629]
■
AK4629 ADC DAC
(PDN) “L”
PDN pin = “L”
SDTO1-2, DZF1-2 pin
VCOM
ADC
, SDTO1-2 516 x LRCK
“L”
DAC
VCOM
ADC
DAC PWADN bit PWDAN bit
PDDA1-4bit ADC1-2 PDAD1-2 bit
PWADN bit= “0”
PDAD1-2 bit= “0”
PDDA1-4 bit= “0”
VCOM
DAC1-4
SDTO1-2 “L”
DZF1-2 pin “H”
PDN
516/fs
ADC Internal
State
Normal Operation
Figure 16
Power-down
PWDAN bit= “0”
(1)
Init Cycle
Normal Operation
512/fs (2)
DAC Internal
State
Normal Operation
Power-down
Init Cycle
Normal Operation
GD (3)
GD
ADC In
(Analog)
(4)
ADC Out
(Digital)
“0”data
DAC In
(Digital)
“0”data
GD
(5)
(3)
GD
(6)
DAC Out
(Analog)
(6)
(7)
Clock In
Don’t care
MCLK,LRCK,SCLK
10∼11/fs (10)
(8)
DZF1/DZF2
External
Mute
(9)
Mute ON
(1) ADC
(2) DAC
(3)
(4)
(5)
(6) PDN
(7)
(8)
(9)
(6)
(10) PDN “↑”
(GD)
ADC
“0”
ADC
PDN
(PDN = “L”)
(PDN pin = “L”)
10∼11/fs
512/fs
(MCLK, BICK, LRCK)
DZF1-2 pin “L”
DZF1-2 pin = “L”
Figure 16.
MS1277-J-02
2012/03
- 26 -
[AK4629]
■
(1) RSTN bit
RSTN bit= “0”
VCOM
ADC DAC
DZF1-2 pin “H”
SDTO1-2 pin “L”
Figure 17 RSTN bit
RSTN bit
4~5/fs (9)
1~2/fs (9)
Internal
RSTN bit
516/fs (1)
ADC Internal
State
Normal Operation
Digital Block Power-down
DAC Internal
State
Normal Operation
Digital Block Power-down
Normal Operation
Init Cycle
Normal Operation
GD (2)
GD
ADC In
(Analog)
(3)
ADC Out
(Digital)
(4)
“0”data
DAC In
(Digital)
“0”data
(2)
GD
GD
(6)
DAC Out
(Analog)
(6)
(5)
(7)
Clock In
Don’t care
MCLK,LRCK,SCLK
4∼5/fs (8)
DZF1/DZF2
(1) ADC
(2)
(3)
(4)
(GD)
ADC
“0”
ADC
(5) RSTN bit= “0”
VCOM
(6) RSTN bit “0”
4∼5/fs
RSTN bit “1”
1∼2/fs
(7)
(RSTN = “0”)
(MCLK, BICK, LRCK)
(MCLK, BICK, LRCK)
RSTN= “1”
(8) DZF1-2 pin RSTN bit “0”
“H”
RSTN bit “1”
6~7/fs
(9) RSTN bit “0”
LSI
RSTN bit
4~5/fs
“L”
Figure 17.
MS1277-J-02
2012/03
- 27 -
[AK4629]
(2) MCLK
LRCK/BICK
(RSTN pin = “H”) MCLK
LRCK BICK
VCOM
SDTO1-2 DZF1-2 pin
MCLK
LRCK BICK
LRCK
DAC
VCOM
AK4629
“L”
ADC
SDTO1-2 516 x
Figure 18
RSTN bit
Clock In
CLK Stop
MCLK, BICK, LRCK
516/fs
ADC Internal
State
Normal Operation
Power-down
(1)
Init Cycle
Normal Operation
512/fs (2)
DAC Internal
State
Normal Operation
Power-down
Init Cycle
Normal Operation
GD (3)
GD
ADC In
(Analog)
(4)
ADC Out
(Digital)
“0”data
DAC In
(Digital)
“0”data
GD
(5)
(3)
GD
DAC Out
(Analog)
(6)
DZF1/DZF2
(7)
(6)
10∼11/fs (10)
External
Mute
(1) ADC
(2) DAC
(3)
(4)
(5)
(6)MCLK
(7)
(8)
(8)
Mute ON
(GD)
ADC
“0”
ADC
LRCK
BICK
DZF1-2 pin
MCLK
LRCK
BICK
20usec
“L”
(6)
Figure 18.
2
MS1277-J-02
2012/03
- 28 -
[AK4629]
■
AK4629
ADC
PDAD2-1 bit
“1”
PDAD2-1 bit
ADC
(GD)
ADC
ADC
“0”
ADC
PDAD2-1 bit
Power Down Channel
ADCDigital
Internal State
Normal Operation
Normal Operation
Power-down
Power-down
516/fs (1)
ADC Analog
Internal State
Normal Operation
Power-down
Init Cycle
Normal Operation
516/fs (1)
Normal Operation Power-down
Init Cycle
Normal Operation
(2)
GD
GD (2)
ADC In
(Analog)
(3)
“0”data
ADC Out
(Digital)
Normal Operation Channel
(4)
GD (2)
(4)
GD (2)
ADC In
(Analog)
(3)
“0”data
ADC Out
(Digital)
Clock In
MCLK,LRCK,SCLK
(1) ADC
(2)
(3)
(4)
(GD)
ADC
“0”
ADC
Figure 19. ADC
MS1277-J-02
2012/03
- 29 -
[AK4629]
■ DAC
AK4629
DAC
“1”
PDDA1-4 bit
DZF
PDDA1-4 bit
DAC
DAC
VCOM
DZF
DZF1-2 pin
PWDAN bit = “0”
bit
RSTN bit = “0”
PDDA1-4
Figure 20 PDDA1-4 bit
PDDA1-4 bit
Power Down Channel
DAC Digital
Internal State
DAC Analog
Internal State
Normal Operation
Normal Operation
Normal Operation
Power-down
DAC In
(Digital)
Power-down
Normal
Normal
Operation
Operation
“0”data
(1)
GD
GD
(3)
DAC Out
(Analog)
(2)
(3)
(3)
(2)
(3)
8192/fs
DZF Detect
Internal State
(4)
(4)
Normal Operation Channel
DAC In
(Digital)
“0”data
GD
GD
DAC Out
(Analog)
8192/fs
DZF Detect
Internal State
Clock In
MCLK,LRCK,SCLK
(5)
(6)
DZF1/DZF2
(1)
(2) PDDA1-4 bit
(3) PDDA1-4 bit
(4)
(GD)
DAC
PDDA bit
DZF
DAC
(5)
(6)
VCOM
DAC
DZF1-2 pin
DAC DZF
DAC
DZF1-2 pin ”H”
DZF1-2 pin
”H”
Figure 20. DAC
MS1277-J-02
2012/03
- 30 -
[AK4629]
■
AK4629
“L”
PS pin
2
CAD0, CAD1 pin
RSTN bit “0”
PS pin
PDN pin
I2C
(3
“L”
)
PDN pin
* PDN = “L”
(1) 3
(I2C pin= “L”)
3
I/F pin: CSN, CCLK, CDTI
I/F
Chip
address(2bits, CAD0/1), Read/Write(1bit, Fixed to “1”, Write only), Register address(MSB first, 5bits), Control
data(MSB first, 8bits)
CCLK
CSN
CCLK
5MHz(max)
* AK4629 3
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1=CAD1, C0=CAD0)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 21. 3
I/F
MS1277-J-02
2012/03
- 31 -
[AK4629]
(2) I2C
AK4629 I2C
(I2C pin= “H”)
(max:400kHz)
1. WRITE
I2C
(Start Condition)
(Figure 28)
8
2
7
“00100”
R/W bit
2
3
IC
“H”
SDA
“H”
(R/W)
IC
AK4629
“0”
R/W bit
“L”
(Figure 23)
CAD1-0 pin
8
MSB first
(Stop Condition)
“H”
SDA
“L”
5
(Acknowledge)
“1”
(
)
(Figure 24)
3
(Figure 25) AK4629
“0”
MSB first
8
Figure 22
SCL
SCL
“H”
(Figure 28)
AK4629
1
“0DH”
“00H”
“H”
SDA
SCL
“H”
“H” “L”
(Figure 30) SCL
“L”
SDA
S
T
A
R
T
SDA
S
S
T
O
P
R/W
Slave
Address
Sub
Address(n)
A
C
K
Data(n)
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 22. I2C
0
0
1
0
0
(CAD1, CAD0 pin
Figure 23. 1
0
0
0
A4
Figure 24.
D7
D6
D5
Figure 25.
CAD1
CAD0
R/W
)
A3
A2
A1
A0
D3
D2
D1
D0
2
D4
3
MS1277-J-02
2012/03
- 32 -
[AK4629]
2. READ
R/W bit “1”
AK4629
READ
“0DH”
“00H”
AK4629
2
READ
2-1.
AK4629
AK4629
(READ
WRITE
“n+1”
(R/W bit = “1”)
READ
)
“n”
1
READ
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
A
C
K
Data(n+1)
Data(n+2)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 26.
2-2.
READ
(R/W bit = “1”)
WRITE
WRITE
= “0”)
AK4629
(R/W bit= “1”)
READ
(R/W bit
AK4629
1
READ
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 27.
MS1277-J-02
2012/03
- 33 -
[AK4629]
SDA
SCL
S
P
start condition
stop condition
Figure 28.
DATA
OUTPUT BY
MASTER
not acknowledge
DATA
OUTPUT BY
SLAVE(AK4529)
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 29. I2C
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 30. I2C
MS1277-J-02
2012/03
- 34 -
[AK4629]
■
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
:
Register Name
Control 1
Control 2
LOUT1 Volume Control
ROUT1 Volume Control
LOUT2 Volume Control
ROUT2 Volume Control
LOUT3 Volume Control
ROUT3 Volume Control
De-emphasis
ATT speed
& Power Down Control
Zero detect
LOUT4 Volume Control
ROUT4 Volume Control
Power Down Control
D7
0
0
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
DEMD1
D6
0
DFS1
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
DEMD0
D5
TDM1
LOOP1
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
DEMA1
D4
TDM0
LOOP0
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
DEMA0
D3
DIF1
0
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
DEMB1
D2
DIF0
DFS0
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
DEMB0
D1
0
ACKS
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
DEMC1
D0
SMUTE
0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
DEMC0
0
PDDA4
ATS1
ATS0
PDDA3
PDDA2
PDDA1
RSTN
0
ATT7
ATT7
0
DZFM3
ATT6
ATT6
0
DZFM2
ATT5
ATT5
0
DZFM1
ATT4
ATT4
0
DZFM0
ATT3
ATT3
0
PWVRN
ATT2
ATT2
0
PWADN
ATT1
ATT1
PDAD2
PWDAN
ATT0
ATT0
PDAD1
0EH, 0FH
PDN pin “L”
RSTN bit “0”
DZF1-2 pin
SMUTE, DFS0
“H”
OR
MS1277-J-02
2012/03
- 35 -
[AK4629]
■
Addr
00H
Register Name
Control 1
Default
D7
0
0
SMUTE:
0:
1: DAC
PS pin= “L”
D6
0
0
D5
TDM1
0
D4
TDM0
0
SMUTE bit
D3
DIF1
1
D2
DIF0
0
D1
0
0
D0
SMUTE
0
OR
DIF1-0:
(Table 8, Table 9, Table 10)
: “10”, mode 2
TDM1-0: TDM
(Table 8, Table 9, Table 10)
Mode
TDM1
TDM0
0
1
2
3
0
0
1
1
0
1
0
1
Data Output
Pins
SDTO1-2
SDTO1
SDTO1
Data Input
Pins
SDTI1-3
SDTI1
SDTI1-2
MS1277-J-02
Sampling Speed
Normal, Double, Quad Speed
Normal Speed
N/A
Normal, Double Speed
(N/A: Not Available)
2012/03
- 36 -
[AK4629]
Addr
01H
Register Name
Control 2
Default
D7
0
0
D6
DFS1
0
D5
LOOP1
0
D4
LOOP0
0
D3
0
0
D2
DFS0
0
D1
ACKS
0
D0
0
0
ACKS:
0:
, Manual Setting Mode
1:
, Auto Setting Mode
ACKS= “1”
MCLK
ACKS= “0”
DFS1-0:
PS pin= “L”
ACKS bit= “1”
DFS
DFS0,1
MCLK
(Table 1)
DFS0 bit
DFS
OR
LOOP1-0:
00:
(
)
01: LIN1 → LOUT1, LOUT2, LOUT3, LOUT4
RIN1 → ROUT1, ROUT2, ROUT3, ROUT4
ADC
DAC
SDTI1-4
mode0
mode2
10: SDTI1(L) → SDTI2(L), SDTI3(L), SDTI4(L)
SDTI1(R) → SDTI2(R), SDTI3(R), SDTI4(R)
DAC
SDTI2-4
11: LIN2 → LOUT1, LOUT2, LOUT3, LOUT4
RIN2 → ROUT1, ROUT2, ROUT3, ROUT4
ADC
DAC
SDTI1-4
mode0
mode2
MS1277-J-02
DAC
SDTO1-2
mode1
mode3
DAC
SDTO1-2
mode1
mode3
2012/03
- 37 -
[AK4629]
Addr
02H
03H
04H
05H
06H
07H
0BH
0CH
Register Name
LOUT1 Volume Control
ROUT1 Volume Control
LOUT2 Volume Control
ROUT2 Volume Control
LOUT3 Volume Control
ROUT3 Volume Control
LOUT4 Volume Control
ROUT4 Volume Control
Default
ATT7-0:
Addr
08H
Register Name
De-emphasis
Default
D7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
0
D6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
0
D5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
0
D4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
0
D3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
0
D2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
0
D1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
0
D0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
0
(Table 12)
D7
DEMD1
0
D6
DEMD0
1
D5
DEMA1
0
D4
DEMA0
1
D3
DEMB1
0
DEMA1-0: DAC1
: “01”, OFF
(Table 7)
DEMB1-0: DAC2
: “01”, OFF
(Table 7)
DEMC1-0: DAC3
: “01”, OFF
(Table 7)
DEMD1-0: DAC4
: “01”, OFF
(Table 7)
MS1277-J-02
D2
DEMB0
1
D1
DEMC1
0
D0
DEMC0
1
2012/03
- 38 -
[AK4629]
Addr
09H
Register Name
ATT speed &
Power Down Control
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
PDDA4
ATS1
ATS0
PDDA3
PDDA2
PDDA1
RSTN
0
0
0
0
0
0
0
1
RSTN:
0:
1:
DZF1-2 pin
“H”
ATS1-0:
(Table 13)
: “00”, mode 0
PDDA4-1: Power-down control (0: Power-up, 1: Power-down)
PDDA1: Power down control of DAC1
PDDA2: Power down control of DAC2
PDDA3: Power down control of DAC3
PDDA4: Power down control of DAC4
Addr
0AH
Register Name
Zero detect
Default
D7
0
0
D6
DZFM3
0
D5
DZFM2
1
D4
DZFM1
1
D3
DZFM0
1
D2
PWVRN
1
D1
PWADN
1
D0
PWDAN
1
PWDAN: DAC1-4
0:
1:
PWADN: ADC
0:
1:
PWVRN:
0:
1:
DZFM3-0:
(Table 11)
: “0111”,
Addr
0DH
Register Name
Power Down Control
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
PDAD2
0
D0
PDAD1
0
PDAD2-1: Power-down control (0: Power-up, 1: Power-down)
PDAD1: Power down control of ADC1
PDAD2: Power down control of ADC2
MS1277-J-02
2012/03
- 39 -
[AK4629]
Figure 31
(AKD4629)
: TVDD=5V, 3
, CAD1-0 = “00”
Analog 5V
+
10u
MUTE
2.2u
+
MUTE
MUTE
0.1u
0.1u
MUTE
MUTE
LOUT3
LOUT2
ROUT3
LOUT1
ROUT2
VCOM
ROUT1
VREFH
VSS2
34 33 32 31 30 29 28 27 26 25
AVDD
2.2u
DZF1
DZF2
36 35
MUTE
37 RIN2-
ROUT4 24
38 RIN2+/RIN2
LOUT4 23
MUTE
TST2 22
39 LIN2-
I2C/TST6 21
40 LIN2+/LIN2
DFS0 20
41 RIN1-
AK4629
42 RIN1+/RIN1
SDTI4 19
SDTO2
TVDD
DVDD
VSS1
TDM0/SDA/CDTI
1
2
3
4
5
6
7
8
9 10 11 12
Audio
DSP
LRCK 15
BICK 14
MCLK 13
PDN
47 DZFE
DIF0/CSN
46 SGL
DIF1/SCL/CCLK
SDTO1
SDTI1 16
PS
SDTI2 17
45 TST1
CAD1
SDTI3 18
44 LIN1+/LIN1
CAD0
43 LIN1-
48 SMUTE
MUTE
Digital
Audio
Source
0.1u
10u
(DIR)
+
Power-down
control
5
Analog Ground
uP
Digital Ground
Figure 31.
MS1277-J-02
2012/03
- 40 -
[AK4629]
LIN2- 37
RIN2- 39
LIN2+/LIN2 38
RIN1- 41
RIN2+/RIN2 40
LIN1- 43
RIN1+/RIN1 42
1 CAD0
LIN1+/LIN1 44
SGL 46
TST1 45
DZFE 47
Analog Ground
SMUTE 48
Digital Ground
DZF2 36
DZF1 35
2 CAD1
System
VSS2 34
3 P/S
AVDD 33
4 SDTO1
Controller
VREFH 32
5 SDTO2
AK4629
VCOM 31
6 TVDD
ROUT1 30
7 DVDD
LOUT1 29
8 VSS1
ROUT2 28
9 TDM0/SDA/CDTI
LOUT2 27
10 DIF1/SCL/CCLK
24 ROUT4
22 TST2
23 LOUT4
20 DFS0
19 SDTI4
18 SDTI3
17 SDTI2
16 SDTI1
15 LRCK
14 BICK
13 MCLK
12 PDN
21 I2C/TST6
ROUT3 26
11 DIF0/CSN
LOUT3 25
Figure 32.
: VSS1
VSS2
1.
AVDD DVDD
VSS1
PC
AVDD DVDD
VSS2
2.
VREFH pin
VSS2 pin
VREFH pin
VCOM pin AVDD/2
0.1μF
AVDD pin
2.2μF
0.1μF
VSS2 pin
VCOM pin
VREFH,VCOM pin
3.
ADC
SGL pin
14k (typ) VCOM(AVDD1x1/2)
0.68 x VREFH
Vpp (typ)@fs=48kHz
32k (typ) VCOM
LIN(RIN)+
LIN(RIN)−
0.68 x VREFH Vpp (typ)@fs=48kHz
AK4629 VSS1
AVDD1
2’s
(2
)
DC
HPF
AK4629 64fs
64fs
AK4629 64fs
(RC
)
MS1277-J-02
2012/03
- 41 -
[AK4629]
4.
DAC
2’s
800000H(@24bit)
(
VCOM
0.6xVREFH Vpp(typ)
(2
)
7FFFFFH(@24bit)
000000H(@24bit)
VCOM
)
(SCF)
(CTF)
LSI
DC
VCOM
mV
5.
±3.4Vpp
Analog In
3.4Vpp
AIN+
2.2uF+- 50%
AK4629
Analog In
3.4Vpp
AIN2.2uF +- 50%
Figure 33. Input buffer circuit example 1 (AC coupled
)
3.4Vpp
Analog In
3.4Vpp
AIN+
2.2uF +- 50%
Open
Figure 34. Input buffer circuit example 2 (AC coupled
MS1277-J-02
AK4629
AIN-
)
2012/03
- 42 -
[AK4629]
6.
I/F
AK4629 TTL
3.3V(typ)
3.3V(typ)
Figure 35
I/F
3.3V Analog
(TVDD) 3.3V
5V for input
3.3V 5V
3.3V Digital
Audio signal
PLL
I/F
DSP
AK4113
5V Analog
3.3V for output
5V Digital
uP &
Others
Analog Digital
Control signal
AK4629
Figure 35.
MS1277-J-02
2012/03
- 43 -
[AK4629]
48pin LQFP(Unit: mm)
1.70Max
9.0
0.13 ± 0.13
7.0
36
1.40 ± 0.05
24
48
13
7.0
37
1
9.0
25
12
0.09 ∼ 0.20
0.22 ± 0.08
0.5
0.10 M
0° ∼ 10°
S
0.10 S
0.30 ~ 0.75
■
:
:
:
(
)
MS1277-J-02
2012/03
- 44 -
[AK4629]
AK4629VQ
XXXXXXX
1
1) Pin #1 indication
2) Date Code: XXXXXXX(7 digits)
3) Marking Code: AK4629VQ
4) Asahi Kasei Logo
Date (YY/MM/DD)
11/01/26
11/08/29
Revision
00
01
Reason
Page
Contents
7
8
ADC Analog Input Characteristics (Single-ended Inputs)
S/(N+D), fs=48kHz: 92 → 96dB (typ)
fs=96kHz: 86 → 92dB (typ)
DR, fs=96kHz: 96 → 99dB (typ)
fs=96kHz, A-weighted: 102 → 105dB (typ)
S/N: fs=96kHz: 96 → 99dB (typ)
fs=96kHz, A-wieghted: 102 → 105dB (typ)
ADC Analog Input Characteristics (Differential Inputs)
S/(N+D), fs=48kHz: 92 → 96dB (typ)
fs=96kHz: 86 → 94dB (typ)
DR, fs=96kHz: 97 → 100dB (typ)
fs=96kHz, A-weighted: 103 → 106dB (typ)
S/N: fs=96kHz: 97 → 100dB (typ)
fs=96kHz, A-wieghted: 103 → 106dB (typ)
DAC Analog Output Characteristics
S/(N+D), fs=48kHz: 90 → 98dB (typ)
fs=96kHz: 88 → 98dB (typ)
fs=192kHz: 88 → 98dB (typ)
MS1277-J-02
2012/03
- 45 -
[AK4629]
Date (Y/M/D)
12/03/07
Revision
02
Reason
Page
3
9
Contents
■
AK4629 → AK4629VQ
DC
High-level Output Voltage
:
SDTO1-2, LRCK, BICK pins → SDTO1-2 pins
Low-level Output Voltage
:
SDTO1-2, LRCK, BICK, DZF1, DZF2 pins
→ SDTO1-2, DZF1, DZF2 pins
z
z
z
z
z
z
MS1277-J-02
2012/03
- 46 -