[AK4104] AK4104 192kHz 24-Bit 3.3V DIT AK4104 192kHz IEC60958, S/PDIF, EIAJ CP1201 (DIT) AK4104 AK4104 AES3, 8 192kHz AES3, IEC60958, S/PDIF, EIAJ CP1201 & 42 : 128/192/256/384/512/768/1024/1536fs : / /I2S 4 3 CMOS : 2.7 ∼ 3.6V : 16 TSSOP Ta: -20 ∼ 85 °C MS0642-J-01 2010/09 -1- [AK4104] ■ MCLK CSN CCLK CDTI µP Interface VDD Prescaler VSS CDTO SDTI1 LRCK BICK Audio Data Interface Biphase Encoder TX PDN Figure 1. AK4104 Block Diagram (MODE bit = “0”) MCLK CSN CCLK CDTI µP Interface VDD Prescaler VSS SDTI2 SDTI1 LRCK Audio Data Interface Biphase Encoder TX BICK PDN Figure 2. AK4104 Block Diagram (MODE bit = “1”) MS0642-J-01 2010/09 -2- ASAHI KASEI [AK4104] ■ −20 ∼ +85°C AK4104 AK4104ET AKD4104 16pin TSSOP (0.65mm pitch) ■ MCLK 1 16 TX BICK 2 15 CDTO/ SDTI2 SDTI1 3 14 VDD LRCK 4 13 VSS PDN 5 12 TEST4 CSN 6 11 TEST3 CCLK 7 10 TEST2 CDTI 8 9 TEST1 AK4104 Top View MS0642-J-01 2010/09 -3- ASAHI KASEI No. 1 2 3 4 Pin Name MCLK BICK SDTI1 LRCK [AK4104] I/O I I I I 5 PDN I 6 7 8 CSN CCLK CDTI I I I 9 TEST1 I 10 TEST2 O 11 TEST3 O 12 TEST4 O 13 14 VSS VDD CDTO SDTI2 O I TX O 15 16 Function Master Clock Input Pin Audio Serial Data Clock Pin Audio Serial Data Input 1 Pin Input Channel Clock Pin Power Down and Reset Pin “L”: Power down and Reset, “H”: Power up Chip Select Pin Control Data Clock Pin Control Data Input Pin TEST Pin This pin should be connected to VDD. TEST Pin This pin should be OPEN. TEST Pin This pin should be OPEN. TEST Pin This pin should be OPEN. Ground Pin Power Supply Pin, 2.7 ∼ 3.6V Control Data Output Pin, The output is “Hi-Z” when PDN pin = “L”. Audio Serial Data Input 2 Pin Transmit Channel Output Pin, The output is “L” when PDN pin = “L” or RSTN bit =“0” or PW bit = “0” or MCLK stops. MS0642-J-01 2010/09 -4- ASAHI KASEI [AK4104] (VSS = 0V; Note 1) Parameter Power Supply Input Current, Any Pin Except Supplies Digital Input Voltage Symbol VDD IIN min −0.3 - VIND −0.3 (Note 2) −20 −65 Ambient Temperature (Powered applied) Ta Storage Temperature Tstg Note 1. Note 2. MCLK, BICK, SDTI1, LRCK, PDN, CSN, CCLK, CDTI, SDTI2 max 4.6 ±10 VDD+0. 3 85 150 Units V mA V °C °C : (VSS = 0V; Note 1) Parameter Power Supply Note 1. Symbol VDD min 2.7 typ 3.3 max 3.6 Units V : DC (Ta = 25°C; VDD = 2.7 ∼ 3.6V) Parameter Power Supply Current (Note 3) Normal Operation (PDN pin = “H”, fs=44.1kHz) (Note 3) Full power-down mode (PDN pin = “L”) (Note 4) High-Level Input Voltage Low-Level Input Voltage Symbol VIH VIL min 70%VD D VDD-0.4 - typ max Units 0.9 10 - 1.8 50 30%VD D 0.4 ± 10 mA μA V V VOH1 High-Level Output Voltage (Iout=-80μA) VOL1 Low-Level Output Voltage (Iout=80µA) Input Leakage Current Iin Note 3. TX pin: VDD = 3.3V = 1.0mA(typ)@fs = 48kHz, 1.4mA(typ)@fs = 96kHz 2.6mA(typ)@fs = 192kHz PDN= “L” VSS 10μA(typ) TX pin: 20pF , VDD = 3.3V IDD = 3.3mA(typ)@fs = 192kHz Note 4. VDD VSS V V µA TX (Ta = 25°C; VDD = 2.7 ∼ 3.6V) Parameter High-Level Output Voltage ( Iout=-400μA) Low-Level Output Voltage ( Iout=400μA) Load Capacitance Symbol VOH2 VOL2 CL MS0642-J-01 min VDD-0.4 - typ - max 0.4 50 Units V V pF 2010/09 -5- ASAHI KASEI (Ta = 25°C; VDD = 2.7 ∼ 3.6V, CL = 20pF) Parameter Master Clock Frequency Frequency Duty Cycle LRCK Frequency Frequency Duty Cycle Audio Interface Timing BICK Period BICK Pulse Width Low Pulse Width High BICK “↑” to LRCK Edge (Note 5) LRCK Edge to BICK “↑” (Note 5) SDTI Hold Time SDTI Setup Time Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” CDTO Delay CSN “↑” to CDTO Hi-Z Power-Down & Reset Timing PDN Pulse Width (Note 6) Note 5. LRCK BICK “↑” Note 6. PDN pin = “L” AK4104 [AK4104] Symbol min fCLK dCLK max Units 2.048 40 36.864 60 MHz % fs dCLK 8 45 192 55 kHz % tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 81 30 30 20 20 20 20 ns ns ns ns ns ns ns tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ 200 80 80 40 40 150 150 50 ns ns ns ns ns ns ns ns ns ns tPD 150 MS0642-J-01 typ 45 70 ns 2010/09 -6- ASAHI KASEI [AK4104] ■ 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Figure 3. Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDH tSDS VIH SDTI VIL Figure 4. Serial Interface Timing MS0642-J-01 2010/09 -7- ASAHI KASEI [AK4104] VIH CSN VIL tCSS tCCK tCCKL tCCKH VIH CCLK VIL tCDH tCDS CDTI C1 C0 A4 R/W VIH VIL Hi-Z CDTO Figure 5. WRITE/READ Command Input Timing in 3-wire/4-wire serial mode tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 VIH D0 VIL Hi-Z CDTO Figure 6. WRITE Data Input Timing in 3-wire/4-wire serial mode VIH CSN VIL VIH CCLK VIL CDTI A1 VIH A0 VIL tDCD CDTO Hi-Z D7 D6 D5 50%VDD Figure 7. READ Data Output Timing 1 in 4-wire serial mode MS0642-J-01 2010/09 -8- ASAHI KASEI [AK4104] tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI VIL tCCZ CDTO D3 D2 D1 D0 Hi-Z 50%VDD Figure 8. READ Data Output Timing 2 in 4-wire serial mode tPD PDN VIL Figure 9. Power-Down & Reset Timing MS0642-J-01 2010/09 -9- ASAHI KASEI [AK4104] ■ ■ MCLK LRCK MCLK 128fs 192fs 256fs 384fs 512fs 768fs 1024fs 1536fs Fs 16k-192kHz 16k-192kHz 8k-128kHz 8k-96kHz 8k-48kHz 8k-48kHz 8k-32kHz 8k-24kHz Table 1. MCLK Frequency MS0642-J-01 2010/09 - 10 - ASAHI KASEI [AK4104] ■ BICK Mode3 I2S Compatible format Mode 0 1 2 3 LRCK MSB ≥ 48fs SDTI 2’s complement BICK=32fs DIF1 0 0 1 1 4 (Table 2) BICK LSB DIF0 SDTI Format 0 16bit, LSB justified 1 24bit, LSB justified 0 24bit, MSB justified 1 16/24bit, I2S Compatible Table 2. Audio Interface Format DIF1-0 pin “0” 16bit, BICK ≥ 32fs ≥ 48fs ≥ 48fs ≥ 48fs or 32fs Figure Figure 10 Figure 11 Figure 12 Figure 13 LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 0 1 2 3 17 18 19 20 31 0 1 2 3 7 6 5 4 3 2 1 0 15 17 18 19 20 31 0 1 BICK(64fs) SDTI(i) Don't Care 15 14 13 12 1 0 Don't Care 15 14 13 12 2 1 0 SDTI-15:MSB, 0:LSB Lch Data Rch Data Figure 10. Mode 0 Timing LRCK 0 1 2 8 9 24 31 0 1 2 8 9 24 31 0 1 BICK(64fs) SDTI(i) 23 Don't Care 8 1 0 Don't Care 23 8 1 0 23:MSB, 0:LSB Lch Data Rch Data Figure 11. Mode 1 Timing LRCK 0 1 2 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1 BICK(64fs) SDTI(i) 23 22 4 3 2 1 0 Don't Care 23 22 4 3 2 1 0 Don't Care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 12. Mode 2 Timing MS0642-J-01 2010/09 - 11 - ASAHI KASEI [AK4104] LRCK 0 1 2 3 21 22 23 24 25 0 1 2 21 22 23 24 25 0 1 BICK(64fs) SDTI(i) 23 22 4 3 2 1 0 Don't Care 23 22 4 3 2 1 0 Don't Care 23:MSB, 0:LSB Lch Data Rch Data Figure 13. Mode 3 Timing ■ DIT AK4104 μP I/F 4 μP I/F MODE 0 1 1 1 1 (MODE bit = “0”) SDTI1 SEL1 x 0 0 1 1 3 μP I/F SDTI2 data SEL0 x 0 1 0 1 μP I/F 4-wire 3-wire 3-wire 3-wire Reserved (MODE bit = “1”) 3 DIT input SDTI1 SDTI1 SDTI2 SDTI2:DIT Bypass (x: Don’t care) Table 3. DIT Input MS0642-J-01 2010/09 - 12 - ASAHI KASEI [AK4104] ■ TX Figure 14 192 2 32 2 0 Figure 15 1 16 8 M Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1 W Channel 2 Sub-frame Frame 191 Sub-frame Frame 0 Frame 1 Figure 14. 0 1 1 0 0 0 1 0 Figure 15. Figure 16 0-3 3 (B) 1 (M) 0 (W) 1 2 2 Table 4 27 MSB 2 0 4-27 16 28 29 24 4-11 “H” 192 0 191 192 31 191 0 0 1 30 0 4-31 3 4 L S Sync B Audio sam ple 27 28 29 30 31 M S V U C P B Figure 16. (fs) L 64 A 1 2 Preamble B M W Preceding state = 0 11101000 11100010 11100100 R B 1 Preceding state = 1 00010111 00011101 00011011 Table 4. MS0642-J-01 2010/09 - 13 - ASAHI KASEI [AK4104] bit0 = “0” AK4104 bits20-23= “0100” bits20-23= “0000” bits20-23(audio channel) CT20 bit bits20-23 = “1000” CT20 bit = “0” CT20 bit = “1” 2 2 1 ■ AK4104 4 I/F (MODE bit = “0”) 3 I/F (MODE bit = “1”) 1. 4 (MODE bit = “0”,default) 4 I/F pin(CSN,CCLK,CDTI,CDTO) I/F Chip address(2bits, C1/0; “11” ), Read/Write(1bit), Register address(MSB first, 5bits) Control data(MSB first, 8bits) CCLK “↓” “↑” CCLK 16 “↑” CCLK 16 CSN “H” CSN “↑” Hi-Z CCLK 5MHz (max) PDN pin= “L” CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 WRITE Hi-Z CDTO CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 READ Hi-Z CDTO C1-C0: R/W: A4-A0: D7-D0: D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z Chip Address: (Fixed to “11”) READ/WRITE (0:READ, 1:WRITE) Register Address Control Data Figure 17. 4-wire μP I/F Timing *AK4104 (PDN pin = “L”) MCLK MS0642-J-01 2010/09 - 14 - ASAHI KASEI [AK4104] 2. 3 (MODE bit = “1”) 3 I/F pin(CSN,CCLK,CDTI) I/F Chip address(2bits, C1/0; “11” ), Read/Write(1bit, “1” , ), Register address(MSB first, 5bits) Control data(MSB first, 8bits) CCLK “↑” “↓” CCLK 16 CCLK 16 CSN “H” CCLK 5MHz (max) PDN pin= “L” PDN pin = “L” RSTN bit CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (Fixed to “11”) READ/WRITE (Fixed to “1”, Write only) Register Address Control Data Figure 18. 3-wire μP I/F Timing *AK4104 *AK4104 3 (PDN pin = “L”) Chip address C1/0 MCLK MS0642-J-01 R/W “011” 2010/09 - 15 - ASAHI KASEI ■ [AK4104] Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 1 1 0 0 0 DIF1 DIF0 PW RSTN 01H 02H Reserved Control 2 0 0 1 0 0 0 1 0 1 0 0 MODE 1 SEL1 1 SEL0 03H TX 1 0 0 0 0 0 V TXE 04H 05H 06H 07H 08H 09H Channel Status Byte0 Channel Status Byte1 Channel Status Byte2 Channel Status Byte3 Channel Status Byte4 Channel Status Byte5 CS7 CS15 CS23 CS31 CS39 0 CS6 CS14 CS22 CS30 CS38 0 CS5 CS13 CS21 CS29 CS37 0 CS4 CS12 CS20 CS28 CS36 0 CS3 CS11 CS19 CS27 CS35 0 CS2 CS10 CS18 CS26 CS34 0 CS1 CS9 CS17 CS25 CS33 CS41 CS0 CS8 CS16 CS24 CS32 CS40 Notes: 0AH∼1FH PDN pin = “L” RSTN bit = “0” “0” PW “0” “1” RSTN bit = “0” “1” ■ Addr 00H Register Name Control 1 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 DIF1 DIF0 PW RSTN 1 1 1 1 R/W R/W Default 1 0 0 0 RSTN: 0: 1: PW: 0: 1: DIF1-0: (Table 2) Default: “11”, Mode 3 MS0642-J-01 2010/09 - 16 - ASAHI KASEI [AK4104] Register Name 02H Control 3 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 MODE SEL1 SEL0 0 0 0 0 0 R/W R/W Default 0 0 0 MODE: 0: 4 1: 3 SEL1-0: DIT 00: SDTI1 01: SDTI2 10: SDTI2 11: Reserved (NOTE) SEL1-0 bits 4 Register Name 03H TX (DIT Bypass) (MODE bit = “0”) D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 V TXE 0 0 0 1 R/W R/W Default 1 0 0 0 V: 0: Valid 1: Invalid TXE: TX 0: “L” 1: Register Name 04H Channel Status Byte0 Default 05H Channel Status Byte1 Default D7 D6 D5 D4 D3 D2 D1 D0 CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 0 0 0 0 0 1 0 0 CS15 CS14 CS13 CS12 CS11 CS10 CS9 CS8 0 0 0 0 0 0 0 0 CS23 CS22 CS21 CS20 CS19 CS18 CS17 CS16 06H Channel Status Byte2 0 0 0 0 0 0 0 0 07H Channel Status Byte3 CS31 CS30 CS29 CS28 CS27 CS26 CS25 CS24 Default Channel Status Byte4 Default Channel Status Byte5 Default 0 CS39 0 0 0 0 CS38 0 0 0 0 CS37 0 0 0 0 CS36 0 0 0 0 CS35 0 0 0 0 CS34 0 0 0 0 CS33 0 CS41 0 0 CS32 0 CS40 0 Default 08H 09H CS7-0: Transmitter Channel Status Byte 0 Default: “00000100” CS39-8: Transmitter Channel Status Byte 4-1 Default: “00000000” CS41-CS40: Transmitter Channel Status Byte 5 Default: “00000000”, D7-D2 bits should be written “1”. MS0642-J-01 2010/09 - 17 - ASAHI KASEI Figure 19 [AK4104] Figure 20 4-wire serial mode (AKD4104) Master Clock 1 MCLK 64fs 2 BICK 24bit Audio Data 3 SDTI1 fs Reset & Power down Micro Controller 3-wire serial mode TX Optic transmitting module 16 CDTO 15 VDD 14 0.1u 4 LRCK VSS 13 5 PDN TEST4 12 6 CSN TEST3 11 7 CCLK TEST2 10 8 CDTI TEST1 9 AK4104 + 10u Analog Supply 2.7 to 3.6V Figure 19. Typical Connection Diagram (MODE bit = “0”, 4 wire mode ) 24bit Audio Data2 Master Clock 1 MCLK 64fs 2 BICK 3 SDTI1 24bit Audio Data1 fs Reset & Power down Micro Controller TX 16 SDTI2 15 VDD 14 Optic transmitting module 0.1u 4 LRCK VSS 13 5 PDN TEST4 12 6 CSN TEST3 11 7 CCLK TEST2 10 8 CDTI TEST1 9 AK4104 + 10u Analog Supply 2.7 to 3.6V Figure 20. Typical Connection Diagram (MODE bit = “1”, 3 wire mode ) MS0642-J-01 2010/09 - 18 - ASAHI KASEI [AK4104] 16pin TSSOP (Unit: mm) 1.1 (max) *5.0±0.1 16 9 8 1 0.13 M 6.4±0.2 *4.4±0.1 A 0.65 0.22±0.1 0.17±0.05 Detail A 0.5±0.2 0.1±0.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° ■ MS0642-J-01 2010/09 - 19 - ASAHI KASEI [AK4104] AKM 4104ET XXYYY 1) 2) 3) 4) Date (YY/MM/DD) 07/10/15 10/09/28 Revision 00 01 Reason Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4104ET Asahi Kasei Logo Page Contents 19 MS0642-J-01 2010/09 - 20 - ASAHI KASEI [AK4104] z z z z z z MS0642-J-01 2010/09 - 21 -