AK7722 Japanese Datasheet

[AK7722]
AK7722
24bit 4ch ADC + 24bit 4ch DAC with Audio DSP
AK7722 4ch 24
DAC
4ch DAC 108dB
2chADC 95dB
DSP
DSP 1536step/fs (48kHz
)
RAM
DSP
80pin LQFP
1
ADC 2ch
ADC
2ch ADC 96dB
3
5kword
SRC
RAM
DSP
[ADC
[ADC
: 24-bit (F24
)
: 13.6ns ( 1536step/fs fs=48kHz)
: 20 x 24
44-bit
: 20 / 20
20-bit
- ALU: 48bit
(overflow margen 4bit) 20bit
RAM:
3072 x 36-bit
RAM:
2048 x 24-bit (F24
)
RAM:
2048 x 24-bit (F24
)
: 64 x 13-bit
RAM1:
3072 x 24-bit
RAM2:
2048 x 24-bit
: fs= 7.35k ~ 48kHz
: 1536fs
PLL
32fs, 48fs, 64fs, 128fs, 256fs, 384fs
/
ADC1]
6
- DR, S/N: 96dB
(fs=48kHz,
)
- S/(N+D): 90dB
(fs=48kHz)
HPF (fc=1Hz)
-6
(2
,4
)
(24dB -103dB,0.5dB Step, Mute)
ADC2]
- DR, S/N: 95dB
(fs=48kHz)
(24dB -103dB,0.5dB Step, Mute)
[SRC ]
-3
- 2ch x 1
-
MS1328-J-00
1
Fin = 7.35kHz ~ 96kHz
(FSO/FSI = 0.167~ 6.0
- 1 -
Fout = 7.35kHz ~ 48kHz
)
2011/09
[AK7722]
[
SRC GSRC]
-1
(24bit
)
Fin = 7.35kHz ~ 12kHz
Fout = 44.1kHz or 48kHz
[DAC ]
- 4ch (
2
)
- 24bit 128 x Over-sampling advanced multi-bit (fs=8kHz~48kHz
- DR, S/N: 108dB
- S/(N+D): 90dB
(12dB -115dB,0.5dB Step, Mute)
[
(4ch)
(6ch)
24bit/
24bit/
24, 20, 16bit
24, 16bit
)
I2S
IS
2
]
- I2C
or 4
- PLL
- 3.3V
1.8V
: 3.3V ± 0.3V
: -40
85
- 80pin LQFP
MS1328-J-00
- 2 -
2011/09
[AK7722]
■
LFLT
2 DVDD
pull down
Hi-z
XTO
2
3 VSS2
Open Drain
3 AVDD
3 VSS3
XTI
REF
BICKI
LRCKI
VCOM
LDO
AVDRV
CLKGEN & CONT
TESTI1
TESTI2
DVOL
IRESETN
ADC2
2 A2INL,A2INR
SDOUTAD2
CLKOE
CLKO
ASEL[2:0]
DVOL
BICKOE
BICKO
LRCKOE
LRCKO
SDOUTAD1
SELDI5
1
0
SDIN5
2 AIN5L,AIN5R
2 AIN4L,AIN4R
2 AIN3L,AIN3R
2
DIN5
0
MUX[2:0]
DVOL DAC2
SELDO5[1:0]
SELDI4
0
1
SRIN2
3
2
0
SDINDA2
2
MUX2[2:0]
SRCBICKI
DOUT4
0
DVOL DAC1
MUX2
SDINDA1
2
AOUT1LP
AOUT1LN
AOUT1RP
AOUT1RN
1
SRCI
3
SRCLFLT
UNLOCK
SRCO
SELDO4[1:0]
DOUT3
0
1
SRIN1
DIN3
IRPT
OUT3E
DOUT2
SDOUT3 / IRPT
2
3
DIN1
SDIN1
0
1
SELDI3
SELDO3[1:0]
0
OUT2E
SDOUT2
1
SDIN2 / JX1
2
DIN2
JX1E
JX0
3
SELDO2[1:0]
JX1
JX0
SRIN3
AOUT2LP
AOUT2LN
3
DSP
SRC
1
3
AIN1RP,AIN1RN
AOUT2RP
AOUT2RN
1
DIN4
SRCLRCKI
3
AIN2LP,AIN2LN
4 AIN2RP,AIN2RN
4 AIN1LP,AIN1LN
0
DOUT5
DSEL[1:0]
SRIN1,SRBICK1
SRLRCK1
SRCLFLT
UNLOCK
2 AIN6L,AIN6R
4
3
MUX1
GSRC
GLRCKI
SRIN2,SRBICK2
SRLRCK2
5
1
GBICKI
SRIN3,SRBICK3
SRLRCK3
ADC1
DOUT1
0
OUT1E
1
JX2E
JX2
SDOUT1 / GP0
2
GP0
3
SELDO1[1:0]
WDTEN
WDT
CRC
STO
MICIF
CRCE
GP1
RDY
SO
RDY
SO
I2CSEL
RQN / CAD1
SI / CAD0
SCLK / SCL
SDA
GP1
Figure 1.
Figure 1.
MS1328-J-00
AK7722
- 3 -
2011/09
[AK7722]
CP0,CP1
DRAM
2048w 24-Bit
CRAM
2048W
DLP0,DLP1
DP0,DP1
24-Bit
DLRAM1:3072W
24-Bit
DLRAM2:2048W
24-Bit
OFREG
64w 13-Bit
CBUS(24-Bit)
DBUS(24-Bit)
MPX24
Micon I/F
MPX20
X
Control
PRAM
DEC
Y
3072w
Multiply
24
20
44-Bit
Serial I/F
36-Bit
PC
Stack : 5level(max)
24-Bit
44-Bit
TMP 12
24-Bit
PTMP(LIFO) 6 24-Bit
MUL
DBUS
SHIFT
48-Bit
44-Bit
A
B
ALU
48-Bit
2
24(,16)-Bit
DIN5 (ADC2 or GSRC)
2
24(,16)-Bit
DIN4 (ADC1)
2
24,20,16-Bit
DIN3 (SRC)
2
24,20,16-Bit
DIN2
2
24,20,16-Bit DIN1
2
24,20,16-Bit
DOUT5(DAC2)
2
24,20,16-Bit
DOUT4(DAC1)
2
24,20,16-Bit
DOUT3
2
24,20,16-Bit
DOUT2
2
24,20,16-Bit
DOUT1
Overflow Margin: 4-Bit
48-Bit
DR0 ∼ 3
48-Bit
Over Flow Data
Generator
Division 20÷20 20
Peak Detector
Figure 2. AK7722
MS1328-J-00
DSP
4
2011/09
[AK7722]
■
-40 ∼ +85°C
80pin LQFP
Evaluation Board for AK7722
AK7722VQ
AKD7722
SDOUT1 / GP0
SDOUOT2
SDOUT3 / IRPT
STO
SRLRCK2
SRIN2
SRBICK2
SRLRCK3
SRBICK3
SRIN3
UNLOCK
I2CSEL
INITRSTN
TESTI2
AVDRV
VSS4
DVDD
SRCLFLT
VSS5
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AVDD
■
AOUTR2N
AOUTR2P
61
62
40
39
BICKO
AOUTL2N
63
38
CLKO
AOUTL2P
64
37
VSS3
AOUTR1N
AOUTR1P
65
66
36
35
DVDD
AOUTL1N
67
34
SO
AOUTL1P
68
69
33
32
SI / CAD0
31
RQN / CAD1
AVDD
VCOM
VSS6
A2INR
80 pin LQFP
70
71
LRCKO
SDA
SCLK / SCL
30
RDY
29
28
SRIN1
A2INL
72
73
AINR6
74
27
SRLRCK1
AINL6
26
25
SDIN2 / JX1
AINR5
75
76
BICKI
(TOP VIEW)
SRBICK1
SDIN1
AINL5
77
24
AINR4
78
23
LRCKI
AINL4
79
80
22
21
JX0
GP1
XTO
XTI
VSS2
DVDD
SDIN5
GBICK
TESTI1
GLRCK
VSS1
LFLT
AVDD
AINL1P
AINR1P
AINL1N
AINR1N
AINL2P
AINR2P
AINL2N
AINL3
AINR2N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AINR3
pin
Input
Output
I/O
Power
MS1328-J-00
5
2011/09
[AK7722]
No.
1
2
3
4
5
6
7
8
9
10
11
I/O
AINL3
AINR2N
AINR2P
AINL2N
AINL2P
AINR1N
AINR1P
AINL1N
AINL1P
AVDD
VSS1
I
I
I
I
I
I
I
I
I
O
12 LFLT
ADC1 Lch
ADC1 Rch
ADC1 Rch
ADC1 Lch
ADC1 Lch
ADC1 Rch
ADC1 Rch
ADC1 Lch
ADC1 Lch
3
2
2
2
2
1
1
1
1
3.0 3.6V
0V
PLL R,C
LFLT Pin
“L”
13 TESTI1
14
15
16
17
18
GLRCKI
GBICKI
SDIN5
DVDD
VSS2
I
1
18pin VSS2
I
I
I
-
19 XTI
I
20 XTO
O
3.0~3.6V
0V
XTI pin XTO pin
XTI pin
XTI pin XTO pin
Hi-Z
21 GP1
bit
O
“L”
0
22 JX0
I
JX0E bit = “1”
JX0
LR
1
LR
23 LRCKI
I
24 BICKI
I
1
BITCLOCK(48fs or 64fs)
25 SDIN1
SDIN2
I
I
1
2
26
1
JX1
I
27 SRLRCK1
I LR
28 SRBICK1
I
MS1328-J-00
JX1E bit = “1”
1
JX1
(SRC )
1
(SRC )
6
2011/09
[AK7722]
No.
29 SRIN1
SDIN3
I/O
I
I
30 RDY
O
RQN
I
CAD1
RQN pin =“H”
I I2CSEL pin = “H” I2C
I I2CSEL pin = “L”
31
32
(SRC )
RDY
I2CSEL pin = “L”
IF
”H”
N
IF
I 2C
1
IF
SCLK
SCLK pin = “H”
SCL
33
1
3
I I2CSEL pin = “H”
I I2CSEL pin = “L”
I2C
I 2C
IF
SI
SI pin= “L”
CAD0
34 SO
I I2CSEL pin = “H” I2C
I 2C
0
O
IF
“L”
O I2CSEL pin = “L”
35 SDA
SDA “L”
I/O I2CSEL pin = “H” I2C
I 2C
“Hi-Z”
36 DVDD
37 VSS3
-
38 CLKO
O
39 LRCKO
O
40 BICKO
O
SDOUT1
O
GP0
O
42 SDOUT2
O
41
SDOUT3
43
3.0~3.6V
0V
“L”
LR
O
IRPT
O
44 STO
O
45 SRLRCK2
I LR
46 SRBICK2
I
47
SRIN2
SDIN4
48 SRLRCK3
MS1328-J-00
“L”
“L”
1
“L”
bit
2
“L”
3
“L”
”H”
2
(SRC )
2
I
I
2
(SRC )
4Pin
I LR
3
(SRC )
(SRC )
7
2011/09
[AK7722]
No.
I/O
49 SRBICK3
I
SRIN3
I
I
50
3
3
(SRC )
(SRC )
2
JX2E bit = 1
JX2
51 UNLOCK
O SRC UNLOCK
52 INITRSTN
I
pin JX2
”H”
N
(
SRC
)
AK7722
”L”
2
55 AVDRV
I CBUS
I2CSEL pin =“L”: 4
I
I2CSEL pin =“H”: I2C
SCL, SDA
I2CSEL
“L(VSS)”, “H(DVDD)”
2
(
)
I
56pin (VSS4)
O AVDRV Pin
1μF
56pin(VSS4)
56 VSS4
57 DVDD
-
53 I2CSEL
54 TESTI2
I2C
“L”
58 SRCLFLT
59 VSS5
60 AVDD
61 AOUTR2N
62 AOUTR2P
3.0~3.6V
SRCPLL C
C=1µF 56pin(VSS4)
O
“L”
0V
3.0 3.6V
DAC2 Rch
O
O
63 AOUTL2N
O
64 AOUTL2P
O
65 AOUTR1N
O
66 AOUTR1P
O
67 AOUTL1N
O
68 AOUTL1P
O
69 AVDD
O
70 VCOM
MS1328-J-00
0V
“Hi-Z”
DAC2 Rch
“Hi-Z”
DAC2 Lch
“Hi-Z”
DAC2 Lch
“Hi-Z”
DAC1 Rch
“Hi-Z”
DAC1 Rch
“Hi-Z”
DAC1 Lch
“Hi-Z”
DAC1 Lch
“Hi-Z”
3.0 3.6V
0.1μF
2.2μF
71pin(VSS6)
“L”
8
2011/09
[AK7722]
No.
71
72
73
74
75
76
77
78
79
80
I/O
I
I
I
I
I
I
I
I
I
VSS6
A2INR
A2INL
AINR6
AINL6
AINR5
AINL5
AINR4
AINL4
AINR3
0V
ADC2 Rch
ADC2 Lch
ADC1 Rch
ADC1 Lch
ADC1 Rch
ADC1 Lch
ADC1 Rch
ADC1 Lch
ADC1 Rch
6
6
5
5
4
4
3
■
Classification
Analog
Digital
Pin Name
ANL1P, AINL1N, AINR1P, AINR1N, AINL2P, AINL2N, AINR2P
AINR2N, AINL3, AINR3, AINL4, AINR4, AINL5, AINR5, AINL6, AINR6
AOUTL1P, AOUTL1N, AOUTR1P, AOUTR1N
AOUTL2P, AOUTL2N, AOUTR2P, AOUTR2N
XTO, GP1, RDY, SO, SDA(I2CSEL= “L”), CLKO, LRCKO, BICKO, SDOUT1
SDOUT2, SDOUT3, STO, UNLOCK
TESTI1, GLRCK, GBICK, SDIN5, XTI, JX0, LRCKI, BICKI, SDIN1, SDIN2
SRLRCK1, SRBICK1, SRIN1, RQN, SI, SRLRCK2, SRBICK2, SRIN2,
SRLRCK3
SRBICK3, SRIN3, TESTI2
I2CSEL Pin
I2C
MS1328-J-00
Setting
VSS
SDA Pin
I2CSEL
L
L
H
H
INITRSTN
L
H
L
H
9
SDA
L
L
“Hi-Z”
function
2011/09
[AK7722]
(VSS1~VSS6=0V: Note 1)
Parameter
Analog
Digital
(
)
Symbol
min
max
Unit
AVDD
DVDD
IIN
VINA
VIND
Ta
Tstg
-0.3
-0.3
4.3
4.3
±10
AVDD+0.3
DVDD+0.3
85
150
V
V
mA
V
V
-0.3
-0.3
-40
-65
Note 1.
Note 2. VSS1-6
:
(VSS1~VSS6=0V: Note 1)
Parameter
Analog
Digital
Note 3. AVDD, DVDD
Note 4. I2C BUS
SCL pin
Symbol
min
typ
max
Unit
AVDD
DVDD
3.0
3.0
3.3
3.3
3.6
3.6
V
V
(I2CSEL pin = “H”)
SDA, SCL
DVDD
ON
DVDD
AK7722
OFF
SDA,
:
MS1328-J-00
10
2011/09
[AK7722]
(CODEC)
■
ADC
1. ADC1
(
Ta=25 ; AVDD=DVDD=3.3V, BITCLK=64fs;
1kHz;
[email protected]=48kHz; CKM mode0(CKM[2:0]=000); BITFS[1:0]=00(64fs); Differential
; SRC
Parameter
min
typ
max
24
ADC
S/(N+D) (-1dBFS)
82
88
88
90
(A-weighted) (Note 5)
S/N (A-weighted)
(fin=1kHz)
(Note 6)
(Note 7)
(Note 8)
Note 5. -60dBFS
Note 6. -1dBFS
Note 7.
Note 8.
±2.00
2.00
41
S/(N+D) (-1dBFS)
(A-weighted)
(Note 9)
S/N (A-weighted)
(fin=1kHz)
(Note 10)
80
87
87
90
2.00
41
(Note 11)
MS1328-J-00
90
96
96
110
dB
dB
dB
dB
0.0
0.3
dB
±2.20
2.20
62
±2.40
2.40
Vp-p
Vp-p
k
S/(N+D)
AINL, AINR
AINL1P, AINL1N, AINR1P, AINR1N, AINL2P, AINL2N, AINR2P, AINR2N
AINL3, AINR3, AINL4, AINR4, AINL5, AINR5, AINL6, AINR6
FS=AVDD 2.2/3.3
2. ADC2
(
Ta=25 ; AVDD=DVDD=3.3V, BITCLK=64fs;
[email protected]=48kHz; CKM mode0(CKM[2:0]=000), BITFS[1:0]=00(64fs); SRC
Parameter
min
ADC
Note 9. -60dBFS
Note 10. -1dBFS
Note 11.
=20Hz
)
Unit
Bits
1kHz;
)
typ
=20Hz
max
24
88
95
95
110
Unit
Bits
dB
dB
dB
dB
0.1
0.3
dB
2.20
62
2.40
Vp-p
k
S/(N+D)
AINL, AINR
FS=AVDD 2.2/3.3
11
2011/09
[AK7722]
■
DAC1/2
(
Ta=25 ; AVDD = DVDD=3.3V; VSS1~VSS6=0V;
=20Hz [email protected]; CKM[2:0]=000, BITFS[1:0]=00, SRC
Parameter
min
DAC1
DAC2
S/(N+D)
(0 dBFS)
(A-weighted) (Note 12)
S/N (A-weighted)
(f=1kHz)
82
98
98
90
1kHz;
)
typ
max
24
Unit
Bits
90
108
108
110
dB
dB
dB
dB
(Note 13)
(Note 14)
3.78
5
0.0
0.5
dB
4.16
4.53
Vp-p
k
pF
30
Note 12. -60dBFS
Note 13.
DAC
Note 14.
S/(N+D)
Lch-Rch
SRC
Ta=25°C; AVDD = DVDD=3.3V; VSS1~VSS6 =0V, data = 24bit; measurement bandwidth = 20Hz~
(
FSO/2)
Parameter
Resolution
Input Sample Rate
Output Sample Rate
THD+N
(Input= 1kHz, 0dBFS)
FSO/FSI=44.1kHz/48kHz
FSO/FSI=44.1kHz/96kHz
FSO/FSI=48kHz/44.1kHz
FSO/FSI=48kHz/96kHz
FSO/FSI=48kHz/8kHz
FSO/FSI=8kHz/48kHz
FSO/FSI=8kHz/44.1kHz
Dynamic Range (Input= 1kHz, -60dBFS)
FSO/FSI=44.1kHz/48kHz
FSO/FSI=44.1kHz/96kHz
FSO/FSI=48kHz/44.1kHz
FSO/FSI=48kHz/96kHz
FSO/FSI=48kHz/8kHz
FSO/FSI=8kHz/48kHz
FSO/FSI=8kHz/44.1kHz
Dynamic Range (Input= 1kHz, -60dBFS, A-weighted
FSO/FSI=44.1kHz/48kHz
Ratio between Input and Output Sample Rate
MS1328-J-00
Symbol
min
FSI
FSO
7.35
7.35
typ
-112
-104
-112
-112
-111
-113
-100
109
max
24
96
48
-103
113
113
113
113
112
113
113
12
0.167
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
115
FSO/FSI
Unit
Bits
kHz
kHz
6
dB
-
2011/09
[AK7722]
DC
(Ta=-40
85
Parameter
; AVDD=DVDD=3.0 3.6V)
(Note 15)
(Note 15)
SCL,SDA
SCL,SDA
Symbol
VIH
VIL
VIH
VIL
VOH
VOL
VOL
Iin
Iid
Iix
min
80%DVDD
MS1328-J-00
(
30%DVDD
typ
55
65
120
5
) (Note 20)
13
Unit
V
V
V
V
V
V
V
μA
μA
μA
70%DVDD
(Ta=25 ; AVDD=DVDD=3.0 3.6V(typ=3.3V , max=3.6V)
Parameter
min
(Note 19)
max
20%DVDD
DVDD-0.5
Iout=-100μA
Iout=100μA (Note 16)
SDA
Iout=3mA
(Note 17)
(Note 18)
XTI pin
Note 15. SCL, SDA pin
(SCLK pin
)
Note 16. SDA pin
Note 17.
XTI pin
Note 18.
(Typ150k ) TESTI1, TESTI2
AVDD
DVDD
AVDD+DVDD
INITRSTN pin= “L”
Note 19. DVDD
Note 20.
typ
0.5
0.4
10
22
26
max
180
Unit
mA
mA
mA
mA
2011/09
[AK7722]
■ ADC
(ADC1/2)
1. fs=48kHz
(Ta=-40 ~85 , AVDD=DVDD=3.0~3.6V, fs=48kHz) Note 21)
Parameter
Symbol
min
(±0.1dB)
(Note 22)
PB
0
(-0.2dB)
(-3.0dB)
SB
28
(Note 22)
PR
(Note 23, Note 24)
SA
68
GD
(Ts=1/fs)
GD
Note 21.
fs
Note 22.
fs=48kHz
Note 23.
fs=48kHz
Note 24. fs=48kHz
typ
max
18.9
20.0
23.0
±0.04
0
16
18.9kHz
3.044MHz
3.072MHz
(n x 3.072MHz ±28kHz; n=0, 1, 2, 3
Unit
kHz
kHz
kHz
kHz
dB
dB
μs
Ts
DC
28kHz
)
■ DAC1-2
(Ta=-40 ~85 ; AVDD=DVDD=3.0~3.6V; fs=48kHz)
Parameter
Symbol
(±0.05dB) (Note 25)
PB
(-6.0dB)
(Note 25)
SB
PR
SA
(Ts=1/fs)
(Note 26)
GD
min
0
MS1328-J-00
fs
max
21.7
24
26.2
±0.01
64
24
20Hz~20.0kHz
Note 25.
Note 26.
typ
PB=0.4535
14
±0.5
fs(@±0.05dB) SB=0.5465 fs
Unit
kHz
kHz
kHz
dB
dB
Ts
dB
2011/09
[AK7722]
■ SRC
(Ta=-40 ~85
Parameter
; AVDD=DVDD=3.0~3.6V)
0.980
0.900
0.450
0.225
0.167
0.980
0.900
0.450
0.225
0.167
0.225
0.167
(Ts=1/fs)
Note 27.
L, R
MS1328-J-00
FSO/FSI
FSO/FSI
FSO/FSI
FSO/FSI
FSO/FSI
FSO/FSI
FSO/FSI
FSO/FSI
FSO/FSI
FSO/FSI
FSO/FSI
FSO/FSI
6.000
0.990
0.910
0.455
0.227
6.000
0.990
0.910
0.455
0.227
0.455
0.227
(Note 27)
PB
PB
PB
PB
PB
SB
SB
SB
SB
SB
PR
PR
SA
GD
L, R
LRCLKO
15
min
0
0
0
0
0
0.5417FSI
0.5021FSI
0.2813FSI
0.1573FSI
0.1354FSI
typ
max
0.4583FSI
0.4167FSI
0.2177FSI
0.0917FSI
0.0917FSI
Unit
kHz
kHz
0.0100
0.0612
92.3
56
SRLRCKn
dB
dB
Ts
2011/09
[AK7722]
■
(Ta=-40 ~85 ; AVDD=DVDD=3.0~3.6V, VSS1~VSS6=0V)
Parameter
Symbol
min
XTI CKM[2:0]=000, 001, 010
a)
CKM[2:0]=000 fs=44.1kHz
fXTI
fs=48kHz
CKM[2:0]=001 fs=44.1kHz
fXTI
fs=48kHz
b)
40
CKM[2:0]=000, 010 fs=44.1kHz
fXTI
11.0
fs=48kHz
CKM[2:0]= 001 fs=44.1kHz
fXTI
16.5
fs-48kHz
fs
7.35
LRCKI
(Note 28)
Unit
typ
max
11.2896
12.288
16.9344
18.432
-
MHz
-
MHz
50
11.2896
12.288
16.9344
18.432
60
%
MHz
12.4
18.6
MHz
48
kHz
3.1
ns
ns
MHz
BICKI
Note 28. LRCKI
Note 29. BICKI
MS1328-J-00
tBCLKH
tBCLKL
fBCLK
(fs)
64
64
0.23
MCLK
3.072
LRCKI
16
2011/09
[AK7722]
■ SRC
(Ta=-40 ~85
Parameter
SRLRCKn
; AVDD=DVDD=3.0~3.6V; VSS1~VSS6=0V)
Symbol
min
fs
7.35
typ
max
96
Unit
kHz
3.072
6.144
MHz
ns
ns
typ
max
12
Unit
kHz
SRBICKn
0.23
32
32
fBCLK
tBCLKH
tBCLKL
■ GSRC
(Ta=-40 ~85
Parameter
GLRCK
; AVDD=DVDD=3.0~3.6V; VSS1~VSS6=0V)
Symbol
min
fs
7.35
GBICK
fBCLK
tBCLKH
tBCLKL
230
100
100
512
780
kHz
ns
ns
; AVDD=DVDD=3.0~3.6V)
Symbol
(Note 30)
tRST
“L”
min
600
typ
max
Unit
ns
■
(Ta=-40 ~85
Parameter
INITRSTN
Note 30.
MS1328-J-00
17
2011/09
[AK7722]
■
(SDIN1~2, SRIN1~3, SDOUT1~3)
(Ta=-40 ~85 ; AVDD=DVDD=3.0~3.6V, CL=20pF)
Parameter
DSP
SDIN1~2,SRIN1~3
BICKI “↑”
LRCKI
LRCKI
BICKI “↑”
(Note 31)
(Note 32)
(Note 32)
SRC
SRIN1-SRIN3
SRBICK1~3 “↑”
SRLRCK1~3
SRLRCK1~3
SRBICK1~3 “↑”
(Note 33)
(Note 34)
(Note 34)
Symbol
MS1328-J-00
typ
max
Unit
tBLRD
tLRBD
tBSIDS
tBSIDH
20
20
80
80
ns
ns
ns
ns
tBLRD
tLRBD
tBSIDS
tBSIDH
20
20
40
40
ns
ns
ns
ns
SDOUT1-3
(Note 31)
fBCLK
BICKO
BICKO
tBLRD
BICKO “↓”
LRCKO
(Note 35)
tLRD
LRCKI
(Note 36)
tBSOD
BICKI
(Note 33)
tLRD
LRCKO
(Note 36)
tBSOD
BICKO
(Note 33)
SDINn -> SDOUTn (n=1-2)
(Note 37)
tIOD
SDINn
SDOUTn
Note 31. CKM mode 4
BICKI=SRBICKn (n=1, 2, 3)
Note 32.
LRCKI
BICKI
BICKI
Note 33. CKM mode 4
Note 34.
SRLRCK1~3
SRBICK1~3
BIEDGE bit= “1”
SRBICK1~3
“ ”
Note 35.
SELBCK bit= “1”
BICKO
Note 36. I2S
Note 37. SDIN1
SDOUT1:
SDIN2/JX1
SDOUT2:
SRIN1/SDIN3
SDOUT3:
min
64
50
fs
-20
40
80
80
80
80
ns
ns
ns
ns
ns
60
ns
PCM mode 0/2
SRBICK1~3
BICKO “ ”
SELDO1[1:0]=1h,OUT1E=1
SELDO2[1:0]=1h,OUT2E=1
SELDI3=1,SELDO3[1:0]=1h,OUT3E=1
18
2011/09
[AK7722]
■
(Ta=-40 ~85
Parameter
; AVDD=DVDD=3.0 3.6V; CL=20pF)
Symbol
RQN
RQN
SCLK
SCLK
SCLK
SCLK
SCLK
AK7722
RQN
RQN “↓”
SCLK “↓”
SCLK “↑”
RQN “↑”
SI
SI
AK7722
SCLK “↓”
SO
SCLK
“↑”
SO
(Note 38)
Note 38.
min
typ
max
Unit
30
30
30
30
2.1
tWRF
tWRR
tSF
tSR
fSCLK
tSCLKL
tSCLKH
200
200
ns
ns
ns
ns
MHz
ns
ns
tWRQH
tWSC
tSCW
tSIS
tSIH
500
500
800
200
200
ns
ns
ns
ns
ns
tSOS
200
tSOH
ns
200
ns
8bit
■ I2CBUS
(Ta=-40 ~85 ; AVDD=DVDD=3.0~3.6V)
Parameter
I2C Timing
SCL clock frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first Clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed
by Input Filter
Capacitive load on bus
2
Note 39. I C-bus
MS1328-J-00
Symbol
Min
typ
max
Unit
400
fSCL
tBUF
1.3
kHz
μs
tHD:STA
0.6
μs
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
1.3
0.6
0.6
0
0.1
μs
μs
μs
μs
μs
μs
μs
μs
tSP
0.3
0.3
0.6
0
Cb
0.9
50
ns
400
pF
NXP B.V.
19
2011/09
[AK7722]
■
1/fXTI
1/fXTI
tXTI=1/fXTI
XTI
VIH
VIL
1/fs
ts=1/fs
1/fs
LRCKI
VIH
VIL
1/fBCLK
1/fBCLK
tBCLK=1/fBCLK
VIH
BICKI
VIL
tBCLKH
tBCLKL
Figure 3.
INITRSTN
tRST
VIL
Figure 4.
Note 40.
MS1328-J-00
INITRSTN pin = “L”
20
2011/09
[AK7722]
1)
VIH
VIL
LRCKI
tBLRD
tLRBD
VIH
VIL
BICKI
tBSIDS
tBSIDH
VIH
VIL
SDINn
n=1, 2
Figure 5. DSP
50%DVDD
LRCKO
tMBL
tMBL
BICKO
50%DVDD
tBSIDS
tBSIDH
VIH
VIL
SDINn
n=1, 2
Figure 6. DSP
VIH
VIL
SRLRCKn
tBLRD
tLRBD
VIH
VIL
SRBICKn
tBSIDS
tBSIDH
VIH
VIL
SRINn
Figure 7. SRC
MS1328-J-00
21
2011/09
[AK7722]
VIH
VIL
GLRCK
tBLRD
tLRBD
VIH
VIL
GBICK
tBSIDS
tBSIDH
VIH
VIL
SDIN5
Figure 8. GSRC
VIH
VIL
LRCKI
tLRD
VIH
VIL
BICKI
tBSOD
tLRD
SDOUTn
n=1, 2, 3
tBSOD
50%DVDD
Figure 9.
MS1328-J-00
22
2011/09
[AK7722]
2)
VIH
VIL
RQN
tWRF
tWRR
tSF
tSR
VIH
VIL
SCLK
tSCLKL
tSCLKH
1/fSCLK
1/fSCLK
INITRSTN
VIH
VIL
RQN
VIH
VIL
tRST
tIRRQ
Figure 10.
VIH
tWRQH
RQN
VIL
VIH
SI
VIL
tSIS
tSIH
VIH
SCLK
VIL
tWSC
tSCW
Figure 11.
MS1328-J-00
tWSC
tSCW
AK7722
23
2011/09
[AK7722]
VIH
SCLK
VIL
VIH
SO
VIL
tSOH
tSOS
Figure 12. AK7722
3) I2C
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
2
Figure 13. I C
MS1328-J-00
24
2011/09
[AK7722]
■
CKM[2:0]
AK7722
(
CKM[2:0]
bit
(ICLK)
)
CKM
Mode
CKM
[2:0]
Master
Slave
MCLK
0
1
2
3
4
000
001
010
011
100
Master
Master
Slave
Slave
Slave
XTI
XTI
XTI
BICKI
SRBICKIn
(Master)
(Slave)
ICLK
fs (Note 41, Note 42)
DFS[1:0] bits
DFS[1:0] bits
DFS[1:0] bits
DFS[1:0] bits
DFS[1:0] bits
MCLK
CKM[2:0]bit
XTI 256fs
XTI 384fs
XTI, BICKI, LRCKI
BICKI, LRCKI
SRBICKn, SRLRCKn
(N/A: Not available)
Note 41.
(fs)
DFS[1:0]bits(CONT0)
Note 42. CKMmode 2, 3
BICKI
fs
BITFS[1:0]bit
Note 43. CKM mode 4
SRBICKn
fs BITFS[1:0]bit
Note 44. CKM mode 0, 1
BITFS[1:0]bit
BICKO 64fs
Note 45. SRBICKn SRLRCKn
DSEL[1:0]
Note 46. CKM mode 2
XTI
BICKI, LRCKI
Note 47. CKM mode 7
[
]
)
##h
MS1328-J-00
16
“L”
“H”
“0”, “1”
(# = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F)
25
(
2011/09
[AK7722]
■
MCLK
(ICLK)
MCLK
ICLK
XTI Pin
CKM mode 0/1/2
(MCLK
ICLK
(MCLK
REFCLK
ICLK
(MCLK
PLL
REFCLK
)
MCLK
(XTI
PLL
MCLK
MCLK 73.728MHz(@fs=48kHz)
Figure 14. MCLK
1.
MCLK
)
SRBICKn Pin
CKM mode 4
PLL
)
BICKI Pin
CKM mode 3
REFCLK
(ICLK)
MCLK
CKM Mode 0/ 1)
fs:
CKM
Mode
0
1
CKM
[2:0]
000
001
XTI
fs=48kHz
12.288MHz
18.432MHz
XTI
fs=44.1kHz
11.2896MHz
16.9344MHz
(MHz)
11.0~12.4
16.5~18.6
XTI
LRCKO(1fs) , BICKO(64fs)
BITFS[1:0]
LRCKO, BICKO
CONT0 DFS[1:0] (D3.D2)
AK7722 XTI pin
1) XTI XTO
2) XTI
XTI
XTI
External Clock
XTO
Figure 15.
MS1328-J-00
XTO
AK7722
(CKM Mode 0/1)
Figure 16.
26
AK7722
(CKM Mode 0/1)
2011/09
[AK7722]
2.
XTI
CKM Mode 2
fs:
CKM
Mode
CKM
[2:0]
2
010
XTI
fs=48kHz
12.288MHz
(MHz)
fs=44.1kHz
11.2896MHz
XTI, LRCKI, BICLKI
11.0~12.4
-
XTI LRCKI
XTI
AK7722
XTO
Figure 17.
3.
BICKI
CKM mode 3
BICKI XTI
LRCKI
BICKI pin
(2
(CKM Mode 2)
CKM Mode 3
BICKI,
PLL
)
BICKI
(MCLK)
BICKI
LRCKI
fs:
DFS
[1:0]
0
0
0
1
1
1
2
2
2
3
3
3
MS1328-J-00
BITFS
Fs
48kHz
48kHz
48kHz
32kHz
32kHz
32kHz
16kHz
16kHz
16kHz
8kHz
8kHz
8kHz
[1:0]
2
1
0
2
1
0
2
1
0
2
1
0
BICKI
BICKI
32fs
48fs
64fs
32fs
48fs
64fs
32fs
48fs
64fs
32fs
48fs
64fs
44.1kHz
1.4112MHz
2.1168MHz
2.8224MHz
0.9408MHz
1.4112MHz
1.8816MHz
470.4kHz
705.6kHz
940.8kHz
27
48kHz
1.536MHz
2.304MHz
3.072MHz
1.024MHz
1.536MHz
2.048MHz
512kHz
786kHz
1024kHz
256kHz
384kHz
512kHz
1.368~1.582MHz
2.053~2.373MHz
2.737~3.164MHz
0.912~1.054MHz
1.368~1.582MHz
1.825~2.109MHz
456kHz~527kHz
684kHz~791kHz
912kHz~1054kHz
248kHz~263kHz
372kHz~395kHz
496kHz~527kHz
2011/09
[AK7722]
BITFS=0
@(DIFPCM=0 & DIFI2S=0)
LRCKI
Right ch
Left ch
BICKI
32
BITFS=2
BICK
32
BICK
@(DIFPCM=0 & DIFI2S=0)
LRCKI
Right ch
Left ch
BICKI
16
BITFS=1
BICK
16
BICK
@(DIFPCM=0 & DIFI2S=0)
LRCKI
Right ch
Left ch
BICKI
24
BICK
DIFPCM CONT01: D7, DIFI2S
24
CONT01: D6
(CONT0)
XTI
MS1328-J-00
BICK
DFS mode
XTI pin = “L”(DVSS)
28
2011/09
[AK7722]
4.
SRBICKn
CKM mode 4
2, 3) SRC
CKM Mode 4
CKM mode 3
BICKI
SRBICKn
SRBICKn
LRCKI SRLRCKn
SRCRST= “1” (SRC
PLL
SRBICKn
)
SRBICKn
(MCLK)
SRLRCKn
(n=1,
)
(2
fs:
DFS
BITFS
[1:0]
0
0
0
1
1
1
2
2
2
3
3
3
SRBICKn
Fs
48kHz
48kHz
48kHz
32kHz
32kHz
32kHz
16kHz
16kHz
16kHz
8kHz
8kHz
8kHz
[1:0]
2
1
0
2
1
0
2
1
0
2
1
0
SRBICKn
32fs
48fs
64fs
32fs
48fs
64fs
32fs
48fs
64fs
32fs
48fs
64fs
BITFS=0
@(DIFPCM=0 & DIFI2S=0)
SRLRCKn
44.1kHz
1.4112MHz
2.1168MHz
2.8224MHz
0.9408MHz
1.4112MHz
1.8816MHz
470.4kHz
705.6kHz
940.8kHz
48kHz
1.536MHz
2.304MHz
3.072MHz
1.024MHz
1.536MHz
2.048MHz
512kHz
786kHz
1024kHz
256kHz
384kHz
512kHz
1.368~1.582MHz
2.053~2.373MHz
2.737~3.164MHz
0.912~1.054MHz
1.368~1.582MHz
1.825~2.109MHz
456kHz~527kHz
684kHz~791kHz
912kHz~1054kHz
248kHz~263kHz
372kHz~395kHz
496kHz~527kHz
Right ch
Left ch
SRBICKn
32
BITFS=2
SRBICKn
32
SRBICKn
@(DIFPCM=0 & DIFI2S=0)
SRLRCKn
Right ch
Left ch
SRBICKn
16
BITFS=1
SRBICKn
16
SRBICKn
@(DIFPCM=0 & DIFI2S=0)
SRLRCKn
Right ch
Left ch
SRBICKn
24
DIFPCM CONT01: D7, DIFI2S
MS1328-J-00
SRBICKn
24
SRBICKn
CONT01: D6
29
2011/09
[AK7722]
■
AK7722
CONT00, CONT01, CONT0B
AK7722
(CKRSTN bit= “0”)
(CRSTN bit= “0”
DSPRSTN bit= “0”)
CONT0C, CONT0D, CONT0E, CONT10-CONT17
“1”
“0”
CONT00-CONT0E
Name
W
D7
D6
D5
D4
D3
D2
D1
D0
Default
R
C0h
40h
CONT00
Reserved
CKM[2]
CKM[1]
CKM[0]
DFS[1]
DFS[0]
BITFS[1]
BITFS[0]
00h
C1h
41h
CONT01
DIFPCM
DIFI2S
PCM[1]
PCM[0]
TEST
TEST
TEST
TEST
00h
C2h
42h
CONT02
Reserved
Reserved
BANK[1]
BANK[0]
JX1E
JX2E
SS[1]
SS[0]
00h
C3h
43h
CONT03
POMODE
DATARAM
WDTEN
WAVM
WAVP[1]
WAVP[0]
EFEN
CRCE
00h
C4h
44h
CONT04
DIF2[1]
DIF2[0]
DIF1[1]
DIF1[0]
TEST
TEST
TEST
TEST
00h
C5h
45h
CONT05
DOF3[1]
DOF3[0]
DOF2[1]
DOF2[0]
DOF1[1]
DOF1[0]
SELDO5[1]
SELDO5[0]
00h
C6h
46h
CONT06
BICKOE
LRCKOE
OUTS
SELBCK
SELDI5
SELDI4
SELDI3
Reserved
00h
C7h
47h
CONT07
CLKOE
CLKS[2]
CLKS[1]
CLKS[0]
CLKOP
OUT3E
OUT2E
OUT1E
00h
C8h
48h
CONT08
SELDO3[1]
SELDO3[0]
SELDO2[1]
SELDO2[0]
SELDO1[1]
SELDO1[0]
SELDO4[1]
SELDO4[0]
00h
C9h
49h
CONT09
MUX2E
MUX2[2]
MUX2[1]
MUX2[0]
Reserved
MUX1[2]
MUX1[1]
MUX1[0]
00h
CAh
4Ah
CONT0A
BIEDGE
IDIF[2]
IDIF[1]
IDIF[0]
BIFS[1]
BIFS[0]
SEMIAUTO
AUTOSEL
00h
CBh
4Bh
CONT0B
Reserved
TEST
DSEL[1]
DSEL[0]
Reserved
Reserved
Reserved
SETSRC
00h
CCh
4Ch
CONT0C
TEST
ASEL[2]
ASEL[1]
ASEL[0]
TEST
GIDIF[2]
GIDIF[1]
GIDIF[0]
00h
CDh
4Dh
CONT0D
AD2RST
AD1RST
ATSPAD
GSRCRST
DA2RST
DA1RST
ATSPDA
SRCRST
00h
CEh
4Eh
CONT0E
AD2SMUTE
AD1SMUTE
DA2SMUTE
DA1SMUTE
SRCSMUTE
CRSTN
DSPRSTN
CKRSTN
00h
CONT10 - CONT17
Name
W
D7
D6
D5
D4
D3
D2
D1
D0
Default
R
D0h
50h
CONT10
VOLA1L[7]
VOLA1L[6]
*VOLA1L[5]
*VOLA1L[4]
VOLA1L[3]
VOLA1L[2]
VOLA1L[1]
VOLA1L[0]
30h
D1h
51h
CONT11
VOLA1R[7]
VOLA1R[6]
*VOLA1R[5]
*VOLA1R[4]
VOLA1R[3]
VOLA1R[2]
VOLA1R[1]
VOLA1R[0]
30h
D2h
52h
CONT12
VOLA2L[7]
VOLA2L[6]
*VOLA2L[5]
*VOLA2L[4]
VOLA2L[3]
VOLA2L[2]
VOLA2L[1]
VOLA2L[0]
30h
D3h
53h
CONT13
VOLA2R[7]
VOLA2R[6]
*VOLA2R[5]
*VOLA2R[4]
VOLA2R[3]
VOLA2R[2]
VOLA2R[1]
VOLA2R[0]
30h
D4h
54h
CONT14
VOLD1L[7]
VOLD1L[6]
VOLD1L[5]
*VOLD1L[4]
*VOLD1L[3]
VOLD1L[2]
VOLD1L[1]
VOLD1L[0]
18h
D5h
55h
CONT15
VOLD1R[7]
VOLD1R[6]
VOLDA1R[5]
*VOLD1R[4]
*VOLD1R[3]
VOLD1R[2]
VOLD1R[1]
VOLD1R[0]
18h
D6h
56h
CONT16
VOLD2L[7]
VOLD2L[6]
VOLD2L[5]
*VOLD2L[4]
*VOLD2L[3]
VOLD2L[2]
VOLD2L[1]
VOLD2L[0]
18h
D7h
57h
CONT17
VOLD2R[7]
VOLD2R[6]
VOLD2R[5]
*VOLD2R[4]
*VOLD2R[3]
VOLD2R[2]
VOLD2R[1]
VOLD2R[0]
18h
MS1328-J-00
30
2011/09
[AK7722]
1. CONT00:
W
C0h
R
40h
Name
CONT00
D7: Reserved
0:
0
D7
Reserved
D6
CKM[2]
D5
CKM[1]
D4
CKM[0]
D3
DFS[1]
D2
DFS[0]
D1
BITFS[1]
D0
BITFS[0]
Default
00h
(default)
D6, D5, D4: CKM[2:0]
CKM Master MCLK
CKM
Mode [2:0] Slave
0
000 Master XTI
1
001 Master XTI
2
010 Slave
XTI
3
011 Slave
BICKI
4
100 Slave
SRBICKn
5
101 6
110 7
111 CKM mode 5~7 Reserved
12.288MHz
18.432MHz
12.288MHz
DFS[1:0],BITFS[1:0]
DFS[1:0],BITFS[1:0]
-
XTI (
)
XTI (
)
XTI BICKI LRCKI
BICKI, LRCKI
SRBICKn, SRLRCKn
-
(default)
D3, D2: DFS[1:0]
DFS
Mode
0
1
2
3
DFS
[1:0]
00
01
10
11
48kHz
48
32
16
8
(kHz)
44.1kHz
44.1
29.4
14.7
7.35
(default)
D1, D0: BITFS[1:0] BITCLK fs
BITFS
Mode
0
1
2
3
BITFS[1:0]
00
01
10
11
BITCLK
64fs
48fs
32fs
N/A
(default)
64fs
MS1328-J-00
BITFS mode 0
31
2011/09
[AK7722]
2. CONT01:
W
C1h
R
41h
Name
CONT01
D7
DIFPCM
D7: DIFPCM
0:
1: PCM
PCM
D6
DIFI2S
D5
PCM[1]
I2S
D4
PCM[0]
D3
TEST
D2
TEST
D1
TEST
D0
TEST
Default
00h
(default)
I2S mode
D6: DIFI2S
IF I2S
2
0: I S
(default)
2
1: I S
DIF2[1:0], DIF1[1:0], DOF3[1:0], DOF2[1:0], DOF1[1:0]
PCM
I2S mode
D5, D4: PCM[1:0] PCM
DIFPCM bit= “1”
PCM[1:0]
PCM
PCM BITCLK
LRCLK
Mode [1:0] (FRAME) BITCLK
0
00
short(SF)
1
01
short(SF)
2
10
long(LF)
3
11
long(LF)
p58 PCM
(RE)
(FE)
(RE)
(FE)
fs
(default)
CONT00: D1, D0, BITFS[1:0]
D3, D2, D1, D0: TEST
“0” (default)
MS1328-J-00
32
2011/09
[AK7722]
3. CONT02: RAM
W
C2h
R
42h
Name
CONT02
D7
Reserved
D7: Reserved
0:
0
(default)
D6: Reserved
0:
0
(default)
D6
Reserved
D5
BANK[1]
D4
BANK[0]
D3
JX1E
D2
JX2E
D1
SS[1]
D0
SS[0]
Default
00h
D5, D4: BANK[1:0] DLRAM Mode
DLRAM Mode
0
1
2
3
BANK[1:0]
00
01
10
11
D3: JX1E
0: JX1
1: JX1
(default)
D2: JX2E
0: JX2
1: JX2
(default)
DLRAM1
Ring 20.4f
5120word
3072word
2048word
1024word
DLRAM2
Ring 20.4f
(default)
2048word
2048word
2048word
D1, D0: SS[1:0] DLRAM
SS Mode
SS[1:0]
0
00
1
01
2
2
10
4
3
11
8
* SS mode 1, 2, 3
(DLRAM mode 0 DLYRAM1 Ring 20.4f
MS1328-J-00
DLRAM1
Linear 20.4f
33
1024word
2048word
(default)
*
*
*
DLRAM mode 1, 2, 3
)
DLRAM2 Ring20.4f
2011/09
[AK7722]
4. CONT03: RAM
W
R
Name
C3h
43h
CONT03
D7
D6
D5
D4
D3
D2
D1
D0
Default
POMODE
DATARAM
WDTEN
WAVM
WAVP[1]
WAVP[0]
EFEN
CRCE
00h
D7: POMODE
DLYRAM
0: OFREG (default)
1: DBUS
D6: DATARAM DATARAM
DATARAM
Mode
0
1
0
A(000h-3FFh)
1024word
B(400h-7FFh)
1024word
(default)
DP0
D5: WDTEN
0: WDTE
1: WDTE
(default)
D4: WAVM CRAM WAV
0: 1/4
(default)
1: 1/2
1/4
CRAM
D3, D2: WAVP[1:0] CRAM
WAVP Mode
WAVP[1:0]
0
00
1
01
2
10
3
11
D1: EFEN
0: EF, SJ, IN
1: EF, SJ, IN
WAVM= “0”
33word
65word
129word
257word
WAVM= “1”
65word
129word
257word
513word
FFT
128
256
512
1024
(default)
EF, SJ, IN
(default)
D0: CRCE
0: CRC
(default)
1: CRC
CRCE bit= “0”
STO
MS1328-J-00
DP1
WDT
CRCE bit=“1”
34
WDT, CRC
2011/09
[AK7722]
5. CONT04:
W
C4h
R
44h
IF
Name
CONT04
D7
DIF2[1]
D6
DIF2[0]
D5
DIF1[1]
D4
DIF1[0]
D3
TEST
D2
TEST
D7, D6: DIF2[1:0] DSP DIN2
DIF Mode
DIF2[1:0]
0
00
(24Bits)
1
01
24Bits
2
10
20Bits
3
11
16Bits
DIFI2S bit=“1”
DIF mode 0
BITFS[1:0] bits=“10”
DSP DIN4, DSP DIN5, DAC1 SDINDA1, DAC2 SDINDA2, MUX2
D5, D4: DIF1[1:0] DSP DIN1
DIF Mode
D1
TEST
D0
TEST
Default
00h
(default)
DIF mode3
DSP DIN3,
DIF1[1:0]
0
00
(default)
(24Bits)
1
01
24Bits
2
10
20Bits
3
11
16Bits
DIFI2S bit= “1”
DIF mode 0
BITFS[1:0] bits = “10”
DIF mode 3
DSP DIN3, DSP DIN4, DSP DIN5, DAC1 SDINDA1, DAC2 SDINDA2, MUX2
D3, D2: TEST
00:
00
(default)
D1, D0: TEST
00:
00
(default)
MS1328-J-00
35
2011/09
[AK7722]
6. CONT05:
IF
W
R
Name
C5h
45h
CONT05
D7
D6
D5
D4
D3
D2
D1
D0
Default
DOF3[1]
DOF3[0]
DOF2[1]
DOF2[0]
DOF1[1]
DOF1[0]
SELDO5[1]
SELDO5[0]
00h
D7, D6: DOF3[1:0] DSP DOUT3
DOF3 Mode
DOF3[1:0]
0
00
(default)
(24Bits)
1
01
24Bits
2
10
20Bits
3
11
16Bits
DIFI2S bit= “1”
DOF3 mode 0
BITFS[1:0] bits= “10”
DOF3 mode 0
DSP DOUT5 DSP DOUT4 SRC SRCO ADC1 SDOUTAD1 ADC2 SDOUTAD2
D5, D4: DOF2[1:0] DSP DOUT2
DOF2 Mode
DOF2[1:0]
0
00
(default)
(24Bits)
1
01
24Bits
2
10
20Bits
3
11
16Bits
DIFI2S bit = “1”
DOF3 mode 0
BITFS[1:0] bits = “10”
DOF3 mode 0
DOUT5 DSP DOUT4 SRC SRCO ADC1 SDOUTAD1 ADC2 SDOUTAD2
DSP
D3, D2: DOF1[1:0] DSP DOUT1
DOF1 Mode
DOF1[1:0]
0
00
(default)
(24Bits)
1
01
24Bits
2
10
20Bits
3
11
16Bits
DIFI2S bit = “1”
DOF3 Mode 0
BITFS[1:0] bits= “10”
DOF3 mode 0
DSP DOUT5 DSP DOUT4 SRC SRCO ADC1 SDOUTAD ADC2 SDOUTAD2
D1, D0: SELDO5[1:0] DAC2
SELDO5 Mode
SELDO5[1:0]
0
00
1
01
2
10
3
11
DAC2
SDINDA2
MS1328-J-00
DSP DOUT5
SELDI3 OUT
ADC2 SDOUTAD2
ADC1 SDOUTAD1
36
(default)
2011/09
[AK7722]
7. CONT06: DSP
W
C6h
R
46h
Name
CONT06
D7
BICKOE
D6
LRCKOE
D5
OUTS
D4
SELBCK
D3
SELDI5
D2
SELDI4
D1
SELDI3
D0
DIF3SEL
Default
00h
D7: BICKOE
0: BICKO pin = “L” (default)
1:
BICKO
“L”
D6: LRCKOE
0: LRCKO pin= “L” (default)
1:
LRCKO
“L”
D5: OUTS
LRCKO, BICKO
0:
LRCKI, BICKI
1: LRCKI1, BICKI1
BICKI/SRBICKn 64fs (BITFS mode 0)
BICKI/SRBICKn 48fs (BITFS mode 1)
BICKI/SRBICKn 32fs (BITFS mode 2)
(default)
LRLKO BICKI/SRBICKn 32
LRCKO BICKI/SRBICKn 24
LRCKO BICKI/SRBICKn 16
“H”
“H”
“H”
“L”
“L”
“L”
OUTS
■
D4: SELBCK BICKO
0: BICKO
1: BICKO
(default)
D3: SELDI5 DSP DIN5
0: MUX1 OUT (default)
1: SDIN5
D2: SELDI4 DSP DIN4
0: ADC1 SDOUTAD1 (default)
1: SRIN2
D1: SELDI3 DSP DIN3
0: SRCO (default)
1: SRIN1
D0: DIF3SEL DSP DIN3
DIF3SEL
DIF1[1:0]
00
0
00
00
1
00
DSP DIN1
MS1328-J-00
DSP DIN3
(24Bits)
(default)
24Bits
DSP DIN3
37
2011/09
[AK7722]
8. CONT07:
W
C7h
R
47h
Name
CONT07
D7
CLKOE
D6
CLKS[2]
D5
CLKS[1]
D4
CLKS[0]
D3
CLKOP
D2
OUT3E
D1
OUT2E
D0
OUT1E
Default
00h
D7: CLKOE
0: CLKO pin= “L” (default)
1: CLKO
D6, D5, D4: CLKS[2:0]: CLKO
CLKS CLKS[2:0] fs=48kHz
fs=44.1kHz
Mode
0
000
12.288MHz
11.2896MHz
1
001
6.144MHz
5.6448MHz
2
010
3.072MHz
2.8224MHz
3
011
8.192MHz
7.5264MHz
4
100
4.096MHz
3.7632MHz
5
101
2.048MHz
1.8816MHz
6
110
18.432MHz
16.9344MHz
7
111
256fs
256fs
* CLKS mode 1-5
CLKOP bit = “1”
* CLKO
CLKS mode 0-6
CLKOP (*)
(CONT7 D1)
0
1
1
1
1
1
0
1
(default)
CLKS mode 7
D3: CLKOP CLKO
0: CLKS[2:0] (CONT3) =0h,6h (default)
1: CLKS[2:0] (CONT3) =1-5h
D2: OUT3E
0: SDOUT3/IRPT pin= “L” (default)
1: SDOUT3/IRPT
D1: OUT2E
0: SDOUT2 pin= “L” (default)
1: SDOUT2
D0: OUT1E
0: SDOUT1 pin = “L” (default)
1: SDOUT1
MS1328-J-00
38
2011/09
[AK7722]
9. CONT08: DSP
W
R
Name
C8h
48h
CONT08
D7
D6
D5
D4
D3
D2
D1
D0
SELDO3
SELDO3
SELDO2
SELDO2
SELDO1
SELDO1
SELDO4[1]
SELDO4[0]
[1]
[0]
[1]
[0]
[1]
[0]
D7, D6: SELDO3[1:0] SDOUT1
SELDO3 Mode
SELDO3[1:0]
0
00
1
01
2
10
3
11
DSP DOUT3
SRCO/SRIN1
DSP IRPT
DSP DOUT5
(default)
D5, D4: SELDO2[1:0] SDOUT2
SELDO1 Mode
SELDO2[1:0]
0
00
1
01
2
10
3
11
DSP DOUT2
SDIN2
DSP DOUT4
ADC2 SDOUTAD2
(default)
D3, D2: SELDO1[1:0] SDOUT1
SELDO1 Mode
SELDO3[1:0]
0
00
1
01
2
10
3
11
DSP DOUT1
SDIN1
ADC1 SDOUTAD1
DSP GP0
(default)
DSP DOUT4
SDIN1
ADC1 SDOUTAD1
ADC2 SDOUTAD2
(default)
D1, D0: SELDO4[1:0] MUX2
SELDO1 Mode
SELDO3[1:0]
0
00
1
01
2
10
3
11
MUX2
MS1328-J-00
39
Default
00h
2011/09
[AK7722]
10. CONT09: MUX
W
R
Name
C9h
49h
CONT09
D7: MUX2E
0 MUX2
1 MUX2
MUX2
MUX2
D7
D6
D5
D4
D3
D2
D1
D0
Default
MUX2E
MUX2[2]
MUX2[1]
MUX2[0]
Reserved
MUX1[2]
MUX1[1]
MUX1[0]
00h
(Default)
1[1/fs]
SELDO4[1:0]bits
D6, D5, D4: MUX2[2:0] MUX2
MUX2[2:0]
MUX2
Lch
000
DO4L
001
M1L
010
DO4L
011
DO4L/2+M1L/2
100
DO4L
101
DO4L/2+M1L/2
110
M1L
111
M1L
DO4L/R: SELDO4[1:0]
M1L/R: MUX1
Lch/Rch
D3: Reserved
0:
0
Rch
DO4R
DO4R
M1L
DO4R
DO4R/2+M1L/2
DO4R/2+M1L/2
M1L
M1R
Lch/Rch
(default)
D2, D1, D0: MUX1[2:0] MUX1
MUX1[2:0]
MUX1
Lch
000
ADC2L
001
ADC2R
010
GSRC
011
ADC2L/2+GSRC/2
100
ADC2R/2+GSRC/2
101
ADC2L/2+ADC2R/2
110
ADC2L
111
GSRC
ADC2L/R: ADC2
Lch/Rch
GSRC:
SRC
MS1328-J-00
Rch
ADC2R
ADC2L
GSRC
ADC2R
ADC2L
GSRC
GSRC
ADC2R
40
2011/09
[AK7722]
11. CONT0A: SRC
W
CAh
R
4Ah
Name
CONT0A
D7
BIEDGE
D6
IDIF[2]
D5
IDIF[1]
D4
IDIF[0]
D3
BIFS[1]
D2
BIFS[0]
D1
SEMIAUTO
D0
AUTOSEL
Default
00h
D7: BIEDGE SRC
SRBICKn
0: SRLRCKn
(default)
1: SRLRCKn
SRC
PCM mode (IDIF mode 6, 7)
(IDIF[2:0] D6~D4
)
D6, D5, D4: IDIF[2:0]
SRIN1-3
fsi: SRC
IDIF Mode
0
1
2
3
4
5
6
7
SRBICKn
IDIF[2:0]
000
001
010
011
100
101
110
111
SRC PLL
D3, D2: BIFS[1:0] SRC
SRBICKn(SRC)
(default)
16bit
32fsi
20bit
40fsi
24/20bit
48fsi
24/16bit
48fsi or 32fsi
I 2S
24bit
48fsi
N/A
PCM SHORT
BIFS[1:0]
PCM LONG
BIFS[1:0]
(SETSRC bit= “0”) SRBICKn
SRC
SRBICKn 48fsi
SRBICKn (n=1, 2, 3)
BIFS Mode
BIFS[1]
BIFS[0]
0
0
0
1
0
1
2
1
0
3
1
1
SRBICKn (n=1, 2, 3)
SRC
mode 6, 7
D1: SEMI_AUTO SRC
0: SEMIAUTO OFF (default)
1: SEMIAUTO ON
D0: AUTOSEL SRC
0: 2205/fso (default)
1: 8820/fso
MS1328-J-00
BIFS[1:0]
SETSRC bit= “1”
SRBICKn (n=1, 2, 3)
32fsi
64fsi
128fsi
N/A
PLL
(default)
(CONT0B D0: SETSRC bit= “0”)
IDIF
SEMI_AUTO
Semi-Auto
41
2011/09
[AK7722]
12. CONT0B: MUX
W
CBh
R
4Bh
Name
CONT0B
D7
Reserved
D7: Reserved
0:
0
(default)
D6: TEST
0:
0
(default)
D6
TEST
D5
DSEL[1]
D4
DSEL[0]
D3
Reserved
D2
Reserved
D1
Reserved
D0
SETSRC
Default
00h
D5, D4: DSEL[1:0] SRC
DSEL[1:0] SRC
00
SRIN1, SRBICK1, SRLRCK1
01
SRIN2, SRBICK2, SRLRCK2
10
SRIN3, SRBICK3, SRLRCK3
11
N/A
D3: Reserved
0:
0
(default)
D2: Reserved
0:
0
(default)
D1: Reserved
0:
0
(default)
D0: SETSRC SRCPLL
0: SRBICKn (default)
1: SRLRCKn
MS1328-J-00
42
2011/09
[AK7722]
13. CONT0C: ADC
W
CCh
R
4Ch
Name
CONT0C
D7: TEST
0:
0
D7
TEST
D6
ASEL[2]
D4
ASEL[0]
D3
TEST
D2
GDIF[2]
D1
GIDIF[1]
D0
GIDIF[0]
Default
00h
(default)
D6, D5, D4: ASEL[2:0] ADC
ASEL Mode
ASEL1[2:0]
0
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
D3: TEST
0:
0
D5
ASEL[1]
AIN1LP, AIN1LN, AIN1RP, AIN1RN
AIN2LP, AIN2LN, AIN2RP, AIN2RN
AIN3L, AIN3R
AIN4L, AIN4R
AIN5L, AIN5R
AIN6L, AIN6R
No connection
No connection
MUTE
(default)
(default)
D2, D1, D0: GIDIF[2:0] GSRC
Fsi: GSRC
GIDIF Mode
0
1
2
3
4
5
6
7
MS1328-J-00
GIDIF[2:0]
000
001
010
011
100
101
110
111
GBICK
32fsi
40fsi
48fsi/40fsi
48fsi or 32fsi
48fsi
16bit
20bit
24/20bit
24/16bit
I2S
24bit
N/A
N/A
N/A
43
(default)
2011/09
[AK7722]
14. CONT0D:
W
R
Name
CDh
4Dh
CONT0D
D7
D6
D5
D4
D3
D2
D1
D0
Default
AD2RST
AD1RST
ATSPAD
GSRCRST
DA2RST
DA1RST
ATSPDA
SRCRST
00h
D7: AD2RST ADC2
0: ADC2
1: ADC2
ADC2
(default)
AD2RST bit = “1”
D6: AD1RST ADC1
0: ADC1
1: ADC1
ADC1
(default)
AD1RST bit= “1”
D5: ATSPAD ADC1/ADC2
0: 1/fs (default)
1: 4/fs
D4: GSRCRST
0:
1:
SRC
SRC
SRC
GSRC
(default)
GSRCRST bit = “1”
D3: DA2RST DAC2
0: DAC2
1: DAC2
DAC2
(default)
DA2RST bit= “1”
D2: DA1RST DAC1
0: DAC1
1: DAC1
DAC1
(default)
DA1RST bit= “1”
D1: ATSPDA DAC1/DAC2
0: 1/fs (default)
1: 4/fs
D0: SRCRST SRC
0: SRC
1: SRC
SRC
CKM mode 4, 6
MS1328-J-00
(default)
SRCRST bit= “1”
SRCRST bit = “1”
44
2011/09
[AK7722]
15. CONT0E:
W
R
Name
CEh
4Eh
CONT0E
D7
D6
D5
D4
D3
AD2
AD1
DA2
DA1
SRC
SMUTE
SMUTE
SMUTE
SMUTE
SMUTE
D2
D1
D0
CRSTN
DSPRSTN
CKRSTN
Default
00h
D7: AD2SMUTE ADC2 SMUTE
0: ADC2 SMUTE
(default)
1: ADC2 SMUTE
D6: AD1SMUTE ADC2 SMUTE
0: ADC2 SMUTE
(default)
1: ADC2 SMUTE
D5: DA2SMUTE DAC2 SMUTE
0: DAC2 SMUTE
(default)
1: DAC2 SMUTE
D4: DA1SMUTE DAC2 SMUTE
0: DAC2 SMUTE
(default)
1: DAC2 SMUTE
D3: SRCSMUTE SRC SMUTE
0: SRC SMUTE
(default)
1: SRC SMUTE
D2: CRSTN CODEC
(
0: CODEC
(default)
1: CODEC
CODEC ADC, DAC, SRC, GSRC
Low)
D1: DSPRSTN DSP
0: DSP
(default)
1: DSP
Low)
D0: CKRSTN
0:
1:
CKM mode
MS1328-J-00
(
(
Low)
(default)
45
2011/09
[AK7722]
16. CONT10-13: ADC1, ADC2
Name
W
D0h
D1h
D2h
D3h
R
50h
51h
52h
53h
CONT10
CONT11
CONT12
CONT13
D7
D6
D5
D4
D3
D2
D1
D0
Default
VOLA1L
VOLA1L
*VOLA1L
*VOLA1L
VOLA1L
VOLA1L
VOLA1L
VOLA1L
30h
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
VOLA1R
VOLA1R
*VOLA1R
*VOLA1R
VOLA1R
VOLA1R
VOLA1R
VOLA1R
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
VOLA2R
VOLA2R
*VOLA2R
*VOLA2R
VOLA2R
VOLA2R
VOLA2R
VOLA2R
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
VOLA2R
VOLA2R
*VOLA2R
*VOLA2R
VOLA2R
VOLA2R
VOLA2R
VOLA2R
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
30h
30h
30h
Note 48. ADC
17. CONT14-17: DAC1, DAC2
Name
W
D4h
D5h
D6h
D7h
R
54h
55h
56h
57h
CONT14
CONT15
CONT16
CONT17
D7
D6
D5
D4
D3
D2
D1
D0
Default
VOLD1L
VOLD1L
*VOLD1L
*VOLD1L
VOLD1L
VOLD1L
VOLD1L
VOLD1L
30h
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
VOLD1R
VOLD1R
*VOLD1R
*VOLD1R
VOLD1R
VOLD1R
VOLD1R
VOLD1R
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
VOLD2R
VOLD2R
*VOLD2R
*VOLD2R
VOLD2R
VOLD2R
VOLD2R
VOLD2R
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
VOLD2R
VOLD2R
*VOLD2R
*VOLD2R
VOLD2R
VOLD2R
VOLD2R
VOLD2R
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Note 49. DAC
MS1328-J-00
46
2011/09
30h
30h
30h
[AK7722]
■
1.
INITRSTN pin=“L” (
INITRSTN pin = “H”
AVDD, DVDD
2-4
)
REF
INITRSTN pin =“H”
(CKM mode 0, 1
) CKRSTN bit= “1”
AK7722
)
1ms
(CKM mode
PLL
PLL
INITRSTN pin
XTI
DVDD, AVDD
INITRSTN pin
AVDRV pin
RQN pin(I2CSEL= “L”)
SCLK pin(I2CSEL= “L”)
SCL pin(I2CSEL= “H”)
SI pin (I2CSEL pin= “L”)
SDA pin (I2CSEL pin= “H”
CONT Reg.
DSP
CONT Reg.
DSP
CKRSTN bit
DSPRSTN bit
CRSTN bit
XTI pin CKM0-2
(SR)BICK(n) pin CKM3,4
(
)
100us(min)
1ms(min)
PLL
DSP
(50ms)
Figure 18.
MS1328-J-00
47
2011/09
[AK7722]
2.
(INITRSTN pin= “L”)
(AK7722
OFF
)
DVDD, AVDD
INITRSTN (pin)
OFF
Figure 19.
3. LDO(
)
AK7722
1[uF] ( 30%)
(LDO)
AVDRV pin VSS4
LDO
1[ms]
AVDRV pin GND
AVDRV pin
STO pin
“L”
■
1.
AK7722
“L”
INITRST pin
VREF
3
“H”
(RUN
)
ADC1, ADC2, DAC1, DAC2, DSP, SRC
CRSTN bit DSPSTN bit
ADC1, ADC2, DAC1, DAC2, DSP, SRC
CKRSTN “0”
INITRSTN pin
“0”
PLL
PLL
2.
INITRSTN
AK7722
ADC1, ADC2, DAC1, DAC2, DSP, PLL
INITRSTN pin = “L”
REF
(
)
1ms
MS1328-J-00
48
INITRSTN pin= “L”
100us(min)
INITRSTN pin
“L”
“H”
2011/09
[AK7722]
3.
(INITRSTN pin=“L”
“H”)
CRSTN bit=“0” (CONT0E D2)
(CONT0E D1)
(CONT0E D0)
AK7722
DSPRSTN bit= “0”
CKRSTN bit=“0”
REF
PLL
1ms
CONT00, CONT01, CONT0B
8bit
(■
(■I2C
AK7722
8bit
) I2C
, 1-4.
SCLK
16bit
Acknowledge
)
RQN
8 9
1
16
SCLK
D7
SI
Data
Command
Figure 20.
(CKRSTN bit= “1”)
PLL
RQN
SCLK
SI
D7
D7
Command CEh
D7
D7
Data
(“L”=
01h
Command
CEh
Data
07h
)
Figure 21.
MS1328-J-00
49
2011/09
[AK7722]
4.
CKM[2:0] bits
ICLK [email protected] mode0-2
[email protected] mode3
[email protected] mode4
[email protected] mode5 [email protected] mode6
(INITRSTN pin = “L”)
PLL
CKRSTN bit = “0”
PLL
CKRSTN bit
([email protected] mode0-4) DSP
PLL
(“0”
DSP
DSPRSTN bit
“1”
“1”)
CRSTN bit
AK7722
CKM mode3
CKM mode0
XTI
BICKI
600ns(min)
RQN
SCLK
SI
DSPRSTN
CRSTN
CKRSTN
CEh 01h
C0h
CEh 00h
3×h
CEh
CEh 01h
DSPRSTN bit = “0”:
CRSTN bit = “0”
DSPRSTN bit = “1”:
CRSTN bit = “1”
CKRSTN bit = “0”:
CKRSTN bit = “1”:
07h
PLL
& DSP
Figure 22.
(
CKM mode0
CKM mode3)
■ RAM
AK7722
DRAM
PLL
200 s
RAM
RAM
RAM
DSP
RAM
DLRAM
“0”
(RAM
)
RAM
RUN
RAM
(
RAM
)
INITRSTN(Pin)
DSPRSTN (Reg.)
CRSTN (Reg.)
RAM
DSP
RAM
DSP
Figure 23. RAM
MS1328-J-00
50
2011/09
[AK7722]
■
Status Output Pin
STO pin (
)
LDO
, CRC
)
INITRSTN pin
“H”
WDT (
LDO
INITRSTN
pin
L
H
“L”
WDT
CRCE bit
CONT03 D0
0
WDTEN bit
CONT03 D5
0
0
1
1
0
1
1
LDO
STO
pin
H
WDTERRN
L
H
L
CRCERRN
WDTERRN
L
CRCERRN
L
(default)
Table 1. STO pin
MS1328-J-00
51
2011/09
[AK7722]
■
SDIN1, SDIN2, SDIN3, SDIN4, SDIN5, SDOUT1, SDOUT2, SDOUT3
LRCKI,
BICKI (LRCKO, BIKCO)
(
)
2's
MSB
(I2S
I2S
I2S
PCM
SDIN1, SDIN2
24bit,
)
20bit,
(24bit)
SDIN3
16bit
(24bit)
24bit
DAC1, DAC2
SDINDA1, SDINDA2
SDOUT1, SDOUT2, SDOUT3
24bit
SDOUTAD2
DIFPCM
20bit
16bit
(24bit)
ADC1, ADC2
DSP DIN1
SDIN2/JX1
SDOUT1 pin
DAC1
SDINDA1
DSP DIN2
SELDO1[1:0] bits= “01”
SELDO4[1:0] bits= “01”
MUX2[2:0] (P.40
)
JX1E bit= “0”
SDOUT2 pin
DSP DIN3
DSP DIN4
DSP DIN5
OUT2E bit= “1”
SELDI3 bit= “1”
SELDI4 bit= “1”
SELDI5 bit= “1”
DSP DIN1
SDOUT1 pin
DAC1
SDINDA1
DSP DIN2
SDOUT2 pin
DSP DIN3
DSP DIN4
DSP DIN5
SELDO1[1:0] bits= “01”
SELDO4[1:0] bits= “01”
MUX2[2:0] (P.40
)
JX1E bit= “0”
OUT2E bit= “1”
SELDI3 bit= “1”
SELDI4 bit= “1”
SELDI5 bit= “1”
0
0
SRIN1/SDIN3
SRIN2/SDIN4
SDIN5
DIFPCM bit = “0”, DIFI2S bit = “0”
DIFPCM
DIF1[1:0]
(P.35
)
DIF2[1:0]
(P.35
)
/(
)
DIFI2S
SDIN1
0
SRIN1/SDIN3
SRIN2/SDIN4
SDIN5
DIFPCM bit= “0”, DIFI2S bit = “1”
MS1328-J-00
SDOUTAD1,
DIFI2S
SDIN1
SDIN2/JX1
SDIN1
SDIN4, SDIN5
1
52
I2S
2011/09
[AK7722]
DIFPCM
DIFI2S
SDIN1
SDIN2/JX1
1
0
SRIN1/SDIN3
SRIN2/SDIN4
SDIN5
DIFPCM bit = “1”, DIFI2S bit = “0”
DIFPCM
DSP DIN1
SDOUT1 pin
DAC1
SDINDA1
DSP DIN2
SDOUT2 pin
DSP DIN3
DSP DIN4
DSP DIN5
PCM[1:0]
(P.32
)
DIFI2S
SDOUT1/GP0
DSP DOUT1
SDIN1 Pin
ADC1 SDOUTAD1
SDOUT2
DSP DOUT2
SDIN2 pin
0
SELDO1[1:0] bits= “01”
SELDO4[1:0] bits= “01”
MUX2[2:0] (P.41
)
JX1E bit= “0”
OUT2E bit= “1”
SELDI3 bit= “1”
SELDI4 bit= “1”
SELDI5 bit= “1”
0
SDOUT3/IRPT
DSP DOUT4
ADC2
SDOUTAD2
DSP DOUT3
SRIN1 pin/SRCO
DSP DOUT5
SELDO1[1:0] bits= “00”
OUT1E bit = “1”
SELDO1[1:0] bits = “01”
OUT1E bit= “1”
SELDO1[1:0] bits= “10”
OUT1E bit= “1”
SELDO2[1:0] bits = “00”
OUT2E bit= “1”
SELDO2[1:0] bits= “01”
OUT2E bit= “1”
SELDO2[1:0] bits= “10”
OUT2E bit= “1”
SELDO2[1:0] bits= “11”
OUT2E bit= “1”
SELDO3[1:0] bits= “00”
OUT3E bit= “1”
SELDO3[1:0] bits= “10”
OUT3E bit= “1”
SELDO3[1:0] bits= “11”
OUT3E bit= “1”
DOF1[1:0]
(P.36
)
DOF2[1:0]
(P.36
)
DOF3[1:0]
(P.36
)
DIFPCM bit = “0”, DIFI2S bit = “0”
MS1328-J-00
53
2011/09
[AK7722]
DIFPCM
DIFI2S
SDOUT1/GP0
DSP DOUT1
SDIN1 pin
ADC1
SDOUTAD1
DSP DOUT2
SDOUT2
SDIN2 pin
0
1
DSP DOUT4
ADC2
SDOUTAD2
DSP DOUT3
SDOUT3/IRPT
SRIN1 pin/SRCO
DSP DOUT5
SELDO1[1:0] bits= “00”
OUT1E bit= “1”
SELDO1[1:0] bits= “01”
OUT1E bit= “1”
SELDO1[1:0] bits= “10”
OUT1E bit= “1”
SELDO2[1:0] bits= “00”
OUT2E bit= “1”
SELDO2[1:0] bits= “01”
OUT2E bit= “1”
SELDO2[1:0] bits= “10”
OUT2E bit= “1”
SELDO2[1:0] bits= “11”
OUT2E bit= “1”
SELDO3[1:0] bits= “00”
OUT3E bit= “1”
SELDO3[1:0] bits= “10”
OUT3E bit= “1”
SELDO3[1:0] bits= “11”
OUT3E bit= “1”
I2S
DIFPCM bit = “0”, DIFI2S bit = “1”
DIFPCM
DIFI2S
SDOUT1/GP0
DSP DOUT1
SDIN1 pin
ADC1
SDOUTAD1
DSP DOUT2
SDOUT2
SDIN2 pin
1
0
SDOUT3/IRPT
DSP DOUT4
ADC2
SDOUTAD2
DSP DOUT3
SRIN1 pin/SRCO
DSP DOUT5
SELDO1[1:0] bits= “00”
OUT1E bit= “1”
SELDO1[1:0] bits= “01”
OUT1E bit= “1”
SELDO1[1:0] bits= “10”
OUT1E bit= “1”
SELDO2[1:0] bits= “00”
OUT2E bit= “1”
SELDO2[1:0] bits= “01”
OUT2E bit= “1”
SELDO2[1:0] bits= “10”
OUT2E bit= “1”
SELDO2[1:0] bits= “11”
OUT2E bit= “1”
SELDO3[1:0] bits= “00”
OUT3E bit= “1”
SELDO3[1:0] bits= “10”
OUT3E bit= “1”
SELDO3[1:0] bits= “11”
OUT3E bit= “1”
PCM[1:0]
(P.32
)
DIFPCM bit = “1”, DIFI2S bit = “0”
MS1328-J-00
54
2011/09
[AK7722]
1.
1)
(CKM Mode 0, 1)
CONT01 D7
DIFPCM
0
CONT01 D6
DIFI2S
0
(24bit), BICKO=64fs
CONT01 D5
PCM[1]
0
CONT01 D4
PCM[0]
0
CONT00 D1,D2
BITFS
00
Left ch
LRCKO
Right ch
BICKO
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1, 2
DIF Mode 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
M: MSB, L: LSB
SDOUT1~3
DOF Mode 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
M: MSB, L: LSB
2)
(CKM mode 0, 1)
CONT01 D7
DIFPCM
0
CONT01 D6
DIFI2S
0
, BICKO=64fs
CONT01 D5
PCM[1]
0
CONT01 D4
PCM[0]
0
CONT00 D1,D2
BITFS
00
Left ch
LRCKO
Right ch
BICKO
31 30
23 22 21 20 19 18 17 16 15 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
SDIN1, 2 (SDIN3)
DIF Mode 1
Don’t care M 22 21 20 19 18 17 16 15 14
1 L Don’t care M 22 21 20 19 18 17 16 15 14
1 L
SDIN1, 2
DIF Mode 2
Don’t care
M 18 17 16 15 14
1 L Don’t care
M 18 17 16 15 14
1 L
SDIN1, 2
DIF Mode 3
Don’t care
M 14
1 L Don’t care
M 14
1 L
M: MSB, L: LSB
SDOUT1, 2, 3
DOF Mode 1
MSB
22 21 20 19 18 17 16 15 14
1 L
MSB
22 21 20 19 18 17 16 15 14
1 L
SDOUT1, 2, 3
DOF Mode 2
MSB
18 17 16 15 14
1 L
MSB
18 17 16 15 14
1 L
SDOUT1, 2, 3
DOF Mode 3
MSB
14
1 L
MSB
14
1 L
SDIN3-5
SDIN3
CONT06: D0= “1”
SDIN1 DIF Mode 1~3
24bit
MS1328-J-00
55
2011/09
[AK7722]
3)
(CKM Mode 2, 3, 4)
CONT01 D7
DIFPCM
0
CONT01 D6
DIFI2S
0
(24bit), BICK/SRBICKn=64fs
CONT01 D5
PCM[1]
0
CONT01 D4
PCM[0]
0
CONT00 D1,D2
BITFS
00
Left ch
LRCKI/SRLRCKn
Right ch
BICKI/SRBICKn
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1, 2
DIF Mode 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
M: MSB, L: LSB
SDOUT1~3
DOF Mode 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
M: MSB, L: LSB
4)
(CKM Mode2, 3, 4)
CONT01 D7
DIFPCM
0
CONT01 D6
DIFI2S
0
, BITCLK64fs
CONT01 D5
PCM[1]
0
CONT01 D4
PCM[0]
0
CONT00 D1, D2
BITFS
00
Left ch
LRCKI/SRLRCKn
Right ch
BICKI/SRBICKn
31 30
23 22 21 20 19 18 17 16 15 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
SDIN1, 2 (SDIN3)
DIF Mode 1
Don’t care M 22 21 20 19 18 17 16 15 14
1 L Don’t care M 22 21 20 19 18 17 16 15 14
1 L
SDIN1, 2
DIF Mode 2
Don’t care
M 18 17 16 15 14
1 L Don’t care
M 18 17 16 15 14
1 L
SDIN1, 2
DIF Mode 3
Don’t care
M 14
1 L Don’t care
M 14
1 L
M: MSB, L: LSB
SDOUT1, 2, 3
DOF Mode 1
MSB
22 21 20 19 18 17 16 15 14
1 L
MSB
22 21 20 19 18 17 16 15 14
1 L
SDOUT1, 2, 3
DOF Mode 2
MSB
18 17 16 15 14
1 L
MSB
18 17 16 15 14
1 L
SDOUT1, 2, 3
DOF Mode 3
MSB
14
1 L
MSB
14
1 L
SDIN3-5
SDIN3
CONT06: D0= “1”
SDIN1 DIF Mode 1~3
24bit
MS1328-J-00
56
2011/09
[AK7722]
2. I2S
1)
(CKM Mode 0, 1)
CONT01 D7
DIFPCM
0
CONT01 D6
DIFI2S
1
CONT01 D5
PCM[1]
0
CONT01 D4
PCM[0]
0
CONT00 D1, D2
BITFS
00
Left ch
LRCKO
Right ch
BICKO
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1, 2
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
M: MSB, L: LSB
SDOUT1, 2, 3
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
M: MSB, L: LSB
(24bit)
2)
(CKM Mode 2, 3, 4)
CONT01 D7
DIFPCM
0
CONT01 D6
DIFI2S
1
CONT01 D5
PCM[1]
0
CONT01 D4
PCM[0]
0
CONT00 D1, D2
BITFS
00
Left ch
LRCKI
Right ch
BICKI
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1, 2
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
M: MSB, L: LSB
SDOUT1, 2, 3
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
M: MSB, L: LSB
(24bit)
MS1328-J-00
57
2011/09
[AK7722]
3. PCM
1) PCM Mode 0 (CKM Mode 2, 3, 4)
CONT01 D7
DIFPCM
1
LRCKI
CONT01 D6
DIFI2S
0
CONT01 D5
PCM[1]
0
CONT01 D4
PCM[0]
0
CONT00 D1,D2
BITFS
00
tBICK
SF
BICKI
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
SDIN1, 2
M 22 21 20 19
2 1 L
SDOUT1, 2, 3
M 22 21 20 19
2 1 L
M: MSB, L: LSB
Left ch
10 9 8 7 6 5 4 3 2 1 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
Right ch
24bit
2) PCM Mode 1 (CKM Mode 2, 3, 4)
CONT01 D7
DIFPCM
1
LRCKI
CONT01 D6
DIFI2S
0
CONT01 D5
PCM[1]
0
CONT01 D4
PCM[0]
1
CONT00 D1,D2
BITFS
00
tBICK
SF
BICKI
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
SDIN1, 2
M 22 21 20 19
2 1 L
SDOUT1, 2, 3
M 22 21 20 19
2 1 L
M: MSB, L: LSB
Left ch
10 9 8 7 6 5 4 3 2 1 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
Right ch
24bit
MS1328-J-00
58
2011/09
[AK7722]
3) PCM Mode 2 (CKM Mode 2, 3, 4)
CONT01 D7
DIFPCM
1
CONT01 D6
DIFI2S
0
CONT01 D5
PCM[1]
1
CONT01 D4
PCM[0]
0
CONT00 D1,D2
BITFS
00
1 ≤ tBICK ≤ 60
LRCKI
LF
BICKI
63 62 61 60 59
SDIN1, 2
SDOUT1, 2, 3
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
tBICK
M: MSB, L: LSB
10 9 8 7 6 5 4 3 2 1 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
Left ch
Right ch
tBICK × 32
tBICK × 32
24bit
4) PCM Mode 3 (CKM Mode 2, 3, 4)
CONT01 D7
DIFPCM
1
CONT01 D6
DIFI2S
0
CONT01 D5
PCM[1]
1
CONT01 D4
PCM[0]
1
CONT00 D1,D2
BITFS
00
1 ≤ tBICK ≤ 60
LRCKI
LF
BICKI
63 62 61 60 59
SDIN1, 2
SDOUT1, 2, 3
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M 22 21 20 19
2 1 L
tBICK
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
M: MSB, L: LSB
M 22 21 20 19
2 1 L
Left ch
Right ch
tBICK × 32
tBICK × 32
24bit
MS1328-J-00
59
2011/09
[AK7722]
4. General Purpose Output
AK7722
2
General Purpose Output (GPO) pin
SELDO1[1:0](CONT08 D3, D2)
GP0 pin, GP1 pin
“L”
SELDO1 Mode
0
1
2
3
SDOUT1/GP0 pin
DSP
SELDO3[1:0]
00
DSP DOUT1
01
SDIN1
10
ADC1 SDOUTAD1
11
DSP GP0
Table 2. SDOUT1/GP0pin
■
(default)
(I2CSEL pin= “L”)
1.
(8bit) +
Bit
8
MSB first
bit
R/W
7bit
PRAM/CRAM/Register
Command
16 / 0
Address
Data
Note 50. PRAM
PRAM/CRAM/OFREG
0bit (
16bit
)
0
RQN
SCLK
SI
SO
don’t care
(L/H)
Low
MS1328-J-00
Command (8bit)
Address (16bit or 0bit )
Data ( write )
don’t care
(L/H)
Data ( read )
Low or Echo back
60
2011/09
[AK7722]
2.
BIT7
R/W
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
R/W
“1”
WRITE
“0”
READ
BIT6
0
0
0
BIT5
0
0
1
BIT4
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
BIT3~0
0100/0010
1000/0100/0010
0000
0000
0010
0100
0110
1000
1010
1100
CRAM
RUN
OFREG
RUN
CRAM, OFREG RUN
PRAM, CRAM, OFREG
(
)
00~0C
10~17
(
)
CRC
JX
MIR1
MIR2
MIR3
MIR4
3.
LSB
BIT[6:4]= “000” → “011”
BIT[6:4]= “100” → “111”
MS1328-J-00
16bit
61
2011/09
[AK7722]
4.
RAM
CRAM
80h~8Fh
16bit
24bit × n
90h~9Fh
16bit
24bit × n
A2h
A4h
B2h
B4h
B8h
C0h~CEh
D0h~D7h
F2h
F4h
16bit
16bit
16bit
16bit
16bit
OFREG
24bit × n
24bit × n
40bit × n
8bit
8bit
16bit
8bit
RUN
(80h
1 81h
2
8Fh
BIT3 BIT0
16)
(90h
1 91h
2
9Fh
BIT3 BIT0
16)
RUN
OFREG RUN
CRAM RUN
OFREG
(
CRAM
(
PRAM
(
00h~0Eh
10h~17h
CRC
JX
)
)
)
RAM
24h
32h
34h
38h
16bit
16bit
16bit
ALL0
24bit × n
24bit × n
24bit × n
40bit × n
40h~4Eh
50h~57h
60h
70h
72h
8bit
8bit
8bit
8bit
16bit
76h
32bit
78h
32bit
7Ah
32bit
7Ch
32bit
MS1328-J-00
CRAM, OFREG
OFREG
CRAM
PRAM
(
(
(
RUN
)
)
)
00h~0Eh
10h~17h
CRC
@MIR1
28bit
@MIR2
28bit
@MIR3
28bit
@MIR4
28bit
62
4bit Validity
0000
4bit Validity
0000
4bit Validity
0000
4bit Validity
0000
2011/09
[AK7722]
5.
AK7722
SO
(1)
RQN
SI
COMMAND
SO
OLD ECHO
SI
ADDRESS1
ADDRESS2
COMMAND
8bit
ADDRESS1
DATA1
“L” or “H” Fix
DATA2
ADDRESS2
DATA1
COMMAND
ADDRESS1
DATA2
COMMAND
SO
Figure 24.
1
RQN
SI
COMMAND
SO
OLD ECHO
Dummy 8bit
PRAM
OFREG
ADDRESS1
ADDRESS2
COMMAND
ADDRESS1
40bit
24bit
DATA1
ADDRESS2
Dummy
DATA2
Dummy 8bit
DATA1
DATA2
Dummy
(CRAM
)
Figure 25.
2
(2)
RQN
SI
SO
COMMAND
OLD ECHO
ADDRESS1
COMMAND
“L” or “H” Fix
ADDRESS2
ADDRESS1
READ DATA
READ
READ DATA
COMMAND
ADDRESS1
“L” or “H” Fix
COMMAND
PRAM
Figure 26.
MS1328-J-00
63
2011/09
[AK7722]
6.
6-1.
RAM(PRAM)
(
(1) COMMAND
B8h
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
(4) DATA1
0 0 0 0 D35 D34 D33 D32
(5) DATA2
D31~D24
(6) DATA3
D23~D16
(7) DATA4
D15~D8
(8) DATA5
D7~D0
(5byte
RAM(CRAM)
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
(
B4h
0 0 0 0 A11 A10 A9 A8
A7~A0
D23~D16
D15~D8
D7~D0
(3byte
)
)
)
)
REG(OFREG)
(
(1) COMMAND
B2h
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 A5 A4 A3 A2 A1 A0
(4) DATA1
00000000
(5) DATA2
0 0 0 D12 D11 D10 D9 D8
(6) DATA3
D7~D0
(3byte
6-2.
)
)
RUN
(1) COMMAND
(2) DATA
Note 51.
(
Input
C0h~CDh, D0h~D7h
D7~D0
RUN
(1) COMMAND
(2) DATA
Input
F4h
D7~D0
RUN
(
CRC
(1) COMMAND
(2) DATA
(3) DATA
MS1328-J-00
(
)
RUN )
RUN )
SI
F2h
D15~D8
D7~D0
64
2011/09
[AK7722]
6-3. RUN
RAM(CRAM)
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
Note 52. COMMAND
(RUN )
Input
80h~8Fh (80h
1
0 0 0 0 A11 A10 A9 A8
A7~A0
D23~D16
D15~D8
D7~D0
(3byte
MS1328-J-00
16 )
)
Input
A4h
00000000
00000000
REG (OFREG)
(RUN )
Input
(1) COMMAND
90h~9Fh (90h
1
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 A5 A4 A3 A2 A1 A0
(4) DATA1
00000000
(5) DATA2
0 0 0 D12 D11 D10 D9 D8
(6) DATA3
D7~D0
(3byte
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
Note 53. COMMAND
8Fh
9Fh
16 )
)
Input
A2h
00000000
00000000
65
2011/09
[AK7722]
6-4.
RAM(PRAM)
(
)
Input
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
(7) DATA4
(8) DATA5
Output
38h
00000000
00000000
0 0 0 0 D35 D34 D33 D32
D31~D24
D23~D16
D15~D8
D7~D0
)
(5byte
RAM(CRAM)
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
(
)
Input
34h
0 0 0 0 A11 A10 A9 A8
A7~A0
Output
D23~D16
D15~D8
D7~D0
(3byte
REG(OFREG)
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
)
(
)
Input
32h
00000000
0 0 A5 A4 A3 A2 A1 A0
Output
00000000
0 0 0 D12 D11 D10 D9 D8
D7~D0
)
(3byte
MS1328-J-00
66
2011/09
[AK7722]
6-5.
RUN
(
RUN
)
Input
(1) COMMAND
(2) DATA
Output
40h~4Eh, 50h~57h
D7~D0
(
RUN )
Input
(1) COMMAND
(2) DATA
CRC
D7
0
(
RUN
D6
0
D5
1
2
D4
0
D3
0
D2
0
2
D1
1
D0
0
)
Write data
0x72
(1) COMMAND
(2) DATA
(3) DATA
(1) COMMAND
(2) DATA
Output
60h
Readout data
D15~D8
D7~D0
(
Write data
0x70
RUN )
Readout data
D7
D6
D5
D4
CRCERRN
WDTERRN
GPO0
GPO1
D3
0
D2
0
D1
0
D0
0
6-6. RUN
CRAM/OFREG
(RUN )
Input
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
MIR1/2/3/4
A15~A8
A8~A0
D23~D16
D15~D8
D7~D0
(RUN )
Input
76h (MIR1
)
78h (MIR2
)
7Ah (MIR3
)
7Ch (MIR4
)
(1) COMMAND
(2) DATA1
(3) DATA2
(4) DATA3
(5) DATA4
Note 54. flag
MS1328-J-00
Output
24h
Output
D19~D12
D11~D4
D3~D0 0 0 0 0
Exp3~Exp0 (flag) (flag) (flag) (flag)
flag bit
“1”
“0”
67
2011/09
[AK7722]
7.
7-1.
RAM
RAM(PRAM)
RAM(CRAM)
REG(OFREG)
PRAM
0h
RQN pin
“H”
“L”
PRAM
DSPRSTN
CRSTN
RQN
SCLK
SI
don’tcare
(L/H)
Command
Address
DATA
DATA
DATA
DATA
DATA
don’tcare
(L/H)
Address
DATA
don’tcare
(L/H)
RDY = “H”
Figure 27.
RAM
DSPRSTN
CRSTN
RQN
SCLK
SI
don’tcare
(L/H)
Command
don’tcare
(L/H)
Address DATA
Command
RDY = “H”
Figure 28.
MS1328-J-00
RAM
68
2011/09
[AK7722]
7-2. RUN
RAM
RAM(CRAM)
REG(OFREG)
1)
1~16
(16bit),
(8bit)
2)
24h
0x000001
3)
RUN
(16bit all “0”)
RUN
Note 55.
RDY
“H”
RAM
RAM
RAM
5
“10”
7
RAM
8
9
10
↓
11
↓
13
16
11
12
↓
13
↓
14
↓
15
↑
“13”
“12”
DSPRSTN= “1”
RQN
DATA
SCLK
SI
4
OFRAM Command 0x93
CRAM Command 0x83
don’tcare
(L/H)
RDY = “H”
Command
Address
DATA
DATA
DATA
don’tcare
(L/H)
DATA
CRAM
0x80(DATA
1
) ~ 0x8F(DATA
16
)
OFREG
0x90(DATA
1
) ~ 0x9F(DATA
16
)
Figure 29. CRAM, OFREG
MS1328-J-00
69
2011/09
[AK7722]
RQN
SCLK
don’t care
(L/H)
SI
don’t care
(L/H)
24h
SO
Address
DATA
DATA
DATA
DATA
DATA
RDY= “H”
Figure 30. CRAM, OFREG
DSPRSTN = “1”
RQN
SCLK
SI
don’tcare
(L/H)
Command
00000000
00000000
don’tcare
(L/H)
max 400ns
CRAM0xA4, OFREG0xA2
RDY
RDYLG (Note 56)
Note 56. RDYLG
RQN pin
1
2LRCK
“L”
RDY
RDY
CHIP
“L”
Figure 31. CRAM, OFREG
MS1328-J-00
70
2011/09
[AK7722]
7-3.
(
(1) COMMAND
(2) DATA
RUN )
F4h
D7~D0
DSP
RDY pin
RUN
“L”
LRCKO
“H”
“1” 1
RDY
8 bit
“H”
IFCON
IFCON
INITRSTN pin = “L”
00h
7
■
6
■
5
■
IFCON
16
4
3
■ ■
↑
“1”
2
■
↓
1
■
0
■
9
IFCON
DSPRSTN
SCLK
SI
don’tcare
(L/H)
F4h
D7
D0
don’tcare
(L/H)
Lch
RQN
Rch
LRCKO
RDY
Figure 32.
MS1328-J-00
(
71
)
2011/09
[AK7722]
DSPRSTN bit= “1”
SCLK
SI
F4h
don’tcare
(L/H)
D7 ….
D0
don’tcare
(L/H)
RQN
L ch
R ch
LRCKO
max 2LRCK
RDY
max0.25LRCK
(RUN
Figure 33.
7-4.
)
RAM
RAM(PRAM)
RAM(CRAM)
SO
REG(OFREG)
PRAM
(SI
Don’t care
0h
)
SCLK
SCLK
DSPRSTN
RQN
SCLK
SI
don’t care
(L/H)
Command
Address
SO
don’t care
(L/H)
DATA
DATA
DATA
DATA
DATA
RDY = “H”
Figure 34.
7-5.
RUN
CRC
RUN
SO
MS1328-J-00
SCLK
(SI
Don’t care
72
)
2011/09
[AK7722]
DSPRSTN
RQN
SCLK
don’tcare
(L/H)
SI
Command
Address
don’tcare
(L/H)
SO
DATA
RDY = “H”
Figure 35.
■ I2C
RUN
(I2CSEL= “H”)
AK7722
I 2C
I2CSEL pin= “H”
(max: 400kHz)
I2C
Hs
(max: 3.4MHz)
1.
IC
·
1
·
IC
IC
IC
READ
WRITE
·
1-1.
SDA
SCL
“L”
“L”
SCL
“H”
“H”
“H”
“L”
SDA
SDA
SCL
·
·
SCL
SDA
DATA LINE
STABLE:
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 36.
MS1328-J-00
73
2011/09
[AK7722]
1-2.
(Start Condition)
SCL
“H”
SDA
“H”
(Stop Condition)
“L”
·
·
“H”
SCL
·
SDA
“L”
“H”
·
SCL
SDA
START CONDITION
STOP CONDITION
Figure 37.
1-3.
(Repeated Start Condition)
SCL
SDA
START CONDITION
Repeated Start CONDITION
Figure 38.
1-4.
(Acknowledge)
IC
IC
1
SDA
SDA
)
“L”
AK7722
WRITE
AK7722
·
READ
SDA
·
SDA
AK7722
·
AK7722
MS1328-J-00
(HIGH
(Not Acknowledge)
74
2011/09
[AK7722]
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
not acknowledge
acknowledge
START
CONDITION
Figure 39.
(acknowledge)
1-5.
IC
“00110”
IC
7
2
5
IC
·
READ
R/W bit=“0”
Note 57.
8
WRITE
(
)
CAD1, CAD0 pin
IC
R/W bit
R/W bit= “1”
R/W bit= “0”
R/W
bit= “1”
0
0
1
1
0
CAD1
CAD0
R/W
(CAD1, CAD0
)
Figure 40.
1-6.
I2C
AK7722
8
I2C
MS1328-J-00
75
MSB
8
2011/09
[AK7722]
A1B2C3(hex)
24bit
2
IC
(1)I2C
(1)
A1
B2
C3
A1
B2
A
24BIT
8BIT
C3
A
8BIT
8BIT
A …Acknowledge
Figure 41.
Note 58.
Write
Read
Write
Read
2. Write
AK7722
Write
(Figure 42 *1)
Write
Table 3. Write
S
SLAD
W
A
Cmd
A
Data
A
Write
Stp
repeat N times (*1)
Figure 42. Write
MS1328-J-00
76
2011/09
[AK7722]
80h~8Fh
2byte
3byte
×n
CRAM
RUN
(80h
90h~9Fh
2byte
3byte
×n
OFREG
C0h~CEh
2byte
2byte
2byte
2byte
2byte
ALL0
3byte
3byte
5byte
×n
×n
×n
OFREG RUN
CRAM RUN
OFREG
CRAM
PRAM
1byte
1byte
1byte
1byte
1 91h
(
BIT3~BIT0
9Fh
16)
2
)
(
(
)
)
RUN
)
10h~17h
CRC
JX
RAM
Table 3. Write
MS1328-J-00
BIT3~BIT0
8Fh
16)
2
00h~0Eh
(
D0h~D7h
F2h
F4h
Note 59.
81h
RUN
(90h
A2h
A4h
B2h
B4h
B8h
1
Write
77
2011/09
[AK7722]
3. Read
AK7722
Read
Read
Figure 43 (*2)
)
(
Figure 43
(*3)
Read
AK7722
Read
Table 4. Read
S
SLAD
W
A
Cmd
A
Data
A
rS
SLAD
R
Repeat N times (*2)
Read
A
Data
A
Data
Na
Stp
Repeat N-1 times (*3)
Figure 43. Read
24h
32h
34h
38h
2byte
2byte
2byte
ALL0
3byte
3byte
3byte
5byte
40h~4Eh
50h~57h
60h
70h
72h
76h
1byte
1byte
1byte
1byte
2byte
4byte
78h
4byte
7Ah
4byte
7Ch
4byte
n
n
n
n
OFREG
CRAM
PRAM
(
)
)
00h~0Eh
10h~17h
CRC
@MIR1
28bit
@MIR2
28bit
@MIR3
28bit
@MIR4
28bit
Note 60.
4bit Validity
0000
4bit Validity
0000
4bit Validity
0000
4bit Validity
0000
RAM
Note 61.
0x70(
Table 4. Read
MS1328-J-00
)
(
(
)
Read
78
2011/09
[AK7722]
4.
AK7722
RDY pin
“L”
“H”
pin
“L”
RDY pin
(I2CSEL= “L”)
RDY pin
AK7722
“H”
4-1.
AK7722
RDY pin
“L”
RDY pin “L”
RDY pin
RDY pin “L”
RDY pin
“H”
Figure 44. RDY pin
4-2.
RDY
RDY pin
RDY pin
“L”
RDY pin
“L”
Figure 44. RDY pin
4-3. RDY pin
High
RDY pin
“H”
Note 62.
RDY pin
“H”
Figure 44. RDY pin
RDY= “L”
RDY
…
Data
RDY= “L”
A
Stp
S
SLAD
W Na …
S
SLAD
W Na …
RDY= “H”
S
SLAD
W
A
…
RDY
Figure 44. RDY pin
MS1328-J-00
79
2011/09
[AK7722]
4-4. Read
Read
AK7722
Read
Read
AK7722
Read
RDY pin
“L”
Read
“H”
(Note 63)
Note 63.
I2C
S
SLAD
W Na
Cmd
Na
xxx
Na
rS
SLAD
R Na
Read
N
RDY
Read
RDY “H”
Figure 45. Read
I2C
I2C
(1) Hs
(max: 3.4MHz)
(max: 400kHz)
(2)
(3)
Note 64. I2C BUS
(I2CSEL pin= “H”)
SDA pin , SCL pin
SDA, SCL pin
DVDD
MS1328-J-00
ON
DVDD
80
AK7722
OFF
2011/09
[AK7722]
Note: I2C
SLAD
…SlaveAddress (7 bits)
Cmd
…Command Code (8 bits)
S
…StartCondition
rS
…Repeated StartCondition
Stp
…St opCondition
W
…
R/W
Write(=0)
Write (1 bit)
R
…
R/W
Read(=1)
Read (1 bit)
A
…Acknowledge (1 bit)
Na
…NotAcknowledge (1 bit)
(Gray)
(White)
MS1328-J-00
…
AK7722
81
2011/09
[AK7722]
■ ADC
1. ADC
AK7722
ADC1, ADC2
HPF
(fs)
DC
(HPF)
48kHz
0.93Hz
2. ADC1
AK7722 ADC1
2
ASEL[2:0]bits (CONT 0C D6, D5, D4)
MUTE
D6, D5, D4: ASEL[2:0] ADC
ASEL Mode
ASEL1[2:0]
0
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
44.1kHz
0.86Hz
8kHz
0.16Hz
4
( 5. ADC1
)
AIN1LP, AIN1LN, AIN1RP, AIN1RN
AIN2LP, AIN2LN, AIN2RP, AIN2RN
AIN3L, AIN3R
AIN4L, AIN4R
AIN5L, AIN5R
AIN6L, AIN6R
No connection
No connection
MUTE
(default)
3. ADC
ADC
bit
ADC1, ADC2
AD1SMUTE, AD2SMUTE bit
VOLA** × ATT Speed
-∞ (0)
“0”
-∞
VOLA** × ATT Speed VOLA**
-∞
-∞
“L”
“1”
Attenuation 0dB
912LRCLK
ADC
(VOLA**=VOLA1L, VOLA1R, VOLA2L, VOLA2R)
VOLA**
AD1SMUTE, AD2SMUTE
-∞
VOLA**
Attenuation 0dB
INITRSTN pin=
AD*SMUTE
GD
GD
0dB
Attenuation
-
912LRCK
dB
(max)
912LRCK
(max)
Figure 46.
MS1328-J-00
82
2011/09
[AK7722]
4. ADC (ADC1, ADC2)
AK7722 ADC
Lch, Rch
(256
ADC1 Lch
VOLA1L [7:0]
ADC2 Lch
VOLA2L [7:0]
00h
01h
02h
:
2Fh
30h
31h
:
FDh
FEh
FFh
, 0.5dB
ADC1 Rch
VOLA1R [7:0]
ADC2 Rch
VOLA2R [7:0]
00h
01h
02h
:
2Fh
30h
31h
:
FDh
FEh
FFh
)
Attenuation Level
Attenuation Level
+24.0dB
+23.5dB
+23.0dB
:
+0.5dB
0.0dB
-0.5dB
:
-102.5dB
-103.0dB
Mute (-∞)
(default)
Table 5. ADC (ADC1, ADC2)
ATSPAD bit
ADC1 ADC2
MODE
0
1
ATSPAD bit
0
1
ATT speed
1/fs
4/fs
(default)
Table 6. ADC
ATT
([email protected]=48kHz)
MS1328-J-00
1021
00h
ADC
83
FFh (MUTE)
30h
Mode0
1021/fs
2011/09
[AK7722]
CODE
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
dB
24.0
23.5
23.0
22.5
22.0
21.5
21.0
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
CODE
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
dB
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
-5.5
-.6.0
-6.5
-7.0
-7.5
CODE
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
dB
-8.0
-8.5
-9.0
-9.5
-10.0
-10.5
-11.0
-11.5
-12.0
-12.5
-13.0
-13.5
-14.0
-14.5
-15.0
-15.5
-16.0
-16.5
-17.0
-17.5
-18.0
-18.5
-19.0
-19.5
-20.0
-20.5
-21.0
-21.5
-22.0
-22.5
-23.0
-23.5
CODE
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
dB
-24.0
-24.5
-25.0
-25.5
-26.0
-26.5
-27.0
-27.5
-28.0
-28.5
-29.0
-29.5
-30.0
-30.5
-31.0
-31.5
-32.0
-32.5
-33.0
-33.5
-34.0
-34.5
-35.0
-35.5
-36.0
-36.5
-37.0
-37.5
-38.0
-38.5
-39.0
-39.5
CODE
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
dB
-40.0
-40.5
-41.0
-41.5
-42.0
-42.5
-43.0
-43.5
-44.0
-44.5
-45.0
-45.5
-46.0
-46.5
-47.0
-47.5
-48.0
-48.5
-49.0
-49.5
-50.0
-50.5
-51.0
-51.5
-52.0
-52.5
-53.0
-53.5
-54.0
-54.5
-55.0
-55.5
CODE
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
dB
-56.0
-56.5
-57.0
-57.5
-58.0
-58.5
-59.0
-59.5
-60.0
-60.5
-61.0
-61.5
-62.0
-62.5
-63.0
-63.5
-64.0
-64.5
-65.0
-65.5
-66.0
-66.5
-67.0
-67.5
-68.0
-68.5
-69.0
-69.5
-70.0
-70.5
-71.0
-71.5
CODE
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
DB
-72.0
-72.5
-73.0
-73.5
-74.0
-74.5
-75.0
-75.5
-76.0
-76.5
-77.0
-77.5
-78.0
-78.5
-79.0
-79.5
-80.0
-80.5
-81.0
-81.5
-82.0
-82.5
-83.0
-83.5
-84.0
-84.5
-85.0
-85.5
-86.0
-86.5
-87.0
-87.5
CODE
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
dB
-88.0
-88.5
-89.0
-89.5
-90.0
-90.5
-91.0
-91.5
-92.0
-92.5
-93.0
-93.5
-94.0
-94.5
-95.0
-95.5
-96.0
-96.5
-97.0
-97.5
-98.0
-98.5
-99.0
-99.5
-100.0
-100.5
-101.0
-101.5
-102.0
-102.5
-103.0
Mute
Table 7. ADC(ADC1, ADC2)
MS1328-J-00
84
2011/09
[AK7722]
5. ADC1
ADSMUTE
(2)
(1)
(1)
DATT Level
(3)
Attenuation
-∞
AINL1/AINR1
Channel
AINL2/AINR2
Figure 47.
(1)
DATT
Attenuation 0dB
ATSPAD
(CONT0D D5)
0
1
200ms
MS1328-J-00
-∞
-∞
DATT
+24dB
Attenuation 0dB
(1)
LRCLK
912LRCLK
912LRCLKx4
(max)
fs=48kHz
19ms
76ms
Mute
fs=44.1kHz
20.68ms
82.72ms
1021/fs
fs=8kHz
114ms
456ms
(2)
(3)
85
2011/09
[AK7722]
■ DAC
1. DAC
AK7722 DAC Lch, Rch
DAC
VOLDA2R[7:0] (DAC2) bit
DAC2 Lch
VOLDA2L
[7:0]
00h
01h
02h
:
17h
18h
19h
:
FDh
FEh
FFh
(256
, 0.5dB
)
VOLDA1L[7:0], VOLDA1R[7:0] (DAC1), VOLDA2L[7:0],
DAC2 Rch
VOLDA2R
[7:0]
00h
01h
02h
:
17h
18h
19h
:
FDh
FEh
FFh
DAC1 Lch
VOLDA1L
[7:0]
00h
01h
02h
:
17h
18h
19h
:
FDh
FEh
FFh
DAC1 Rch
VOLDA1R
[7:0]
00h
01h
02h
:
17h
18h
19h
:
FDh
FEh
FFh
Attenuation
Level
+12.0dB
+11.5dB
+11.0dB
:
+0.5dB
0.0dB
-0.5dB
:
-114.5dB
-115.0dB
Mute (-∞)
(default)
Table 8. DAC1, DAC2
ATSPDA bit
DAC1 DAC2
MODE
ATSPDA
ATT speed
0
1
0
1
1/fs
4/fs
(default)
Table 9. DAC1, DAC2
ATT
([email protected]=48kHz)
MS1328-J-00
1021
00h
DAC1, DAC2
86
FFh (MUTE)
18h
Mode0
1021/fs
2011/09
[AK7722]
CODE
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
dB
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
CODE
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
dB
-4.0
-4.5
-5.0
-5.5
-.6.0
-6.5
-7.0
-7.5
-8.0
-8.5
-9.0
-9.5
-10.0
-10.5
-11.0
-11.5
-12.0
-12.5
-13.0
-13.5
-14.0
-14.5
-15.0
-15.5
-16.0
-16.5
-17.0
-17.5
-18.0
-18.5
-19.0
-19.5
CODE
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
dB
-20.0
-20.5
-21.0
-21.5
-22.0
-22.5
-23.0
-23.5
-24.0
-24.5
-25.0
-25.5
-26.0
-26.5
-27.0
-27.5
-28.0
-28.5
-29.0
-29.5
-30.0
-30.5
-31.0
-31.5
-32.0
-32.5
-33.0
-33.5
-34.0
-34.5
-35.0
-35.5
CODE
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
dB
-36.0
-36.5
-37.0
-37.5
-38.0
-38.5
-39.0
-39.5
-40.0
-40.5
-41.0
-41.5
-42.0
-42.5
-43.0
-43.5
-44.0
-44.5
-45.0
-45.5
-46.0
-46.5
-47.0
-47.5
-48.0
-48.5
-49.0
-49.5
-50.0
-50.5
-51.0
-51.5
CODE
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
dB
-52.0
-52.5
-53.0
-53.5
-54.0
-54.5
-55.0
-55.5
-56.0
-56.5
-57.0
-57.5
-58.0
-58.5
-59.0
-59.5
-60.0
-60.5
-61.0
-61.5
-62.0
-62.5
-63.0
-63.5
-64.0
-64.5
-65.0
-65.5
-66.0
-66.5
-67.0
-67.5
CODE
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
dB
-68.0
-68.5
-69.0
-69.5
-70.0
-70.5
-71.0
-71.5
-72.0
-72.5
-73.0
-73.5
-74.0
-74.5
-75.0
-75.5
-76.0
-76.5
-77.0
-77.5
-78.0
-78.5
-79.0
-79.5
-80.0
-80.5
-81.0
-81.5
-82.0
-82.5
-83.0
-83.5
CODE
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
dB
-84.0
-84.5
-85.0
-85.5
-86.0
-86.5
-87.0
-87.5
-88.0
-88.5
-89.0
-89.5
-90.0
-90.5
-91.0
-91.5
-92.0
-92.5
-93.0
-93.5
-94.0
-94.5
-95.0
-95.5
-96.0
-96.5
-97.0
-97.5
-98.0
-98.5
-99.0
-99.5
CODE
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
dB
-100.0
-100.5
-101.0
-101.5
-102.0
-102.5
-103.0
-103.5
-104.0
-104.5
-105.0
-105.5
-106.0
-106.5
-107.0
-107.5
-108.0
-108.5
-109.0
-109.5
-110.0
-110.5
-111.0
-111.5
-112.0
-112.5
-113.0
-113.5
-114.0
-114.5
-115.0
Mute
Table 10. DAC
MS1328-J-00
87
2011/09
[AK7722]
2. DAC
DAC1, DAC2
DA1SMUTE, DA2SMUTE bit = “1”
VOLDA** × ATT Speed
-∞ (0)
= “0”
-∞
VOLDA** × ATT Speed VLODAxx
DAC
DA1RST bit = “1”, DA2RST bit = “1”
CRSTN bit = “0”
VOLDA**
DA1SMUTE, DA2SMUTE bit
-∞
VOLDA**
dB
DAC
INITRSTN pin = “L”
(VOLA**=VOLDA1L,
VOLDA1R, VOLDA2L, VOLDA2R)
SMUTE
+2LRCK(max)
+2LRCK(max)
0dB
Attenuation
-
dB
GD
GD
Figure 48. DAC
MS1328-J-00
88
2011/09
[AK7722]
■ SRC
1.
AK7722
(FSI)
FSO/FSI 1
7.35kHz~48kHz
(FSO/FSI)
FSO/FSI = 0.167~6.0
1-1.
FSO
48kHz
48kHz
48kHz
48kHz
48kHz
48kHz
48kHz
44.1kHz
44.1kHz
44.1kHz
44.1kHz
44.1kHz
44.1kHz
32kHz
8kHz
Note 65. Pass Band
1-2.
FSO
48kHz
44.1kHz
44.1kHz
16kHz
8kHz
8kHz
8kHz
8kHz
Note 66. Pass Band
Note 67.
Note 68.
MS1328-J-00
(0.98
FSO/FSI
FSI
48kHz
44.1kHz
32kHz
24kHz
16kHz
12kHz
8kHz
44.1kHz
32kHz
24kHz
16kHz
12kHz
8kHz
32kHz
8kHz
Stop Band
FSI
(SRC)
7.35kHz~48kHz
7.35kHz~96kHz
(FSO)
6.00)
FSO/FSI
1.00
1.09
1.50
2.00
3.00
4.00
6.00
1.00
1.38
1.84
2.76
3.68
5.51
1.00
1.00
Pass Band
22.00kHz
20.21kHz
14.67kHz
11.00kHz
7.33kHz
5.50kHz
3.67kHz
20.21kHz
14.67kHz
11.00kHz
7.33kHz
5.50kHz
3.67kHz
14.67kHz
3.67kHz
Stop Band
26.00kHz
23.89kHz
17.33kHz
13.00kHz
8.67kHz
6.50kHz
4.33kHz
23.89kHz
17.33kHz
13.00kHz
8.67kHz
6.50kHz
4.33kHz
17.33kHz
4.33kHz
(0.167
FSO/FSI 0.99)
(FSO/FSI)
0.919, 0.50, 0.25, 0.181, 0.167 5
FSI
FSO/FSI
Pass Band
Stop Band
96kHz
0.50
19.25kHz
26.23kHz
88.2kHz
0.50
17.69kHz
24.10kHz
48kHz
0.919
20.00kHz
24.10kHz
32kHz
0.50
6.42kHz
8.74kHz
48kHz
0.167 (Note 67)
4.40kHz
6.50kHz
44.1KHz
0.181 (Note 68)
4.04kHz
5.97kHz
32kHz
0.25
2.93kHz
3.98kHz
16kHz
0.50
3.21kHz
4.37kHz
Stop Band
FSI
FSO=8kHz / FSI=48kHz
fs=8kHz
4kHz
Pass Band, Stop Band
FSO=8kHz / FSI=44.1kHz
89
fs=8kHz
4kHz
Pass Band, Stop Band
2011/09
[AK7722]
2. SRC
2-1.
AK7722 SRC
(SRCI)
SRIN1-3 pin 3
3
DSEL[1:0]bits (CONT 0B D5,D4)
PLL
(SETSRC bit= “0”)
SRLRCKn (n=1, 2, 3)
(SETSRC bit= “1”)
SRBICKn (n=1, 2, 3)
PLL
SRC
2's
MSB
CONT 0B
D5, D4: DSEL[1:0] SRC
DSEL[1:0] SRC
00
SRIN1, SRBICK1, SRLRCK1
01
SRIN2, SRBICK2, SRLRCK2
10
SRIN3, SRBICK3, SRLRCK3
11
N/A
CONT 0A
D7: BIEDGE SRBICKn (n=1, 2, 3)
0: SRLRCKn (n=1, 2, 3)
(default)
tBICK
SF
SRLRCK1-3
SRBICK1-3
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
1: SRLRCK1-3
tBICK
SF
SRLRCK1-3
SRBICK1-3
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
Figure 49. SRBICK1-3
D6, D5, D4: IDIF[2:0]
SRC
fsi: SRC
IDIF Mode
IDIF[2]
IDIF[1]
IDIF[0]
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
Note 69. SRBICK1-3
PLL
BIFS[1:0]
SETSRC bit= “1”
Table 11. SRC
MS1328-J-00
SRBICK1-3
32fsi
40fsi
48fsi
48fsi or 32fsi
48fsi
16bit
20bit
24/20bit
24/16bit
I2S
24bit
N/A
PCM SHORT(24bit)
BIFS[1:0]
PCM LONG(24bit)
BIFS[1:0]
(SETSRC bit= “0”) SRBICK1-3 pin
SRBICK1-3
48fsi
90
(default)
2011/09
[AK7722]
D3, D2: BIFS[1:0] SRBICK1-3
BIFS Mode
BIFS[1]
BIFS[0]
SRBICK1-3
0
0
0
32fsi
(default)
1
0
1
64fsi
2
1
0
128fsi
3
1
1
N/A
Note 70.
SRBICK1-3
PLL
(SETSRC bit = “0”)
128fsi fsi=48kHz
Table 12. SRBICK1-3
IDIF mode6/7
Left ch
SRLRCK1-3
Right ch
SRBICK1-3
31 30
23 22 21 20 19 18 17 16 15 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
SRIN1-3
IDIF mode 4
Don’t care M 22 21 20 19 18 17 16 15 14
1 L Don’t care M 2221 20 19 18 17 16 15 14
1 L
SRIN1-3
IDIF mode 1
Don’t care
M 18 17 16 15 14
1 L Don’t care
M 18 17 16 15 14
1 L
SRIN1-3
IDIF mode 0
Don’t care
M 14
1 L Don’t care
M 14
1 L
M: MSB, L: LSB
Figure 50. IDIF Mode 0/1/4 @BIEDGE bit= “0”, SRBICK1-3 64fs
Left ch
SRLRCK1-3
Right ch
SRBICK1-3
SRIN1-3
IDIF mode 2
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M 22 21 20 19
2 1 L
2 1 L
M 22 21 20 19
M: MSB ,L: LSB
Figure 51. IDIF Mode 2 @BIEDGE bit= “0”, SRBICK1-3 64fs
SRLRCK1-3
Left ch
Right ch
SRBICLK1-3
23 22 21 20 19 18 17 16 23 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0
SRIN1-3
IDIF mode 2
M 22 21 20 19 18 17 16 7 6 5 4 3 2 1 L M 22 21 20 19 18 17 16 7 6 5 4 3 2 1 L
Figure 52. IDIF Mode 2 @BIEDGE bit= “0”, SRBICK1-3 48fs (SETSRC bit = “1”
MS1328-J-00
91
M: MSB
L: LSB
)
2011/09
[AK7722]
Left ch
SRLRCK1-3
Right ch
SRBICK1-3
31 30 29 28 27
SRIN1-3
IDIF mode 3
M 22 21 20
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
3 2 1 L
3 2 1 L
M 22 21 20
M: MSB, L: LSB
Figure 53. IDIF Mode 3 @BIEDGE bit= “0”, SRBICK1-3 64fs
SRLRCK1-3
tBICK
SF
SRBICK1-3
SRIN1-3
IDIF mode 6
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
M 22 21 20 19
2 1 L
L ch
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
2 1 L
R ch
tBICK × 32
Figure 54. IDIF Mode 6 @BIEDGE bit= “1”, BIFS[1:0]=1h
SRLRCK1-3
tBICK
SF
SRBICK1-3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRIN1-3
IDIF mode 6
M: MSB
L: LSB
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L
tBICK × 16
Lch
R ch
Figure 55. IDIF Mode 6 @BIEDGE bit= “1”, BIFS[1:0]=0h
MS1328-J-00
92
2011/09
[AK7722]
1 ≤ tBICK ≤ 60
SRLRCK1-3
LF
SRBICK1-3
SRIN1-3
IDIF mode 7
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
M 22 21 20 19
2 1 L
tBCLK M 22 21 20 19
L ch
10 9 8 7 6 5 4 3 2 1 0
2 1 L
M: MSB, L: LSB
R ch
tBICK × 32
Figure 56. IDIF Mode 7 @BIEDGE bit= “1”, BIFS[1:0]=1h
LF
tBCLK
1 ≤ tBICK ≤ 28
SRLRCK1-3
SRBICK1-3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRIN1-3
IDIF mode 7
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L
L ch
M: MSB
L: LSB
R ch
tBICK × 16
Figure 57. IDIF Mode 7 @BIEDGE bit= “1”, BIFS[1:0]=0h
MS1328-J-00
93
2011/09
[AK7722]
2-2.
SRC
2's
fs=48kHz
bit = “1”
24bit
44.1kHz
LRCKO, BICKO
CONT0 DIFI2S
I2S
CONT0 DIFI2S(D6) bit= “0”
Left ch
LRCKO
Right ch
BICKO
31 30 29 28 27
SRCO
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
2 1 L
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
2 1 L
M: MSB, L: LSB
CONT0 DIFI2S(D6) bit = “1”
Left ch
LRCKO
Right ch
BICKO
31 30 29 28 27
SRCO
M 22 21 20
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
3 2 1 L
M 22 21 20
10 9 8 7 6 5 4 3 2 1 0
3 2 1 L
M: MSB, L: LSB
Figure 58. SRC
MS1328-J-00
94
2011/09
[AK7722]
3.
3-1. Manual Mode
SRCSMUTE bit “1”
SRCSMUTE bit “0”
1024 LRCKO
-∞
1024 LRCKO
-∞
-∞ (“0”)
1024 LRCKO
0dB
0dB
SRCSMUTE
0dB
Attenuation Level
on SRCO
(2)
-∞dB
(1)
(1) 1024LRCLKO
(2)
(1)
−∞ (“0”)
(GD)
(1024/fso)
1024LRCLKO
0dB
Figure 59.
Manual Mode
3-2. Semi-Auto Mode
FSO=44.1kHz
bit= “0”)
SRCRST
FSO
(fso)
8kHz
44.1kHz
48kHz
SRCRST
(SRCRST bit = “1”→ “0”)
200ms (SETSRC bit= “1”)
SRCSMUTE bit “1”
FSO, SETSRC
(
)
Bit
SETSRC
1
0
1
0
1
0
50ms (SETSRC
FSO, SETSRC bit
AUTOSEL bit
AUTOSEL
1
1103ms
8820/fso
0
276ms
2205/fso
1
200 ms
8820/fso
0
50 ms
2205/fso
1
184ms
8820/fso
0
46ms
2205/fso
(AUTOSEL bit= “0”: 2205/fso, AUTOSEL bit=“1”: 8820/fso)
Table 13. Semi-Auto mode
MS1328-J-00
- 95 -
2011/09
[AK7722]
SRCRST
“H”
SRCSMUTE
Don’t Care
“L”
(1)
2205/fso(SAUTOSEL=0)
@44.1kHz,48kHz
8820/fso(SAUTOSEL=1)
@44.1kHz,48kHz
0dB
Attenuation
-∞
(2)
GD
SRCO
(1) 1024LRCKO
(2)
(1024/fso)
0dB
(GD)
Figure 60.
Semi-Auto Mode
4. SRC
AK7722 SRC SRCRST bit “1”
SRCRST bit = “1”
SRCO
“L”
“0”
50ms
SETSRC bit = “1”
200ms
SRC
SRC
SRC
SRC
SETSRC bit =
“L”
AK7722
Case 1
External clocks
(Input port)
Don’t care
Input Clocks 1
Input Clocks 2
Don’t care
SRCI(SRINn)
Don’t care
Input Data 1
Input Data 2
Don’t care
LRCKO
BICKO
(Output port)
Don’t care
Output Clocks 1
Output Clocks 2
Don’t care
(Internal state) Power-down
SRCO
< 200ms(SETSRC=”1”)
< 200ms(SETSRC=”1”)
< 50ms(SETSRC=”0”)
SRCRST
PLL lock &
fs detection
“0” data
< 50ms(SETSRC=”0”)
Normal
operation
Normal data
PD
PLL lock &
fs detection
“0” data
Normal
operation
Power-down
Normal data
“0” data
SRC UNLOCK
1
Figure 61.
MS1328-J-00
- 96 -
2011/09
[AK7722]
Case 2
External clocks
(Input port)
(No Clock)
SRCI
External clocks
(Output port)
Input Clocks
Don’t care
(Don’t care)
Input Data
Don’t care
(Don’t care)
Output Clocks
Don’t care
< 200ms(SETSRC=”1”)
< 50ms(SETSRC=”0”)
SRCRST
(Internal state) Power-down
PLL lock &
fs detection
PLL Unlock
SRCO
“0” data
Normal
operation
Power-down
Normal data
“0” data
SRC UNLOCK
Figure 62.
2
5.
5-1.
AK7722 SRC
SETSRC bit = “0”
50 ms
SETSRC bit = “1”
200 ms
5-2.
AK7722 SRC
Figure 63
clocks
(input or output)
state 1
(unknown)
< 200ms(SETSRC bit=”1”)
< 50ms(SETSRC bit=”0”)
SRCRST
(interlal state)
SRCO
normal operation Power down PLL locktime
& fs detection
normal data
SRCSMUTE
(Note2,recommended)
Att.Level
state 2
normal operation
Note 1
normal data
1024/fso
1024/fso
0dB
-∞dB
Figure 63.
Note:
1.
2.
SRCRST bit
“0”
(SRINn = 1, 2, 3) “0”
Note 1
SRCMUTE bit = “1”
MS1328-J-00
- 97 -
“1”
GD
SRCI
2011/09
[AK7722]
6. SRCPLL
6-1. SETSRC bit
SETSRC bit (CONT0B: D0)
SRC PLL
SRBICKn (n=1, 2, 3) PLL
64fsi, 128fsi
“L”
“H”
BIFS[1:0]bits (CONT0A: D3, D2)
32fsi,
SETSRC Mode SETSRC bit PLL
0
0
SRBICKn (n=1, 2, 3)
1
1
SRLRCKn (n=1, 2, 3)
6-2. SRC PLL
SRCLFLT pin
(C)1μF 30% VSS
SRCLFLT pin
AK7722
SRCLFLT
C
VSS
Figure 64. PLL Loop Filter
(1) SRBICK1-3 PLL
SRC
50ms
(SETSRC bit = “0”)
(2) SRLRCK1-3 PLL
SRC
200ms
(SETSRC bit = “1”)
Note 71. SRBICK1-3
Note 72. SRBICK1-3= 32fsi 16bit LSB justified
Note 73. SRBICK1-3 PLL
N=32, 64, 128
I2S Compatible
SRBICK1-3
7. UNLOCK
SRC PLL
UNLOCK pin
UNLOCK pin “L”
PLL
(SRCRSTbit = “1”)
“H”
MS1328-J-00
N
AK7722 SRC PLL
UNLOCK pin “H”
- 98 -
SRC
2011/09
[AK7722]
■ GSRC
1.
1-1.
AK7722
(GSRC)
(FSI)
[
7.35kHz~12kHz
(FSO)
44.1kHz/48kHz
]
FSO
FSI
48kHz
7.35kHz
48kHz
12kHz
44.1kHz
44.1kHz
44.1kHz
7.35kHz
44.1kHz
12kHz
Pass Band Stop Band FSI
FSO/FSI
1.00
1.09
1.00
1.38
1.84
Pass Band
22.00kHz
20.21kHz
20.21kHz
14.67kHz
11.00kHz
Stop Band
26.00kHz
23.89kHz
23.89kHz
17.33kHz
13.00kHz
1-2. GSRC
[
GSRC
]
SDIN5 pin,
GLRCK pin, GBICK pin
GSRC
AK7722
SRC
GIDIF[2:0]bits (CONT0C)
2's
MSB
D2, D1, D0: GIDIF[2:0] GSRC
fsi : GSRC
GIDIF Mode
0
1
2
3
4
5
6
7
GIDIF[2:0]
000
001
010
011
100
101
110
111
GBICK
≥ 32fsi
≥ 40fsi
≥ 48fsi/40fsi
≥ 48fsi or 32fsi
≥ 48fsi
16bit
20bit
24/20bit
2
24/16bit
IS
24bit
N/A
N/A
N/A
Left ch
GLRCK
(default)
Right ch
GBICK
31 30
SDIN5
GIDIF Mode 0
Don’t care
23 22 21 20 19 18 17 16 15 14
M 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
1 L
M: MSB, L: LSB
Figure 65. GIDIF Mode 0 @GBICK 64fs
MS1328-J-00
- 99 -
2011/09
[AK7722]
Right ch
Left ch
GLRCK
GBICK
SDIN5
IDIF Mode 1
Don’t care
M 18 17 16 15 14
1 L
M: MSB, L: LSB
Figure 66. GIDIF Mode 1 @GBICK 64fs
Left ch
GLRCK
Right ch
GBICK
31 30 29 28 27
SDIN5
GIDIF Mode 2
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1
0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M: MSB, L: LSB
2 1 L
Figure 67. GIDIF Mode 2 @GBICK 64fs
Left ch
GLRCK
Right ch
GBICK
31 30 29 28 27
SDIN5
GIDIF Mode 3
M 22 21 20
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M: MSB, L: LSB
3 2 1 L
Figure 68. GIDIF Mode 3 @GBICK 64fs
Left ch
GLRCK
Right ch
GBICK
31 30
SDIN5
IDIF Mode 4
23 22 21 20 19 18 17 16 15 14
Don’t care M 22 21 20 19 18 17 16 15 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
1 L
Figure 69. GIDIF Mode 4 @GBICK 64fs
MS1328-J-00
- 100 -
2011/09
[AK7722]
■ MUX1
GSRC
GSRC
ADC2
MUX1[2:0]bits
ADC2
MUX1
1Ts(1/fs)
MUX1[2:0]
MUX1
Lch
000 (Default)
ADC2L
001
ADC2R
010
GSRC
011
ADC2L/2+GSRC/2
100
ADC2R/2+GSRC/2
101
ADC2L/2+ADC2R/2
110
ADC2L
111
GSRC
ADC2L/R:ADC2
Lch/Rch
GSRC:
SRC
Rch
ADC2R
ADC2L
GSRC
ADC2R
ADC2L
GSRC
GSRC
ADC2R
■ MUX2
SELDI5 bit
SELDO4[1:0]bits
MUX2E bit=”1”
MUX2
MUX2E
0 (Default)
MUX2[2:0]
Don’t care
000 (Default)
001
010
011
1
100
101
110
111
DO4L/R:SELDO4[1:0]
M1L/R:MUX1
Lch/Rch
MS1328-J-00
MUX2
Lch
DO4L
DO4L
M1L
DO4L
DO4L/2+M1L/2
DO4L
DO4L/2+M1L/2
M1L
M1L
Lch/Rch
- 101 -
MUX2[1:0]bits
MUX2
Rch
DO4R
DO4R
DO4R
M1L
DO4R
DO4R/2+M1L/2
DO4R/2+M1L/2
M1L
M1R
1Ts(1/fs)
1Ts(1/fs)
0Ts
1Ts
2011/09
[AK7722]
Figure 70, Figure 71
(AKD7722)
<
>
Digital +3.3V
0.1μ
0.1μ
17
CLKO
BICKO
LRCKO
SDOUT1
SDOUT2
SDOUT3
38
40
39
41
42
43
CLOCK
27
28
29
SRLRCK1
SRBICK1
SRIN1
45
46
47
SRLRCK2
SRBICK2
SRIN2
48
49
50
58
0.1μ
36
DVDD × 3
AK7722
10μ
57
I2CSEL
53
SCLK
32
SDA
35
SI
33
RQN
31
SO
34
STO
44
RDY
30
“L”
Micom
I/F
&
Audio I/F
Digital Ground
Analog Ground
INITRSTN
52
TESTI1
13
SRLRCK3
SRBICK3
SRIN3
TESTI2
54
SRCLFLT
XTO
20
XTI
9,8
7,6
AINR1P, AINR2N
AINL2P, AINL2N
5,4
AINL2P, AINL2N
AINR2P, AINR2N
3,2
AINR2P, AINR2N
AINL3, AINR3
1,80
AINL3, AINR3
AINL4, AINR4
79,78
AINL4, AINR4
AINL5, AINR5
77,76
AINL5, AINR5
AINL6, AINR6
75,74
AINL6, AINR6
12
66,65
AOUTL2P, AOUTL1N
64,63
AOUTR2P, AOUTR2N
62,61
A2INL, A2INR
73,72
A2INL, A2INR
LFLT
AVDD
GBICK
AVDD
GLRCK
16
SDIN5
15
GBICKI
14
GLRCKI
0.1μ
69
VCOM
AVDD
VSS
Figure 70.
70
0.1μ
0.1μ
11,59,71
MS1328-J-00
AOUTR1P, AOUTR1N
SDIN5
60
10μ
68,67
0.1μ
Analog +3.3V
10μ
CL=22pF
AOUTL1P, AOUTL1N
8.2k
10
10μ
19
AINL1P, AINL1N
AINR1P, AINR1N
33n
CL=22pF
Rd
1μ
AINL1P, AINL1N
RESET
CONTROL
VSS
2.2μ
18,37,56
(I2CSEL pin = “L”)
- 102 -
2011/09
[AK7722]
2
<I C
>
Digital +3.3V
0.1μ
0.1μ
17
0.1μ
36
DVDD × 3
10μ
57
I2CSEL
CLKO
BICKO
LRCKO
SDOUT1
SDOUT2
SDOUT3
38
40
39
41
42
43
CLOCK
27
28
29
SRLRCK1
SRBICK1
SRIN1
45
46
47
SRLRCK2
SRBICK2
SRIN2
SCL
SDA
CAD0
AK7722
CAD1
53
“H”
32
35
Micom
33
31
SO
34
STO
44
I/F
&
Audio I/F
INITRSTN
TESTI1
Digital Ground
48
49
50
SRLRCK3
SRBICK3
SRIN3
TESTI2
58
SRCLFLT
XTO
52
RESET
CONTROL
13
54
20
CL=22pF
Rd
Analog Ground
1μ
XTI 19
AINL1P, AINL1N
9,8
AINL1P, AINL1N
AINR1P, AINR1N
7,6
AINR1P, AINR2N
AINL2P, AINL2N
5,4
AINL2P, AINL2N
AINR2P, AINR2N
3,2
AINR2P, AINR2N
AINL3, AINR3
1,80
AINL3, AINR3
AINL4, AINR4
79,78
AINL4, AINR4
AINL5, AINR5
77,76
AINL5, AINR5
AINL6, AINR6
75,74
AINL6, AINR6
CL=22pF
AOUTL1P, AOUTL1N
AOUTR1P, AOUTR1N
AOUTL2P, AOUTL1N
AOUTR2P, AOUTR2N
A2INL, A2INR
68,67
66,65
64,63
62,61
73,72
A2INL, A2INR
12 LFLT
33n
8.2k
SDIN5
10
10μ
GBICK
0.1μ
Analog +3.3V
60
10μ
AVDD
GLRCK
VCOM
AVDD
15
GBICKI
14
GLRCKI
VSS
Figure 71.
70
0.1μ
0.1μ
11,59,71
MS1328-J-00
SDIN5
0.1μ
69
10μ
16
AVDD
VSS
2.2μ
18,37,56
(I2CSEL pin = “H”)
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2011/09
[AK7722]
1.
AK7722
AVDD
AVDD DVDD
VSS1-6
AK7722
2.
AVDD
VCOM pin AVDD/2
2.2μF
0.1μF
VSS
VCOM pin
VCOM pin
3.
FS=(AVDD-VSS)
2.0/3.3
AVDD=3.3V VSS=0.0V
2’s complement(2
)
2.00Vpp(typ)
HPF
DC
AK7722
AVDD/2
35kohm([email protected]=48kHz)
AK7722 fs=48kHz
3.042MHz
DC
3.072MHz
30kHz
AK7722
AAF
3.042MHz 3.072MHz
3.072MHz
ADC
D/A
ADC
+3.3V(typ)
AK7722
10mA
AVDD+0.3V
IC
VSS-0.3V
15V
10k
Signal
22μ
+
+12V
10k
68p
10k
+
+12V
2k
10k
2.20Vpp
68p
+
2k
+
LME49720MA
+
10k
2.2μ
10μ
10k
+
AIN2.20Vpp
0.1μ
Figure 72.
MS1328-J-00
AIN+
2.2μ
(
- 104 -
)
2011/09
[AK7722]
4.
8.2k
2.08Vpp
+
AOUT-
8.2k
300
22u
22u
AOUT+
4.16Vpp
+12V
2.2n
+
8.2k
+12V
22u
+
+
300
8.2k
270p
LME49720MA
220
VAOUT
10k
270p
4.7k
2.08Vpp
4.7k
10u +
0.1u
Figure 73.
AVDD/2
±2.08Vpp(typ)
VAOUT = (AOUT+) – (AOUT-)
AOUT+ AOUTVAOUT =4.16Vpp
7FFFFFH(@24bit)
VAOUT
0V
AVDD/2 + mV
Figure 73
LPF
2’s complement(2
)
000000H(@24bit)
800000H(@24bit)
DC
DC
5.
AK7722
CMOS
CMOS
74HC 74AC
74LV 74LV-A 74ALVC 74AVC
6.
AK7722 XTI pin
XTO pin
XTI XTO
CKM Mode
0
1
MS1328-J-00
R1 max
C0 max
70Ω
5pF
50Ω
5pF
Table 14.
- 105 -
XTI, XTO pin
22pF
10pF or 15pF
2011/09
[AK7722]
7. LFLT pin
AK7722 LFLT pin
CKM Mode
DFS[1:0]
0, 1, 2
0, 1, 2, 3
3, 4
0
0
1, 2
BITFS[1:0]
0, 1, 2
0, 1
2
0, 1, 2
R
8.2[k ]
5%
C1
33[nF]
30%
C2
or
0.1[nF] 30%
LFLTpin
R
C2
C1
AVSS
8. SRCLFLT pin
AK7722 SRCLFLT pin
C
1 F± 30%
MS1328-J-00
- 106 -
2011/09
[AK7722]
80pin LQFP (Unit: mm)
1.60 Max.
14.0±0.2
12.0
40
12.0
61
14.0±0.
0.05~0.15
41
60
80
21
20
1
0.22±0.05
0.5
0.09~0.20
0.10 M
1.0
S
0°~10°
0.60±0.15
0.10 S
■
(
MS1328-J-00
)
- 107 -
2011/09
[AK7722]
AK7722VQ
XXXXXXX
1) Pin #1 indication
2) Date Code: XXXXXXX(7digits)
3) Marking Code: AK7722VQ
Date (YY/MM/DD)
11/09/09
MS1328-J-00
Revision
00
Reason
Page
- 108 -
Contents
2011/09
[AK7722]
z
z
z
z
z
z
MS1328-J-00
- 109 -
2011/09