[AK4588] AK4588 2/8-Channel Audio CODEC with DIR GENERAL DESCRIPTION The AK4588 is a single chip CODEC that includes two channels of ADC and eight channels of DAC. The ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit architecture with wide dynamic range. The DAC introduces the new developed Advanced Multi-Bit architecture, and achieves wider dynamic range and lower outband noise. The AK4588 has a dynamic range of 102dB for ADC, 106dB for DAC and is well suited for digital surround for home theater and car audio. The AK4588 also has the balance volume control corresponding to Dolby Digital (AC-3) system, digital audio receiver (DIR) and transmitter (DIT) compatible with 192kHz, 24bits. The DIR has 8-channel input selector and can automatically detect a Non-PCM bit stream. The AK4588 provides a fully compatibility of hardware and software with the AK4628A and the AK4114. *Dolby Digital is a trademark of Dolby Laboratories. FEATURES ADC/DAC part 2ch 24bit ADC - 64x Oversampling - Sampling Rate up to 96kHz - Linear Phase Digital Anti-Alias Filter - Single-Ended Input - S/(N+D): 92dB - Dynamic Range, S/N: 102dB - Digital HPF for offset cancellation - Overflow flag 8ch 24bit DAC - 128x Oversampling - Sampling Rate up to 192kHz - 24bit 8 times Digital Filter - Single-Ended Outputs - On-chip Switched-Capacitor Filter - S/(N+D): 90dB - Dynamic Range, S/N: 106dB - Individual channel digital volume with 128 levels and 0.5dB step - Soft mute - Zero Detect Function High Jitter Tolerance Extenal Master Clock Input: - 256fs, 384fs, 512fs (fs=32kHz ∼ 48kHz) - 128fs, 192fs, 256fs (fs=64kHz ∼ 96kHz) - 128fs (fs=120kHz ∼ 192kHz) MS0287-E-03 2009/05 -1- [AK4588] DIR/DIT Part AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible Low jitter Analog PLL PLL Lock Range : 32kHz to 192kHz Clock Source: PLL or X'tal 8-channel Receiver input 2-channel Transmission output (Through output or DIT) Auxiliary digital input De-emphasis for 32kHz, 44.1kHz, 48kHz and 96kHz Detection Functions - Non-PCM Bit Stream Detection - DTS-CD Bit Stream Detection - Sampling Frequency Detection (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz) - Unlock & Parity Error Detection - Validity Flag Detection Up to 24bit Audio Data Format Audio I/F: Master or Slave Mode 40-bit Channel Status Buffer Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream Q-subcode Buffer for CD bit stream Serial μP I/F Two Master Clock Outputs: 64fs/128fs/256fs/512fs TTL Level Digital I/F 4-wire Serial and I2C Bus μP I/F for mode setting Operating Voltage: 4.5 to 5.5V with 5V tolerance Power Supply for output buffer: 2.7 to 5.5V 80pin LQFP Package (0.5mm pitch) MS0287-E-03 2009/05 -2- [AK4588] ■ Block Diagram PVSS PVDD R XTI XTO RX0 X'tal Clock Recovery RX1 RX2 RX3 RX4 RX5 8 to 3 Oscillator Clock Generator Input MCKO1 MCKO2 Selector DEM RX6 DAIF RX7 Audio Decoder I/F LRCK2 BICK2 SDTO2 TX0 DAUX2 PDN TX1 AVDD I2C DIT AVSS DVDD CSN AC-3/MPEG DVSS TVDD VIN Detect Error & STATUS Detect Q-subcode buffer CCLK CDTO CDTI INT0 INT1 B,C,U, VOUT ADC LIN RIN LOUT1 μP I/F LPF HPF Audio I/F ADC HPF DAC DATT DEM MCLK MCLK LRCK BICK LRCK1 BICK1 ROUT1 LPF DAC DATT DEM LOUT2 LPF DAC DATT DEM ROUT2 LPF DAC DATT DEM LOUT3 LPF DAC DATT DEM ROUT3 LPF DAC DATT DEM LOUT4 LPF DAC DATT DEM ROUT4 LPF DAC DATT DEM DAUX1 Format Converter SDOUT SDTO1 SDIN1 SDIN2 SDIN3 SDIN4 MS0287-E-03 SDTI1 SDTI2 SDTI3 SDTI4 2009/05 -3- [AK4588] ■ Ordering Guide AK4588VQ AKD4588 -40 ∼ +85°C 80pin LQFP(0.5mm pitch) Evaluation Board for AK4588 (Top View) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC LOUT3 NC ROUT4 NC LOUT4 DZF1 DZF2 MASTER PDN XTL0 XTL1 SDTI1 SDTI2 SDTI3 SDTI4 DAUX1 CSN CDTI/SDA CCLK/SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 INT1 BOUT TVDD DVDD DVSS XTO XTI TEST3 MCKO2 MCKO1 COUT UOUT VOUT SDTO2 BICK2 LRCK2 SDTO1 BICK1 LRCK1 CDTO RX2 NC RX3 PVSS R PVDD RX4 TEST2 RX5 CAD0 RX6 CAD1 RX7 I2C DAUX2 VIN MCLK TX0 TX1 INT0 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 60 59 TEST1 RX1 NC RX0 AVSS AVDD VREFH VCOM RIN LIN NC ROUT1 NC LOUT1 NC ROUT2 NC LOUT2 NC ROUT3 ■ Pin Layout MS0287-E-03 2009/05 -4- [AK4588] ■ Compatibility with AK4628 + AK4114 Functions AK4628+ AK4114 AK4588 Parallel control mode Yes No TDM0, DFS0, DZFE, SDOS, Available Not available SMUTE pins Chip 4 wire serial AK4628: Set by CAD1/0 pins ADC/DAC part: Set by CAD1/0 pins address(*) (I2C pin= “L”) AK4114: Fixed to “00” DIR/DIT part: Fixed to “00” I2C Bus AK4628: Set by CAD1/0 pins ADC/DAC part: Set by CAD1/0 pins (I2C pin = “H”) AK4114: Set by CAD1/0 pins DIR/DIT part: Fixed to “00” (*) The AK4588 has two register maps including ADC/DAC part (compatible with the AK4628) and DIR/DIT part (compatible with the AK4114). Each register is selected by Chip Address. MS0287-E-03 2009/05 -5- [AK4588] PIN/FUNCTION No. 1 Pin Name INT1 I/O O 2 3 4 5 6 7 BOUT O TVDD DVDD DVSS XTO XTI O I 8 TEST3 I 9 10 11 12 13 14 15 16 17 18 19 20 MCKO2 MCKO1 COUT UOUT VOUT SDTO2 BICK2 LRCK2 SDTO1 BICK1 LRCK1 CDTO CCLK SCL CDTI SDA 21 22 23 CSN 24 25 26 27 28 29 30 DAUX1 SDTI4 SDTI3 SDTI2 SDTI1 XTL1 XTL0 O O O O O O I/O I/O O I/O I/O O I I I I/O I I I I I I I I I Function Interrupt 1 Pin Block-Start Output Pin for Receiver Input “H” during first 40 flames. Output Buffer Power Supply Pin, 2.7V∼5.5V Digital Power Supply Pin, 4.5V∼5.5V Digital Ground Pin X'tal clock Output Pin X'tal / External clock Input Pin Test 3 Pin This pin should be connected to DVSS. Master Clock Output 2 Pin Master Clock Output 1 Pin C-bit Output Pin for Receiver Input U-bit Output Pin for Receiver Input V-bit Output Pin for Receiver Input Audio Serial Data Output Pin (DIR/DIT part) Audio Serial Data Clock Pin (DIR/DIT part) Channel Clock Pin (DIR/DIT part) Audio Serial Data Output Pin (ADC/DAC part) Audio Serial Data Clock Pin (ADC/DAC part) Input Channel Clock Pin Control Data Output Pin in Serial Mode, I2C pin= “L”. Control Data Clock Pin in Serial Mode, I2C pin= “L” Control Data Clock Pin in Serial Mode, I2C pin= “H” Control Data Input Pin in Serial Mode, I2C pin= “L”. Control Data Pin in Serial Mode, I2C pin= “H”. Chip Select Pin in Serial Mode, I2C pin= “L”. This pin should be connected to DVSS, I2C pin= “H”. AUX Audio Serial Data Input Pin (ADC/DAC part) DAC4 Audio Serial Data Input Pin DAC3 Audio Serial Data Input Pin DAC2 Audio Serial Data Input Pin DAC1 Audio Serial Data Input Pin X’tal Frequency Select 0 Pin X’tal Frequency Select 1 Pin MS0287-E-03 2009/05 -6- [AK4588] No. Pin Name I/O 31 PDN I 32 MASTER I DZF2 O OVF O 34 DZF1 O 35 LOUT4 O 36 NC - 37 ROUT4 O 38 NC - 39 LOUT3 O 40 NC - 41 ROUT3 O 42 NC - 43 LOUT2 O 44 NC - 45 ROUT2 O 46 NC - 47 LOUT1 O 48 NC - 49 ROUT1 O 50 NC - 51 52 LIN RIN I I 53 VCOM - 54 VREFH - 33 Function Power-Down Mode Pin When “L”, the AK4588 is powered-down, all output pin goes “L”, all registers are reset. When CAD1-0 pins are changed, the AK4588 should be reset by the PDN pin. Master Mode Select Pin “H”: Master mode, “L”: Slave mode Zero Input Detect 2 Pin (Table 13) When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin goes to “H”. When RSTN1 bit is “0” or PWDAN bit is “0”, this pin goes to “H”. Analog Input Overflow Detect Pin This pin goes to “H” if the analog input of Lch or Rch overflows. This pin becomes OVF pin if OVFE bit is set to 1. Zero Input Detect 1 Pin (Table 13) When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin goes to “H”. When RSTN1 bit is “0” or PWDAN bit is “0”, this pin goes to “H”. DAC4 Lch Analog Output Pin No Connect pin No internal bonding. This pin should be opened. DAC4 Rch Analog Output Pin No Connect pin No internal bonding. This pin should be opened. DAC3 Lch Analog Output Pin No Connect pin No internal bonding. This pin should be opened. DAC3 Rch Analog Output Pin No Connect pin No internal bonding. This pin should be opened. DAC2 Lch Analog Output Pin No Connect pin No internal bonding. This pin should be opened. DAC2 Rch Analog Output Pin No Connect pin No internal bonding. This pin should be opened. DAC1 Lch Analog Output Pin No Connect pin No internal bonding. This pin should be opened. DAC1 Rch Analog Output Pin No Connect pin No internal bonding. This pin should be opened. Lch Analog Input Pin Rch Analog Input Pin Common Voltage Output Pin 2.2μF capacitor should be connected to AVSS externally. Positive Voltage Reference Input Pin, AVDD MS0287-E-03 2009/05 -7- [AK4588] No. 55 56 57 Pin Name AVDD AVSS RX0 I/O I Function Analog Power Supply Pin, 4.5V∼5.5V Analog Ground Pin, 0V Receiver Channel 0 Pin (Internal biased pin. Internally biased at PVDD/2) No Connect pin 58 NC No internal bonding. This pin should be connected to PVSS. 59 RX1 I Receiver Channel 1 Pin (Internal biased pin. Internally biased at PVDD/2) Test 1 Pin 60 TEST1 I This pin should be connected to PVSS. 61 RX2 I Receiver Channel 2 Pin (Internal biased pin. Internally biased at PVDD/2) No Connect pin 62 NC No internal bonding. This pin should be connected to PVSS. 63 RX3 I Receiver Channel 3 Pin (Internal biased pin. Internally biased at PVDD/2) 64 PVSS PLL Ground pin External Resistor Pin 65 R 12kΩ +/-1% resistor should be connected to PVSS externally. 66 PVDD PLL Power supply Pin, 4.5V∼5.5V 67 RX4 I Receiver Channel 4 Pin (Internal biased pin. Internally biased at PVDD/2) Test 2 Pin 68 TEST2 I This pin should be connected to PVSS. 69 RX5 I Receiver Channel 5 Pin (Internal biased pin. Internally biased at PVDD/2) Chip Address 0 Pin (ADC/DAC part) 70 CAD0 I 71 RX6 I Receiver Channel 6 Pin (Internal biased pin. Internally biased at PVDD/2) Chip Address 1 Pin (ADC/DAC part) 72 CAD1 I 73 RX7 I Receiver Channel 7 Pin (Internal biased pin. Internally biased at PVDD/2) Control Mode Select Pin. 74 I2C I “L”: 4-wire Serial, “H”: I2C Bus 75 DAUX2 I Auxiliary Audio Data Input Pin (DIR/DIT part) 76 VIN I V-bit Input Pin for Transmitter Output Master Clock Input Pin 77 MCLK I 78 TX0 O Transmit Channel (Through Data) Output 0 Pin Transmit Channel Output1 pin 79 TX1 O When TX bit = “0”, Transmit Channel (Through Data) Output 1 Pin. When TX bit = “1”, Transmit Channel (DAUX2 Data) Output Pin (default). 80 INT0 O Interrupt 0 Pin Note: All input pins except internal biased pins and internal pull-down pin should not be left floating. PVDD RX pin 20k(typ) 20k(typ) PVSS VCOM Internal biased pin Circuit MS0287-E-03 2009/05 -8- [AK4588] ■ Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Analog Digital Pin Name RX7-0, LOUT4-1, ROUT4-1, LIN, RIN INT1-0, BOUT, XTO, MCKO2-1, COUT, UOUT, VOUT, SDTO2-1, CDTO, DZF2-1, TX1-0 CSN, DAUX2-1, SDTI4-1, XTL1-0, TEST3 TEST1-2 MS0287-E-03 Setting These pins should be open. These pins should be open. These pins should be connected to DVSS. These pins should be connected to PVSS. 2009/05 -9- [AK4588] ABSOLUTE MAXIMUM RATINGS (AVSS=DVSS=PVSS=0V; Note 1) Parameter Power Supplies Analog Digital PLL Output buffer |AVSS-DVSS| (Note 2) |AVSS-PVSS| (Note 2) Input Current (any pins except for supplies) Analog Input Voltage (LIN, RIN pins) Digital Input Voltage Except LRCK1-2, BICK1-2, RX0-7, CAD0-1, TEST1-2 pins LRCK1-2, BICK1-2 pins RX0-7, CAD0-1, TEST1-2 Ambient Temperature (power applied) Storage Temperature Symbol AVDD DVDD PVDD TVDD ΔGND1 ΔGND2 IIN min -0.3 -0.3 -0.3 -0.3 - max 6.0 6.0 6.0 6.0 0.3 0.3 ±10 Units V V V V V V mA VINA -0.3 AVDD+0.3 V VIND1 -0.3 DVDD+0.3 V VIND2 VIND3 Ta Tstg -0.3 -0.3 -40 -65 TVDD+0.3 PVDD+0.3 85 150 V V °C °C Note 1 All voltages with respect to ground. Note 2. AVSS, DVSS and PVSS must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS=DVSS=PVSS=0V; Note 3) Parameter Symbol min typ Analog Power Supplies AVDD 4.5 5.0 Digital (Note 4) DVDD 4.5 5.0 PLL PVDD 4.5 5.0 Output buffer TVDD 2.7 5.0 max 5.5 AVDD AVDD DVDD Units V V V V Note 3. All voltages with respect to ground. Note 4. The power up sequence between AVDD, DVDD, PVDD and TVDD is not critical. To save leak current in power down mode, AVDD, DVDD, PVDD become the same voltage as much as possible. WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0287-E-03 2009/05 - 10 - [AK4588] ANALOG CHARACTERISTICS (Ta=25°C; AVDD=DVDD=PVDD=TVDD=5V; AVSS=DVSS=0V; VREFH=AVDD; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at fs=48kHz, 20Hz~40kHz at fs=96kHz; 20Hz~40kHz at fs=192kHz, unless otherwise specified) Parameter min typ max Units ADC Analog Input Characteristics Resolution 24 Bits S/(N+D) (-0.5dBFS) fs=48kHz 84 92 dB fs=96kHz 86 dB DR (-60dBFS) fs=48kHz, A-weighted 94 102 dB fs=96kHz 88 96 dB fs=96kHz, A-weighted 93 102 dB S/N (Note 5) fs=48kHz, A-weighted 94 102 dB fs=96kHz 88 96 dB fs=96kHz, A-weighted 93 102 dB Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.3 dB Gain Drift 20 ppm/°C Input Voltage AIN=0.62xVREFH 2.90 3.10 3.30 Vpp Input Resistance fs=48kHz 15 25 kΩ fs=96kHz 9 16 kΩ Power Supply Rejection (Note 6) 50 dB DAC Analog Output Characteristics Resolution 24 Bits S/(N+D) fs=48kHz 80 90 dB fs=96kHz 78 88 dB fs=192kHz 88 dB DR (-60dBFS) fs=48kHz, A-weighted 95 106 dB fs=96kHz 88 100 dB fs=96kHz, A-weighted 94 106 dB fs=192kHz 100 dB fs=192kHz, A-weighted 106 dB S/N (Note 7) fs=48kHz, A-weighted 95 106 dB fs=96kHz 88 100 dB fs=96kHz, A-weighted 94 106 dB fs=192kHz 100 dB fs=192kHz, A-weighted 106 dB Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 20 ppm/°C Output Voltage AOUT=0.6xVREFH 2.75 3.0 3.25 Vpp Load Resistance 5 kΩ Power Supply Rejection (Note 6) 50 dB Power Supplies Power Supply Current Normal Operation (PDN = “H”) (Note 7) 50 AVDD fs=48kHz,fs=96kHz 70 mA 37 fs=192kHz 52 mA 12 PVDD 17 mA 44 DVDD+TVDD fs=48kHz (Note 9) 62 mA fs=96kHz 57 80 mA fs=192kHz 68 95 mA Power-down mode (PDN = “L”) (Note 10) 80 200 μA MS0287-E-03 2009/05 - 11 - [AK4588] Note 5. S/N measured by CCIR-ARM is 96dB(@fs=48kHz). Note 6. PSR is applied to AVDD, DVDD, PVDD and TVDD with 1kHz, 50mVpp. VREFH pin is held a constant voltage. Note 7. S/N measured by CCIR-ARM is 102dB(@fs=48kHz). Note 8. CL=20pF, X’tal=24.576MHz, CM1-0=“10”, CM1-0=“10”, OCKS1-0= “10”@48kHz, “00”@96kHz, “11”@192kHz. Note 9. TVDD=13mA(typ). Note 10. In the power-down mode. RX inputs are open and all digital input pins including clock pins (MCLK, BICK, LRCK) are held DVSS. FILTER CHARACTERISTICS (Ta=25°C; AVDD=DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; fs=48kHz) Parameter Symbol min ADC Digital Filter (Decimation LPF): Passband PB 0 ±0.1dB (Note 11) -0.2dB -3.0dB Stopband SB 28.0 Passband Ripple PR Stopband Attenuation SA 68 Group Delay (Note 12) GD Group Delay Distortion ΔGD ADC Digital Filter (HPF): Frequency Response (Note 11) -3dB FR -0.1dB DAC Digital Filter: Passband (Note 11) -0.1dB PB 0 -6.0dB Stopband SB 26.2 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 12) GD DAC Digital Filter + Analog Filter: FR Frequency Response: 0 ∼ 20.0kHz FR 40.0kHz (Note 13) FR 80.0kHz (Note 13) typ max Units 20.0 23.0 18.9 - 16 0 kHz kHz kHz kHz dB dB 1/fs µs 1.0 6.5 Hz Hz ±0.04 19.2 kHz kHz kHz dB dB 1/fs ±0.2 ±0.3 ±1.0 dB dB dB 24.0 21.8 ±0.02 Note 11. The passband and stopband frequencies scale with fs. For example, 21.8kHz at –0.1dB is 0.454 x fs (DAC). The reference frequency of these responses is 1kHz. Note 12. The calculating delay time which occurred by digital filtering. This time is from setting the input of analog signal to setting the 24bit data of both channels to the output register for ADC. For DAC, this time is from setting the 20/24bit data of both channels on input register to the output of analog signal. Note 13. 40kHz@fs=96kHz, 80kHz@fs=192kHz MS0287-E-03 2009/05 - 12 - [AK4588] DC CHARACTERISTICS (Ta=25°C; AVDD=DVDD=PVDD=4.5∼5.5V; TVDD=2.7∼5.5V) Parameter Symbol min 2.2 VIH High-Level Input Voltage (Except XTI pin) 70%DVDD VIH (XTI pin) VIL Low-Level Input Voltage (Except XTI pin) VIL (XTI pin) Input Voltage at AC Coupling (XTI pin) (Note 14) VAC 40%DVDD High-Level Output Voltage TVDD-0.4 VOH (Except TX0-1, DZF pins : Iout=-400μA) DVDD-0.4 VOH (TX0-1 pin : Iout=-400μA) AVDD-0.4 VOH (DZF pin : Iout=-400μA) VOL Low-Level Output Voltage (Iout=400μA) Iin Input Leakage Current Note 14. In case of connecting capacitance to XTI pin. typ - max 0.8 30%DVDD - Units V V V V Vpp - 0.4 ±10 V V V V μA max Units kΩ mVpp mV kHz S/PDIF RECEIVER CHARACTERISTICS (Ta=25°C; AVDD=DVDD=2.7~3.6V; TVDD=2.7~5.5V) Parameter Symbol min typ Input Resistance Zin 10 Input Voltage (internally biased at PVDD/2) VTH 200 Input Hysteresis VHY 50 Input Sample Frequency fs 32 - 192 PVDD RX pin 20k(typ) 20k(typ) PVSS VCOM Internal biased pin Circuit MS0287-E-03 2009/05 - 13 - [AK4588] SWITCHING CHARACTERISTICS (ADC/DAC part) (Ta=25°C; AVDD=DVDD=PVDD=4.5∼5.5V; TVDD=2.7∼5.5V; CL=20pF) Parameter Symbol min typ Master Clock Timing Master Clock 256fsn, 128fsd: fCLK 8.192 Pulse Width Low tCLKL 27 Pulse Width High tCLKH 27 384fsn, 192fsd: fCLK 12.288 Pulse Width Low tCLKL 20 Pulse Width High tCLKH 20 512fsn, 256fsd: fCLK 16.384 Pulse Width Low tCLKL 15 Pulse Width High tCLKH 15 LRCK1 Timing (Slave Mode) Normal mode Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle TDM 256 mode LRCK1 frequency “H” time “L” time TDM 128 mode LRCK1 frequency “H” time “L” time LRCK1 Timing (Master Mode) Normal mode Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle TDM 256 mode LRCK1 frequency “H” time (Note 15) TDM 128 mode LRCK1 frequency “H” time (Note 15) Power-down & Reset Timing PDN Pulse Width (Note 16) PDN “↑” to SDTO1 valid (Note 17) max Units 12.288 MHz ns ns MHz ns ns MHz ns ns 18.432 24.576 fsn fsd fsq Duty 32 64 120 45 48 96 192 55 kHz kHz kHz % fsd tLRH tLRL 32 1/256fs 1/256fs 48 kHz ns ns fsd tLRH tLRL 64 1/128fs 1/128fs 96 kHz ns ns fsn fsd fsq Duty 32 64 120 48 96 192 kHz kHz kHz % fsn tLRH 32 48 kHz ns fsd tLRH 64 96 1/4fs kHz ns tPD tPDV 150 522 ns 1/fs 50 1/8fs Note 15. “L” time at I2S format. Note 16. The AK4588 can be reset by bringing PDN “L” to “H” upon power-up. Note 17. These cycles are the number of LRCK rising from PDN rising. MS0287-E-03 2009/05 - 14 - [AK4588] Parameter Audio Interface Timing (Slave Mode) Normal mode BICK1 Period BICK1 Pulse Width Low Pulse Width High LRCK1 Edge to BICK1 “↑” (Note 18) BICK1 “↑” to LRCK1 Edge (Note 18) LRCK1 to SDTO1(MSB) BICK1 “↓” to SDTO1 SDTI1-4,DAUX1 Hold Time SDTI1-4,DAUX1 Setup Time TDM 256 mode BICK1 Period BICK1 Pulse Width Low Pulse Width High LRCK1 Edge to BICK1 “↑” (Note 18) BICK1 “↑” to LRCK1 Edge (Note 18) BICK1 “↓” to SDTO1 SDTI1 Hold Time SDTI1 Setup Time TDM 128 mode BICK1 Period BICK1 Pulse Width Low Pulse Width High LRCK1 Edge to BICK1 “↑” (Note 18) BICK1 “↑” to LRCK1 Edge (Note 18) BICK1 “↓” to SDTO1 SDTI1-2 Hold Time SDTI1-2 Setup Time Audio Interface Timing (Master Mode) Normal mode BICK1 Frequency BICK1 Duty BICK1 “↓” to LRCK1 Edge BICK1“↓” to SDTO1 SDTI1-4,DAUX1 Hold Time SDTI1-4,DAUX1 setup Time TDM 256 mode BICK1 Frequency BICK1 Duty (Note 19) BICK1 “↓” to LRCK1 Edge BICK1 “↓” to SDTO1 SDTI1 Hold Time SDTI1 Setup Time TDM 128 mode BICK1 Frequency BICK1 Duty (Note 20) BICK1 “↓” to LRCK1 Edge BICK1 “↓” to SDTO1 SDTI1-2 Hold Time SDTI1-2 Setup Time Symbol min tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS 81 32 32 20 20 tBCK tBCKL tBCKH tLRB tBLR tBSD tSDH tSDS 81 32 32 20 20 tBCK tBCKL tBCKH tLRB tBLR tBSD tSDH tSDS 81 32 32 20 20 fBCK dBCK tMBLR tBSD tSDH tSDS fBCK dBCK tMBLR tBSD tSDH tSDS fBCK dBCK tMBLR tBSD tSDH tSDS typ max 40 40 20 20 20 10 10 20 10 10 64fs 50 -20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 40 12 20 Hz % ns ns ns ns 12 20 Hz % ns ns ns ns 256fs 50 10 10 128fs 50 -12 ns ns ns ns ns ns ns ns ns Hz % ns ns ns ns 20 20 -12 Units 10 10 Note 18. BICK1 rising edge must not occur at the same time as LRCK1 edge. Note 19. When MCLK is 512fs, dBCK is guaranteed. When 384fs and 256fs, dBCK can not be guaranteed. Note 20. When MCLK is 256fs, dBCK is guaranteed. When 128fs, dBCK can not be guaranteed. MS0287-E-03 2009/05 - 15 - [AK4588] ■ Timing Diagram(ADC/DAC part) 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fsn, 1/fsd, 1/fsq VIH LRCK1 VIL tBCK VIH BICK1 VIL tBCKH tBCKL Clock Timing (Normal mode) 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs VIH LRCK1 VIL tLRH tLRL tBCK VIH BICK1 VIL tBCKH tBCKL Clock Timing (TDM 256 mode, TDM 128 mode) MS0287-E-03 2009/05 - 16 - [AK4588] VIH LRCK1 VIL tBLR tLRB VIH BICK1 VIL tLRS tBSD 50%TVDD SDTO1 tSDS tSDH VIH SDTI VIL Audio Interface Timing (Normal mode) VIH LRCK1 VIL tBLR tLRB VIH BICK1 VIL tBSD SDTO1 50%TVDD tSDS tSDH VIH SDTI VIL Audio Interface Timing (TDM 256 mode, TDM 128 mode) MS0287-E-03 2009/05 - 17 - [AK4588] LRCK1 50%TVDD tMBLR 50%TVDD BICK1 tBSD 50%TVDD SDTO1 tDXS tDXH VIH DAUX1 VIL Audio Interface timing (Master Mode) MS0287-E-03 2009/05 - 18 - [AK4588] SWITCHING CHARACTERISTICS (DIR/DIT part) (Ta=25°C; DVDD=AVDD4.5~5.5V, TVDD=2.7~5.5V; CL=20pF) Parameter Symbol min typ Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 External Clock Frequency fECLK 11.2896 Duty dECLK 40 50 MCKO1 Output Frequency fMCK1 4.096 Duty dMCK1 40 50 MCKO2 Output Frequency fMCK2 2.048 Duty dMCK2 40 50 PLL Clock Recover Frequency (RX0-7) fpll 32 LRCK2 Frequency fs 32 Duty Cycle dLCK 45 Audio Interface Timing Slave Mode BICK2 Period tBCK 80 BICK2 Pulse Width Low tBCKL 30 Pulse Width High tBCKH 30 tLRB 20 LRCK2 Edge to BICK2 “↑” (Note 21) tBLR 20 BICK2 “↑” to LRCK2 Edge (Note 21) tLRM LRCK2 to SDTO2 (MSB) tBSD BICK2 “↓” to SDTO2 tDXH 20 DAUX2 Hold Time tDXS 20 DAUX2 Setup Time Master Mode BICK2 Frequency fBCK 64fs BICK2 Duty dBCK 50 tMBLR -20 BICK2 “↓” to LRCK2 tBSD BICK2 “↓” to SDTO2 tDXH 20 DAUX2 Hold Time tDXS 20 DAUX2 Setup Time Note 21. BICK2 rising edge must not occur at the same time as LRCK2 edge. MS0287-E-03 max Units 24.576 24.576 60 24.576 60 24.576 60 192 192 55 MHz MHz % MHz % MHz % kHz kHz % 30 30 20 15 ns ns ns ns ns ns ns ns ns Hz % ns ns ns ns 2009/05 - 19 - [AK4588] ■ Timing Diagram(DIR/DIT part) 1/fECLK VIH XTI VIL tECLKH tECLKL dECLK = tECLKH x fECLK x 100 = tECLKL x fECLK x 100 1/fMCK1 MCKO1 50%TVDD tMCKH1 tMCKL1 dMCK1 = tMCKH1 x fMCK1 x 100 = tMCKL1 x fMCK1 x 100 1/fMCK2 MCKO2 50%TVDD tMCKH2 tMCKL2 dMCK2 = tMCKH2 x fMCK2 x 100 = tMCKL2 x fMCK2 x 100 1/fs VIH LRCK2 VIL tLRH tLRL dLCK = tLRH x fs x 100 = tLRL x fs x 100 VIH LRCK2 VIL tBCK tBLR tLRB tBCKL tBCKH VIH BICK2 VIL tLRM tBSD 50%TVDD SDTO2 tDXS tDXH VIH DAUX2 VIL Serial Interface Timing (Slave Mode) MS0287-E-03 2009/05 - 20 - [AK4588] LRCK2 50%TVDD tMBLR 50%TVDD BICK2 tBSD 50%TVDD SDTO2 tDXS tDXH VIH DAUX2 VIL Serial Interface Timing (Master Mode) tPD PDN VIL Power Down & Reset Timing MS0287-E-03 2009/05 - 21 - [AK4588] SWITCHING CHARACTERISTICS (ADC/DAC part and DIR/DIT part) (Ta=25°C; AVDD=DVDD=PVDD=4.5∼5.5V; TVDD=2.7∼5.5V; CL=20pF) Parameter Symbol min typ max Control Interface Timing (4-wire serial mode) CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Setup Time tCDS 50 CDTI Hold Time tCDH 50 CSN “H” Time tCSW 150 tCSS 50 CSN “↓” to CCLK “↑” tCSH 50 CCLK “↑” to CSN “↑” tDCD 45 CDTO Delay tCCZ 70 CSN “↑” to CDTO Hi-Z Control Interface Timing (I2C Bus mode) SCL Clock Frequency fSCL 100 Bus Free Time Between Transmissions tBUF 4.7 Start Condition Hold Time (prior to first clock pulse) tHD:STA 4.0 Clock Low Time tLOW 4.7 Clock High Time tHIGH 4.0 Setup Time for Repeated Start Condition tSU:STA 4.7 SDA Hold Time from SCL Falling (Note 22) tHD:DAT 0 SDA Setup Time from SCL Rising tSU:DAT 0.25 Rise Time of Both SDA and SCL Lines tR 1.0 Fall Time of Both SDA and SCL Lines tF 0.3 Setup Time for Stop Condition tSU:STO 4.0 Capacitive load on bus Cb 400 Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 50 Units ns ns ns ns ns ns ns ns ns ns kHz μs μs μs μs μs μs μs μs μs μs pF ns Note 22. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 23. I2C is a registered trademark of Philips Semiconductors. MS0287-E-03 2009/05 - 22 - [AK4588] ■ Timing Diagram (ADC/DAC part and DIR/DIT part) VIH CSN VIL tCSS tCCK tCCKL tCCKH VIH CCLK VIL tCDH tCDS C1 CDTI C0 A4 R/W VIH VIL Hi-Z CDTO WRITE/READ Command Input Timing in 4-wire serial mode The ADC/DAC part doesn’t support READ command. tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 VIH D0 VIL Hi-Z CDTO WRITE Data Input Timing in 4-wire serial mode VIH CSN VIL VIH CCLK VIL CDTI A1 VIH A0 VIL tDCD CDTO Hi-Z D7 D6 D5 50%TVDD READ Data Output Timing 1 in 4-wire serial mode The ADC/DAC part doesn’t support READ command.. MS0287-E-03 2009/05 - 23 - [AK4588] tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI VIL tCCZ CDTO D3 D2 D1 50%TVDD D0 READ Data Input Timing 2 in 4-wire serial mode The ADC/DAC part doesn’t support READ command. VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop I2C Bus mode Timing The ADC/DAC part doesn’t support READ command. tPD VIH PDN VIL tPDV 50%TVDD SDTO Power-down & Reset Timing MS0287-E-03 2009/05 - 24 - [AK4588] OPERATION OVERVIEW (ADC/DAC part) ■ System Clock The external clocks, which are required to operate the AK4588, are MCLK, LRCK1 and BICK1. MCLK should be synchronized with LRCK1 but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS bit = “0”: Default), the sampling speed is set by DFS1-0 bit (Table 1). The frequency of MCLK at each sampling speed is set automatically. (Table 3, Table 4, Table 5) In Auto Setting Mode (ACKS bit = “1”), as MCLK frequency is detected automatically (Table 6) and the internal master clock becomes the appropriate frequency (Table 7), it is not necessary to set DFS1-0 bits. Only MCLK is necessary in the master mode. Master Clock Input Frequency should be selected by CKS1-0 bits (Table 2), and Sampling Speed should be selected by DFS1-0 bits (Table 1). The frequencies and the duties of the clocks (LRCK1, BICK1) may not be stabile after setting CKS1-0 bits and DFS1-0 bits up. External clocks (MCLK, BICK1, LRCK1) should always be present whenever the AK4588 is in normal operation mode (PDN pin = “H”). If these clocks are not provided, the AK4588 may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4588 should be in the power-down mode (PDN pin = “L”) or in the reset mode (RSTN1 bit = “0”). After exiting reset at power-up etc., the AK4588 is in the power-down mode until MCLK and LRCK are input. In the Master mode, External clock(MCLK) should always be supplied except in the power-down mode. It is in power-down mode until MCLK will be supplied, when Reset was canceled by Power-ON and so on. DFS1 0 0 1 DFS0 0 1 0 Sampling Speed (fs) Normal Speed Mode 32kHz~48kHz Double Speed Mode 64kHz~96kHz Quad Speed Mode 120kHz~192kHz (default) Table 1. Sampling Speed (Manual Setting Mode) CKS1 0 0 1 1 CKS0 0 1 0 1 Normal 256fs 384fs 512fs 256fs Double 128fs 192fs 256fs 256fs Quad 128fs 128fs 128fs 128fs (default) Table 2.Master clock input select (Master Mode) LRCK1 Fs 32.0kHz 44.1kHz 48.0kHz 256fs 8.1920 11.2896 12.2880 MCLK (MHz) 384fs 12.2880 16.9344 18.4320 512fs 16.3840 22.5792 24.5760 BICK1 (MHz) 64fs 2.0480 2.8224 3.0720 Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode) LRCK1 Fs 88.2kHz 96.0kHz 128fs 11.2896 12.2880 MCLK (MHz) 192fs 16.9344 18.4320 256fs 22.5792 24.5760 BICK1 (MHz) 64fs 5.6448 6.1440 Table 4. System Clock Example (Double Speed Mode @Manual Setting Mode) (Note: At Double speed mode (DFS1= “0”, DFS0 = “1”), 128fs and 192fs are not available for ADC.) MS0287-E-03 2009/05 - 25 - [AK4588] LRCK1 Fs 176.4kHz 192.0kHz MCLK (MHz) 192fs - 128fs 22.5792 24.5760 256fs - BICK1 (MHz) 64fs 11.2896 12.2880 Table 5. System Clock Example (Quad Speed Mode @Manual Setting Mode) (Note: At Quad speed mode (DFS1= “1”, DFS0 = “0”) are not available for ADC.) MCLK 512fs 256fs 128fs Sampling Speed Normal Double Quad Table 6. Sampling Speed (Auto Setting Mode) LRCK1 fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs 22.5792 24.5760 MCLK (MHz) 256fs 22.5792 24.5760 - 512fs 16.3840 22.5792 24.5760 - Sampling Speed Normal Double Quad Table 7. System Clock Example (Auto Setting Mode) ■ De-emphasis Filter The AK4588 includes the digital de-emphasis filter (tc=50/15μs) by IIR filter. De-emphasis filter is not available in Double Speed Mode and Quad Speed Mode. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis of each DAC can be set individually by register data of DEMA1-C0 bits (DAC1: DEMA1-0 bits, DAC2: DEMB1-0 bits, DAC3: DEMC1-0 bits, DAC4: DEMD1-0 bits, see “Register Definitions”). Mode 0 1 2 3 Sampling Speed Normal Speed Normal Speed Normal Speed Normal Speed DEM1 0 0 1 1 DEM0 0 1 0 1 DEM 44.1kHz OFF 48kHz 32kHz (default) Table 8. De-emphasis control ■ Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz and scales with sampling rate (fs). MS0287-E-03 2009/05 - 26 - [AK4588] ■ Master mode and Slave mode Master Mode can be selected by setting the MASTER pin to “H”. LRCK1 and BICK1 will be outputs in Master Mode. And, Slave Mode can be selected by setting this pin to “L”. LRCK1 and BICK1 will be inputs in Slave Mode. Operation of LRCK1 and BICK1 is shown below Table 9. PDN pin PWADN bit, PWDAN bit MASTER pin LRCK1 pin L Input -H “L” output L Input “00” H “L” output L Input Except for “00” H Output Table 9. Operation of LRCK1 and BICK1 L H H BICK1 pin Input “L” output Input “L” output Input Output ■ Audio Serial Interface Format When TDM1-0 bit = “00”, 8 modes can be selected by the DIF1-0 bits as shown in Table 10. In all modes the serial data is MSB-first, 2’s complement format. The SDTO1 is clocked out on the falling edge of BICK1 and the SDTI/DAUX1 are latched on the rising edge of BICK1. Figure 1∼Figure 4 shows the timing at SDOS bit = “0”. In this case, the SDTO1 outputs the ADC output data. When SDOS bits = “1”, the data input to DAUX1 is converted to SDTO1’s format and output from SDTO1. Mode 2/3/6/7/10/11/14/15/18/19/22/23 in SDTI input formats can be used for 16-20bit data by zeroing the unused LSBs. Mode MASTER TDM 1 TDM0 DIF1 DIF0 0 0 0 0 0 0 1 0 0 0 0 1 2 0 0 0 1 0 3 0 0 0 1 1 4 1 0 0 0 0 5 1 0 0 0 1 6 1 0 0 1 0 7 1 0 0 1 1 SDTO1 SDTI1-4, DAUX1 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S LRCK1 I/O BICK1 I/O H/L I ≥ 48fs I H/L I ≥ 48fs I H/L I ≥ 48fs I L/H I ≥ 48fs I H/L O 64fs O H/L O 64fs O H/L O 64fs O L/H O 64fs O (default) Table 10. Audio data formats (Normal mode) The audio serial interface format becomes the TDM 256 mode if TDM1-0 bits are set to “01”. In the TDM 256 Mode, the serial data of all DAC (eight channels) is input to the SDTI1 pin. The input data to SDTI2-4 pins is ignored. BICK1 should be fixed to 256fs. “H” time and “L” time of LRCK1 pin should be 1/256fs at least. Eight modes can be selected by the DIF1-0 bits was shown in Table 11. In all modes the serial data is MSB-first, 2’s complement format. The SDTO1 pin is clocked out on the falling edge of BICK1 pin and the SDTI1 pin are latched on the rising edge of BICK1 pin. SDOS bit and LOOP1-0 bits should be set to “0” in the TDM mode. TDM 128 Mode can be set by TDM1-0 bit = “10”. In this Mode, the serial data of DAC (four channels; L1, R1, L2, R2) is input to the SDTI1 pin. Other four data (L3, R3, L4, R4) are input to the SDTI2 pin. MS0287-E-03 2009/05 - 27 - [AK4588] Mode MASTER TDM 1 TDM0 DIF1 DIF0 8 0 0 1 0 0 9 0 0 1 0 1 10 0 0 1 1 0 11 0 0 1 1 1 12 1 0 1 0 0 13 1 0 1 0 1 14 1 0 1 1 0 15 1 0 1 1 1 SDTO1 SDTI1 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S LRCK1 I/O BICK1 I/O ↑ I 256fs I ↑ I 256fs I ↑ I 256fs I ↓ I 256fs I ↑ O 256fs O ↑ O 256fs O ↑ O 256fs O ↓ O 256fs O Table 11. Audio data formats (TDM 256 mode) Mode MASTER TDM 1 TDM 0 DIF1 DIF0 16 0 1 1 0 0 17 0 1 1 0 1 18 0 1 1 1 0 19 0 1 1 1 1 20 1 1 1 0 0 21 1 1 1 0 1 22 1 1 1 1 0 23 1 1 1 1 1 SDTO1 SDTI1, SDTI2 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S LRCK1 I/O BICK1 I/O ↑ I 128fs I ↑ I 128fs I ↑ I 128fs I ↓ I 128fs I ↑ O 128fs O ↑ O 128fs O ↑ O 128fs O ↓ O 128fs O Table 12. Audio data formats (TDM 128 mode) MS0287-E-03 2009/05 - 28 - [AK4588] LRCK1 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 1 BICK1(64fs) SDTO1(o) 23 22 SDTI(i) 12 11 10 0 19 18 8 Don’t Care 23 22 7 1 12 11 10 Don’t Care 0 0 19 18 SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB Lch Data 23 8 7 1 0 Rch Data Figure 1. Mode 0/4 Timing LRCK1 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 1 BICK1(64fs) SDTO1(o) 23 22 SDTI(i) 16 15 14 Don’t Care 0 23 22 23:MSB, 0:LSB 23 22 8 7 1 16 15 14 Don’t Care 0 0 23 22 Lch Data 23 8 7 1 0 Rch Data Figure 2. Mode 1/5 Timing LRCK1 0 1 2 21 22 23 24 28 29 30 31 0 1 2 22 23 24 28 29 30 31 0 1 BICK1(64fs) SDTO1(o) 23 22 2 1 0 SDTI(i) 23 22 2 1 0 23:MSB, 0:LSB Don’t Care 23 22 2 1 0 23 22 2 1 0 Lch Data 23 Don’t Care 23 Rch Data Figure 3.Mode 2/6 Timing LRCK1 0 1 2 3 22 23 24 25 29 30 31 0 1 2 3 22 23 24 25 29 30 31 0 1 BICK1(64fs) SDTO1(o) 23 22 2 1 0 SDTI(i) 23 22 2 1 0 23:MSB, 0:LSB Don’t Care 23 22 2 1 0 23 22 2 1 0 Lch Data Don’t Care Rch Data Figure 4. Mode 3/7 Timing MS0287-E-03 2009/05 - 29 - [AK4588] 256 B ICK LRCK1 (m ode 8) LRCK1 (m ode 12) BICK1(256fs) SDTO1(o) 23 22 0 23 22 Lch 32 B ICK SDTI1(i) 0 23 22 Rch 19 18 32 B ICK 0 19 18 0 19 18 0 19 18 0 19 18 0 19 18 0 19 18 0 19 18 0 L1 R1 L2 R2 L3 R3 L4 R4 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK 19 Figure 5. Mode 8/12 Timing 256 B ICK LRCK1 (m ode 9) LRCK1 (m ode 13) BICK1(256fs) SDTO1(o) SDTI1(i) 23 22 0 23 22 0 Lch Rch 32 B ICK 32 B ICK 23 22 0 23 22 23 22 0 L1 R1 32 B ICK 32 B ICK 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 L2 R2 L3 R3 L4 R4 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK 23 Figure 6. Mode 9/13 Timing 256 B ICK LRCK1 (m ode 10) LRCK1 (m ode 14) BICK1(256fs) SDTO1(o) 23 22 0 Lch SDTI1(i) 0 23 22 Rch 32 B ICK 23 22 23 22 0 32 B ICK 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 L1 R1 L2 R2 L3 R3 L4 R4 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK 23 22 Figure 7. Mode 10/14 Timing 256 B ICK LRCK1 (m ode 11) LRCK1 (m ode 15) BICK1(256fs) SDTO1(o) 23 0 Lch 23 0 23 Rch 32 B ICK SDTI1(i) 23 0 32 B ICK 23 0 23 0 23 0 23 0 23 0 23 0 23 0 L1 R1 L2 R2 L3 R3 L4 R4 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK 23 Figure 8. Mode 11/15 Timing MS0287-E-03 2009/05 - 30 - [AK4588] 128 B ICK LRCK1 (m ode 16) LRCK1 (m ode 20) BICK1(128fs) SDTO1(o) 23 22 0 SDTI2(i) 23 22 Rch 32 B ICK SDTI1(i) 0 23 22 Lch 32 BICK 19 18 0 19 18 0 19 18 0 L1 R1 L2 32 B ICK 32 B ICK 32 B ICK 19 18 0 19 18 0 19 18 0 19 18 R2 32 B ICK 19 18 L3 R3 L4 R4 32 B ICK 32 B ICK 32 B ICK 32 B ICK 0 19 0 19 Figure 9. Mode 16/20 Timing 128 B ICK LRCK1 (m ode 17) LRCK1 (m ode 21) BICK1(128fs) 23 22 0 SDTI2(i) 23 22 Rch 32 B ICK SDTI1(i) 0 23 22 Lch 32 BICK 23 22 0 23 22 0 23 22 0 L1 R1 L2 32 B ICK 32 B ICK 32 B ICK 23 22 0 23 22 0 23 22 0 23 22 R2 32 B ICK 23 22 L3 R3 L4 R4 32 B ICK 32 B ICK 32 B ICK 32 B ICK 0 19 0 19 Figure 10. Mode 17/21 Timing 128 B ICK LRCK1 (m ode 18) LRCK1 (m ode 22) BICK1(128fs) SDTO1(o) 23 22 0 SDTI1(i) SDTI2(i) 23 22 Rch 32 B ICK 23 22 0 23 22 Lch 32 BICK 0 23 22 0 23 22 0 23 22 L1 R1 L2 R2 32 B ICK 32 B ICK 32 B ICK 32 B ICK 23 22 0 23 22 0 23 22 0 23 22 L3 R3 L4 R4 32 B ICK 32 B ICK 32 B ICK 32 B ICK 0 23 22 0 23 22 Figure 11. Mode 18/22 Timing MS0287-E-03 2009/05 - 31 - [AK4588] 128 B ICK LRCK1 (m ode 19) LRCK1 (m ode 23) BICK1(128fs) SDTO1(o) 23 22 0 SDTI1(i) SDTI2(i) 23 Rch 32 B ICK 23 22 0 23 22 Lch 32 BICK 0 23 22 0 0 23 22 23 22 L1 R1 L2 R2 32 B ICK 32 B ICK 32 B ICK 32 B ICK 23 22 0 23 22 0 0 23 22 23 22 L3 R3 L4 R4 32 B ICK 32 B ICK 32 B ICK 32 B ICK 0 23 0 23 Figure 12. Mode 19/23 Timing MS0287-E-03 2009/05 - 32 - [AK4588] ■ Overflow Detection The AK4588 has overflow detect function for the analog input. Overflow detect function is enable if OVFE bit is set to “1”. The OVF pin goes to “H” if analog input of Lch or Rch overflows (more than -0.3dBFS). OVF output for overflowed analog input has the same group delay as ADC (GD = 19.1/fs = 398μs @fs=48kHz). The OVF pin is “L” for 522/fs (=11.8ms @fs=48kHz) after PDN = “↑”, and then overflow detection is enabled. ■ Zero Detection The AK4588 has two pins for zero detect flag outputs. Channel grouping can be selected by DZFM3-0 bits (Table 13). The DZF1 pin corresponds to the group 1 channels and the DZF2 pin corresponds to the group 2 channels. However the DZF2 pin becomes the OVF pin if OVFE bit is set to “1”. Zero detection mode is set to mode 0. DZF1 is AND of all eight channels and DZF2 is disabled (“L”) at mode 0. Table 14 shows the relation of OVFE bit and DZF. When the input data of all channels in the group 1(group 2) are continuously zeros for 8192 LRCK1 cycles, DZF1 (DZF2) pin goes to “H”. DZF1 (DZF2) pin immediately returns to “L” if input data of any channels in the group 1 (group 2) is not zero after going DZF1 (DZF2) “H”. Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DZFM 2 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 L1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 R1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 DZF2 DZF1 DZF1 DZF1 DZF1 AOUT L2 R2 L3 R3 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 DZF1 DZF1 DZF2 DZF2 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 disable (DZF1=DZF2 = “L”) DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 L4 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 R4 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF1 DZF2 DZF2 DZF2 (default) disable (DZF1=DZF2 = “L”) Table 13. Zero detect control OVFE bit 0 1 DZF1 pin DZF2/OVF pin Selectable (Table 13) Selectable (Table 13) Selectable (Table 13) OVF output Table 14. DZF1-2 pins outputs MS0287-E-03 2009/05 - 33 - [AK4588] ■ Digital Attenuator The AK4588 has channel-independent digital attenuator (128 levels, 0.5dB step). Attenuation level of each channel can be set by each ATT7-0 bits (Table 15). ATT7-0 00H 01H 02H : 7DH 7EH 7FH FEH FFH Attenuation Level 0dB -0.5dB -1.0dB : -62.5dB -63dB MUTE (-∞) : MUTE (-∞) MUTE (-∞) (default) Table 15. Attenuation level of digital attenuator Transition time between set values of ATT7-0 bits can be selected by ATS1-0 bits (Table 16). Transition between set values is the soft transition. Therefore, the switching noise does not occur in the transition. Mode 0 1 2 3 ATS1 0 0 1 1 ATS0 0 1 0 1 ATT speed 1792/fs 896/fs 256/fs 256/fs (default) Table 16. Transition time between set values of ATT7-0 bits The transition between set values is soft transition of 1792 levels in mode 0. It takes 1792/fs (37.3ms@fs=48kHz) from 00H(0dB) to 7FH(MUTE) in mode 0. If the PDN pin goes to “L”, the ATTs are initialized to 00H. The ATTs are 00H when RSTN bit = “0”. When RSTN bit return to “1”, the ATTs fade to their current value. MS0287-E-03 2009/05 - 34 - [AK4588] ■ Soft mute operation Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by -∞ during ATT_DATA×ATT transition time (Table 16) from the current ATT level. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE bit ATT Level (1) (1) (3) Attenuation -∞ GD (2) GD AOUT DZF1,2 (4) 8192/fs Notes: (1) ATT_DATA×ATT transition time (Table 16). For example, in Normal Speed Mode, this time is 1792LRCK1 cycles (1792/fs) at ATT_DATA=00H. ATT transition of the soft-mute is from 00H to 7FH (2) The analog output corresponding to the digital input has a group delay, GD. (3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. (4) When the input data at all the channels of the group are continuously zeros for 8192 LRCK1 cycles, the DZF pin of each channel goes to “H”. the DZF pin immediately goes to “L” if the input data of either channel of the group are not zero after going DZF “H”. Figure 13. Soft mute and zero detection ■ System Reset The AK4588 should be reset once by bringing the PDN pin = “L” upon power-up. The AK4588 is powered up and the internal timing starts clocking by LRCK1 “↑” after exiting reset and power down state by MCLK. The AK4588 is in the power-down mode until MCLK and LRCK1 are input. MS0287-E-03 2009/05 - 35 - [AK4588] ■ Power ON/OFF Sequence The ADC and DACs of the AK4588 are placed in the power-down mode by bringing the PDN pin “L” and both digital filters are reset at the same time. PDN pin “L” also reset the control registers to their default values. In the power-down mode, the analog outputs go to VCOM voltage and DZF1-2 pins go to “L”. This reset should always be executed after power-up. In case of the ADC, an analog initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO1 becomes available after 522 cycles of LRCK1 clock. In case of the DAC, an analog initialization cycle starts after exiting the power-down mode. The analog outputs are VCOM voltage during the initialization. Figure 14 shows the sequences of the power-down and the power-up. The ADC and all DACs can be powered-down individually by PWADN and PWDAN bits. And DAC1-4 can be power-down individually by PD1-4 bits. In this case, the internal register values are not initialized. When PWADN bit = “0”, the SDTO1 pin goes to “L”. When PWDAN bit = “0” and PD1-4 bits = “0”, the analog outputs go to VCOM voltage and DZF1-2 pins go to “H”. Because some click noise occurs, the analog output should muted externally if the click noise influences system application. Power PDN 522/fs ADC Internal State (1) Init Cycle 516/fs DAC Internal State Normal Operation Power-down Normal Operation Power-down (2) Init Cycle GD (3) GD ADC In (Analog) ADC Out (Digital) “0”data (4) DAC In (Digital) “0”data (5) “0”data “0”data GD (3) GD (6) DAC Out (Analog) (6) (7) Clock In Don’t care Don’t care MCLK,LRCK,SCLK 10∼11/fs (10) (8) DZF1/DZF2 External Mute (9) Mute ON Mute ON Notes: (1) The analog part of ADC is initialized after exiting the power-down state. (2) The analog part of DAC is initialized after exiting the power-down state. (3) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay (GD). (4) ADC output is “0” data at the power-down state. (5) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the click noise influences system application. (6) Click noise occurs at the falling edge of PDN and at 512/fs after the rising edge of PDN. (7) When the external clocks (MCLK, BICK1 and LRCK1) are stopped, the AK4588 should be in the power-down mode. (8) DZF1-2 pins are “L” in the power-down mode (PDN pin = “L”). (9) Please mute the analog output externally if the click noise (6) influences system application. (10) DZF= “L” for 10∼11/fs after PDN= “↑”. Figure 14. Power-down/up sequence example MS0287-E-03 2009/05 - 36 - [AK4588] ■ Reset Function When RSTN1 bit = “0”, ADC and DACs are powered-down but the internal register are not initialized. The analog outputs go to VCOM voltage, DZF1-2 pins go to “H” and the SDTO1 pin goes to “L”. Because some click noise occurs, the analog output should muted externally if the click noise influences system application. Figure 15 shows the power-up sequence. RSTN bit 4~5/fs (9) 1~2/fs (9) Internal RSTN bit 516/fs (1) ADC Internal State Normal Operation Digital Block Power-down DAC Internal State Normal Operation Digital Block Power-down Normal Operation Init Cycle Normal Operation GD (2) GD ADC In (Analog) (3) ADC Out (Digital) DAC In (Digital) (4) “0”data “0”data (2) GD DAC Out (Analog) GD (6) (6) (5) (7) Clock In MCLK,LRCK,SCLK Don’t care 4∼5/fs (8) DZF1/DZF2 Notes: (1) The analog part of ADC is initialized after exiting the reset state. (2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay (GD). (3) ADC output is “0” data at the power-down state. (4) Click noise occurs when the internal RSTN bit becomes “1”. Please mute the digital output externally if the click noise influences system application. (5) When RSTN1 bit = “0”, the analog outputs go to VCOM voltage. (6) Click noise occurs at 4∼5/fs after RSTN1 bit becomes “0”, and occurs at 1∼2/fs after RSTN1 bit becomes “1”. This noise is output even if “0” data is input. (7) The external clocks (MCLK, BICK1 and LRCK1) can be stopped in the reset mode. When exiting the reset mode, “1” should be written to RSTN1 bit after the external clocks (MCLK, BICK1 and LRCK1) are fed. (8) DZF pins go to “H” when the RSTN1 bit becomes “0”, and go to “L” at 6~7/fs after RSTN1 bit becomes “1”. (9) There is a delay, 4~5/fs from RSTN1 bit “0” to the internal RSTN bit “0”. Figure 15. Reset sequence example MS0287-E-03 2009/05 - 37 - [AK4588] ■ DAC partial Power-Down Function All DACs of The AK4588 can be powered-down individually by PD1-4 bits. The analog part of DAC is in power-down by PD1-4 bits = “1”, however, the digital part is not powered-down by it. Even if all DACs were set in power-down by the partial power-down bits, the digital part operation is continued. The analog output of the channel which is set in power-down by PD1-4 bits is fixed to VCOM voltage. And though DZF detection is being done, the result of DZF detection stops reflecting to DZF1-2 pins. Because some click noise occurs in both set-up and release of power-down, either the analog output should be muted externally or PD1-4 bits should be set up when it is in PWDAN bit = “0” or RSTN bit = “0”, if the click noise influences system application. Figure 16 shows the sequence of the power-down and the power-up by PD1-4 bits. PD1-4 bit Power Down Channel DAC Digital Internal State DAC Analog Internal State Normal Operation Normal Operation Normal Operation Power-down DAC In (Digital) Normal Operation Normal Operation Power-down “0”data (1) GD GD (3) DAC Out (Analog) (2) (3) (3) (2) (3) 8192/fs DZF Detect Internal State (4) (4) Normal Operation Channel DAC In (Digital) “0”data GD GD DAC Out (Analog) 8192/fs DZF Detect Internal State Clock In MCLK,LRCK,SCLK (5) (6) DZF1/DZF2 Notes: (1) Digital output corresponding to analog input and analog output corresponding to digital input have group delay (GD). (2) Analog output of the DAC powered down by PD1-4 bits = “1” is fixed to the voltage of VCOM. (3) Immediately after PD1-4 bits are changed, some click noise occurs at the output of the channel changed by the own PD bits. (4) Though DZF detection is being done at a certain channel which set up PD1-4 bits = “1”, the result of DZF detection stops reflecting to DZF1-2 pins. (5) DZF detection of the DAC which is powered-down is ignored, and DZF1-2 pins go to “H”. (6) When the power-down function is set up and the channel has input signal, even if the partial power-down function is set up, DZF1-2 pins will not be “H”. Figure 16. DAC partial power-down example MS0287-E-03 2009/05 - 38 - [AK4588] ■ Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH Register Name Control 1 Control 2 LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control LOUT3 Volume Control ROUT3 Volume Control De-emphasis ATT speed & Power Down Control Zero detect LOUT4 Volume Control ROUT4 Volume Control D7 0 CKS1 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 DEMD1 D6 0 DFS1 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 DEMD0 D5 TDM1 LOOP1 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 DEMA1 D4 TDM0 LOOP0 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 DEMA0 D3 DIF1 SDOS ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 DEMB1 D2 DIF0 DFS0 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 DEMB0 D1 0 ACKS ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 DEMC1 D0 SMUTE CKS0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 DEMC0 0 PD4 ATS1 ATS0 PD3 PD2 PD1 RSTN1 OVFE ATT7 ATT7 DZFM3 ATT6 ATT6 DZFM2 ATT5 ATT5 DZFM1 ATT4 ATT4 DZFM0 ATT3 ATT3 PWVRN ATT2 ATT2 PWADN ATT1 ATT1 PWDAN ATT0 ATT0 Note: For addresses from 0DH to 1FH, data is not written. When the PDN pin goes to “L”, the registers are initialized to their default values. When RSTN1 bit set to “0”, the internal timing is reset and the DZF1-2 pins go to “H”, but registers are not initialized to their default values. ■ Register Definitions Addr 00H Register Name Control 1 Default D7 0 0 D6 0 0 D5 TDM1 0 D4 TDM0 0 D3 DIF1 1 D2 DIF0 0 D1 0 0 D0 SMUTE 0 SMUTE: Soft Mute Enable 0: Normal operation 1: All DAC outputs soft-muted DIF1-0: Audio Data Interface Modes (Table 10) Initial: “10”, mode 2 TDM1-0: TDM Format Select (Table 11, Table 12) Mode 0 1 2 TDM1 TDM0 0 0 0 1 1 1 SDTI 1-4 1 1-2 Sampling Speed Normal, Double, Four Times Speed Normal Speed Double Speed MS0287-E-03 2009/05 - 39 - [AK4588] Addr 01H Register Name Control 2 Default D7 CKS1 0 D6 DFS1 0 D5 LOOP1 0 D4 LOOP0 0 D3 SDOS 0 D2 DFS0 0 D1 ACKS 0 D0 CKS0 0 ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0 bits are ignored. When this bit is “0”, DFS1-0 bits set the sampling speed mode. DFS1-0: Sampling speed mode (Table 1.) The setting of DFS1-0 bits are ignored at ACKS bit “1”. CKS0-1: Master clock frequency select (Table 2) SDOS: SDTO1 source select 0: ADC 1: DAUX SDOS bit should be set to “0” at TDM bit “1”. In case of PWADN bit = “0” and PWDAN bit = “0”, the setting of SDOS bit becomes invalid. And ADC is selected. The output of SDTO1 becomes “L” at PWADN bit = “0”. LOOP1-0: Loopback mode enable 00: Normal (No loop back) 01: LIN → LOUT1, LOUT2, LOUT3, LOUT4 RIN → ROUT1, ROUT2, ROUT3, ROUT4 The digital ADC output (DAUX1 input if SDOS = “1”) is connected to the digital DAC input. In this mode, the input DAC data to SDTI1-3 is ignored. The audio format of SDTO1 at loopback mode becomes mode 2 at mode 0, and mode 3 at mode 1, respectively. 10: SDTI1(L) → SDTI2(L), SDTI3(L), SDTI4(L) SDTI1I → SDTI2I, SDTI3I, SDTI4I In this mode the input DAC data to SDTI2-4 is ignored. 11: N/A LOOP1-0 bits should be set to “00” at TDM bit “1”. In case of PWADN bit = “0” and PWDAN bit = “0”, the setting of LOOP1-0 bits become invalid. And ADC is selected. And it becomes the normal operation (No loop back). MS0287-E-03 2009/05 - 40 - [AK4588] Addr 02H 03H 04H 05H 06H 07H 0BH 0CH Register Name LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control LOUT3 Volume Control ROUT3 Volume Control LOUT4 Volume Control ROUT4 Volume Control Default D7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 0 D6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 0 D5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 0 D4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 0 D3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 0 D2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 0 D1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 0 D0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 0 ATT7-0: Attenuation Level (Table 15) Addr 08H Register Name De-emphasis Default D7 DEMD1 0 D6 DEMD0 1 D5 DEMA1 0 D4 DEMA0 1 D3 DEMB1 0 D2 DEMB0 1 D1 DEMC1 0 D0 DEMC0 1 DEMA1-0: De-emphasis response control for DAC1 data on SDTI1 (Table 8) Initial: “01”, OFF DEMB1-0: De-emphasis response control for DAC2 data on SDTI2 (Table 8) Initial: “01”, OFF DEMC1-0: De-emphasis response control for DAC3 data on SDTI3 (Table 8) Initial: “01”, OFF DEMD1-0: De-emphasis response control for DAC4 data on SDTI4 (Table 8) Initial: “01”, OFF MS0287-E-03 2009/05 - 41 - [AK4588] Addr 09H Register Name ATT speed & Power Down Control Default D7 D6 D5 D4 D3 D2 D1 D0 0 PD4 ATS1 ATS0 PD3 PD2 PD1 RSTN1 0 0 0 0 0 0 0 1 RSTN1: Internal timing reset 0: Reset. DZF1-2 pins go to “H”, but registers are not initialized. 1: Normal operation ATS1-0: Digital attenuator transition time setting (Table 16) Initial: “00”, mode 0 PD1-0: Power-down control (0: Power-up, 1: Power-down) PD1: Power down control of DAC1 PD2: Power down control of DAC2 PD3: Power down control of DAC3 PD4: Power down control of DAC4 Addr 0AH Register Name Zero detect Default D7 OVFE 0 D6 DZFM3 0 D5 DZFM2 1 D4 DZFM1 1 D3 DZFM0 1 D2 PWVRN 1 D1 PWADN 1 D0 PWDAN 1 PWDAN: Power-down control of DAC1-4 0: Power-down 1: Normal operation PWADN: Power-down control of ADC 0: Power-down 1: Normal operation PWVRN: Power-down control of reference voltage 0: Power-down 1: Normal operation DZFM3-0: Zero detect mode select (Table 13) Initial: “0111”, disable OVFE: Overflow detection enable 0: Disable, pin#33 becomes DZF2 pin. 1: Enable, pin#33 becomes OVF pin. MS0287-E-03 2009/05 - 42 - [AK4588] OPERATION OVERVIEW (DIR/DIT part) ■ Non-PCM (AC-3, MPEG, etc.) and DTS-CD Bitstream Detection The AK4588 has a Non-PCM steam auto-detect function. When the 32bit mode Non-PCM preamble based on Dolby “AC-3 Data Stream in IEC60958 Interface” is detected, the AUTO bit goes “1”. The 96bit sync code consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the AUTO bit “1”. Once the AUTO bit is set “1”, it will remain “1” until 4096 frames pass through the chip without additional sync pattern being detected. When those preambles are detected, the burst preambles Pc and Pd that follow those sync codes are stored to registers. The AK4588 also has the DTS-CD bitstream auto-detection function. When The AK4588 detects DTS-CD bitstreams, DTSCD bit goes to “1”. When the next sync code does not come within 4096 flames, DTSCD bit goes to “0” until when AK4114 detects the stream again. ■ 192kHz Clock Recovery On chip low jitter PLL has a wide lock range with 32kHz to 192kHz and the lock time is less than 20ms. The AK4588 has the sampling frequency detect function. By either the clock comparison against X’tal oscillator or using the channel status, AK4588 detects the sampling frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz). The PLL loses lock when the received sync interval is incorrect. ■ Master Clock The AK4588 has two clock outputs, MCKO1 and MCKO2. These clocks are derived from either the recovered clock or from the X’tal oscillator. The frequencies of the master clock outputs (MCKO1 and MCKO2) are set by OCKS0 and OCKS1 as shown in Table 17. The 512fs clock will not output when 96kHz and 192kHz. The 256fs clock will not output when 192kHz. No. 0 1 2 3 OCKS1 0 0 1 1 OCKS0 0 1 0 1 MCKO1 256fs 256fs 512fs 128fs MCKO2 256fs 128fs 256fs 64fs X’tal 256fs 256fs 512fs 128fs fs (max) 96 kHz 96 kHz 48 kHz 192 kHz (default) Table 17. Master Clock Frequency Select (Stereo mode) ■ Clock Operation Mode The CM0/CM1 pins (or bits) select the clock source and the data source of SDTO. In Mode 2, the clock source is switched from PLL to X’tal when PLL goes unlock state. In Mode3, the clock source is fixed to X’tal, but PLL is also operating and the recovered data such as C bits can be monitored. For Mode2 and 3, it is recommended that the frequency of X’tal is different from the recovered frequency from PLL. Mode 0 1 CM1 0 0 CM0 0 1 UNLOCK PLL X’tal Clock source SDTO (default) ON ON(Note) PLL RX OFF ON X’tal DAUX 0 ON ON PLL RX 2 1 0 1 ON ON X’tal DAUX 3 1 1 ON ON X’tal DAUX ON: Oscillation (Power-up), OFF: STOP (Power-down) Note : When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is off. Table 18. Clock Operation Mode select MS0287-E-03 2009/05 - 43 - [AK4588] ■ Clock Source The clock for the XTI pin can be generated b following methods. 1) X’tal XTI C 25kΩ(typ) C XTO AK4588 Figure 17. X’tal mode Note: External capacitance depends on the crystal oscillator (Typ. 10-40pF) 2) External clock C XTI XTI External Clock External Clock 25kΩ(typ) 25kΩ(typ) XTO XTO AK4588 AK4588 Figure 18 (5V). (a).External clock mode (Input :CMOS Level) - Note: Input clock must not exceed DVDD. Figure 19 (3.3V). (b). External clock mode (Input : ≥40%DVDD) 3) Fixed to the Clock Operation Mode 0 XTI 25kΩ(typ) XTO AK4588 Figure 20. OFF mode MS0287-E-03 2009/05 - 44 - [AK4588] ■ Sampling Frequency and Pre-emphasis Detection The AK4588 has two methods for detecting the sampling frequency as follows. 1. Clock comparison between recovered clock and X’tal oscillator 2. Sampling frequency information on channel status Those could be selected by XTL1, 0 bits. And the detected frequency is reported on FS3-0 bits. XTL1 0 0 1 1 XTL0 0 1 0 1 X’tal Frequency 11.2896MHz 12.288MHz 24.576MHz (Use channel status) (default) Table 19. Reference X’tal frequency Except XTL1,0= “1,1” XTL1,0= “1,1” Consumer Register output fs Professional mode mode Clock comparison (Note 25) (Note 24) Byte3 Byte0 Byte4 FS3 FS2 FS1 FS0 Bit3/2/1/0 Bit7/6 Bit6/5/4/3 0 0 0 0 44.1kHz 44.1kHz 0000 01 0000 0 0 0 1 Reserved Reserved 0001 (Others) 0 0 1 0 48kHz 48kHz 0010 10 0000 0 0 1 1 32kHz 32kHz 0011 11 0000 1 0 0 0 88.2kHz 88.2kHz (1000) 00 1010 1 0 1 0 96kHz 96kHz (1010) 00 0010 1 1 0 0 176.4kHz 176.4kHz (1100) 00 1011 1 1 1 0 192kHz 192kHz (1110) 00 0011 Note 24. At least ±3% range is identified as the value in the Table 20. In case of intermediate frequency of those two, FS3-0 bits indicate nearer value. When the frequency is much bigger than 192kHz or much smaller than 32kHz, FS3-0 bits may indicate “0001”. Note 25. When consumer mode, Byte3 Bit3-0 are copied to FS3-0 bits. Table 20. fs Information The pre-emphasis information is detected and reported on PEM bit. These information are extracted from channel 1 at default. It can be switched to channel 2 by CS12 bit in control register. PEM Pre-emphasis 0 1 OFF ON Byte 0 Bits 3-5 ≠ 0X100 0X100 Table 21. PEM in Consumer Mode PEM Pre-emphasis 0 1 OFF ON Byte 0 Bits 2-4 ≠110 110 Table 22. PEM in Professional Mode MS0287-E-03 2009/05 - 45 - [AK4588] ■ De-emphasis Filter Control The AK4588 has a digital de-emphasis filter (tc=50/15µs) which corresponds to four sampling frequencies (32kHz, 44.1kHz, 48kHz and 96kHz) by IIR filter. When DEAU bit=“1”, the de-emphasis filter is enabled automatically by sampling frequency and pre-emphasis information in the channel status. This is the default setting of de-emphasis filter of the AK4588. In Serial Mode, DEM0/1 and DFS bits can control the de-emphasis filter when DEAU bit is “0”. The internal de-emphasis filter is bypassed and the recovered data is output without any change if either pre-emphasis or de-emphasis Mode is OFF. PEM 1 1 1 1 1 0 FS3 0 0 0 1 FS2 0 0 0 0 FS1 0 1 1 1 FS0 0 0 1 0 Mode 44.1kHz 48kHz 32kHz 96kHz (Others) OFF x x x x OFF (x: Don’t care) Table 23. De-emphasis Auto Control at DEAU bit = “1” (Default) PEM 1 1 1 1 1 1 1 1 0 DFS 0 0 0 0 1 1 1 1 x DEM1 0 0 1 1 0 0 1 1 x DEM0 0 1 0 1 0 1 0 1 x Mode 44.1kHz OFF (default) 48kHz 32kHz OFF OFF 96kHz OFF OFF (x: Don’t care) Table 24. De-emphasis Manual Control at DEAU bit = “0” ■ System Reset and Power-Down The AK4588 has power-down mode for all circuits by the PDN pin and partially powered-down by PWN bit. The RSTN bit initializes the register and resets the internal timing. In Parallel Mode, only the control by PDN pin is enabled. The AK4588 should be reset once by bringing the PDN pin = “L” upon power-up. PDN Pin: All analog and digital circuit are placed in the power-down and reset mode by bringing the PDN pin = “L”. All registers are initialized, and clocks are stopped. Reading and witting to the register are disabled. RSTN2 Bit (Address 00H; D0): All the registers except PWN and RSTN2 bits are initialized by bringing RSTN2 bit = “0”. The internal timings are also initialized. Witting to the register is not available except PWN and RSTN2 bits. Reading to the register is disabled. PWN Bit (Address 00H; D1): The clock recovery part is initialized by bringing PWN bit = “0”. In this case, clocks are stopped. The registers are not initialized and the mode settings are kept. Writing and Reading to the registers are enabled. MS0287-E-03 2009/05 - 46 - [AK4588] ■ Biphase Input and Through Output Eight receiver inputs (RX0-7) are available in Serial Control Mode. Each input includes amplifier corresponding to unbalance mode and can accept the signal of 200mV or more. IPS2-0 bits selects the receiver channel. When BCU bit = “1”, the Block start signal, C bit and U bit can be output from each pins. IPS2 0 0 0 0 1 1 1 1 IPS1 0 0 1 1 0 0 1 1 IPS0 0 1 0 1 0 1 0 1 INPUT Data RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 (default) Table 25. Recovery Data Select B 1/4fs COUT (or U,V) SDTO2 C(R191) C(L0) R190 C(R0) L191 C(L1) R191 C(L31) L0 L30 C(R31) C(L32) R30 L31 LRCK2 (except I2S) LRCK2 (I2S) Figure 21. B/C/U/V output/input timings MS0287-E-03 2009/05 - 47 - [AK4588] ■ Biphase Output The AK4588 can output the data either the through output(from DIR) or transmitter output(DIT; the data from DAUX2 is transformed to IEC60958 format.) from TX1/0 pins. Those could be selected by DIT bit. The source of the through output from TX0 could be selected among RX0-8 by OPS00/ 01/ 02 bits, for TX1, by OPS10/ 11/ 12 bits respectively. When output DAUX2 data, V bit could be controlled by the VIN pin and first 5 bytes of C bit could be controlled by CT39-CT0 bits in control registers. When bit0= “0”(consumer mode), bit20-23 (Audio channel) could not be controlled directly but be controlled by CT20 bit. When the CT20 bit is “1”, the AK4588 outputs “1000” as C20-23 for left channel and output “0100” at C20-23 for right channel automatically. When CT20 bit is “0”, the AK4588 outputs “0000” set as “1000” for sub frame 1, and “0100” for sub frame 2. U bits are fixed to “0”.as C20-23 for both channel. U bit could be controlled by UDIT bit as follows; When UDIT bit is “0”, U bit is always “0”. When UDIT bit is “1”, the recovered U bits are used for DIT (DIR/DIT loop mode of U bit). This mode is only available when PLL is locked in master mode. OPS02 0 0 0 0 1 1 1 1 OPS01 0 0 1 1 0 0 1 1 OPS00 0 1 0 1 0 1 0 1 Output Data RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 (default) Table 26. Output Data Select for TX0 DIT 0 0 0 0 0 0 0 0 1 OPS12 0 0 0 0 1 1 1 1 x OPS11 0 0 1 1 0 0 1 1 x OPS10 0 1 0 1 0 1 0 1 x Output Data RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 DAUX2 (default) Table 27. Output Data Select for TX1 LRCK2 (except I2S) LRCK2 (I2S) DAUX2 L0 R0 L1 R1 VIN R191 L0 R0 L1 Figure 22. DAUX2 and VIN input timings MS0287-E-03 2009/05 - 48 - [AK4588] ■ Biphase signal input/output circuit 0.1uF RX 75Ω Coax 75Ω AK4588 Figure 23. Consumer Input Circuit (Coaxial Input) Note: In case of coaxial input, if a coupling level to this input from the next RX input line pattern exceeds 50mV, there is a possibility of malfunction. Connecting a decoupling capacitor can lower this coupling noise. Optical Receiver Optical Fiber 470 RX O/E AK4588 Figure 24. Consumer Input Circuit (Optical Input) For coaxial input, as the input level of RX line is small in Serial Mode, cross-talking among RX input lines have to be avoided. For example, by inserting the shield pattern among them. In Parallel Mode, only one channel input (RX1) is available and RX2-4 change to other pins for audio format control. Those pins must be fixed to “H” or “L”. The AK4588 has a TX output buffer. The output level meets 0.5V+/-20% with the external resistors. The T1 in Figure 25 is a transformer of 1:1. 330±2% TX 75Ω cable 100±2% DVSS T1 Figure 25. TX External Resistor Network MS0287-E-03 2009/05 - 49 - [AK4588] ■ Q-subcode buffers The AK4588 has Q-subcode buffer for CD application. The AK4588 takes Q-subcode into registers in following conditions. 1. The sync word (S0,S1) is constructed at least 16 “0”s. 2. The start bit is “1”. 3. Those 7bits Q-W follows to the start bit. 4. The distance between two start bits are 8-16 bits. The QINT bit in the control register goes “1” when the new Q-subcode differs from old one, and goes “0” when QINT bit is read. S0 S1 S2 S3 : S97 S0 S1 S2 S3 : 1 0 0 1 1 : 1 0 0 1 1 : 2 3 4 5 6 7 8 * 0 0 0 0 0 0 0 0… 0 0 0 0 0 0 0 0… Q2 R2 S2 T2 U2 V2 W2 0… Q3 R3 S3 T3 U3 V3 W3 0… : : : : : : : : Q97 R97 S97 T97 U97 V97 W97 0… 0 0 0 0 0 0 0 0… 0 0 0 0 0 0 0 0… Q2 R2 S2 T2 U2 V2 W2 0… Q3 R3 S3 T3 U3 V3 W3 0… : : : : : : : : ↑ Q Q2 Q3 Q4 CTRL Q5 Q6 Q7 Q8 ADRS (*) number of “0” : min=0; max=8. Figure 26. Configuration of U-bit(CD) Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25 TRACK NUMBER INDEX Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49 MINUTE SECOND FRAME Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73 ZERO ABSOLUTE MINUTE ABSOLUTE SECOND Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97 ABSOLUTE FRAME CRC G(x)=x^16+x^12+x^5+1 Figure 27. Q-subcode Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 16H Q-subcode Address / Control 17H Q-subcode Track 18H Q-subcode Index Q9 Q17 ··· Q8 Q16 ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· Q3 Q11 ··· Q2 Q10 ··· 19H Q-subcode Minute ··· ··· ··· ··· ··· ··· ··· ··· 1AH Q-subcode Second ··· ··· ··· ··· ··· ··· ··· ··· 1BH Q-subcode Frame ··· ··· ··· ··· ··· ··· ··· ··· 1CH Q-subcode Zero ··· ··· ··· ··· ··· ··· ··· ··· 1DH Q-subcode ABS Minute ··· ··· ··· ··· ··· ··· ··· ··· 1EH Q-subcode ABS Second ··· ··· ··· ··· ··· ··· ··· ··· 1FH Q-subcode ABS Frame Q81 Q80 ··· ··· ··· ··· Q75 Q74 Figure 28. Q-subcode register MS0287-E-03 2009/05 - 50 - [AK4588] ■ Error Handling There are the following eight events that make INT0/1 pins “H”. INT0/1 pins show the status of following conditions. 1. UNLOCK: “1” when the PLL loses lock. The AK4588 loses lock when the distance between two preambles is not correct or when those preambles are not correct. “1” when parity error or biphase coding error is detected, and keeps “1” until this register is read. 2. PAR: Updated every sub-frame cycle. Reading this register resets itself. “1” when Non-PCM bitstream is detected. 3. AUTO: Updated every 4096 frames cycle. “1” when DTS-CD bitstream is detected. 4. DTSCD: Updated every DTS-CD sync cycle. “1” when the “AUDIO” bit in recovered channel status indicates “1”. 5. AUDION: Updated every block cycle. “1” when “PEM” in recovered channel status indicates “1”. 6. PEM: Updated every block cycle. “1” when Q-subcode differ from old one, and keeps “1” until this register is read. 7. QINT: Updated every sync code cycle for Q-subcode. Reading this register resets itself. “1” when received C bits differ from old one, and keeps “1” until this register is read. 8. CINT: Updated every block cycle. Reading this register resets itself. Both INT0/1 are fixed to “L” when the PLL is off (CM1,0= “01”). Once the INT0 pin goes to “H”, this pin holds “H” for 1024/fs cycles (this value can be changed by EFH0/1 bits) after those events are removed. INT1 pin goes to “L” at the same time when those events are removed. Each INT0/1 pins can mask those eight events individually. Once PAR, QINT and CINT bit goes to “1”, those registers are held to “1” until those registers are read. While the AK4588 is unlocked, registers regarding C-bit or U-bits are not initialized and keep previous value. INT0/1 pin output the ORed signal on those eight events. However, each events can be masked by each mask bits. When each bit masks those events, the event does not affect INT0/1 pins operation (those mask do not affect those registers (UNLOCK, PAR, etc.) themselves. Once the INT0 pin goes “H”, it maintains “H” for 1024/fs cycles (this value can be changed by EFH0-1 bits) after the all events are removed. Once those PAR, QINT or CINT bit goes “1”, it holds “1” until reading those registers. While the AK4588 loses lock, the channel status an Q-subcode bits are not updated and holds the previous data. At initial state, the INT0 pin outputs the ORed signal between UNLOCK and PAR, the INT1 pin outputs the ORed signal among AUTO, DTSCD and AUDION. UNLOCK 1 0 0 0 0 0 0 0 PAR x 1 0 0 0 0 0 0 AUTO x x 1 x x x x x Register DTSCD AUDION PEM QINT x x x x x x x x x x x x 1 x x x x 1 x x x x 1 x x x x 1 x x x x Table 28. Error Handling MS0287-E-03 Pin CINT x x x x x x x 1 SDTO2 L Previous Data Output Output Output Output Output Output V L Output Output Output Output Output Output Output TX Output Output Output Output Output Output Output Output 2009/05 - 51 - [AK4588] Error (UNLOCK, PAR,..) (Error) INT0 pin Hold Time (max: 4096/fs) INT1 pin Hold Time = 0 Register (PAR,CINT,QINT) Reset Hold ”1” Register (others) Command MCKO,BICK2,LRCK2 (UNLOCK) MCKO,BICK2,LRCK2 (except UNLOCK) READ 06H Free Run (fs: around 20kHz) SDTO2 (UNLOCK) SDTO2 (PAR error) Previous Data SDTO2 (others) VOUT pin (UNLOCK) VOUT pin (except UNLOCK) Normal Operation Figure 29. INT0/1 pin timing MS0287-E-03 2009/05 - 52 - [AK4588] PDN pin ="L" to "H" Initialize Read 06H INT0/1 pin ="H" No Yes Release Muting Mute DA C output Read 06H (Each Error Handling) Read 06H (Res ets registers) No INT0/1 pin ="H" Yes Figure 30. Error Handling Sequence Example 1 MS0287-E-03 2009/05 - 53 - [AK4588] PDN pin ="L" to "H" Initialize Read 06H No INT1 pin ="H" Yes Read 06H and Detect QSUB= “1” (Read Q-buffer) QCRC = “0” No New data is invalid Yes INT1 pin ="L" No Yes New data is valid Figure 31. Error Handling Sequence Example 2 (for Q/CINT) MS0287-E-03 2009/05 - 54 - [AK4588] ■ Audio Serial Interface Format The DIF0, DIF1 and DIF2 pins can select eight serial data formats as shown in Table 29. In all formats the serial data is MSB-first, 2’s complement format. The SDTO2 is clocked out on the falling edge of BICK2 and the DAUX2 is latched on the rising edge of BICK2. BICK2 outputs 64fs clock in Mode 0-5. Mode 6-7 are Slave Modes, and BICK2 is available up to 128fs at fs=48kHz. In the format equal or less than 20bit (Mode0-2), LSBs in sub-frame are truncated. In Mode 3-7, the last 4LSBs are auxiliary data (Figure 32). When using Master mode, BICK2 and KRCK2 output pins are Hi-Z during PDN pin = “L” and from PDN pin = “H” to entering Master mode. When the Parity Error, Biphase Error or Frame Length Error occurs in a sub-frame, the AK4588 continues to output the last normal sub-frame data from SDTO2 repeatedly until the error is removed. When the Unlock Error occurs, the AK4588 outputs “0” from the SDTO2 pin. In case of using the DAUX2 pin, the data is transformed and output from SDTO2. The DAUX2 pin is used in Clock Operation Mode 1/ 3 and unlock state of Mode 2. The input data format to DAUX2 should be left justified except in Mode5 and 7(Table 29). In Mode5 or 7, both the input data format of DAUX2 and output data format of SDTO2 are I2S. Mode6 and 7 are Slave Mode that is corresponding to the Master Mode of Mode4 and 5. In salve Mode, LRCK2 and BICK2 should be fed with synchronizing to MCKO1/2. sub-frame of IEC60958 0 3 4 preamble 7 8 11 12 27 28 29 30 31 Aux. V U C P LSB MSB MSB LSB 23 0 AK4588 Audio Data (MSB First) Figure 32. Bit configuration Mode DIF2 DIF1 DIF0 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 DAUX2 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S SDTO2 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S LRCK2 I/O H/L O H/L O H/L O H/L O H/L O L/H O H/L I L/H I BICK2 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs I/O O O O O O O I I (default) Table 29. Audio data format MS0287-E-03 2009/05 - 55 - [AK4588] LRCK2 0 1 2 15 16 17 31 0 1 2 15 16 17 31 0 1 0 1 0 1 BICK2 (0:64fs) 15 14 1 0 15 14 1 0 SDTO2 15:MSB, 0:LSB Rch Data Lch Data Figure 33. Mode 0 Timing LRCK2 0 1 2 9 10 12 11 31 0 1 2 9 10 11 12 31 BICK2 (0:64fs) 23 22 21 20 1 0 23 22 21 20 1 0 SDTO2 23:MSB, 0:LSB Rch Data Lch Data Figure 34. Mode 3 Timing LRCK2 0 1 2 21 22 24 23 31 0 1 2 21 22 23 24 31 BICK2 (64fs) 23 22 21 2 1 0 23 22 3 2 1 0 23 22 SDTO2 23:MSB, 0:LSB Rch Data Lch Data Figure 35. Mode 4/6 Timing Mode4: LRCK2, BICK2: Output Mode6: LRCK2, BICK2: Input LRCK2 0 1 2 22 24 23 25 31 0 1 2 21 22 23 24 25 31 0 1 BICK2 (64fs) SDTO2 23 22 21 2 1 23 22 0 3 2 1 0 23 23:MSB, 0:LSB Rch Data Lch Data Figure 36. Mode 5/7 Timing MS0287-E-03 Mode5: LRCK2, BICK2: Output Mode7: LRCK2, BICK2: Input 2009/05 - 56 - [AK4588] ■ Register Map Addr D7 D6 D5 D4 D3 D2 D1 D0 CS12 BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN2 01H Register Name CLK & Power Down Control Format & De-em Control 0 DIF2 DIF1 DIF0 DEAU DEM1 DEM0 DFS 02H Input/ Output Control 0 TX1E OPS12 OPS11 OPS10 TX0E OPS02 OPS01 OPS00 03H Input/ Output Control 1 EFH1 EFH0 UDIT 0 DIT IPS2 IPS1 IPS0 04H INT0 MASK MQIT0 MAUT0 MCIT0 MULK0 MDTS0 MPE0 MAUD0 MPAR0 05H INT1 MASK MQIT1 MAUT1 MCIT1 MULK1 MDTS1 MPE1 MAUD1 MPAR1 06H Receiver status 0 QINT AUTO CINT UNLCK DTSCD PEM AUDION PAR 07H Receiver status 1 FS3 FS2 FS1 V QCRC CCRC 08H RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 09H RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 0AH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16 0BH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24 0CH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32 0DH TX Channel Status Byte 0 CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0 0EH TX Channel Status Byte 1 CT15 CT14 CT13 CT12 CT11 CT10 CT9 CT8 0FH TX Channel Status Byte 2 CT23 CT22 CT21 CT20 CT19 CT18 CT17 CT16 10H TX Channel Status Byte 3 CT31 CT30 CT29 CT28 CT27 CT26 CT25 CT24 11H TX Channel Status Byte 4 CT39 CT39 CT39 CT39 CT39 CT39 CT39 CT32 12H Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 13H Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 14H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 15H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 16H Q-subcode Address / Control Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 17H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 18H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 00H FS0 0 19H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 1AH Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34 1BH Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 1CH Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50 1DH Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58 1EH Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66 1FH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 When PDN pin goes “L”, the registers are initialized to their default values. When RSTN bit goes “0”, the internal timing is reset and the registers are initialized to their default values. All data can be written to the register even if PWN bit is “0”. 01H D7 and 03H D4 should be written “0” data. Q74 MS0287-E-03 2009/05 - 57 - [AK4588] ■ Register Definitions Reset & Initialize Addr Register Name 00H CLK & Power Down Control R/W Default D7 CS12 R/W 0 D6 BCU R/W 1 D5 CM1 R/W 0 D4 CM0 R/W 0 D3 D2 OCKS1 OCKS0 R/W R/W 0 0 D1 PWN R/W 1 D0 RSTN2 R/W 1 RSTN2: Timing Reset & Register Initialize 0: Reset & Initialize 1: Normal Operation PWN: Power Down 0: Power Down 1: Normal Operation OCKS1-0: Master Clock Frequency Select CM1-0: Master Clock Operation Mode Select BCU: Block start & C/U Output Mode When BCU=1, the three Output Pins(BOUT, COUT, UOUT) become to be enabled. The block signal goes high at the start of frame 0 and remains high until the end of frame 31. CS12: Channel Status Select 0: Channel 1 1: Channel 2 Selects which channel status is used to derive C-bit buffers, AUDION, PEM, FS3, FS2, FS1, FS0, Pc and Pd. The de-emphasis filter is controlled by channel 1 in the Parallel Mode. Format & De-emphasis Control Addr Register Name 01H Format & De-em Control R/W Default D7 0 RD 0 D6 DIF2 R/W 1 D5 DIF1 R/W 1 D4 DIF0 R/W 0 D3 DEAU R/W 1 D2 DEM1 R/W 0 D1 DEM0 R/W 1 D0 DFS R/W 0 DFS: 96kHz De-emphasis Control DEM1-0: 32, 44.1, 48kHz De-emphasis Control (Table 24.) DEAU: De-emphasis Auto Detect Enable 0: Disable 1: Enable DIF2-0: Audio Data Format Control (Table 29.) MS0287-E-03 2009/05 - 58 - [AK4588] Input/Output Control Addr Register Name 02H Input/ Output Control 0 R/W Default D7 TX1E R/W 1 D6 D5 D4 OPS12 OPS11 OPS10 R/W R/W R/W 0 0 0 D3 TX0E R/W 1 D2 D1 D0 OPS02 OPS01 OPS00 R/W R/W R/W 0 0 0 OPS02-00: Output Through Data Select for TX0 pin OPS12-10: Output Through Data Select for TX1 pin TX0E: TX0 Output Enable 0: Disable. TX0 pin outputs “L”. 1: Enable TX1E: TX1 Output Enable 0: Disable. TX1 pin outputs “L”. 1: Enable Addr Register Name 03H Input/ Output Control 1 R/W Default D7 EFH1 R/W 0 D6 EFH0 R/W 1 D5 UDIT R/W 0 D4 0 RD 0 D3 DIT R/W 1 D2 IPS2 R/W 0 D1 IPS1 R/W 0 D0 IPS0 R/W 0 IPS2-0: Input Recovery Data Select DIT: Through data/Transmit data select for TX1 pin 0: Through data (RX data). 1: Transmit data (DAUX2 data). UDIT: U bit control for DIT 0: U bit is fixed to “0” 1: Recovered U bit is used for DIT (loop mode for U bit) EFH1-0: Interrupt 0 Pin Hold Count Select 00: 512 LRCK2 01: 1024 LRCK2 10: 2048 LRCK2 11: 4096 LRCK2 MS0287-E-03 2009/05 - 59 - [AK4588] Mask Control for INT0 Addr Register Name 04H INT0 MASK R/W Default D7 MQI0 R/W 1 D6 MAT0 R/W 1 D5 MCI0 R/W 1 D4 MUL0 R/W 0 D3 MDTS0 R/W 1 D2 MPE0 R/W 1 D1 MAN0 R/W 1 D0 MPR0 R/W 0 D5 MCI1 R/W 1 D4 MUL1 R/W 1 D3 MDTS1 R/W 0 D2 MPE1 R/W 1 D1 MAN1 R/W 0 D0 MPR1 R/W 1 MPR0: Mask Enable for PAR bit MAN0: Mask Enable for AUDN bit MPE0: Mask Enable for PEM bit MDTS0: Mask Enable for DTSCD bit MUL0: Mask Enable for UNLOCK bit MCI0: Mask Enable for CINT bit MAT0: Mask Enable for AUTO bit MQI0: Mask Enable for QINT bit 0: Mask disable 1: Mask enable Mask Control for INT1 Addr Register Name 05H INT1 MASK R/W Default D7 MQI1 R/W 1 D6 MAT1 R/W 0 MPR1: Mask Enable for PAR bit MAN1: Mask Enable for AUDN bit MPE1: Mask Enable for PEM bit MDTS1: Mask Enable for DTSCD bit MUL1: Mask Enable for UNLOCK0 bit MCI1: Mask Enable for CINT bit MAT1: Mask Enable for AUTO bit MQI1: Mask Enable for QINT bit 0: Mask disable 1: Mask enable MS0287-E-03 2009/05 - 60 - [AK4588] Receiver Status 0 Addr Register Name 06H Receiver status 0 R/W Default D7 QINT RD 0 D6 AUTO RD 0 D5 CINT RD 0 D4 D3 UNLCK DTSCD RD RD 0 0 D2 PEM RD 0 D1 AUDION RD 0 D0 PAR RD 0 D2 V RD 0 D1 QCRC RD 0 D0 CCRC RD 0 PAR: Parity Error or Biphase Error Status 0:No Error 1:Error It is “1” if Parity Error or Biphase Error is detected in the sub-frame. AUDION: Audio Bit Output 0: Audio 1: Non Audio This bit is made by encoding channel status bits. PEM: Pre-emphasis Detect. 0: OFF 1: ON This bit is made by encoding channel status bits. DTSCD: DTS-CD Auto Detect 0: No detect 1: Detect UNLCK: PLL Lock Status 0: Locked 1: Out of Lock CINT: Channel Status Buffer Interrupt 0: No change 1: Changed AUTO: Non-PCM Auto Detect 0: No detect 1: Detect QINT: Q-subcode Buffer Interrupt 0: No change 1: Changed QINT, CINT and PAR bits are initialized when 06H is read. Receiver Status 1 Addr Register Name 07H Receiver status 1 R/W Default D7 FS3 RD 0 D6 FS2 RD 0 D5 FS1 RD 0 D4 FS0 RD 1 D3 0 RD 0 CCRC: Cyclic Redundancy Check for Channel Status 0:No Error 1:Error QCRC: Cyclic Redundancy Check for Q-subcode 0:No Error 1:Error V: Validity of channel status 0:Valid 1:Invalid FS3-0: Sampling Frequency detection (Table 20.) MS0287-E-03 2009/05 - 61 - [AK4588] Receiver Channel Status Addr 08H 09H 0AH 0BH 0CH Register Name RX Channel Status Byte 0 RX Channel Status Byte 1 RX Channel Status Byte 2 RX Channel Status Byte 3 RX Channel Status Byte 4 R/W Default D7 CR7 CR15 CR23 CR31 CR39 D6 CR6 CR14 CR22 CR30 CR38 D5 CR5 CR13 CR21 CR29 CR37 D4 CR4 CR12 CR20 CR28 CR36 D3 CR3 CR11 CR19 CR27 CR35 D2 CR2 CR10 CR18 CR26 CR34 D1 CR1 CR9 CR17 CR25 CR33 D0 CR0 CR8 CR16 CR24 CR32 D2 CT2 CT10 CT18 CT26 CT34 D1 CT1 CT9 CT17 CT25 CT335 D0 CT0 CT8 CT16 CT24 CT32 D2 PC2 PC10 PD2 PD10 D1 PC1 PC9 PD1 PD9 D0 PC0 PC8 PD0 PD8 RD Not initialized CR39-0: Receiver Channel Status Byte 4-0 Transmitter Channel Status Addr 0DH 0EH 0FH 10H 11H Register Name TX Channel Status Byte 0 TX Channel Status Byte 1 TX Channel Status Byte 2 TX Channel Status Byte 3 TX Channel Status Byte 3 R/W Default D7 CT7 CT15 CT23 CT31 CT39 D6 CT6 CT14 CT22 CT30 CT38 D5 CT5 CT13 CT21 CT29 CT37 D4 D3 CT4 CT3 CT12 CT11 CT20 CT19 CT28 CT27 CT36 CT35 R/W 0 CT39-0: Transmitter Channel Status Byte 4-0 Burst Preamble Pc/Pd in non-PCM encoded Audio Bitstreams Addr 12H 13H 14H 15H Register Name Burst Preamble Pc Byte 0 Burst Preamble Pc Byte 1 Burst Preamble Pd Byte 0 Burst Preamble Pd Byte 1 R/W Default D7 PC7 PC15 PD7 PD15 D6 PC6 PC14 PD6 PD14 D5 PC5 PC13 PD5 PD13 D4 PC4 PC12 PD4 PD12 D3 PC3 PC11 PD3 PD11 RD Not initialized PC15-0: Burst Preamble Pc Byte 0 and 1 PD15-0: Burst Preamble Pd Byte 0 and 1 MS0287-E-03 2009/05 - 62 - [AK4588] Q-subcode Buffer Addr 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Register Name Q-subcode Address / Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode ABS Minute Q-subcode ABS Second Q-subcode ABS Frame R/W Default D7 Q9 Q17 Q25 Q33 Q41 Q49 Q57 Q65 Q73 Q81 D6 Q8 Q16 Q24 Q32 Q40 Q48 Q56 Q64 Q72 Q80 D5 Q7 Q15 Q23 Q31 Q39 Q47 Q55 Q63 Q71 Q79 D4 Q6 Q14 Q22 Q30 Q38 Q46 Q54 Q62 Q70 Q78 D3 Q5 Q13 Q21 Q29 Q37 Q45 Q53 Q61 Q69 Q77 D2 Q4 Q12 Q20 Q28 Q36 Q44 Q52 Q60 Q68 Q76 D1 Q3 Q11 Q19 Q27 Q35 Q43 Q51 Q59 Q67 Q75 D0 Q2 Q10 Q18 Q26 Q34 Q42 Q50 Q58 Q66 Q74 RD Not initialized MS0287-E-03 2009/05 - 63 - [AK4588] ■ Burst Preambles in non-PCM Bitstreams sub-frame of IEC958 0 3 4 preamble 7 8 11 12 Aux. 27 28 29 30 31 LSB MSB V U C P 16 bits of bitstream 0 Pa Pb Pc Pd 15 Burst_payload stuffing repetition time of the burst Figure 37. Data structure in IEC60958 Preamble word Pa Pb Pc Pd Length of field 16 bits 16 bits 16 bits 16 bits Contents sync word 1 sync word 2 Burst info Length code Value 0xF872 0x4E1F see Table 31 Numbers of bits Table 30. Burst preamble words MS0287-E-03 2009/05 - 64 - [AK4588] Bits of Pc Value Contents 0-4 data type NULL data Dolby AC-3 data reserved PAUSE MPEG-1 Layer1 data MPEG-1 Layer2 or 3 data or MPEG-2 without extension MPEG-2 data with extension MPEG-2 AAC ADTS MPEG-2, Layer1 Low sample rate MPEG-2, Layer2 or 3 Low sample rate reserved DTS type I DTS type II DTS type III ATRAC ATRAC2/3 reserved reserved, shall be set to “0” error-flag indicating a valid burst_payload error-flag indicating that the burst_payload may contain errors data type dependent info bit stream number, shall be set to “0” 5, 6 7 8-12 13-15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-31 0 0 1 0 Repetition time of burst in IEC60958 frames ≤4096 1536 384 1152 1152 1024 384 1152 512 1024 2048 512 1024 Table 31. Fields of burst info Pc MS0287-E-03 2009/05 - 65 - [AK4588] ■ Non-PCM Bitstream timing 1) When Non-PCM preamble is not coming within 4096 frames, PDN pin Bit stream Pa Pb Pc1 Pd1 Pa Pb Pc2 Pd2 Repetition time Pa Pb Pc3 Pd3 >4096 frames AUTO bit Pc Register “0” Pd Register “0” Pc1 Pc2 Pd1 Pc3 Pd2 Pd3 Figure 38. Timing example 1 2) When Non-PCM bitstream stops (when MULK0= “0”), INT0 hold time INT0 pin <20mS (Lock time) Bit stream Pa Pb Pc1 Pd1 Stop Pa Pb Pcn Pdn 2~3 Syncs (B,M or W) <Repetition time AUTO bit Pc Register Pd Register Pc0 Pc1 Pd0 Pcn Pd1 Pdn Figure 39. Timing example 2 MS0287-E-03 2009/05 - 66 - [AK4588] OPERATION OVERVIEW (ADC/DAC part, DIR/DIT part) ■ Serial Control Interface The AK4588 has two registers, which are ADC/DAC part (AK4628 compatible) and DIR/DIT part (AK4114 compatible). Each register is set by chip address pin. (1). 4-wire serial control mode (I2C pin = “L”) The internal registers may be either written or read by the 4-wire μP interface pins: CSN, CCLK, CDTI & CDTO. The data on this interface consists of Chip address (2bits, ADC/DAC part register is set by CAD1/0 pins. DIR/DIT part C1-0 bits are fixed to “00”), Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. the PDN pin = “L” resets the registers to their default values. When the state of the P/S pin is changed, the AK4588 should be reset by the PDN pin = “L”. Register of ADC/DAC part can not read. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI WRITE CDTO CDTI READ CDTO C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z C1-C0: Chip Address: (Regarding ADC/DAC part, register is set by CAD1/0 pins. This chip address must be set except “00”.) (Fixed to “00” for DIR/DIT part) R/W: READ/WRITE (0:READ, 1:WRITE) A4-A0: Register Address D7-D0: Control Data Figure 40. 4-wire Serial Control I/F Timing MS0287-E-03 2009/05 - 67 - [AK4588] (2). I2C bus control mode (I2C pin = “H”) The AK4588 supports standard-mode I2C-bus (max: 100kHz). Then the AK4588 does not support fast-mode I2C-bus system (max: 400kHz). (2)-1. Data transfer All commands are preceded by START condition. After the START condition, a slave address is sent. After the AK4588 recognizes START condition, the device interfaced to the bus waits for the slave address to be transmitted over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by STOP condition generated by the master device. (2)-1-1. Data validity The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only be changed when the clock signal on the SCL line is LOW except for the START and the STOP condition. SCL SDA DATA LINE STABLE : DATA VALID CHANGE OF DATA ALLOWED Figure 41. Data transfer (2)-1-2. START and STOP condition HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition. All sequences start from START condition. LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP condition. All sequences end by STOP condition. SCL SDA START CONDITION STOP CONDITION Figure 42. START and STOP conditions MS0287-E-03 2009/05 - 68 - [AK4588] (2)-1-3. ACKNOWLEDGE ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will release the SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the acknowledge clock pulse so that that it remains stable “L” during “H” period of this clock pulse. The AK4588 will generates an acknowledge after each byte has been received. In the read mode, the slave, the AK4588 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await STOP condition. The register of ADC/DAC part can not generate acknowledge for READ operations. Clock pulse for acknowledge SCL FROM MASTER 1 8 9 DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER START CONDITION acknowledge Figure 43. Acknowledge on the I2C-bus (2)-1-4. FIRST BYTE The first byte, which includes seven bits of slave address and one bit of R/W bit, is sent after START condition. If the transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down the SDA line. The most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and CAD0 (device address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 pin and CAD0 pin) set them. The eighth bit (LSB) of the first byte (R/W bit) defines whether a write or read condition is requested by the master. A “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be executed. 0 0 1 0 0 CAD1 CAD0 R/W (Regarding ADC/DAC part, register is set by CAD1/0 pins. “00” is inhibited to set for ADC/DAC.) (Fixed to “00” for DIR/DIT part) Figure 44. The First Byte MS0287-E-03 2009/05 - 69 - [AK4588] (2)-2. WRITE Operations Set R/W bit = “0” for the WRITE operation of the AK4588. After receipt the start condition and the first byte, the AK4588 generates an acknowledge, and awaits the second byte (register address). The second byte consists of the address for control registers of the AK4588. The format is MSB first, and those most significant 3-bits are “Don’t care”. * * * A4 A3 A2 A1 A0 (*: Don’t care) Figure 45. The Second Byte After receipt the second byte, the AK4588 generates an acknowledge, and awaits the third byte. Those data after the second byte contain control data. The format is MSB first, 8bits. D7 D6 D5 D4 D3 D2 D1 D0 Figure 46. Byte structure after the second byte The AK4588 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4588 generates an acknowledge, and awaits the next data again. The master can transmit more than one words instead of terminating the write cycle after the first data word is transferred. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceed 1FH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. S T A R T SDA Register Address(n) Slave Address S T Data(n+x) O P Data(n+1) Data(n) P S A C K A C K A C K A C K Figure 47. WRITE Operation MS0287-E-03 2009/05 - 70 - [AK4588] (2)-3. READ Operations Set R/W bit = “1” for the READ operation of the AK4588. After transmission of a data, the master can read next address’s data by generating the acknowledge instead of terminating the write cycle after the receipt the first data word. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceed 1FH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The AK4588 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ. ADC/DAC part register can not read. (2)-3-1. CURRENT ADDRESS READ The AK4588 has an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would access data from the address “n+1”. After receipt of the slave address with R/W bit set to “1”, the AK4588 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4588 discontinues transmission S T A R T SDA Slave Address Data(n) Data(n+1) S Data(n+x) T O P Data(n+2) P S A C K A C K A C K A C K Figure 48. CURRENT ADDRESS READ (2)-3-2. RANDOM READ Random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues start condition, slave address(R/W=“0”) and then the register address to read. After the register address’s acknowledge, the master immediately reissues start condition and the slave address with the R/W bit set to “1”. Then the AK4588 generates an acknowledge, 1byte data and increments the internal address counter by 1. If the master does not generate an acknowledge but generate the stop condition, the AK4588 discontinues transmission. S T A R T SDA Slave Address S T A R T Word Address(n) S Slave Address Data(n) S Data(n+x) T O P Data(n+1) P S A C K A C K A C K A C K A C K Figure 49. RANDOM READ MS0287-E-03 2009/05 - 71 - [AK4588] SYSTEM DESIGN Figure 50 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. Condition: I2C serial control mode 5 Micro Controller (S/PDIF sources) S/PDIF sources S/PDIF out + C NC 62 RX3 63 PVSS 64 R 65 RX4 67 PVDD 66 RX5 69 TEST2 68 RX6 71 CAD0 70 CAD1 72 I2C 74 BOUT 3 TVDD NC 58 4 DVDD RX0 57 5 DVSS RX1 59 6 XTO 7 XTI VREFH 54 X’tal 8 TEST3 9 MCKO2 VCOM 53 + 0.1u 10u Analog 5V 0.1u 2.2u + RIN 52 AK4588 11 COUT LIN 51 NC 50 12 UOUT ROUT1 49 13 VOUT NC 48 LOUT1 47 14 SDTO2 15 BICK2 NC 46 16 LRCK2 ROUT2 45 17 SDTO1 NC 44 LOUT2 43 18 BICK1 NC 42 Audio DSP (MPEG/AC3) MUTE (Shield) MUTE (Shield) MUTE (Shield) MUTE (Shield) MUTE 40 NC ROUT3 41 (Shield) (Shield) 39 LOUT3 38 NC (Shield) MUTE 36 NC 37 ROUT4 MUTE Micro Controller (Shield) 34 DZF1 35 LOUT4 MUTE 33 DZF2 32 MASTER 31 PDN 29 XTL1 30 XTL0 27 SDTI2 28 SDTI1 26 SDTI3 24 DAUX1 23 CSN 22 SDA 20 CDTO 25 SDTI4 19 LRCK1 21 SCL (Shield) AVSS 56 AVDD 55 10 MCKO1 (Micro Controller) RX7 73 VIN 76 DAUX2 75 MCLK 77 INT1 2 C Audio DSP (MPEG/AC3) TEST1 60 1 (S/PDIF Source) Digital 5V TX1 79 12k 0.1u + TX0 78 INT0 80 10u RX2 61 0.1u Audio DSP (MPEG/AC3) 3.3V to 5V Digital (Shield) 10u + Micro Controller Digital Ground Analog Ground Figure 50. Typical Connection Diagram Notes: - “C” depends on the crystal. - AVSS, DVSS and PVSS must be connected the same analog ground plane. - Digital signals, especially clocks, should be kept away from the R pin in order to avoid an effect to the clock jitter performance. - In case of coaxial input, ground of RCA connector and terminator should be connected to PVSS of the AK4588 with low impedance on PC board. MS0287-E-03 2009/05 - 72 - [AK4588] 1. Grounding and Power Supply Decoupling The AK4588 requires careful attention to power supply and grounding arrangements. AVDD, DVDD, PVDD and TVDD are usually supplied from analog supply in system. Alternatively if AVDD, DVDD, PVDD and TVDD are supplied separately, the power up sequence is not critical. AVSS, DVSS and PVSS of the AK4588 must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4588 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference Inputs The voltage of VREFH sets the analog input/output range. The VREFH pin is normally connected to AVDD with a 0.1μF ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 2.2μF parallel with a 0.1μF ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VREFH and VCOM pins in order to avoid unwanted coupling into the AK4588. 3. Analog Inputs ADC inputs are single-ended and internally biased to VCOM. The input signal range scales with the supply voltage and nominally 0.62 x VREFH Vpp (typ). The ADC output data format is 2’s complement. The DC offset is removed by the internal HPF. The AK4588 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK4588 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. 4. Analog Outputs The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales with the supply voltage and nominally 0.6 x VREFH Vpp. The DAC input data format is 2’s complement. The output voltage is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is VCOM voltage for 000000H(@24bit). The internal analog filters remove most of the noise generated by the delta-sigma modulator of DAC beyond the audio passband. DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV. MS0287-E-03 2009/05 - 73 - [AK4588] PACKAGE z 80-pin LQFP ( Unit : mm ) 14.0±0.2 12.0±0.2 41 61 40 80 21 12.0±0.2 1 20 0.08 0.125+0.10 -0.05 0.50±0.1 0.10 M +0.15 0.10 -0.10 0.50 1.25TYP 1.85MAX 0° ~ 10° 0.20±0.1 1.40±0.2 14.0±0.2 60 ■ Material & Lead finish Package: Epoxy Lead-frame: Copper Lead-finish Soldering (Pb free) plate MS0287-E-03 2009/05 - 74 - [AK4588] MARKING AK4588VQ XXXXXXX 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4588VQ 4) Asahi Kasei Logo REVISION HISTORY Date (YY/MM/DD) 04/01/22 04/03/18 08/05/22 Revision 00 01 02 Reason First Edition Error Correct Spec Change 09/05/25 03 Error Correct Page Contents 12 ADC Digital Filter, Group Delay: 19.1/fs → 16/fs Ambient Temperature range was changed. “-10 ∼ +70°C” → “-40 ∼ +85°C” ■ Handling of Unused Pin The treatment of TEST3 pin was changed. (to DVSS) 9 MS0287-E-03 2009/05 - 75 - [AK4588] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0287-E-03 2009/05 - 76 -