AK4343 Japanese Datasheet

[AK4343]
AK4343
Stereo DAC with HP/RCV/SPK-AMP
AK4343
DAC
1.2W
PLL
PMP(
)
32pin
QFN
1.
•
(tc=50/15μs, fs=32kHz, 44.1kHz, 48kHz)
•
•
•
(+12dB ∼ −115.0dB, 0.5dB Step, Mute)
• Digital ALC (Automatic Level Control)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
•
•
• Programmable EQ
: S/(N+D): 88dB, S/N: 92dB
•
- BTL Output
: [email protected] (AVDD=3.3V)
•
- HP-AMP
: S/(N+D): [email protected], S/N: 90dB
: [email protected] (HVDD=5V), [email protected] (HVDD=3.3V)
ON/OFF
•
- SPK-AMP
: S/(N+D): [email protected], S/N: 90dB
- BTL
: [email protected] (HVDD=5V), [email protected] (HVDD=3.3V)
[email protected] (HVDD=5V)
•
:
-3
(+32dB/+26dB/+20dB or 0dB)
2.
3.
:
(1) PLL
•
(2)
4.
5.
: 11.2896MHz,12MHz,12.288MHz,13.5MHz,24MHz,27MHz (MCKI pin)
1fs (LRCK pin)
32fs or 64fs (BICK pin)
•
: 256fs, 512fs or 1024fs (MCKI pin)
: 32fs/64fs/128fs/256fs
:
• PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
MS0478-J-02
2010/11
-1-
[AK4343]
6.
7.
8.
9.
10.
11.
12.
• EXT Master/Slave Mode:
7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs)
μP
:3
, I2C
(Ver 1.0, 400kHz
)
: MSB First, 2’s complement
• 16bit
, 16bit
, 16-24bit I2S, DSP Mode
Ta = −30 ∼ 85°C (AK4343EN)
−40 ∼ 85°C (AK4343VN)
:
• AVDD, DVDD: 2.6 ∼ 3.6V (typ. 3.3V)
• HVDD: 2.6 ∼ 5.25V (typ. 3.3V/5.0V)
: 32pin QFN (5mm x 5mm, 0.5mm pitch)
AK4642EN
/
■
AVSS
AVDD
VCOM
DVDD
DVSS
I2C
Control
Register
PMMICL
LIN1
CCLK
CDTI
RIN1
PDN
Gain-Amp
LIN2
Line In
CSN
PMMICR
BICK
RIN2
LRCK
SDTI
PMAINR2
LIN3/MIN
RIN3/VCOC
Audio
I/F
PMAINL2
PMAINR3
PMAINL3
PMLO
LOUT/RCP
Stereo Line Out
or
Mono Receiver
ROUT/RCN
PMHPL
PMDAC
D/A
HPL
Headphone
Stereo
DATT Bass ALC
Separation
SMUTE Boost
HPF
PMHPR
HPR
MCKO
PMPLL
MUTET
PLL
MCKI
VCOC
PMSPK
SPP
Speaker
SPN
HVDD
HVSS
Figure 1.
MS0478-J-02
2010/11
-2-
[AK4343]
■
−30 ∼ +85°C
−40 ∼ +85°C
AK4343
AK4343EN
AK4343VN
AKD4343
32pin QFN (0.5mm pitch)
32pin QFN (0.5mm pitch)
HPL
HPR
HVSS
HVDD
SPP
SPN
MCKO
MCKI
23
22
21
20
19
18
17
AK4343
13
LRCK
RIN2 / IN2−
29
Top View
12
TEST2
LIN2 / IN2+
30
11
SDTI
LIN1 / IN1−
31
10
CDTI / SDA
RIN1 / IN1+
32
9
CCLK / SCL
CSN / CAD0
TEST1
8
28
7
MIN / LIN3
PDN
BICK
6
14
I2C
27
5
LOUT / RCP
VCOC / RIN3
DVDD
4
15
AVDD
26
3
ROUT / RCN
AVSS
DVSS
2
16
VCOM
25
1
MUTET
24
■
■ AK4642EN
1.
SPK-Amp
HP-Amp
Receiver-Amp
ADC
ALC
ALC
DSP Format
EXT Master Mode
DAC Group Delay
AK4642EN
[email protected]
[email protected]
No
1 Mono
Yes
128/fs ∼ 1024/fs
4
No
No
22/fs
MS0478-J-02
AK4343
[email protected]
[email protected]
Yes
3 Stereo
No
128/fs ∼ 16384/fs
4 , 8 , 16
Yes
Yes
25/fs
2010/11
-3-
[AK4343]
2.
Pin#
1
5
12
26
27
28
AK4642EN
MPWR
VCOC
SDTO
ROUT
LOUT
MIN
AK4343
TEST1
VCOC/RIN3
TEST2
ROUT/RCN
LOUT/RCP
MIN/LIN3
3.
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Lch Input Volume Control
Lch Digital Volume Control
ALC Mode Control 3
Rch Input Volume Control
Rch Digital Volume Control
Mode Control 3
Mode Control 4
Power Management 3
Digital Filter Select
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
Power Management 4
Mode Control 5
Lineout Mixing Select
HP Mixing Select
SPK Mixing Select
D7
0
0
SPPSN
LOVL
PLL3
PS1
DVTM
0
REF7
AVL7
DVL7
RGAIN1
AVR7
DVR7
0
0
INR1
GN1
F3A7
F3AS
F3B7
0
EQA7
EQA15
EQB7
0
EQC7
EQC15
F1A7
F1AS
F1B7
0
0
0
0
0
0
D6
PMVCM
HPMTN
MINS
LOPS
PLL2
PS0
WTM2
0
REF6
AVL6
DVL6
LMTH1
AVR6
DVR6
LOOP
0
INL1
GN0
F3A6
0
F3B6
0
EQA6
EQA14
EQB6
0
EQC6
EQC14
F1A6
0
F1B6
0
0
0
0
0
0
AK4343
AK4343
D5
PMMIN
PMHPL
DACS
PLL1
FS3
ZTM1
ALC
REF5
AVL5
DVL5
0
AVR5
DVR5
SMUTE
0
HPG
0
F3A5
F3A13
F3B5
F3B13
EQA5
EQA13
EQB5
EQB13
EQC5
EQC13
F1A5
F1A13
F1B5
F1B13
D4
PMSPK
PMHPR
DACL
SPKG1
PLL0
MSBS
ZTM0
ZELMN
REF4
AVL4
DVL4
0
AVR4
DVR4
DVOLC
0
MDIF2
FIL1
F3A4
F3A12
F3B4
F3B12
EQA4
EQA12
EQB4
EQB12
EQC4
EQC12
F1A4
F1A12
F1B4
F1B12
D3
PMLO
M/S
0
SPKG0
BCKO
BCKP
WTM1
LMAT1
REF3
AVL3
DVL3
0
AVR3
DVR3
BST1
AVOLC
MDIF1
EQ
F3A3
F3A11
F3B3
F3B11
EQA3
EQA11
EQB3
EQB11
EQC3
EQC11
F1A3
F1A11
F1B3
F1B11
D2
PMDAC
0
PMMP
MINL
0
FS2
WTM0
LMAT0
REF2
AVL2
DVL2
0
AVR2
DVR2
BST0
HPM
INR0
FIL3
F3A2
F3A10
F3B2
F3B10
EQA2
EQA10
EQB2
EQB10
EQC2
EQC10
F1A2
F1A10
F1B2
F1B10
D1
0
MCKO
0
0
DIF1
FS1
RFST1
RGAIN0
REF1
AVL1
DVL1
VBAT
AVR1
DVR1
DEM1
MINH
INL0
0
F3A1
F3A9
F3B1
F3B9
EQA1
EQA9
EQB1
EQB9
EQC1
EQC9
F1A1
F1A9
F1B1
F1B9
0
DIF0
FS0
RFST0
LMTH0
REF0
AVL0
DVL0
0
AVR0
DVR0
DEM0
DACH
PMADR
0
F3A0
F3A8
F3B0
F3B8
EQA0
EQA8
EQB0
EQB8
EQC0
EQC8
F1A0
F1A8
F1B0
F1B8
PMAINR3
PMAINL3
PMAINR2
PMAINL2
PMMICR
PMMICL
MICR3
0
0
0
MICL3
0
0
0
0
RINR3
RINH3
RINS3
0
LINL3
LINH3
LINS3
AIN3
RINR2
RINH2
RINS2
RCV
LINL2
LINH2
LINS2
MGAIN1
MS0478-J-02
D0
PMADL
PMPLL
MGAIN0
2010/11
-4-
[AK4343]
No.
Pin Name
I/O
Function
1
1
TEST1
-
2
VCOM
O
3
4
AVSS
AVDD
-
VCOC
O
RIN3
I
6
I2C
I
“H”: I2C
7
PDN
I
“H”:
“L”:
5
11
CSN
CAD0
CCLK
SCL
CDTI
SDA
SDTI
I
I
I
I
I
I/O
I
12
TEST2
-
13
14
15
16
17
18
19
20
21
22
23
24
LRCK
BICK
DVDD
DVSS
MCKI
MCKO
SPN
SPP
HVDD
HVSS
HPR
HPL
I/O
I/O
I
O
O
O
O
O
25
MUTET
O
8
9
10
26
27
28
29
30
31
32
PLL
AVSS
Rch
(AIN3 bit = “0” : PLL
3
(AIN3 bit = “1” : PLL
)
)
, “L”: 3
0
(I2C pin = “L” : 3
)
(I2C pin = “H” : I2C
(I2C pin = “L” : 3
(I2C pin = “H” : I2C
(I2C pin = “L” : 3
(I2C pin = “H” : I2C
)
Note 1.
AVDD
)
)
)
)
2
&
&
Rch
Lch
HVSS
O
Rch
(RCV bit = “0” :
O
(RCV bit = “1” : BTL
)
O
Lch
(RCV bit = “0” :
O
(RCV bit = “1” : BTL
)
I
(AIN3 bit = “0” : PLL
)
I
Lch
3
(AIN3 bit = “1” : PLL
)
I
Rch
2
(MDIF2 bit = “0” :
I
Rch
2
(MDIF2 bit = “1 :
”)
I
Lch
2
(MDIF2 bit = “0” :
I
Rch
2
(MDIF2 bit = “1” :
)
I
Lch
1
(MDIF1 bit = “0” :
I
Lch
1
(MDIF1 bit = “1” :
)
I
Rch
1
(MDIF1 bit = “0” :
I
Lch
1
(MDIF1 bit = “1” :
)
(MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3)
ROUT
RCN
LOUT
RCP
MIN
LIN3
RIN2
IN2−
LIN2
IN2+
LIN1
IN1−
RIN1
IN1+
Note 2. I2C pin
, 0.45 x AVDD
DAC
)
)
)
)
)
)
AVSS
MS0478-J-02
2010/11
-5-
[AK4343]
■
Analog
Digital
VCOC/RIN3, SPN, SPP, HPR, HPL, MUTET,
ROUT/RCN, LOUT/RCP, MIN/LIN3, RIN2/IN2−,
LIN2/IN2+, LIN1/IN1−, RIN1/IN1+
MCKO
MCKI
DVSS
(AVSS=DVSS=HVSS=0V; Note 3)
Parameter
Symbol
min
max
Units
Power Supplies:
Analog
AVDD
6.0
V
−0.3
Digital
DVDD
6.0
V
−0.3
Headphone-Amp / Speaker-Amp
HVDD
6.0
V
−0.3
|AVSS – DVSS| (Note 4)
0.3
V
ΔGND1
|AVSS – HVSS| (Note 4)
0.3
V
ΔGND2
Input Current, Any Pin Except Supplies
IIN
mA
±10
Analog Input Voltage (Note 5)
VINA
AVDD+0.3
V
−0.3
Digital Input Voltage (Note 6)
VIND
DVDD+0.3
V
−0.3
Ambient Temperature (powered applied) AK4343EN
Ta
85
−30
°C
AK4343VN
Ta
85
−40
°C
Storage Temperature
Tstg
150
−65
°C
Pd1
750
mW
Maximum Power Dissipation
Ta=85°C (Note 8)
Pd2
1000
mW
(Note 7)
Ta=70°C (Note 9)
Note 3.
Note 4. AVSS DVSS, HVSS
Note 5. I2C, MIN/LIN3, RIN3, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ pins
Note 6. PDN, CSN/CAD0, CCLK/SCL, CDTI/SDA, SDTI, LRCK, BICK, MCKI pins
SDA, SCL pins
(DVDD+0.3)V
Note 7.
100%
Pd1=400mW(max:
), Pd2=550mW(max: HVDD=2.6∼3.6V
)
AK4343
Note 8. HVDD=2.6∼3.6V
Note 9. HVDD=2.6∼5.25V
:
MS0478-J-02
2010/11
-6-
[AK4343]
(AVSS=DVSS=HVSS=0V; Note 3)
Parameter
Power Supplies Analog
(Note 10) Digital
HP / SPK-Amp
Difference
Note 3.
Note 10. AVDD, DVDD, HVDD
OFF
DVDD
HVDD OFF
Symbol
AVDD
DVDD
HVDD
AVDD−DVDD
min
2.6
2.6
2.6
−0.3
typ
3.3
3.3
3.3 / 5.0
0
DVDD
max
3.6
3.6
5.25
+0.3
Units
V
V
V
V
AVDD, HVDD
OFF
AVDD,
:
(Ta=25°C; AVDD=DVDD=HVDD=3.3V; AVSS=DVSS=HVSS=0V; fs=44.1kHz, BICK=64fs;
Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified)
Parameter
min
typ
max
Units
Gain Amplifier: LIN1/RIN1/LIN2/RIN2 pins & LIN3/RIN3 pins (AIN3 bit = “1”);
MDIF1=MDIF2 bits = “0” (Single-ended inputs)
Input
MGAIN1-0 bits = “00”
40
60
80
kΩ
Resistance MGAIN1-0 bits = “01”, “10”or “11”
20
30
40
kΩ
MGAIN1-0 bits = “00”
0
dB
MGAIN1-0 bits = “01”
+20
dB
Gain
MGAIN1-0 bits = “10”
+26
dB
MGAIN1-0 bits = “11”
+32
dB
Gain Amplifier: IN1+/IN1−/IN2+/IN2− pins; MDIF1 = MDIF2 bits = “1” (Full-differential input)
Input Voltage (Note 11)
MGAIN1-0 bits = “01”
0.228
Vpp
MGAIN1-0 bits = “10”
0.114
Vpp
MGAIN1-0 bits = “11”
0.057
Vpp
Note 11.
AC
MGAIN1-0 bits = “00”
IN1+, IN1−, IN2+, IN2− pin
AVDD
Vin = |(IN+) − (IN−)| = 0.069 x AVDD
(max)@MGAIN1-0 bits = “01”, 0.035 x AVDD (max)@MGAIN1-0 bits = “10”, 0.017 x AVDD
(max)@MGAIN1-0 bits = “11”.
Amp
MS0478-J-02
2010/11
-7-
[AK4343]
Parameter
min
typ
max
Units
DAC Characteristics:
Resolution
16
Bits
Stereo Line Output Characteristics: DAC → LOUT/ROUT pins, ALC=OFF, AVOL=0dB, DVOL=0dB, LOVL bit =
“0”, RCV bit = “0”, RL=10kΩ; unless otherwise specified.
Output Voltage (Note 12)
LOVL bit = “0”
1.78
1.98
2.18
Vpp
LOVL bit = “1”
2.25
2.50
2.75
Vpp
78
88
dBFS
S/(N+D) (−3dBFS)
S/N (A-weighted)
82
92
dB
Interchannel Isolation
PMAINL2/R2/L3/R3 bits = “1”
80
100
dB
PMAINL2/R2/L3/R3 bits = “0”
100
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Load Resistance
10
kΩ
Load Capacitance
30
pF
Mono Receiver Output Characteristics: DAC → RCP/RCN pins, ALC=OFF, AVOL=0dB, DVOL=0dB, LOVL bit =
“0”, RCV bit = “1”, RL=32Ω, BTL; unless otherwise specified.
Output Voltage (Note 13)
1.57
1.96
2.35
Vpp
LOVL bit = “0”, −6dBFS, RL=32Ω (Po=15mW)
2.77
Vpp
LOVL bit = “0”, −3dBFS, RL=32Ω (Po=30mW)
1.57
1.96
2.35
Vpp
LOVL bit = “1”, −8dBFS, RL=32Ω (Po=15mW)
2.77
Vpp
LOVL bit = “1”, −5dBFS, RL=32Ω (Po=30mW)
S/(N+D)
40
60
dB
LOVL bit = “0”, −6dBFS, RL=32Ω (Po=15mW)
60
dB
LOVL bit = “0”, −3dBFS, RL=32Ω (Po=30mW)
S/N (A-weighted)
85
95
dBFS
Load Resistance
32
Ω
Load Capacitance
30
pF
Note 12.
AVDD
Vout = 0.6 x AVDD (typ)@LOVL bit = “0”.
Note 13.
AVDD
Vout = 0.59 x AVDD (typ)@LOVL bit = “0”, −6dBFS.
MS0478-J-02
2010/11
-8-
[AK4343]
Parameter
min
typ
max
Units
Headphone-Amp Characteristics: DAC → HPL/HPR pins, ALC=OFF, AVOL=0dB, DVOL=0dB; unless otherwise
specified.
Output Voltage (Note 14)
1.58
1.98
2.38
Vpp
HPG bit = “0”, 0dBFS, HVDD=3.3V, RL=22.8Ω
2.40
3.00
3.60
Vpp
HPG bit = “1”, 0dBFS, HVDD=5V, RL=100Ω
HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW)
1.0
Vrms
HPG bit = “1”, 0dBFS, HVDD=5V, RL=16Ω (Po=70mW)
1.06
Vrms
S/(N+D)
60
70
dBFS
HPG bit = “0”, −3dBFS, HVDD=3.3V, RL=22.8Ω
80
dBFS
HPG bit = “1”, −3dBFS, HVDD=5V, RL=100Ω
HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW)
20
dBFS
HPG bit = “1”, 0dBFS, HVDD=5V, RL=16Ω (Po=70mW)
70
dBFS
(Note 15)
80
90
dB
S/N (A-weighted)
90
dB
(Note 16)
Interchannel Isolation
(Note 15), PMAINL2/R2/L3/R3 bits = “1”
65
75
dB
(Note 15), PMAINL2/R2/L3/R3 bits = “0”
75
dB
(Note 16)
80
dB
(Note 15)
0.1
0.8
dB
Interchannel Gain Mismatch
0.1
0.8
dB
(Note 16)
Load Resistance
16
Ω
30
pF
Figure 2 C1
Load Capacitance
300
pF
Figure 2 C2
Note 14.
AVDD
Vout = 0.6 x AVDD(typ)@HPG bit = “0”, 0.91 x AVDD(typ)@HPG bit = “1”.
Note 15. HPG bit = “0”, HVDD=3.3V, RL=22.8Ω.
Note 16. HPG bit = “1”, HVDD=5V, RL=100Ω.
HP-Amp
HPL/HPR pin
Measurement Point
47μF
6.8Ω
C1
0.22μF
C2
16Ω
10Ω
Figure 2.
MS0478-J-02
2010/11
-9-
[AK4343]
Parameter
min
typ
max
Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, AVOL=0dB, DVOL=0dB, RL=8Ω, BTL,
HVDD=3.3V; unless otherwise specified.
Output Voltage (Note 17)
3.11
SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW)
3.13
3.92
4.71
SPKG1-0 bits = “01”, −0.5dBFS (Po=240mW)
HVDD=5V, SPKG1-0 bits = “11”, 0dBFS (Po=1W)
2.83
Line Input Æ SPP/SPN pins, HVDD=5V,
SPKG1-0 bits = “11”, −1.5dBV Input (Po=1.2W)
S/(N+D)
SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW)
SPKG1-0 bits = “01”, −0.5dBFS (Po=240mW)
HVDD=5V, SPKG1-0 bits = “11”, 0dBFS (Po=1W)
Line Input Æ SPP/SPN pins, HVDD=5V,
SPKG1-0 bits = “11”, −1.5dBV Input (Po=1.2W)
Units
Vpp
Vpp
Vrms
-
3.1
-
Vrms
20
-
60
50
30
-
dB
dB
dB
-
20
-
dB
S/N (A-weighted)
80
90
dB
Load Resistance
8
Ω
Load Capacitance
30
pF
Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, AVOL=0dB, DVOL=0dB, CL=3μF, Rseries=10Ω x
2, BTL, HVDD=5.0V; unless otherwise specified.
Output Voltage SPKG1-0 bits = “10”, 0dBFS
6.75
Vpp
(Note 17) SPKG1-0 bits = “11”, 0dBFS
6.80
8.50
10.20
Vpp
S/(N+D)
SPKG1-0 bits = “10”, 0dBFS
60
dB
(Note 18) SPKG1-0 bits = “11”, 0dBFS
40
50
dB
S/N (A-weighted)
80
90
dB
Load Impedance (Note 19)
50
Ω
Load Capacitance (Note 19)
3
μF
Mono Input: MIN pin (AIN3 bit = “0”; External Input Resistance=20kΩ)
Maximum Input Voltage (Note 20)
1.98
Vpp
Gain (Note 21)
MIN Æ LOUT/ROUT
LOVL bit = “0”
0
+4.5
dB
−4.5
LOVL bit = “1”
+2
dB
MIN Æ HPL/HPR
HPG bit = “0”
dB
−24.5
−20
−15.5
HPG bit = “1”
dB
−16.4
MIN Æ SPP/SPN
ALC bit = “0”, SPKG1-0 bits = “00”
+4.43
+8.93
dB
−0.07
ALC bit = “0”, SPKG1-0 bits = “01”
+6.43
dB
ALC bit = “0”, SPKG1-0 bits = “10”
+10.65
dB
ALC bit = “0”, SPKG1-0 bits = “11”
+12.65
dB
ALC bit = “1”, SPKG1-0 bits = “00”
+6.43
dB
ALC bit = “1”, SPKG1-0 bits = “01”
+8.43
dB
ALC bit = “1”, SPKG1-0 bits = “10”
+12.65
dB
ALC bit = “1”, SPKG1-0 bits = “11”
+14.65
dB
Note 17.
AVDD
Full-differential
Vout = (SPP) − (SPN) = 0.94 x AVDD(typ)@SPKG1-0 bits = “00”, 1.19 x
AVDD(typ)@SPKG1-0 bits = “01”, 2.05 x AVDD(typ)@SPKG1-0 bits = “10”, 2.58 x AVDD(typ)@SPKG1-0
bits = “11”
Note 18.
SPP/SPN pins
Note 19. Figure 58
Load Impedance
(Rseries) 1kHz
Load Capacitance
SPP, SPN pin
10Ω
Note 20.
AVDD
(Rin)
Vin = 0.6 x AVDD x Rin / 20kΩ (typ).
Note 21.
MS0478-J-02
2010/11
- 10 -
[AK4343]
Parameter
min
typ
max
Units
Stereo Input: LIN2/RIN2 pins; LIN3/RIN3 pins (AIN3 bit = “1”)
Maximum Input Voltage (Note 22)
1.98
Vpp
Gain
LIN/RIN Æ LOUT/ROUT
LOVL bit = “0”
0
+4.5
dB
−4.5
LOVL bit = “1”
+2
dB
LIN/RIN Æ HPL/HPR
HPG bit = “0”
0
+4.5
dB
−4.5
HPG bit = “1”
+3.6
dB
LIN/RIN Æ SPP/SPN
ALC bit = “0”, SPKG1-0 bits = “00”
+2.91
dB
−6.09
−1.59
ALC bit = “0”, SPKG1-0 bits = “01”
+0.41
dB
ALC bit = “0”, SPKG1-0 bits = “10”
+4.63
dB
ALC bit = “0”, SPKG1-0 bits = “11”
+6.63
dB
ALC bit = “1”, SPKG1-0 bits = “00”
+0.41
dB
ALC bit = “1”, SPKG1-0 bits = “01”
+2.41
dB
ALC bit = “1”, SPKG1-0 bits = “10”
+6.63
dB
ALC bit = “1”, SPKG1-0 bits = “11”
+8.63
dB
Power Supplies:
Power Up (PDN pin = “H”)
All Circuit Power-up:
AVDD+DVDD (Note 23)
12
18
mA
HVDD: HP-Amp Normal Operation
5
8
mA
No Output (Note 24)
HVDD: SPK-Amp Normal Operation
11
30
mA
No Output (Note 25)
Power Down (PDN pin = “L”) (Note 26)
AVDD+DVDD+HVDD
10
100
μA
Note 22.
AVDD
Vin = 0.6 x AVDD (typ).
Note 23. PLL Master Mode (MCKI=12.288MHz)
PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL =
MCKO = PMMIN = M/S = PMMICL = PMMICR bits = “1”
AVDD=9mA(typ),
DVDD=3mA(typ).
EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”)
: AVDD=8mA(typ), DVDD=2mA(typ).
Note 24. PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = PMMIN bits = “1”,
PMSPK bit = “0”
Note 25. PMDAC = PMLO = PMSPK = PMVCM = PMPLL = PMMIN bits = “1”,
Note 26.
DVDD
PMHPL = PMHPR bits = “0”
DVSS
MS0478-J-02
2010/11
- 11 -
[AK4343]
■
: Ta=25°C; AVDD=DVDD=HVDD=3.3V; AVSS=DVSS=HVSS=0V; fs=44.1kHz, External Slave Mode,
BICK=64fs ; 1kHz, 0dBFS input; Headphone & Speaker = No output
Power Management Bit
01H
PMSPK
PMLO
PMDAC
PMHPL
PMHPR
PMMICL
PMMICR
PMAINL2
PMAINR2
PMAINL3
PMAINR3
All Power-down
DAC Æ Lineout
DAC Æ HP
DAC Æ SPK
LIN2/RIN2 Æ HP
LIN2/RIN2 Æ SPK
MIN Æ RCV
PMMIN
Mode
20H
PMVCM
00H
AVDD
[mA]
0
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
1
0
0
0
0
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5.4
3.7
3.7
1.9
1.9
3.1
Table 1.
DVDD
[mA]
HVDD
[mA]
Total Power
[mW]
0
1.8
1.8
1.8
0
0
0
0
0.2
5
11
5
11
0.2
0
24.4
34.7
54.5
22.8
42.6
10.9
(typ)
(Ta=25°C; AVDD=DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; fs=44.1kHz; DEM=OFF; FIL1=FIL3=EQ=OFF)
Parameter
Symbol
min
typ
max
Units
DAC Digital Filter (LPF):
Passband (Note 27)
PB
0
19.6
kHz
±0.1dB
20.0
kHz
−0.7dB
22.05
kHz
−6.0dB
Stopband
SB
25.2
kHz
Passband Ripple
PR
dB
±0.01
Stopband Attenuation
SA
59
dB
Group Delay (Note 28)
GD
25
1/fs
DAC Digital Filter (LPF) + SCF:
FR
dB
Frequency Response: 0 ∼ 20.0kHz
±1.0
DAC Digital Filter (HPF):
Frequency Response (Note 27) −3.0dB
FR
0.9
Hz
2.7
Hz
−0.5dB
6.0
Hz
−0.1dB
BOOST Filter: (Note 29)
Frequency Response
MIN
FR
20Hz
dB
5.76
100Hz
dB
2.92
1kHz
dB
0.02
MID
FR
20Hz
dB
10.80
100Hz
dB
6.84
1kHz
dB
0.13
MAX 20Hz
FR
dB
16.06
100Hz
dB
10.54
1kHz
dB
0.37
Note 27.
fs (
)
PB=20.0kHz(@−0.7dB) 0.454 x fs
1kHz
Note 28.
16
PMADL=PMADR bits = “0”
DAC
Group Delay
25/fs(typ)
Note 29.
MS0478-J-02
2010/11
- 12 -
[AK4343]
DC
(Ta=25°C; AVDD=DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V)
Parameter
Symbol
High-Level Input Voltage
VIH
Low-Level Input Voltage
VIL
High-Level Output Voltage
VOH
(Iout=−200μA)
Low-Level Output Voltage
VOL
(Except SDA pin: Iout=200μA)
(SDA pin: Iout=3mA)
VOL
Input Leakage Current
Iin
min
70%DVDD
DVDD−0.2
typ
-
max
30%DVDD
-
Units
V
V
V
-
-
0.2
0.4
±10
V
V
μA
(Ta=25°C; AVDD=DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; CL=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
MCKO Output Timing
Frequency
fMCK
0.2352
12.288
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
256fs at fs=32kHz, 29.4kHz
dMCK
33
LRCK Output Timing
Frequency
fs
7.35
48
DSP Mode: Pulse Width High
tLRCKH
tBCK
Except DSP Mode: Duty Cycle
Duty
50
BICK Output Timing
Period
BCKO bit = “0”
tBCK
1/(32fs)
BCKO bit = “1”
tBCK
1/(64fs)
Duty Cycle
dBCK
50
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
MCKO Output Timing
Frequency
fMCK
0.2352
12.288
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
256fs at fs=32kHz, 29.4kHz
dMCK
33
LRCK Input Timing
Frequency
fs
7.35
48
DSP Mode: Pulse Width High
tLRCKH
tBCK−60
1/fs − tBCK
Except DSP Mode: Duty Cycle
Duty
45
55
BICK Input Timing
Period
tBCK
1/(64fs)
1/(32fs)
Pulse Width Low
tBCKL
0.4 x tBCK
Pulse Width High
tBCKH
0.4 x tBCK
-
MS0478-J-02
Units
MHz
ns
ns
MHz
%
%
kHz
ns
%
ns
ns
%
MHz
ns
ns
MHz
%
%
kHz
ns
%
ns
ns
ns
2010/11
- 13 -
[AK4343]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
PLL3-0 bits = “0011”
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Slave Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Input Timing
Frequency
256fs
fs
512fs
fs
1024fs
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Master Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Output Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Output Timing
Period
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
MS0478-J-02
min
typ
max
Units
7.35
tBCK−60
45
-
48
1/fs − tBCK
55
kHz
ns
%
1/(64fs)
130
130
-
1/(32fs)
-
ns
ns
ns
7.35
tBCK−60
45
-
48
1/fs − tBCK
55
kHz
ns
%
0.4 x tBCK
0.4 x tBCK
1/(32fs)
1/(64fs)
-
-
ns
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
7.35
7.35
tBCK−60
45
-
48
26
13
1/fs − tBCK
55
kHz
kHz
kHz
ns
%
312.5
130
130
-
-
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
-
tBCK
50
48
-
kHz
ns
%
-
1/(32fs)
1/(64fs)
50
-
ns
ns
%
2010/11
- 14 -
[AK4343]
Parameter
Symbol
Audio Interface Timing (DSP Mode)
Master Mode
tDBF
LRCK “↑” to BICK “↑” (Note 30)
tDBF
LRCK “↑” to BICK “↓” (Note 31)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
tLRB
LRCK “↑” to BICK “↑” (Note 30)
tLRB
LRCK “↑” to BICK “↓” (Note 31)
tBLR
BICK “↑” to LRCK “↑” (Note 30)
tBLR
BICK “↓” to LRCK “↑” (Note 31)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
2
Audio Interface Timing (Right/Left justified & I S)
Master Mode
tMBLR
BICK “↓” to LRCK Edge (Note 32)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
tLRB
LRCK Edge to BICK “↑” (Note 32)
tBLR
BICK “↑” to LRCK Edge (Note 32)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Note 30. MSBS, BCKP bits = “00” or “11”.
Note 31. MSBS, BCKP bits = “01” or “10”.
Note 32.
LRCK
BICK “↑”
min
typ
max
Units
0.5 x tBCK − 40
0.5 x tBCK − 40
50
50
0.5 x tBCK
0.5 x tBCK
-
0.5 x tBCK + 40
0.5 x tBCK + 40
-
ns
ns
ns
ns
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
50
50
-
-
ns
ns
ns
ns
ns
ns
−40
50
50
-
40
-
ns
ns
ns
50
50
50
50
-
-
ns
ns
ns
ns
MS0478-J-02
2010/11
- 15 -
[AK4343]
Parameter
Control Interface Timing (3-wire Serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 34)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width (Note 35)
Note 33. I2C-bus NXP B.V.
Note 34.
300ns (SCL
)
Note 35. AK4343 PDN pin = “L”
Symbol
min
typ
max
Units
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
-
-
ns
ns
ns
ns
ns
ns
ns
ns
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
tSP
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
tPD
150
-
-
ns
MS0478-J-02
2010/11
- 16 -
[AK4343]
■
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
50%DVDD
LRCK
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
1/fMCK
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 3. Clock Timing (PLL/EXT Master mode)
Note 36. MCKO is not available at EXT Master mode.
tLRCKH
LRCK
50%DVDD
tBCK
tDBF
dBCK
BICK
(BCKP = "0")
50%DVDD
BICK
(BCKP = "1")
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 4. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “0”)
MS0478-J-02
2010/11
- 17 -
[AK4343]
tLRCKH
LRCK
50%DVDD
tBCK
tDBF
dBCK
BICK
(BCKP = "1")
50%DVDD
BICK
(BCKP = "0")
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 5. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “1”)
50%DVDD
LRCK
tBLR
tBCKL
BICK
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 6. Audio Interface Timing (PLL/EXT Master mode, Except DSP mode)
MS0478-J-02
2010/11
- 18 -
[AK4343]
1/fs
VIH
LRCK
VIL
tLRCKH
tBLR
tBCK
VIH
BICK
(BCKP = "0")
VIL
tBCKH
tBCKL
VIH
BICK
(BCKP = "1")
VIL
Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “0”)
1/fs
VIH
LRCK
VIL
tLRCKH
tBLR
tBCK
VIH
BICK
(BCKP = "1")
VIL
tBCKH
tBCKL
VIH
BICK
(BCKP = "0")
VIL
Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “1”)
MS0478-J-02
2010/11
- 19 -
[AK4343]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
= tLRCKL x fs x 100
VIH
BICK
VIL
tBCKH
tBCKL
fMCK
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 9. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin, Except DSP mode)
tLRCKH
VIH
LRCK
VIL
tLRB
VIH
BICK
VIL
(BCKP = "0")
VIH
BICK
(BCKP = "1")
VIL
tSDS
tSDH
VIH
SDTI
MSB
VIL
Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = “0”)
MS0478-J-02
2010/11
- 20 -
[AK4343]
tLRCKH
VIH
LRCK
VIL
tLRB
VIH
BICK
VIL
(BCKP = "1")
VIH
BICK
(BCKP = "0")
VIL
tSDS
tSDH
VIH
SDTI
MSB
VIL
Figure 11. Audio Interface Timing (PLL Slave mode, DSP mode, MSBS = “1”)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 12. Clock Timing (EXT Slave mode)
MS0478-J-02
2010/11
- 21 -
[AK4343]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDS
tSDH
VIH
SDTI
VIL
Figure 13. Audio Interface Timing (PLL/EXT Slave mode, Except DSP mode)
VIH
CSN
VIL
tCSS
tCCKL
tCCKH
VIH
CCLK
VIL
tCCK
tCDH
tCDS
VIH
CDTI
C1
C0
R/W
VIL
Figure 14. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
D2
D1
D0
VIL
Figure 15. WRITE Data Input Timing
MS0478-J-02
2010/11
- 22 -
[AK4343]
VIH
SDA
VIL
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
Figure 16. I2C
tPD
PDN
VIL
Figure 17. Power Down & Reset Timing
MS0478-J-02
2010/11
- 23 -
[AK4343]
■
I/F
4
(Table 2 and Table 3)
Mode
PLL Master Mode (Note 37)
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: LRCK or BICK pin)
EXT Slave Mode
EXT Master Mode
Note 37. PLL Master Mode
PMPLL bit
1
M/S bit
1
PLL3-0 bits
See Table 5
Figure
Figure 18
1
0
See Table 5
Figure 19
1
0
See Table 5
0
0
x
0
1
x
M/S bit = “1”, PMPLL bit = “0”, MCKO bit = “1”
Figure 20
Figure 21
Figure 22
Figure 23
MCKO pin
Table 2. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
0
PLL Master Mode
1
0
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
1
MCKO pin
“L”
PS1-0 bits
MCKI pin
PLL3-0 bits
“L”
PS1-0 bits
PLL3-0 bits
GND
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
0
“L”
EXT Slave Mode
0
“L”
EXT Master Mode
0
“L”
FS1-0 bits
FS1-0 bits
BICK pin
Output
(BCKO bit
)
LRCK pin
Input
(≥ 32fs)
Input
(1fs)
Input
(PLL3-0
bits
)
Input
(≥ 32fs)
Output
(BCKO bit
)
Output
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
Table 3. Clock pins state in Clock Mode
■
M/S bit
(PDN pin = “L”)
AK4343
M/S bit
“1”
“0”
“1”
M/S bit “1”
AK4343 LRCK, BICK pin
AK4343
LRCK, BICK pin
100kΩ
M/S bit
Mode
0
Slave Mode
(default)
1
Master Mode
Table 4. Select Master/Slave Mode
MS0478-J-02
2010/11
- 24 -
[AK4343]
■ PLL
(AIN3 bit = “0”, PMPLL bit = “1”)
PMPLL bit = “1”
PLL
PLL FS3-0 bits, PLL3-0 bits
PMPLL bit “0” Æ “1”
Table 5
AIN3 bit = “1”
PLL
1) PLL Mode
PLL
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
0
1
2
0
0
0
0
0
0
0
0
1
0
1
0
LRCK pin
N/A
BICK pin
1fs
32fs
3
0
0
1
1
BICK pin
64fs
4
5
6
7
12
13
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Others
Others
VCOC pin
R,C
R[Ω] C[F]
6.8k
220n
10k
4.7n
10k
10n
10k
4.7n
10k
10n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
10n
10k
10n
MCKI pin
11.2896MHz
MCKI pin
12.288MHz
MCKI pin
12MHz
MCKI pin
24MHz
MCKI pin
13.5MHz
MCKI pin
27MHz
N/A
Table 5. Setting of PLL Mode (*fs: Sampling Frequency)
PLL
(max)
160ms
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
40ms
40ms
(default)
2) PLL Mode
MCKI
Table 6
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
0
0
8kHz
(default)
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
4
0
1
0
0
7.35kHz
5
0
1
0
1
11.025kHz
6
0
1
1
0
14.7kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
14
1
1
1
0
29.4kHz
15
1
1
1
1
44.1kHz
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = MCKI pin)
LRCK or BICK
(LRCK or BICK
)
FS3, FS1-0 bits
(Table 7)
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency Range
0
Don’t care
0
0
0
(default)
7.35kHz ≤ fs ≤ 8kHz
0
Don’t
care
1
1
0
8kHz < fs ≤ 12kHz
0
Don’t care
0
2
1
12kHz < fs ≤ 16kHz
0
Don’t care
1
3
1
16kHz < fs ≤ 24kHz
1
Don’t care
0
6
1
24kHz < fs ≤ 32kHz
1
Don’t care
1
7
1
32kHz < fs ≤ 48kHz
Others
Others
N/A
Table 7. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin)
MS0478-J-02
2010/11
- 25 -
[AK4343]
■ PLL
1) PLL Master Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “1”)
bit = “1”
MCKO pin
PLL
PMPLL bit = “0” Æ “1”
MCKO pin
“L”
(Table 8)
BICK
LRCK
PLL
BICK
“L”
LRCK “L”
MCKO bit = “0”
1
MCKO
LRCK, BICK
1fs
PMPLL bit = “0”
LRCK
BICK,
“L”
MCKO pin
BICK pin
LRCK pin
MCKO bit = “0”
MCKO bit = “1”
“L” Output
“L” Output
“L” Output
PMPLL bit “0” Æ “1”
“L”
Output
PLL Unlock (
)
“L” Output
1fs Output
See Table 10
See Table 11
PLL Lock
Table 8. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PLL State
2) PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”)
PMPLL bit = “0” Æ “1”
PLL
PLL
DACH, DACS bits “0”
PLL
MCKO pin
DAC
MCKO
Table 10
DACL,
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
PMPLL bit “0” Æ “1”
“L” Output
PLL Unlock (
)
“L” Output
Output
PLL Lock
Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PLL State
MS0478-J-02
2010/11
- 26 -
[AK4343]
■ PLL Master Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “1”)
11.2896MHz, 12MHz , 12.288MHz, 13.5MHz, 24MHz or 27MHz
MCKO, BICK, LRCK
(MCKO)
MCKO bit ON/OFF
BICK
BCKO bit
(Table 11)
PLL
PS1-0 bits (Table 10)
32fs or 64fs
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
DSP or μP
AK4343
MCKI
256fs/128fs/64fs/32fs
MCKO
32fs, 64fs
BICK
1fs
LRCK
MCLK
BCLK
LRCK
SDTO
SDTI
Figure 18. PLL Master Mode
Mode
PS1 bit
0
0
1
0
2
1
3
1
Table 10. MCKO
PS0 bit
0
1
0
1
(PLL
MCKO pin
256fs
(default)
128fs
64fs
32fs
, MCKO bit = “1”)
BCKO bit
BICK
0
32fs
(default)
1
64fs
Table 11. BICK Output Frequency at Master Mode
MS0478-J-02
2010/11
- 27 -
[AK4343]
■ PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”)
MCKI, BICK or LRCK pin
PLL
PLL
a) PLL
: MCKI pin
MCKO
BICK, LRCK
bit
AK4343
(Table 5)
PLL3-0 bits
MCKO LRCK
(MCKO pin) PS1-0 bits (Table 10)
FS3-0 bits
ON/OFF
MCKO
(Table 6)
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
AK4343
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
Figure 19. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
MS0478-J-02
2010/11
- 28 -
[AK4343]
b) PLL
FS3-0 bits
: BICK or LRCK pin
7.35kHz ∼ 48kHz
(Table 7)
AK4343
DSP or μP
MCKO
MCKI
BICK
LRCK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDTI
Figure 20. PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
AK4343
DSP or μP
MCKO
MCKI
BICK
LRCK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
Figure 21 PLL Slave Mode 2 (PLL Reference Clock: LRCK pin)
DAC
(PMDAC bit = “1”)
(MCKI, BICK, LRCK)
(PMDAC bit = “0”)
MS0478-J-02
2010/11
- 29 -
[AK4343]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PMPLL bit
DAC
“0”
(EXT Mode)
MCKI pin
PLL
DAC
I/F
MCKI (256fs, 512fs or 1024fs), BICK (≥32fs), LRCK(fs)
MCKI LRCK
MCKI
FS1-0 bit
(Table 12)
Mode
0
1
2
3
MCKI Input
Sampling Frequency
Frequency
Range
Don’t care
0
0
256fs
7.35kHz ∼ 48kHz
Don’t care
0
1
1024fs
7.35kHz ∼ 13kHz
Don’t care
1
0
256fs
7.35kHz ∼ 48kHz
Don’t care
1
1
512fs
7.35kHz ∼ 26kHz
Table 12. EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
MCKI
FS3-2 bits
FS1 bit
FS0 bit
DAC
S/N
S/N
Table 13 DAC
(default)
MCKI
LOUT/ROUT pin
S/N
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
93dB
1024fs
93dB
Table 13. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI
DAC
(PMDAC bit = “1”)
(MCKI, BICK, LRCK)
(PMDAC bit = “0”
AK4343
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BICK
LRCK
MCLK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
Figure 22. EXT Slave Mode
MS0478-J-02
2010/11
- 30 -
[AK4343]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
PMPLL bit = “0”
M/S bit = “1”
MCKI pin
PLL
(256fs, 512fs or 1024fs)
MCKI
Mode
0
1
2
3
(EXT Master Mode)
MCKI
(Table 14)
DAC
FS1-0 bits
MCKI Input
Sampling Frequency
Frequency
Range
Don’t care
0
0
256fs
7.35kHz ∼ 48kHz
Don’t care
0
1
1024fs
7.35kHz ∼ 13kHz
Don’t care
1
0
256fs
7.35kHz ∼ 48kHz
Don’t care
1
1
512fs
7.35kHz ∼ 26kHz
Table 14. EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
MCKI
FS3-2 bits
FS1 bit
FS0 bit
DAC
S/N
S/N
Table 15 DAC
(default)
MCKI
LOUT/ROUT pin
S/N
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
93dB
1024fs
93dB
Table 15. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI
DAC
(PMDAC bit = “1”)
MCKI
MCKI
MCKI
(PMDAC bit = “0”)
AK4343
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BICK
LRCK
MCLK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDTI
Figure 23. EXT Master Mode
BCKO bit
BICK
0
32fs
(default)
1
64fs
Table 16. BICK Output Frequency at Master Mode
MS0478-J-02
2010/11
- 31 -
[AK4343]
■
PDN pin
“L”
AK4343
PMDAC bit = “0” Æ “1”
[email protected]=44.1kHz
DAC
DAC
DAC
2’s
([email protected]=44.1kHz)
“0”
DAC
■
4
(Table 17)
LRCK
Mode
0
1
2
3
Mode 1, 2, 3
Mode 0 (DSP
(Table 18)
DIF1
0
DIF0
DIF1 bit
0
0
1
1
SDTI
)
BICK
DIF1-0 bits
MSB
BICK
DIF0 bit
SDTI (DAC)
BICK
0
DSP Mode
≥ 32fs
1
≥ 32fs
0
≥ 32fs
2
1
IS
≥ 32fs
Table 17. Audio Interface Format
BCKP
0
0
0
1
1
0
1
1
0
Figure
Table 18
Figure 28
Figure 29
Figure 30
(default)
“↑”
BCKP, MSBS bits
MSBS
2’s
I/F
Audio Interface Format
LRCK “↑”
1
BICK “↑”
BICK “↓”
SDTI MSB
LRCK “↑”
1
BICK “↓”
BICK “↑”
SDTI MSB
LRCK “↑”
2
BICK “↓” SDTI MSB
LRCK “↑”
2
BICK “↑”
SDTI
MSB
Figure
Figure 24
(default)
Figure 25
Figure 26
Figure 27
Table 18. Audio Interface Format in Mode 0
MS0478-J-02
2010/11
- 32 -
[AK4343]
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTI(i)
0
15
Rch
15 14
0
1
8
7
6
14
2
15
5
16
4
3
17
2
18
1
0
30
31
15 14
32
33
8
7
46
34
6
47
5
4
3
48
49
50
26
27
26
2
1
0
62
63
30
31
BICK(64fs)
Rch
Lch
SDTI(i)
15 14
2
1
0
15 14
2
1
0
1/fs
15:MSB, 0:LSB
Figure 24. Mode 0 Timing (BCKP = “0”, MSBS = “0”)
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
29
0
BICK(32fs)
Lch
SDTI(i)
0
15
Rch
15 14
0
1
8
7
6
14
2
15
5
16
4
17
3
2
18
1
0
30
31
15 14
32
33
8
7
46
34
6
47
5
4
3
48
49
50
26
27
26
2
1
0
62
63
30
31
BICK(64fs)
Rch
Lch
SDTI(i)
15 14
2
1
0
15 14
2
1
0
1/fs
15:MSB, 0:LSB
Figure 25. Mode 0 Timing (BCKP = “1”, MSBS = “0”)
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
29
0
BICK(32fs)
Lch
SDTI(i)
0
15
Rch
15 14
0
1
8
7
14
2
6
15
5
16
4
17
3
2
18
1
30
0
31
15 14
32
33
34
8
7
46
6
47
5
48
4
49
3
50
2
1
62
0
63
BICK(64fs)
Lch
SDTI(i)
15 14
Rch
2
1
0
15 14
2
1
0
1/fs
15:MSB, 0:LSB
Figure 26. Mode 0 Timing (BCKP = “0”, MSBS = “1”)
MS0478-J-02
2010/11
- 33 -
[AK4343]
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTI(i)
0
15
Rch
15 14
0
1
8
7
14
2
6
15
5
16
4
17
3
2
18
1
30
0
31
15 14
32
33
8
34
7
46
6
47
5
4
48
49
3
2
50
1
62
0
63
BICK(64fs)
Lch
SDTI(i)
Rch
15 14
2
1
0
15 14
2
1
0
1/fs
15:MSB, 0:LSB
Figure 27. Mode 0 Timing (BCKP = “1”, MSBS = “1”)
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTI(i)
15 14 13
0 1 2 3
7 6 5 4 3 2 1 0 15 14 13
15 16 17 18
31 0 1 2 3
7 6 5 4 3 2 1 0 15
15 16 17 18
31 0 1
BICK(64fs)
SDTI(i)
15 14
Don't Care
1 0
Don't Care
15 14
2 1 0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 28. Mode 1 Timing
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTI(i)
15 14 13
0 1 2 3
7 6 5 4 3 2 1 0 15 14 13
15 16 17 18
31 0 1 2 3
7 6 5 4 3 2 1 0 15
15 16 17 18
31 0 1
BICK(64fs)
SDTI(i)
15 14 13
1 0
Don't Care
15 14 13
1 0
Don't Care
15
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 29. Mode 2 Timing
MS0478-J-02
2010/11
- 34 -
[AK4343]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTI(i)
0 15 14
0 1 2 3
8 7 6 5 4 3 2 1 0 15 14
15 16 17 18
8 7 6 5 4 3 2 1 0
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTI(i)
15 14
2 1 0
Don't Care
15 14
2 1 0
Don't Care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 30. Mode 3 Timing
■
HPF
AK4343 DC
44.1kHz)
HPF
(fs)
HPF
0.9Hz (@fs=
■
AK4343
bits
31)
MDIF1, MDIF2 bits = “0”
INL1-0, INR1-0
LIN1/LIN2/LIN3, RIN1/RIN2/RIN3
MDIF1, MDIF2 bits = “1”
LIN1, RIN1, LIN2, RIN2 pins
IN1−, IN1+, IN2+, IN2− pins
(Figure
Table 20 “X”
MDIF1 bit
0
0
0
0
0
0
0
0
0
0
0
1
1
1
Others
MDIF2 bit
0
0
0
0
0
0
0
0
0
1
1
0
0
1
INL1 bit
0
0
0
0
0
0
1
1
1
0
1
0
0
0
INL0 bit
0
0
0
1
1
1
0
0
0
0
0
0
0
0
INR1 bit
0
0
1
0
0
1
0
0
1
0
0
0
1
0
INR0 bit
0
1
0
0
1
0
0
1
0
0
0
1
0
0
Lch
LIN1
LIN1
LIN1
LIN2
LIN2
LIN2
LIN3
LIN3
LIN3
LIN1
LIN3
IN1+/−
IN1+/−
IN1+/−
N/A
Rch
RIN1
RIN2
RIN3
RIN1
RIN2
RIN3
RIN1
RIN2
RIN3
IN2+/−
IN2+/−
RIN2
RIN3
IN2+/−
N/A
(default)
Table 19. Input Path Select
MS0478-J-02
2010/11
- 35 -
[AK4343]
Register
Pin
RIN2
LIN1
MIN
VCOC
RIN1
LIN2
AIN3 bit
MDIF1 bit MDIF2 bit
LIN3
RIN3
IN1+
IN2+
IN2−
IN1−
0
0
0
O
O
O
O
O
0
0
1
O
X
O
O
O
0
1
0
O
O
X
O
O
0
1
1
O
O
O
O
O
1
0
0
O
O
O
O
O
O
1
0
1
O
X
O
O
O
X
1
1
0
O
O
X
O
X
O
1
1
1
O
O
O
O
X
X
Table 20. Handling of Line Input Pins (“-“: N/A; “X”: Signal should not be input.)
AK4343
INL1-0 bits
LIN1/IN1− pin
RIN1/IN1+ pin
Gain-Amp
MDIF1 bit
INR1-0 bits
RIN2/IN2− pin
LIN2/IN2+ pin
Gain-Amp
MDIF2 bit
These blocks are not
available at PLL mode.
MIN/LIN3 pin
MICL3 bit
MICR3 bit
PMAINL3 bit
PMAINR3 bit
PMAINR2 bit
PMAINL2 bit
VCOC/RIN3 pin
Lineout, Receiver-Amp, HP-Amp, SPK-Amp
Figure 31.
IN1+/− pins
MDIF1 bit
1
0
LIN2/RIN2 pins
MDIF2 bit
0
0
2
INL1 bit
INL0 bit
INR1 bit
INR0 bit
0
0
0
1
0
1
0
1
Table 21.Line In Path Select Example
MS0478-J-02
Lch
IN1+/−
LIN2
Rch
RIN2
RIN2
2010/11
- 36 -
[AK4343]
■
AK4343
MGAIN1-0 bits = “00”
MGAIN1 bit
0
0
1
1
MGAIN1-0 bit
typ. 60kΩ MGAIN1-0 bits = “01”, “10”, “11”
MGAIN0 bit
0
1
0
1
Table 22.
Input Gain
0dB
+20dB
+26dB
+32dB
(Table 22)
typ. 30kΩ
(default)
■ Digital EQ/HPF/LPF
AK4343
ALC
(Figure 32
) FIL1, FIL3, EQ
“ALC
”
ALC
ATT
FIL3
F1AS, F3AS bits
OFF(MUTE)
IIR
FIL3
GN1-0 bits(Table 23
FIL1, FIL3
1
EQ, FIL1
“0”
)
EQ
HPF
F1AS, F3AS bits
0dB
(FIL3
FIL1
F1A13-0
F1B13-0
F1AS
FIL3
F3A13-0
F3B13-0
F3AS
0dB ∼ -10dB
MUTE
(FIL3
FIL3, EQ, FIL1 bits
MUTE)
EQ
)
“1”
EQA15-0
EQB13-0
EQC15-0
+12dB ∼ 0dB
Gain
LPF
“0”
ALC
GN1-0
+24/+12/0dB
Figure 32. Digital EQ/HPF/LPF
GN1
GN0
0
0
0
1
1
x
Table 23. Gain
Gain
0dB
(default)
+12dB
+24dB
(x: Don’t care)
MS0478-J-02
2010/11
- 37 -
[AK4343]
[
]
1) FIL1, FIL3
fs:
fc:
f:
K:
HPF
[dB] (FIL1
0dB
)
FIL1: F1AS bit = “0”, F1A[13:0] bits =A, F1B[13:0] bits =B
FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A = 10K/20 x
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
1 − z −1
H(z) = A
2) FIL1, FIL3
fs:
fc:
f:
K:
2 − 2cos (2πf/fs)
M(f) = A
1 + Bz −1
θ(f) = tan −1
1 + B2 + 2Bcos (2πf/fs)
(B+1)sin (2πf/fs)
1 - B + (B−1)cos (2πf/fs)
LPF
[dB] (FIL1
0dB
)
FIL1: F1AS bit = “1”, F1A[13:0] bits =A, F1B[13:0] bits =B
FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1
A = 10K/20 x
,
1 + 1 / tan (πfc/fs)
1 + z −1
H(z) = A
1 + Bz −1
B=
1 + 1 / tan (πfc/fs)
2 + 2cos (2πf/fs)
M(f) = A
1 + B2 + 2Bcos (2πf/fs)
MS0478-J-02
θ(f) = tan −1
(B−1)sin (2πf/fs)
1 + B + (B+1)cos (2πf/fs)
2010/11
- 38 -
[AK4343]
3) EQ
fs:
fc1:
fc2:
f:
K:
[dB] (
+12dB
)
EQA[15:0] bits =A, EQB[13:0] bits =B, EQC[15:0] bits =C
(MSB=EQA15, EQB13, EQC15; LSB=EQA0, EQB0, EQC0)
A = 10K/20 x
1 − 1 / tan (πfc1/fs)
1 + 1 / tan (πfc2/fs)
,
B=
,
1 + 1 / tan (πfc1/fs)
A + Cz −1
H(z) =
1 + 1 / tan (πfc1/fs)
A2 + C2 + 2ACcos (2πf/fs)
1 + B2 + 2Bcos (2πf/fs)
[
2
(2
) x 213
X=(
X
2
1 − 1 / tan (πfc2/fs)
1 + 1 / tan (πfc1/fs)
(AB−C)sin (2πf/fs)
θ(f) = tan −1
M(f) =
1 + Bz −1
C =10K/20 x
A + BC + (AB+C)cos (2πf/fs)
)
(2
]
)
MSB
[
]
1) FIL1
: fs=44.1kHz, fc=100Hz HPF
F1AS bit = “0”
F1A[13:0] bits = 01 1111 1100 0110
F1B[13:0] bits = 10 0000 0111 0100
2) EQ
: fs=44.1kHz, fc1=300Hz, fc2=3000Hz, Gain=+8dB
Gain[dB]
+8dB
fc1
fc2
Frequency
EQA[15:0] bits = 0000 1001 0110 1110
EQB[13:0] bits = 10 0001 0101 1001
EQC[15:0] bits = 1111 1001 1110 1111
MS0478-J-02
2010/11
- 39 -
[AK4343]
■ ALC
ALC bit = “1”
1.
ALC
ALC
ALC
ALC
Lch, Rch
LMAT1-0 bits
ZELMN bit = “0”(
(Table 25)
)
ZTM1-0 bits
ALC
AVL, AVR (L/R
(Table 24)
)
ALC
AVL, AVR
)
ALC
LMAT1-0 bits
AVL, AVR
1 step
L/R
(Table 26)
ZELMN bit = “1”(
ALC bit
LMTH1
0
0
1
1
“0”
0
1
LMAT1
0
0
1
1
x
Table 25. ALC
ZTM1
ZTM0
0
0
1
1
0
1
0
1
: 1/fs)
ALC
LMTH0 ALC
0
ALC Output ≥ −2.5dBFS
1
ALC Output ≥ −4.1dBFS
0
ALC Output ≥ −6.0dBFS
1
ALC Output ≥ −8.5dBFS
Table 24. ALC
ZELMN
(
ALC
−2.5dBFS > ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
LMAT0 ALC
0
1 step
1
2 step
0
4 step
1
8 step
x
1step
ATT
128/fs
256/fs
512/fs
1024/fs
Table 26. ALC
8kHz
16ms
32ms
64ms
128ms
MS0478-J-02
(default)
ATT
0.375dB
(default)
0.750dB
1.500dB
3.000dB
0.375dB
(x: Don’t care)
16kHz
8ms
16ms
32ms
64ms
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
(default)
2010/11
- 40 -
[AK4343]
2.
ALC
ALC
WTM2-0 bits
(Table 27)
(Table 24)
ALC
(Table 29)
ZTM1-0 bits
(Table 26)
RGAIN1-0 bits
(Table 28)
AVL, AVR (L/R
)
WTM2-0 bits
WTM2-0 bits
ZTM1-0 bits
ALC
bits
AVL, AVR
30H
AVL, AVR
32H
(REF7-0 bits )
AVL, AVR
RGAIN1-0 bits = “01”(2 steps)
0.75dB(0.375dB x 2)
ALC
ALC
ZTM1-0
ALC
ALC
AVL, AVR
ALC
(
) ≤ Output Signal < (
(
) > Output Signal
ALC
)
ALC
(
RFST1-0 bits
WTM2
WTM1
WTM0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RGAIN1
0
0
1
1
128/fs
256/fs
512/fs
1024/fs
2048/fs
4096/fs
8192/fs
16384/fs
Table 27. ALC
RGAIN0
0
1
0
1
Table 28. ALC
)
(Table 30)
ALC
8kHz
16ms
32ms
64ms
128ms
256ms
512ms
1024ms
2048ms
16kHz
8ms
16ms
32ms
64ms
128ms
256ms
512ms
1024ms
GAIN STEP
1 step
0.375dB
2 step
0.750dB
3 step
1.125dB
4 step
1.500dB
MS0478-J-02
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
46.4ms
92.9ms
185.8ms
371.5ms
(default)
(default)
2010/11
- 41 -
[AK4343]
REF7-0
GAIN(dB)
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
E2H
+30.375
E1H
+30.0
E0H
+29.625
:
:
03H
−53.25
02H
−53.625
01H
−54.0
00H
MUTE
Table 29. ALC
RFST1 bit
0
0
1
1
RFST0 bit
0
1
0
1
Step
0.375dB
4
8
16
N/A
(default)
(default)
Table 30.
MS0478-J-02
2010/11
- 42 -
[AK4343]
3.
ALC
Table 31
ALC
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same or
longer data as ZTM1-0 bits.
Maximum gain at recovery operation
WTM2-0
REF7-0
AVL7-0,
AVR7-0
LMAT1-0
RGAIN1-0
RFST1-0
ALC
ALC
bit = “0”
Gain of AVOL
Limiter ATT step
Recovery GAIN step
Fast Recovery Speed
ALC enable
Data
01
0
01
fs=8kHz
Operation
−4.1dBFS
Enable
32ms
Data
01
0
11
fs=44.1kHz
Operation
−4.1dBFS
Enable
23.2ms
001
32ms
011
23.2ms
E1H
+30dB
E1H
+30dB
E1H
+30dB
E1H
+30dB
1 step
1 step
4 times
Enable
00
00
00
1
1 step
1 step
4 times
Enable
00
00
00
1
Table 31. ALC
ALC
(ALC
PMDAC bit = “0”)
LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0
Example:
Limiter = Zero crossing Enable
Recovery Cycle = [email protected]
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
Manual Mode
ALC bit = “1”
WR (ZTM1-0, WTM2-0, RFST1-0)
(1) Addr=06H, Data=14H
WR (REF7-0)
(2) Addr=08H, Data=E1H
WR (AVL/R7-0) * The value of AVOL should be
(3) Addr=09H&0CH, Data=E1H
the same or smaller than REF’s
WR (RGAIN1, LMTH1)
(4) Addr=0BH, Data=00H
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”)
(5) Addr=07H, Data=01H
ALC Operation
WR : Write
Figure 33. ALC
MS0478-J-02
2010/11
- 43 -
[AK4343]
■ ALC
ALC bit = “0”
1.
2.
ALC
L/R
ALC
(
)
ALC
ALC
(ZTM1-0, LMTH1-0 bits
ALC
AVL7-0, AVR7-0 bits
)
(Table 32)
ZTM1-0 bits
AVL7-0 = AVR7-0 bits = 91H (0dB)
AVL7-0
GAIN (dB)
AVR7-0
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
E2H
+30.375
E1H
+30.0
E0H
+29.625
:
:
03H
−53.25
02H
−53.625
01H
−54
00H
MUTE
Table 32. ALC
MS0478-J-02
Step
0.375dB
(default)
2010/11
- 44 -
[AK4343]
AVL7-0, AVR7-0 bits
ALC bit
ALC Status
Disable
Enable
AVL7-0 bits
E1H(+30dB)
AVR7-0 bits
C6H(+20dB)
Internal AVL
E1H(+30dB)
Internal AVR
C6H(+20dB)
E1(+30dB) --> F1(+36dB)
(1)
E1(+30dB)
(2)
E1(+30dB) --> F1(+36dB)
Figure 34. ALC
AVL AVR
AVL7-0 bits
(WTM2-0 bits) +
(2) ALC
AVL, AVR
Disable
C6H(+20dB)
AVOL
(1) ALC
AVL
ALC bit = “1”
ALC
(ZTM1-0 bits)
(09H, 0CH)
ALC bit = “0”
MS0478-J-02
ALC Disable
ALC Enable
ALC bit = “1”
2010/11
- 45 -
[AK4343]
■
IIR
3
(32kHz, 44.1kHz, 48kHz)
DEM1-0 bits
(tc=50/15μs
)
(Table 33)
DEM1
DEM0
0
0
0
1
1
0
1
1
Table 33.
Mode
44.1kHz
OFF
48kHz
32kHz
(default)
■
BST1-0 bits
34)
BST1-0 bits = “01”(MIN)
DAC
(Table
47μF
DC
DAC
Figure 35
−20dB
Boost Filter (fs=44.1kHz)
0
MAX
Level [dB]
-5
MID
-10
MIN
-15
-20
-25
10
100
1000
10000
Frequency [Hz]
Figure 35.
(fs=44.1kHz)
BST1
BST0
0
0
0
1
1
0
1
1
Table 34.
Mode
OFF
MIN
MID
MAX
MS0478-J-02
(default)
2010/11
- 46 -
[AK4343]
■
AK4343
MUTE
0.5dB
DAC
DVOLC bit “1”
“0”
Lch, Rch
256/fs
00H(+12dB)
FFH(MUTE)
256
(DATT)
+12dB
DVL7-0 bits
−115dB
Lch, Rch
DVOLC
ATT
1061
DVTM bit = “0”
bit
DVTM bit
1061/fs([email protected]=44.1kHz)
DVL/R7-0
Gain
00H
+12.0dB
01H
+11.5dB
02H
+11.0dB
:
:
18H
0dB
:
:
FDH
−114.5dB
FEH
−115.0dB
FFH
MUTE (−∞)
Table 35. Digital Volume Code Table
DVTM bit
0
1
DVL/R7-0 bits = 00H
FFH
fs=8kHz
1061/fs
133ms
256/fs
32ms
Table 36.
MS0478-J-02
Step
0.5dB
fs=44.1kHz
24ms
6ms
(default)
(default)
2010/11
- 47 -
[AK4343]
■
DAC
SMUTE bit “1”
SMUTE bit “0”
SMUTE bit
−∞(“0”)
DVTM bit
−∞
−∞
bits
DVTM bit
DVTM bit
DVL/R7-0 bits
DVL/R7-0
(Figure 36)
S M U T E bit
D VTM bit
D VL/R 7-0 bits
D VTM bit
(1)
(3)
A ttenuation
-∞
GD
(2)
GD
A nalog O utput
Figure 36.
(1) DVTM bit
(2)
(3)
−∞(“0”)
(GD)
DVTM bit
DVL/R7-0 bits
MS0478-J-02
2010/11
- 48 -
[AK4343]
■
:
(LIN2/RIN2 pins, AIN3 bit = “1”: LIN3/RIN3 pins)
PMAINL2=PMAINR2 bits = “1”
LIN2/RIN2 pins
LINS2 bit
RINS2 bit “1”
LIN2/RIN2 pins
LINH2 bit
RINH2 bit “1”
LINL2 bit
AIN3 bit = “1”
MIN/VCOC pins
LIN3/RIN3 pins
PMAINL3=PMAINR3 bits = “1”
LIN3/RIN3 pins
PMMICL=PMMICR=MICL3=MICR3 bits = “1”
Gain-Amp
LINS3 bit
RINS3 bit “1”
LINH3 bit
RINH3 bit “1”
LINL3 bit
RINR3 bit “1”
RINR2 bit
“1”
PLL
LIN3/RIN3 pins
LIN3/RIN3 pins
LIN3/RIN3 pins
MICL3=MICR3 bits = “0”
MGAIN1-0 bits = “00”
typ. 30kΩ MGAIN1-0 bits = “01”, “10”, “11”
typ. 20kΩ
MICL3=MICR3 bits = “1”
MGAIN1-0 bits = “00”
typ. 60kΩ MGAIN1-0 bits = “01”, “10”, “11”
typ. 30kΩ
(typ)
Table 37, Table 38, Table 39, Table 40
AK4343
INL1-0 bits
LIN1/IN1− pin
RIN1/IN1+ pin
Gain-Amp
MDIF1 bit
INR1-0 bits
RIN2/IN2− pin
LIN2/IN2+ pin
Gain-Amp
MDIF2 bit
These blocks are not
available at PLL mode.
MIN/LIN3 pin
MICL3 bit
MICR3 bit
PMAINL3 bit
PMAINR3 bit
PMAINR2 bit
PMAINL2 bit
VCOC/RIN3 pin
Lineout, Receiver-Amp, HP-Amp, SPK-Amp
Figure 37.
(
MS0478-J-02
)
2010/11
- 49 -
[AK4343]
PMAINL2 bit
PMAINR2 bit
LINL2/RINR2
LOUT/RCP pin,
ROUT/RCN pin
LIN2/RIN2
LINH2/RINH2
HPL, HPR pin
LINS2/RINS2
SPP, SPN pin
Figure 38.
(LIN2/RIN2)
PMAINL3 bit
PMAINR3 bit
LINL3/RINR3
LOUT/RCP pin,
ROUT/RCN pin
LIN3/RIN3
LINH3/RINH3
HPL, HPR pin
LINS3/RINS3
SPP, SPN pin
Figure 39.
(LIN3/RIN3 : PLL
)
LOVL bit
LIN2/RIN2/LIN3/RIN3 Æ LOUT/ROUT
0
0dB
(default)
1
+2dB
Table 37. LIN2/RIN2/LIN3/RIN3 Input Æ LOUT/ROUT Output Gain (typ)
LOVL bit
LIN2/RIN2/LIN3/RIN3 Æ RCP/RCN
0
0dB
(default)
1
+2dB
Table 38. LIN2/RIN2/LIN3/RIN3 Input Æ RCP/RCN Output Gain (typ)
HPG bit
LIN2/RIN2/LIN3/RIN3 Æ HPL/HPR
0
0dB
(default)
1
+3.6dB
Table 39. LIN2/RIN2/LIN3/RIN3 Input Æ Headphone-Amp Output Gain (typ)
LIN2/RIN2/LIN3/RIN3 Æ SPP/SPN
ALC bit = “0”
ALC bit = “1”
00
+0.41dB
(default)
−1.59dB
01
+0.41dB
+2.41dB
10
+4.63dB
+6.63dB
11
+6.63dB
+8.63dB
Table 40. LIN2/RIN2/LIN3/RIN3 Input Æ Speaker-Amp Output Gain (typ)
SPKG1-0 bits
MS0478-J-02
2010/11
- 50 -
[AK4343]
■
AIN3 bit = “0”
MINS bit
:
“1”
(AIN3 bit = “0”: MIN pin)
MIN pin
MIN pin
PMMIN bit = “1”
MINH bit “1”
MINL bit
Ri
“1”
Ri = 20kΩ
(typ)
Table 41, Table 43, Table 44
Ri
Ri
MINL
MIN
LOUT/RCP pin,
ROUT/RCN pin
MINH
HPL, HPR pin
MINS
SPP, SPN pin
Figure 40. Block Diagram of MIN pin
LOVL bit
0
1
Table 41. Ri = 20kΩ
LOVL bit
0
1
Table 42. Ri = 20kΩ
HPG bit
0
1
Table 43. Ri = 20kΩ
MIN Æ LOUT/ROUT
0dB
+2dB
MIN
Æ LOUT/ROUT
MIN Æ RCP/RCN
0dB
+2dB
MIN
Æ RCP/RCN
MIN Æ HPL/HPR
−20dB
−16.4dB
MIN
Æ
(default)
(typ)
(default)
(typ)
(default)
MIN Æ SPP/SPN
ALC bit = “0”
ALC bit = “1”
00
+4.43dB
+6.43dB
01
+6.43dB
+8.43dB
10
+10.65dB
+12.65dB
11
+12.65dB
+14.65dB
Table 44. Ri = 20kΩ
MIN
Æ
(typ)
SPKG1-0 bits
MS0478-J-02
(default)
(typ)
2010/11
- 51 -
[AK4343]
■
(LOUT/ROUT pins)
DACL bit “1”
DACL bit
“0”
AVSS 100kΩ(typ)
LOPS bit = “1”
20kΩ
300ms
DAC
Lch, Rch
OFF
min. 10kΩ
LOUT, ROUT pins
LOUT, ROUT pins
VCOM
PMLO=LOPS bits = “0”
LOPS bit = “1”
PMLO bit
ON/OFF
ON/OFF
Figure 42
C
C=1μF, AVDD=3.3V
PMLO bit = “1”
LOPS bit = “0”
LOVL bit
“DACL”
“LOVL”
LOUT pin
DAC
ROUT pin
Figure 41.
LOPS
0
1
PMLO
0
1
0
1
Table 45.
Mode
LOUT/ROUT pin
Pull-down to AVSS
(default)
Fall down to AVSS
Rise up to VCOM
(x: Don’t care)
LOVL
Gain
0
0dB
1
+2dB
Table 46.
(typ)
0.6 x AVDD
0.757 x AVDD
LOUT
ROUT
1μF
(default)
220Ω
20kΩ
Figure 42.
(
MS0478-J-02
)
2010/11
- 52 -
[AK4343]
(
)
(2 )
(5 )
P M L O b it
(1 )
(3 )
(4 )
(6 )
L O P S b it
L O U T , R O U T p in s
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
Figure 43.
(1)
(2)
ON
)
C=1μF, AVDD=3.3V
200ms (max
LOPS bit = “1”
PMLO bit = “1”
LOUT, ROUT pins
300ms)
(3) LOUT, ROUT pins
(4)
(5)
(
LOPS bit = “0”
ON
LOPS bit = “1”
PMLO bit = “0”
LOUT, ROUT pins
300ms)
(6) LOUT, ROUT pins
C=1μF, AVDD=3.3V
200ms (max
LOPS bit = “0”
MS0478-J-02
2010/11
- 53 -
[AK4343]
AIN3 bit = “0”
MIN
LIN2/RIN2/DAC
ON/OFF
DACL, MINL, LINL2, RINR2 bits
20kΩ
0dB(typ)@LOVL bit = “0”
0dB(typ)@LOVL bit = “0”
LINL2 bit
LIN2 pin
0dB
MINL bit
MIN pin
0dB
LOUT pin
I
DACL bit
DAC Lch
M
X
0dB
Figure 44. LOUT
(AIN3 bit = “0”, LOVL bit = “0”)
RINR2 bit
RIN2 pin
0dB
MINL bit
MIN pin
0dB
ROUT pin
I
DACL bit
X
0dB
DAC Rch
Figure 45. ROUT
AIN3 bit = “1”
M
(AIN3 bit = “0”, LOVL bit = “0”)
ON/OFF
DACL, LINL2, RINR2, LINL3, RINR3, MICL3, MICR3 bits
0dB(typ)
LINL2 bit
LIN2 pin
0dB
MICL3 bit
LIN3 pin
LINL3 bit
M
0dB
I
LIN1 pin
Gain-Amp Lch
*These blocks are not
available at PLL mode.
DACL bit
LOUT pin
X
0dB
DAC Lch
Figure 46. LOUT
(AIN3 bit = “1”, LOVL bit = “0”)
RINR2 bit
RIN2 pin
0dB
MICR3 bit
RIN3 pin
RINR3 bit
0dB
M
I
RIN1 pin
Gain-Amp Rch
DAC Rch
Figure 47. ROUT
*These blocks are not
available at PLL mode.
DACL bit
ROUT pin
X
0dB
(AIN3 bit = “1”, LOVL bit = “0”)
MS0478-J-02
2010/11
- 54 -
[AK4343]
■
(RCP/RCN pins)
RCV bit = “1”
LOUT/ROUT pins
LIN2/RIN2/LIN3/RIN3
min. 32Ω
PMLO bit = “0”
PMLO bit = “1”, LOPS bit = “1”
= “0”
RCP/RCN pins
DAC
RCP/RCN pins
BTL
RCP/RCN pins Hi-Z
PMLO bit = “1”, LOPS bit
LOVL bit
[(L+R)/2]
“DACL”
“LOVL”
RCP pin
DAC
RCN pin
Figure 48. Mono Receiver Output
LOVL
0
1
PMLO
0
1
LOPS
x
1
0
Gain
Output Voltage (typ)
+6dB
(default)
0.59 x AVDD @−6dBFS
+8dB
0.59 x AVDD @−8dBFS
Table 47. Mono Receiver Output Volume Setting
Mode
RCP
RCN
Power-down
Hi-Z
Hi-Z
Power-save
Hi-Z
VCOM
Normal Operation
Normal Operation Normal Operation
Table 48. Receiver-Amp Mode Setting (x: Don’t care)
(default)
PMLO bit
LOPS bit
RCP pin
RCN pin
Hi-Z
Hi-Z
Hi-Z
VCOM
VCOM
>1ms
>0
Hi-Z
Figure 49. Power-up/Power-down Timing for Receiver-Amp
MS0478-J-02
2010/11
- 55 -
[AK4343]
AIN3 bit = “0”
MIN
LIN2/RIN2/DAC
ON/OFF
DACL, MINL, LINL2, RINR2 bits
20kΩ
+6dB(typ)@LOVL bit = “0”
0dB(typ)@LOVL bit = “0”
LINL2 bit
LIN2 pin
0dB
RINR2 bit
RIN2 pin
0dB
MINL bit
MIN pin
+6dB
RCP/N pin
I
DACL bit
DAC Lch
M
X
0dB
DACL bit
DAC Rch
0dB
Figure 50.
AIN3 bit = “1”
(AIN3 bit = “0”, LOVL bit = “0”)
ON/OFF
DACL, LINL2, RINR2, LINL3, RINR3 MICL3, MICR3 bits
0dB(typ)@LOVL bit = “0”
LINL2 bit
LIN2 pin
0dB
MICL3 bit
LIN3 pin
LINL3 bit
0dB
Gain-Amp Lch
LIN1 pin
*These blocks are not
available at PLL mode.
RINR2 bit
RIN2 pin
0dB
MICR3 bit
RIN3 pin
RIN1 pin
M
RINR3 bit
0dB
Gain-Amp Rch
I
RCP/N pin
X
*These blocks are not
available at PLL mode.
DACL bit
DAC Lch
0dB
DACL bit
DAC Rch
0dB
Figure 51.
(AIN3 bit = “1”, LOVL bit = “0”)
MS0478-J-02
2010/11
- 56 -
[AK4343]
■
(HPL/HPR pins)
HVDD
HPG bit
16Ω (min)
[email protected] bit = “0”
(Table 49)
HPG bit
Output Voltage [Vpp]
0
0.6 x AVDD
1
0.91 x AVDD
Table 49.
HPMTN bit
“0”
HVSS
HPMTN bit “1”
MUTET pin
MUTET pin
[email protected] bit = “0”
HVDD
: MUTET pin
C=1μF, HVDD=3.3V
: 100ms(typ), 250ms(max)
: 500ms(max)
PMHPL, PMHPR bits “0”
HPL, HPR pins “L” (HVSS)
PMHPL bit,
PMHPR bit
HPMTN bit
HPL pin,
HPR pin
(1) (2)
(3)
(4)
Figure 52.
(1)
(2)
(3)
(4)
(PMHPL, PMHPR bits = “1”)
(HPMTN bit = “1”)
(HPMTN bit = “0”)
(PMHPL, PMHPR bits = “0”)
MS0478-J-02
HVSS
HVSS
2010/11
- 57 -
[AK4343]
BOOST=OFF
(fc)
Table 50
(fc)
HVDD=3.0, 3.3, 5V
bit = “0”, 0.91 x AVDD (Vpp)@HPG bit = “1”
R 12Ω
(0.22μF±20%
10Ω±20%
RL 16Ω
0.6 x AVDD (Vpp)@HPG
)
HP-AMP
C
AK4343
0.22μ
R
Headphone
16Ω
10Ω
Figure 53.
HPG bit
R [Ω]
0
0
6.8
16
0
1
100
fc [Hz]
BOOST
=OFF
fc [Hz]
BOOST
C [μF]
=MIN
fs=44.1kHz
220
45
17
100
100
43
100
70
28
47
149
78
100
50
19
47
106
47
220
45
17
100
100
43
22
62
25
10
137
69
Table 50.
Note 38. 16Ω
Note 39.
Output Power [mW]@0dBFS
HVDD=3.0V HVDD=3.3V
AVDD=3.0V AVDD=3.3V
HVDD=5V
AVDD=3.3V
25.3
30.6
30.6
12.5
15.1
15.1
6.3
7.7
7.7
51
(Note 39)
62
(Note 39)
70
1.1
1.3
1.3
PSRR
HVDD
VBAT bit = “1”
AVDD(typ)
PSRR
AVDD=3.3V
VBAT bit
Common Voltage [V]
Table 51.
RF
HVDD
0.64 x
2.1V
0
0.5 x HVDD
MS0478-J-02
HVDD
4.2V
1
0.64 x AVDD
2010/11
- 58 -
[AK4343]
AIN3 bit = “0”
MIN
LIN2/RIN2/DAC
ON/OFF
DACH, MINH, LINH2, RINH2 bits
20kΩ
−20dB(typ)@HPG bit = “0”
0dB(typ)@HPG bit = “0”
LINH2 bit
LIN2 pin
0dB
MINH bit
−20dB
MIN pin
HPL pin
I
DACH bit
DAC Lch
M
X
0dB
Figure 54. HPL
(AIN3 bit = “0”, HPG bit = “0”)
RINH2 bit
RIN2 pin
0dB
MINH bit
−20dB
MIN pin
X
0dB
Figure 55. HPR
AIN3 bit = “1”
HPR pin
I
DACH bit
DAC Rch
M
(AIN3 bit = “0”, HPG bit = “0”)
ON/OFF
DACH, LINH2, RINH2, LINH3, RINH3, MICL3, MICR3 bits
0dB(typ)
LINH2 bit
LIN2 pin
0dB
MICL3 bit
LIN3 pin
LIN1 pin
LINH3 bit
M
0dB
Gain-Amp Lch
*These blocks are not
available at PLL mode.
I
HPL pin
X
DACH bit
DAC Lch
Figure 56. HPL
0dB
(AIN3 bit = “1”, HPG bit = “0”)
RINH2 bit
RIN2 pin
0dB
MICR3 bit
RIN3 pin
RIN1 pin
RINH3 bit
M
0dB
Gain-Amp Rch
*These blocks are not
available at PLL mode.
I
HPR pin
X
DACH bit
DAC Rch
Figure 57. HPR
0dB
(AIN3 bit = “1”, HPG bit = “0”)
MS0478-J-02
2010/11
- 59 -
[AK4343]
■
(SPP/SPN pins)
HVDD
2.6V ∼ 5.25V
(min)
8Ω
30pF
(max)
Note 19. 31HFigure 58
Load Impedance
Load Capacitance
SPP, SPN pin
10Ω
Table 52.
DAC
LIN2/RIN2/LIN3/RIN3
BTL
00
01
10
11
AVDD
HVDD
3.3V
3.3V
5.0V
(Rseries)
[(L+R)/2]
SPKG1-0 bits
SPKG1-0 bits
AVDD
SPKG1-0 bits
ALC bit = “0”
ALC bit = “1”
+4.43dB
+6.43dB
+6.43dB
+8.43dB
+10.65dB
+12.65dB
+12.65dB
+14.65dB
Table 53. SPK-Amp
SPKG1-0 bits
SPK-Amp
ALC bit = “0”
00
01
10
11
00
01
10
11
3.30Vpp
4.15Vpp (Note 40)
6.75Vpp (Note 40)
8.50Vpp (Note 40)
3.30Vpp
4.15Vpp
6.75Vpp (Note 40)
8.50Vpp (Note 40)
Note 40.
SPK-Amp
50Ω (Note 19)
3μF (Note 19)
1kHz
4.0Vpp(HVDD=3.3V)
(default)
(DAC
=0dBFS)
ALC bit = “1”
(LMTH1-0 bits = “00”)
3.11Vpp
3.92Vpp
6.37Vpp (Note 40)
8.02Vpp (Note 40)
3.11Vpp
3.92Vpp
6.37Vpp (Note 40)
8.02Vpp (Note 40)
DAC
0dBFS
DVOL
DAC
6.0Vpp(HVDD=5V)
Table 54. SPK-Amp
MS0478-J-02
2010/11
- 60 -
[AK4343]
ALC
fs=44.1kHz
Operation
−2.5dBFS
Enable
11.6ms
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same or
longer data as ZTM1-0 bits
Maximum gain at recovery operation
011
23.2ms
C1H
+18dB
Gain of AVOL
91H
0dB
00
00
1
1 step
1 step
Enable
WTM2-0
REF7-0
AVL7-0,
AVR7-0
LMAT1-0
RGAIN1-0
ALC
Limiter ATT step
Recovery GAIN step
ALC enable
Table 55.
ALC
Figure 58
Figure 58
0.92 x HVDD ≤
Ex) HVDD = 5.0V
Data
00
0
10
(10Ω
)
SPP pin, SPN pin
GND
(Figure 58 ZD)
: 4.6V ≤ ZD ≤ 5.3V
5.1V(Min 4.97V, Max
≤ HVDD+0.3V
5.24V)
ZD
SPK-Amp
SPP
≥10Ω
SPN
≥10Ω
ZD
Figure 58. SPK
(
)
MS0478-J-02
2010/11
- 61 -
[AK4343]
PMSPK bit
Power-up/down
PMSPK bit “1”
SPPSN bit “0”
SPP pin Hi-Z SPN pin HVDD/2
PDN pin
“L”
PMSPK
0
“H”
SPP pin
SPPSN
x
0
1
Table 56
1
Hi-Z
PMSPK bit
“0”
SPP, SPN pin
Hi-Z
PMSPK bit “1”
SPP, SPN pin
SPN pin HVDD/2
Power-down (PMSPK bit=“0”)
Mode
SPP
Hi-Z
Hi-Z
SPN
Hi-Z
HVDD/2
(default)
(x: Don’t care)
PMSPK bit
SPPSN bit
SPP pin
SPN pin
Hi-Z
Hi-Z
Hi-Z
HVDD/2
HVDD/2
>1ms
>0
Hi-Z
Figure 59. Power-up/Power-down Timing for Speaker-Amp
MS0478-J-02
2010/11
- 62 -
[AK4343]
AIN3 bit = “0”
MIN
LIN2/RIN2/DAC
ON/OFF
DACS, MINS, LINS2, RINS2 bits
20kΩ
+4.43dB(typ)@SPKG1-0 bits = “00”, ALC bit = “0”
−1.59dB(typ)@SPKG1-0 bits = “00”, ALC bit = “0”
LINS2 bit
−1.59dB
LIN2 pin
RINS2 bit
−1.59dB
RIN2 pin
MINS bit
+4.43dB
MIN pin
M
SPP/N pin
I
DACS bit
X
−1.59dB
DAC Lch
DACS bit
−1.59dB
DAC Rch
Figure 60.
AIN3 bit = “1”
(AIN3 bit = “0”, SPKG1-0 bits = “00”, ALC bit = “0”)
ON/OFF
DACS, LINS2, RINS2, LINS3, RINS3 bits
−1.59dB (typ)@SPKG1-0 bits = “00”, ALC bit = “0”
LINS2 bit
−1.59dB
LIN2 pin
LIN3 pin
LIN1 pin
MICL3 bit
Gain-Amp Lch
*These blocks are not
available at PLL mode.
−1.59dB
RIN2 pin
RIN3 pin
RIN1 pin
LINS3 bit
−1.59dB
MICR3 bit
RINS2 bit
RINS3 bit
−1.59dB
Gain-Amp Rch
M
I
SPP/N pin
X
*These blocks are not
available at PLL mode.
DACS bit
DAC Lch
−1.59dB
DACS bit
DAC Rch
Figure 61.
−1.59dB
(AIN3 bit = “1”, SPKG bits = “00”, ALC bit = “0”)
MS0478-J-02
2010/11
- 63 -
[AK4343]
■
(1) 3
(I2C pin = “L”)
I/F
(CSN, CCLK, CDTI)
), Read/Write (1bit, “1”
), Register address (MSB first, 6bits)
CCLK “↓”
CSN “↓” 16
CCLK “↑”
CCLK
PDN pin = “L”
3
address (1bit, “1”
8bits)
(max)
I/F
Chip
Control Data (MSB first,
“↑”
5MHz
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
“1”
“1”
C1:
R/W:
A5-A0:
D7-D0:
Chip Address; Fixed to “1”
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
Register Address
Control data
Figure 62.
MS0478-J-02
2010/11
- 64 -
[AK4343]
(2) I2C
AK4343
(I2C pin = “H”)
I 2C
(max:400kHz)
SDA, SCL pins
(DVDD+0.3)V
(2)-1. WRITE
I2C
(Start Condition)
(Figure 69)
8
IC
AK4343
SDA
R/W bit “1”
2
MSB first
“L”
IC
“H”
SDA
“L”
7
(R/W)
6
“001001”
(Figure 64)
CAD0 pin
1
(Acknowledge)
(Figure 70)
(
)
(Figure 65)
3
(Figure 66) AK4343
“0”
SDA
Figure 63
“H”
SCL
8
“0”
MSB first
2
8
(Stop Condition)
(Figure 69)
“H”
R/W bit
AK4343
SCL
“H”
1
“24H”
“00H”
“H”
SDA
SCL
“L”
(Figure 71)
“H”
SCL
“L”
“H”
SDA
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
A
C
K
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 63. I2C
0
0
1
0
0
(CAD0
Figure 64.
0
0
A5
D6
D5
Figure 66.
CAD0
R/W
A3
A2
A1
A0
D3
D2
D1
D0
)
1
A4
Figure 65.
D7
1
2
D4
3
MS0478-J-02
2010/11
- 65 -
[AK4343]
(2)-2. READ
R/W bit “1”
AK4343
READ
“24H”
“00H”
AK4343
2
READ
(2)-2-1.
AK4343
AK4343
(READ
WRITE
“n+1”
(R/W bit = “1”)
READ
)
“n”
1
READ
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
A
C
K
Data(n+1)
Data(n+2)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 67.
(2)-2-2.
READ
(R/W bit = “1”)
WRITE
WRITE
= “0”)
AK4343
(R/W bit= “1”)
READ
(R/W bit
AK4343
1
READ
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 68.
MS0478-J-02
2010/11
- 66 -
[AK4343]
SDA
SCL
S
P
start condition
stop condition
Figure 69.
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 70. I2C
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 71. I2C
MS0478-J-02
2010/11
- 67 -
[AK4343]
■
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Lch Input Volume Control
Lch Digital Volume Control
ALC Mode Control 3
Rch Input Volume Control
Rch Digital Volume Control
Mode Control 3
Mode Control 4
Power Management 3
Digital Filter Select
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
Power Management 4
Mode Control 5
Lineout Mixing Select
HP Mixing Select
SPK Mixing Select
Note 41. PDN pin
Note 42. “0”
D7
0
0
SPPSN
LOVL
PLL3
PS1
DVTM
0
REF7
AVL7
DVL7
RGAIN1
AVR7
DVR7
0
0
INR1
GN1
F3A7
F3AS
F3B7
0
EQA7
EQA15
EQB7
0
EQC7
EQC15
F1A7
F1AS
F1B7
0
0
0
0
0
0
D6
PMVCM
HPMTN
MINS
LOPS
PLL2
PS0
WTM2
0
REF6
AVL6
DVL6
LMTH1
AVR6
DVR6
0
0
INL1
GN0
F3A6
0
F3B6
0
EQA6
EQA14
EQB6
0
EQC6
EQC14
F1A6
0
F1B6
0
0
0
0
0
0
D5
PMMIN
PMHPL
DACS
PLL1
FS3
ZTM1
ALC
REF5
AVL5
DVL5
0
AVR5
DVR5
SMUTE
0
HPG
0
F3A5
F3A13
F3B5
F3B13
EQA5
EQA13
EQB5
EQB13
EQC5
EQC13
F1A5
F1A13
F1B5
F1B13
D4
PMSPK
PMHPR
DACL
SPKG1
PLL0
MSBS
ZTM0
ZELMN
REF4
AVL4
DVL4
0
AVR4
DVR4
DVOLC
0
MDIF2
FIL1
F3A4
F3A12
F3B4
F3B12
EQA4
EQA12
EQB4
EQB12
EQC4
EQC12
F1A4
F1A12
F1B4
F1B12
D3
PMLO
M/S
0
SPKG0
BCKO
BCKP
WTM1
LMAT1
REF3
AVL3
DVL3
0
AVR3
DVR3
BST1
AVOLC
MDIF1
EQ
F3A3
F3A11
F3B3
F3B11
EQA3
EQA11
EQB3
EQB11
EQC3
EQC11
F1A3
F1A11
F1B3
F1B11
D2
PMDAC
0
0
MINL
0
FS2
WTM0
LMAT0
REF2
AVL2
DVL2
0
AVR2
DVR2
BST0
HPM
INR0
FIL3
F3A2
F3A10
F3B2
F3B10
EQA2
EQA10
EQB2
EQB10
EQC2
EQC10
F1A2
F1A10
F1B2
F1B10
D1
0
MCKO
0
0
DIF1
FS1
RFST1
RGAIN0
REF1
AVL1
DVL1
VBAT
AVR1
DVR1
DEM1
MINH
INL0
0
F3A1
F3A9
F3B1
F3B9
EQA1
EQA9
EQB1
EQB9
EQC1
EQC9
F1A1
F1A9
F1B1
F1B9
PMAINR3
PMAINL3
PMAINR2
PMAINL2
PMMICR
PMMICL
MICR3
0
0
0
MICL3
0
0
0
0
RINR3
RINH3
RINS3
0
LINL3
LINH3
LINS3
AIN3
RINR2
RINH2
RINS2
RCV
LINL2
LINH2
LINS2
MGAIN1
D0
0
PMPLL
MGAIN0
0
DIF0
FS0
RFST0
LMTH0
REF0
AVL0
DVL0
0
AVR0
DVR0
DEM0
DACH
0
0
F3A0
F3A8
F3B0
F3B8
EQA0
EQA8
EQB0
EQB8
EQC0
EQC8
F1A0
F1A8
F1B0
F1B8
“L”
“1”
MS0478-J-02
2010/11
- 68 -
[AK4343]
■
Addr
00H
Register Name
Power Management 1
Default
D7
0
0
D6
PMVCM
0
D5
PMMIN
0
D4
PMSPK
0
D3
PMLO
0
D2
PMDAC
0
D1
0
0
D0
0
0
PMDAC: DAC
0: Power down (default)
1: Power up
PMLO:
0: Power down (default)
1: Power up
PMSPK:
0: Power down (default)
1: Power up
PMMIN:
0: Power down (default)
1: Power up
PMMIN or PMAINL3 bit = “1”
PMVCM: VCOM
0: Power down (default)
1: Power up
PMVCM bit “1”
00H, 01H, 02H, 10H, 20H
“0”
MCKO bit
PMVCM bit
“0”
ON/OFF (“1”/“0”)
PDN pin
“L”
00H, 01H, 02H, 20H
MCKO bit
DAC
“0”
DAC
MS0478-J-02
2010/11
- 69 -
[AK4343]
Addr
01H
Register Name
Power Management 2
Default
D7
0
0
D6
HPMTN
0
D5
PMHPL
0
D4
PMHPR
0
D3
M/S
0
D2
0
0
D1
MCKO
0
D0
PMPLL
0
PMPLL: PLL
0: EXT Mode and Power Down (default)
1: PLL Mode and Power up
MCKO: MCKO
0: Disable: MCKO pin = “L” (default)
1: Enable: Output frequency is selected by PS1-0 bits.
M/S: Master / Slave Mode
0: Slave Mode (default)
1: Master Mode
PMHPR: Rch
0: Power down (default)
1: Power up
PMHPL: Lch
0: Power down (default)
1: Power up
HPMTN:
0: Mute (default)
1: Normal operation
MS0478-J-02
2010/11
- 70 -
[AK4343]
Addr
02H
Register Name
Signal Select 1
Default
MGAIN1-0:
MGAIN1 bit
D7
SPPSN
0
D6
MINS
0
D5
DACS
0
D4
DACL
0
D3
0
0
D2
0
0
D1
0
0
D0
MGAIN0
1
(Table 22)
03H
D5 bit
DACL: DAC
0: OFF (default)
1: ON
PMLO bit = “1”
PMLO bit = “0”
LOUT, ROUT pins
AVSS
DACS: DAC
0: OFF (default)
1: ON
“1” DAC
MINS: MIN pin
0: OFF (default)
1: ON
“1” MIN pin
SPPSN:
0: Power Save Mode (default)
1: Normal Operation
“0”
PMSPK bit =“1”
SPP pin
MS0478-J-02
Hi-Z SPN pin
HVDD/2
2010/11
- 71 -
[AK4343]
Addr
03H
Register Name
Signal Select 2
Default
D7
LOVL
0
D6
LOPS
0
D5
MGAIN1
0
MINL:
0: OFF (default)
1: ON
PMLO bit = “1”
D4
SPKG1
0
D3
SPKG0
0
D2
MINL
0
D1
0
0
D0
0
0
MIN
PMLO bit = “0”
SPKG1-0:
LOUT, ROUT pins
AVSS
(Table 53)
MGAIN1:
(Table 22)
LOPS:
0: Normal Operation (default)
1: Power Save Mode
LOVL:
/
0: 0dB/+6dB (default)
1: +2dB/+8dB
Addr
04H
(Table 46, Table 47)
Register Name
Mode Control 1
Default
DIF1-0:
Default: “10” (
BCKO:
D7
PLL3
0
Register Name
Mode Control 2
Default
D2
0
0
D1
DIF1
1
D0
DIF0
0
D4
MSBS
0
D3
BCKP
0
D2
FS2
0
D1
FS1
0
D0
FS0
0
(Table 5)
D7
PS1
0
D6
PS0
0
D5
FS3
0
(See Table 6 and Table 7)
BICK
, “↓”
, “↑”
MSBS: DSP Mode
LRCK
“0”: LRCK “↑”
“1”: LRCK “↑”
PS1-0: MCKO
Default: “00”(256fs)
D3
BCKO
0
(Table 11)
MCKI
EXT
PLL
BCKP: DSP Mode
“0”: “↑” SDTO
“1”: “↓” SDTO
D4
PLL0
0
(Table 17)
BICK
FS3-0:
D5
PLL1
0
)
PLL3-0: PLL
Default: “0000”(LRCK pin)
Addr
05H
D6
PLL2
0
(Table 12)
MCKI
(Table 18)
SDTI
(default)
SDTI
(Table 18)
BICK
BICK 1
(default)
(Table 10)
MS0478-J-02
2010/11
- 72 -
[AK4343]
Addr
06H
Register Name
Timer Select
Default
D7
DVTM
0
RFST1-0: ALC
Default: “00” (4
D6
WTM2
0
D5
ZTM1
0
D4
ZTM0
0
D3
WTM1
0
D2
WTM0
0
D1
RFST1
0
D0
RFST0
0
D3
LMAT1
0
D2
LMAT0
0
D1
RGAIN0
0
D0
LMTH0
0
D1
REF1
0
D0
REF0
1
(Table 30)
)
WTM2-0: ALC
ALC
“000” (128/fs)
(Table 27)
ZTM1-0: ALC
(Table 26)
ALC
“00” (128/fs)
DVTM: Digital Volume
0: 1061/fs (default)
1: 256/fs
DVL7-0, DVR7-0 bits
Addr
07H
Register Name
ALC Mode Control 1
Default
LMTH1-0: ALC
Default: “00”
LMTH1 bit
RGAIN1-0: ALC
Default: “00”
RGAIN1 bit
D7
0
0
D6
0
0
00H
D5
ALC
0
FFH
D4
ZELMN
0
/
0BH
(Table 24)
D6 bit
(Table 28)
0BH
LMAT1-0: ALC
Default: “00”
D7 bit
ATT
(Table 25)
ZELMN: ALC
0: Enable (default)
1: Disable
ALC: ALC
0: ALC Disable (default)
1: ALC Enable
Addr
08H
Register Name
ALC Mode Control 2
Default
REF7-0: ALC
Default: “E1H” (+30.0dB)
D7
REF7
1
D6
REF6
1
D5
REF5
1
D4
REF4
0
D3
REF3
0
D2
REF2
0
0.375dB step, 242 Level (Table 29)
MS0478-J-02
2010/11
- 73 -
[AK4343]
Addr
09H
0CH
Register Name
Lch Input Volume Control
Rch Input Volume Control
Default
D7
AVL7
AVR7
1
D6
AVL6
AVR6
1
AVL7-0, AVR7-0: ALC
Default: “E1H” (+30.0dB)
Addr
0AH
0DH
Register Name
Lch Digital Volume Control
Rch Digital Volume Control
Default
Register Name
ALC Mode Control 3
Default
D7
DVL7
DVR7
0
D6
DVL6
DVR6
0
D3
AVL3
AVR3
0
D2
AVL2
AVR2
0
D1
AVL1
AVR1
0
D0
AVL0
AVR0
1
D5
DVL5
DVR5
0
D4
DVL4
DVR4
1
D3
DVL3
DVR3
1
D2
DVL2
DVR2
0
D1
DVL1
DVR1
0
D0
DVL0
DVR0
0
D4
0
0
D3
0
0
D2
0
0
D1
VBAT
0
D0
0
0
D1
DEM1
0
D0
DEM0
1
(Table 35)
D7
RGAIN1
0
D6
LMTH1
0
VBAT:
0: 0.5 x HVDD (default)
1: 0.64 x AVDD
/
RGAIN1: ALC
Register Name
Mode Control 3
Default
DEM1-0:
Default: “01” (OFF)
BST1-0:
Default: “00” (OFF)
DVOLC:
0: Independent
1: Dependent (default)
DVOLC bit = “1”
DVR7-0 bit DVL7-0 bit
D5
0
0
(Table 51)
LMTH1: ALC
Addr
0EH
D4
AVL4
AVR4
0
; 0.375dB step, 242 Level (Table 32)
DVL7-0, DVR7-0:
Default: “18H” (0dB)
Addr
0BH
D5
AVL5
AVR5
1
(Table 24)
(Table 28)
D7
0
0
D6
LOOP
0
D5
SMUTE
0
D4
DVOLC
1
D3
BST1
0
D2
BST0
0
(Table 33)
(Table 34)
DVL7-0 bit
SMUTE:
0: Normal Operation (default)
1: DAC outputs soft-muted
LOOP:
0: SDTI → DAC (default)
1: SDTO → DAC
MS0478-J-02
2010/11
- 74 -
[AK4343]
Addr
0FH
Register Name
Mode Control 4
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
AVOLC
1
D2
HPM
0
D1
MINH
0
D0
DACH
0
DACH: DAC
0: OFF (default)
1: ON
MINH: MIN pin
0: OFF (default)
1: ON
HPM:
0:
1:
(default)
HPM bit = “1”
DAC
AVOLC: AVOL
0: Independent
1: Dependent (default)
AVOLC bit = “1”
bit
Addr
10H
(L+R)/2
AVL7-0 bit
Register Name
Power Management 3
Default
D7
INR1
0
D6
INL1
0
INL1-0: Gain-Amp Lch
Default: 00 (LIN1 pin)
(Table 22)
INR1-0: Gain-Amp Rch
Default: 00 (RIN1 pin)
(Table 22)
MDIF1:
0:
1:
MDIF2:
0:
1:
AVOL
D5
HPG
0
D4
MDIF2
0
AVR7-0 bit
D3
MDIF1
0
D2
INR0
0
D1
INL0
0
AVL7-0
D0
0
0
/
1
(LIN1/RIN1 pin: Default)
(IN1+/IN1− pin)
Pin#32 #31
2
(LIN2/RIN2 pin: Default)
(IN2+/IN2− pin)
Pin#30 #29
HPG:
0: 0dB (default)
1: +3.6dB
/
(Table 49)
MS0478-J-02
2010/11
- 75 -
[AK4343]
Addr
11H
Register Name
Digital Filter Select
Default
GN1-0: Gain
Default: “00” (0dB)
FIL3:
0:
1:
D7
GN1
0
D6
GN0
0
D5
0
0
D4
FIL1
0
D3
EQ
0
D2
FIL3
0
D1
0
0
D0
0
0
(Table 23)
FIL3
(default)
FIL3 bit = “1”
F3A13-0, F3B13-0 bit
OFF(MUTE)
EQ:
0:
1:
FIL3 bit = “0”
FIL3
(default)
EQ bit = “1”
EQ
FIL1:
0:
1:
EQA15-0, EQB13-0, EQC15-0 bit
(0dB)
EQ bit = “0”
FIL1
(default)
FIL1 bit = “1”
F1A13-0, F1B13-0 bit
FIL1 bit = “0”
FIL1
(0dB)
MS0478-J-02
2010/11
- 76 -
[AK4343]
Addr
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Register Name
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
Default
D7
F3A7
F3AS
F3B7
0
EQA7
EQA15
EQB7
0
EQC7
EQC15
F1A7
F1AS
F1B7
0
0
F3A13-0, F3B13-0:
Default: “0000H”
F3AS:
0: HPF (default)
1: LPF
D6
F3A6
0
F3B6
0
EQA6
EQA14
EQB6
0
EQC6
EQC14
F1A6
0
F1B6
0
0
FIL3
D5
F3A5
F3A13
F3B5
F3B13
EQA5
EQA13
EQB5
EQB13
EQC5
EQC13
F1A5
F1A13
F1B5
F1B13
0
D3
F3A3
F3A11
F3B3
F3B11
EQA3
EQA11
EQB3
EQB11
EQC3
EQC11
F1A3
F1A11
F1B3
F1B11
0
D2
F3A2
F3A10
F3B2
F3B10
EQA2
EQA10
EQB2
EQB10
EQC2
EQC10
F1A2
F1A10
F1B2
F1B10
0
D1
F3A1
F3A9
F3B1
F3B9
EQA1
EQA9
EQB1
EQB9
EQC1
EQC9
F1A1
F1A9
F1B1
F1B9
0
D0
F3A0
F3A8
F3B0
F3B8
EQA0
EQA8
EQB0
EQB8
EQC0
EQC8
F1A0
F1A8
F1B0
F1B8
0
(14bit x 2)
FIL3
EQA15-0, EQB13-0, EQC15-C0:
Default: “0000H”
F1A13-0, F1B13-B0:
Default: “0000H”
F1AS:
0: HPF (default)
1: LPF
D4
F3A4
F3A12
F3B4
F3B12
EQA4
EQA12
EQB4
EQB12
EQC4
EQC12
F1A4
F1A12
F1B4
F1B12
0
(14bit x 2 + 16bit x 1)
FIL1
(14bit x 2)
FIL1
MS0478-J-02
2010/11
- 77 -
[AK4343]
Addr
20H
Register Name
Power Management 4
Default
D7
0
0
D6
0
0
D5
D4
D3
D2
D1
D0
PMAINR3
PMAINL3
PMAINR2
PMAINL2
PMMICR
PMMICL
0
0
0
0
0
0
D4
MICL3
0
D3
0
0
D2
0
0
D1
AIN3
0
D0
RCV
0
PMMICL: Gain-Amp Lch
0: Power down (default)
1: Power up
PMMICR: Gain-Amp Rch
0: Power down (default)
1: Power up
PMAINL2: LIN2
0: Power down (default)
1: Power up
PMAINR2: RIN2
0: Power down (default)
1: Power up
PMAINL3: LIN3
0: Power down (default)
1: Power up
PMMIN or PMAINL3 bit = “1”
PMAINR3: RIN3
0: Power down (default)
1: Power up
Addr
21H
Register Name
Mode Control 5
Default
D7
0
0
D6
0
0
D5
MICR3
0
RCV: Receiver Select
0: Stereo Line Output (LOUT/ROUT pins) (defautl)
1: Mono Receiver Output (RCP/RCN pins)
AIN3: Analog Mixing Select
0: Mono Input (MIN pin) (default)
1: Stereo Input (LIN3/RIN3 pins): PLL is not available.
MICL3:
0: LIN3 pin
(default)
1: Gain-Amp Lch
MICR3:
0: RIN3 pin
(default)
1: Gain-Amp Rch
MS0478-J-02
2010/11
- 78 -
[AK4343]
Addr
22H
Register Name
Lineout Mixing Select
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
RINR3
0
D2
LINL3
0
D1
RINR2
0
LINL2: LIN2
0: OFF (default)
1: ON
(Gain-Amp
)
RINR2: RIN2
0: OFF (default)
1: ON
(Gain-Amp
)
D0
LINL2
0
LINL3: LIN3 (or Gain-Amp Lch)
0: OFF (default)
1: ON
RINR3: RIN3 (or Gain-Amp Rch)
0: OFF (default)
1: ON
Addr
23H
Register Name
HP Mixing Select
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
RINH3
0
D2
LINH3
0
D1
RINH2
0
LINH2: LIN2
0: OFF (default)
1: ON
(Gain-Amp
)
RINH2: RIN2
0: OFF (default)
1: ON
(Gain-Amp
)
D0
LINH2
0
LINH3: LIN3 (or Gain-Amp Lch)
0: OFF (default)
1: ON
RINH3: RIN3 (or Gain-Amp Rch)
0: OFF (default)
1: ON
MS0478-J-02
2010/11
- 79 -
[AK4343]
Addr
24H
Register Name
SPK Mixing Select
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
RINS3
0
D2
LINS3
0
LINS2: LIN2
0: OFF (default)
1: ON
(Gain-Amp
)
RINS2: RIN2
0: OFF (default)
1: ON
(Gain-Amp
)
D1
RINS2
0
D0
LINS2
0
LINS3: LIN3 (or Gain-Amp Lch)
0: OFF (default)
1: ON
RINS3: RIN3 (or Gain-Amp Rch)
0: OFF (default)
1: ON
MS0478-J-02
2010/11
- 80 -
[AK4343]
Figure 73
(AKD4343)
Headphone
Line Out
200
1u
200
1u
Mono In
22
21
20
19
18
17
HVSS
HVDD
SPP
SPN
MCKO
MCKI
R1
10
47u
6.8
1u
23
0.22u
HPR
10
ZD1
24
0.22u
Dynamic SPK
R1, R2: Short
ZD1, ZD2: Open
Piezo SPK
R1, R2: ≥10Ω
ZD1, ZD2: Required
HPL
10
ZD2
0.1u
47u
6.8
10u
20k
20k
Power Supply
2.6 ∼ 3.6V
Speaker
R2
Figure 72
25 MUTET
DVSS
16
26 ROUT
DVDD
15
27 LOUT
BICK
14
LRCK
13
28 MIN
AK4343
29 RIN2
Top View
0.1u
DSP
TEST2 12
30 LIN2
SDTI
11
31 LIN1
CDTI
10
32 RIN1
CCLK
9
I2C
PDN
CSN
6
7
8
VCOC
AVDD
4
0.1u
5
AVSS
3
2.2u
μP
Rp
VCOM
2
0.1u
1
TEST1
Line In
Cp
Analog Ground
:
- AK4343
- EXT
- PLL
-
Digital Ground
AVSS, DVSS, HVSS
(PMPLL bit = “0”)
(PMPLL bit = “1”)
HVDD
-
VCOC pin
Cp Rp Table 5
2.6 ∼ 5.25V
M/S bit
Figure 72.
“1”
AK4343
SPP, SPN pin
LRCK, BICK pin
AK4343
100kΩ
10Ω
LRCK, BICK pin
(AIN3 bit = “0”, RCV bit = “0”)
MS0478-J-02
2010/11
- 81 -
[AK4343]
Headphone
21
20
19
18
17
HVDD
SPP
SPN
MCKO
MCKI
R1
22
HVSS
1u
10
R2
47u
6.8
0.22u
23
10
ZD1
HPR
0.22u
Dynamic SPK
R1, R2: Short
ZD1, ZD2: Open
Piezo SPK
R1, R2: ≥10Ω
ZD1, ZD2: Required
24
10
ZD2
0.1u
47u
6.8
10u
HPL
Power Supply
2.6 ∼ 3.6V
Speaker
25 MUTET
DVSS
16
26 RCN
DVDD
15
27 RCP
BICK
14
LRCK
13
0.1u
Receiver
AK4343
29 RIN2
Top View
DSP
TEST2 12
I2C
PDN
CSN
7
8
μP
2.2u
0.1u
0.1u
1
6
9
RIN3
CCLK
5
32 RIN1
AVDD
10
4
CDTI
AVSS
31 LIN1
3
11
VCOM
SDTI
2
30 LIN2
TEST1
Line In
28 LIN3
Analog Ground
:
- AK4343 AVSS, DVSS, HVSS
- AIN3 bit = “1”
PLL
HVDD 2.6 ∼ 5.25V
Figure 73.
(AIN3 bit = “1”, RCV bit = “1”, PLL
MS0478-J-02
SPP, SPN pin
,
Digital Ground
10Ω
)
2010/11
- 82 -
[AK4343]
1.
AVDD, DVDD, HVDD
AVDD, DVDD, HVDD
AVSS, DVSS, HVSS
PC
2.
VCOM
2.2μF
0.1μF
AVSS
VCOM pin
VCOM pin
3.
MIN
(0.45 x AVDD)
0.06 x AVDD Vpp(typ)@MGAIN1-0 bits = “01”, 0.03 x AVDD
Vpp(typ)@MGAIN1-0 bits = “10”, 0.015 x AVDD Vpp(typ)@MGAIN1-0 bits = “11”
0.6 x AVDD
Vpp(typ)@MGAIN1-0 bits = “00”
MIN
(0.45 x AVDD)
0.6 x AVDD Vpp(typ)
DC
fc=1/(2πRC)
AK4343 AVSS
AVDD
4.
DAC
8000H(@16bit)
2’s
0000H(@16bit)
0.45 x AVDD (typ)
7FFFH(@16bit)
VCOM
VCOM
HVDD/2
MS0478-J-02
2010/11
- 83 -
[AK4343]
■
DAC
Power-up
1. PLL
Example:
Power Supply
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
(3)
PMVCM bit
(Addr:00H, D6)
(4)
(1) Power Supply & PDN pin = “L” Æ “H”
MCKO bit
(Addr:01H, D1)
PMPLL bit
(2)Addr:01H, Data:08H
Addr:04H, Data:4AH
Addr:05H, Data:27H
(Addr:01H, D0)
(5)
MCKI pin
Input
M/S bit
(3)Addr:00H, Data:40H
(Addr:01H, D3)
40msec(max)
(6)
BICK pin
LRCK pin
Output
(4)Addr:01H, Data:0BH
Output
MCKO, BICK and LRCK output
40msec(max)
(8)
MCKO pin
(7)
Figure 74. Clock Set Up Sequence (1)
<
>
(1)
PDN pin “L” Æ “H”
AK4343
150ns
“L”
DIF1-0, PLL3-0, FS3-0, BCKO, M/S bits
: PMVCM bit = “0” Æ “1”
VCOM
(4) MCKO
: MCKO bit = “1”
MCKO
: MCKO bit = “0”
(5) PMPLL bit “0” Æ “1”
MCKI pin
PLL
40ms(max)
(6) PLL
BICK, LRCK
(7) MCKO bit = “1”
MCKO pin
(8) MCKO bit = “1”
PLL
MCKO pin
(2)
(3) VCOM
MS0478-J-02
PLL
2010/11
- 84 -
[AK4343]
2. PLL
(LRCK or BICK pin)
Example:
Power Supply
Audio I/F Format : MSB justified
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
(3)
PMVCM bit
(Addr:00H, D6)
PMPLL bit
(2) Addr:04H, Data:32H
Addr:05H, Data:27H
(Addr:01H, D0)
LRCK pin
BICK pin
Input
(3) Addr:00H, Data:40H
(4)
Internal Clock
(5)
(4) Addr:01H, Data:01H
Figure 75. Clock Set Up Sequence (2)
<
>
PDN pin “L” Æ “H”
AK4343
150ns
“L”
(2)
DIF1-0, FS3-0, PLL3-0 bits
(3) VCOM
: PMVCM bit = “0” Æ “1”
VCOM
(4) PMPLL bit “0” Æ “1”
PLL
(LRCK or BICK pin)
PLL
LRCK PLL
2ms(max)
(5) PLL
(1)
MS0478-J-02
PLL
160ms(max), BICK
PLL
2010/11
- 85 -
[AK4343]
3. PLL
(MCKI pin)
Example:
Audio I/F Format: MSB justified
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(3)
(2)Addr:04H, Data:4AH
Addr:05H, Data:27H
PMVCM bit
(Addr:00H, D6)
(4)
MCKO bit
(Addr:01H, D1)
(3)Addr:00H, Data:40H
PMPLL bit
(Addr:01H, D0)
(5)
MCKI pin
(4)Addr:01H, Data:03H
Input
40msec(max)
(6)
MCKO pin
MCKO output start
Output
(7)
(8)
BICK pin
LRCK pin
BICK and LRCK input start
Input
Figure 76. Clock Set Up Sequence (3)
<
>
PDN pin “L” Æ “H”
AK4343
150ns
(2)
DIF1-0, PLL3-0, FS3-0 bits
(3) VCOM
PMVCM bit = “0” Æ “1”
VCOM
(4) MCKO
: MCKO bit = “1”
(5) PMPLL bit “0” Æ “1”
MCKI pin
PLL
40ms(max)
(6) PLL
MCKO pin
(7)
MCKO pin
(8) MCKO
BICK, LRCK
(1)
MS0478-J-02
“L”
PLL
2010/11
- 86 -
[AK4343]
4.
(
)
Example:
Audio I/F Format: MSB justified
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(2) Addr:04H, Data:02H
Addr:05H, Data:00H
(3)
PMVCM bit
(Addr:00H, D6)
(4)
MCKI pin
Input
(3) Addr:00H, Data:40H
(4)
LRCK pin
BICK pin
Input
MCKI, BICK and LRCK input
Figure 77. Clock Set Up Sequence (4)
<
>
PDN pin “L” Æ “H”
AK4343
150ns
(2)
DIF1-0, FS1-0 bits
(3) VCOM
PMVCM bit = “0” Æ “1”
VCOM
(4) MCKI, LRCK, BICK
(1)
MS0478-J-02
“L”
2010/11
- 87 -
[AK4343]
5.
(
)
Example:
Audio I/F Format: MSB justified
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
(1) Power Supply & PDN pin = “L” Æ “H”
Power Supply
(1)
PDN pin
(2) MCKI input
(4)
PMVCM bit
(Addr:00H, D6)
(3) Addr:04H, Data:02H
Addr:05H, Data:00H
Addr:01H, Data:08H
(2)
MCKI pin
Input
(3)
M/S bit
BICK and LRCK output
(Addr:01H, D3)
LRCK pin
BICK pin
Output
(4) Addr:00H, Data:40H
Figure 78. Clock Set Up Sequence (5)
<
>
(1)
PDN pin “L” Æ “H”
AK4343
150ns
(2) MCKI
(3) DIF1-0, FS1-0 bits
(4) VCOM
M/S bit “1”
PMVCM bit = “0” Æ “1”
VCOM
MS0478-J-02
“L”
LRCK
BICK
2010/11
- 88 -
[AK4343]
■
FS3-0 bits
(Addr:05H, D5&D2-0)
0,000
1,111
Example:
(1)
PLL Master Mode
Audio I/F Format: MSB justified
Sampling Frequency: 44.1kHz
Digital Volume: -8dB
ALC: Enable
(13)
DACS bit
(Addr:02H, D5)
(2)
SPKG1-0 bits
(Addr:03H, D4-3)
ALC Control 1
(Addr:06H)
ALC Control 2
(Addr:08H)
ALC Control 3
(Addr:0BH)
(1) Addr:05H, Data:27H
00
01
(2) Addr:02H, Data:20H
(3)
00H
3CH
(3) Addr:03H, Data:08H
(4)
E1H
C1H
(4) Addr:06H, Data:3CH
(5)
00H
00H
(5) Addr:08H, Data:E1H
1
(6) Addr:0BH, Data:00H
(6)
ALC bit
(Addr:07H, D5)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
0
(7)
E1H
(7) Addr:07H, Data:20H
91H
(8)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
18H
(8) Addr:09H & 0CH, Data:91H
28H
(9)
(14)
PMDAC bit
(9) Addr:0AH & 0DH, Data:28H
(Addr:00H, D2)
(10) Addr:00H, Data:74H
PMMIN bit
(Addr:00H, D5)
(11) Addr:02H, Data:A0H
(10)
PMSPK bit
(Addr:00H, D4)
Playback
(11)
SPPSN bit
(Addr:02H, D7)
(12) Addr:02H, Data:20H
(12)
SPP pin
Hi-Z
Normal Output
Hi-Z
(13) Addr:02H, Data:00H
SPN pin
Hi-Z
HVDD/2 Normal Output HVDD/2
Hi-Z
(14) Addr:00H, Data:40H
Figure 79. Speaker-Amp Output Sequence
<
>
(1)
(FS3-0 bits)
PLL
PLL
(5) DAC
(2) DAC Æ SPK-Amp
: DACS bit = “0” Æ “1”
(3) SPK-Amp
: SPKG1-0 bits = “00”
“01”
(4) ALC Timer (
06H)
(5) ALC REF (
08H)
(6) LMTH1, RGAIN1 bits
(
0BH)
(7) LMTH0, RGAIN0, LMAT1-0, ALC bits
(
07H)
(8) ALC
(
09H&0CH)
AVL7-0 = AVR7-0 bits = “91H”(0dB)
(9)
(
0AH&0DH)
DVOLC bit = “1”(default)
DVL7-0bits(0AH) Lch
Rch
DAC
Default (0dB)
(10) DAC, MIN-Amp
: PMDAC = PMMIN = PMSPK bits = “0” → “1”
([email protected]=44.1kHz) DAC
2’s
DAC
([email protected]=44.1kHz)
ALC bit = “1”
(1059/fs = 24ms @fs=44.1kHz) ALC
(ALC
AVL/R7-0 bits
ALC AVL/R7-0 bits
(11)
: SPPSN bit = “0” → “1”
(12)
: SPPSN bit = “1” → “0”
(13) DAC Æ SPK-Amp
Disable: DACS bit = “1” Æ “0”
(14) DAC, MIN-Amp
: PMDAC = PMMIN = PMSPK bits = “1” → “0”
MS0478-J-02
“0”
DAC
)
2010/11
- 89 -
[AK4343]
■
Mono
Example:
Clocks can be stopped.
CLOCK
(1) Addr:00H, Data:70H
PMMIN bit
(Addr:00H, D5)
(1)
(5)
(2) Addr:02H, Data:60H
PMSPK bit
(Addr:00H, D4)
DACS bit
(Addr:02H, D5)
(3) Addr:02H, Data:E0H
1
0
(2)
(6)
MINS bit
Mono Signal Output
(Addr:02H, D6)
(3)
SPPSN bit
(4) Addr:02H, Data:60H
(Addr:02H, D7)
(4)
SPP pin
SPN pin
Hi-Z
Hi-Z
Normal Output
HVDD/2
Normal Output
Hi-Z
HVDD/2
(5) Addr:00H, Data:40H
Hi-Z
(6) Addr:02H, Data:00H
Figure 80. “MIN-Amp Æ Speaker-Amp” Output Sequence
<
>
“MIN-Amp Æ SPK-Amp”
(1) MIN-Amp
(2) DAC Æ SPK-Amp
MIN Æ SPK-Amp
(3)
(4)
(5) MIN-Amp
(6) MIN Æ SPK-Amp
: PMMIN = PMSPK bits = “0” → “1”
Disable: DACS bit = “0”
Enable: MINS bit = “0” → “1”
: SPPSN bit = “0” → “1”
: SPPSN bit = “1” → “0”
: PMMIN = PMSPK bits = “1” → “0”
Disable: MINS bit = “1” → “0”
MS0478-J-02
2010/11
- 90 -
[AK4343]
■
Example:
FS3-0 bits
(Addr:05H, D5&D2-0)
0,000
(1)
DACH bit
(2)
(Addr:0FH, D0)
BST1-0 bits
(Addr:0EH, D3-2)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
PLL, Master Mode
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: −8dB
Bass Boost Level : Midddle
1,111
(13)
00
10
00
(3)
(12)
E1H
91H
(1) Addr:05H, Data:27H
(2) Addr:0FH, Data:09H
(3) Addr:0EH, Data:19H
(4) Addr:09H&0CH, Data:91H
(4)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
(5) Addr:0AH&0DH, Data:28H
18H
28H
(6) Addr:00H, Data:64H
(5)
PMDAC bit
(7) Addr:01H, Data:39H
(Addr:00H, D2)
(6)
(11)
(8) Addr:01H, Data:79H
PMMIN bit
(Addr:00H, D5)
PMHPL/R bits
Playback
(7)
(10)
(9) Addr:01H, Data:39H
(Addr:01H, D5-4)
(10) Addr:01H, Data:09H
HPMTN bit
(8)
(9)
(11) Addr:00H, Data:40H
(Addr:01H, D6)
HPL/R pins
Normal Output
(12) Addr:0EH, Data:11H
(13) Addr:0FH, Data:08H
Figure 81. Headphone-Amp Output Sequence
<
>
(1)
(FS3-0 bits)
PLL
PLL
(5) DAC
(2) DAC Æ HP-Amp
: DACH bit = “0” → “1”
(3)
(BST1-0 bits)
(4) ALC
(
09H&0CH)
AVL7-0 = AVR7-0 bits = “91H”(0dB)
(5)
(
0AH&0DH)
DVOLC bit = “1”(default)
DVL7-0bits(0AH) Lch
Rch
DAC
Default (0dB)
(6) DAC
MIN-Amp
: PMDAC = PMMIN bits = “0” → “1”
([email protected]=44.1kHz) DAC
2’s
DAC
([email protected]=44.1kHz)
ALC bit = “1”
(ALC
AVL/R7-0 bits
(1059/fs = 24ms @fs=44.1kHz) ALC
ALC AVL/R7-0 bits
(7)
: PMHPL = PMHPR bits = “0” → “1”
HVSS
(8)
: HPMTN bit = “0” → “1”
MUTET pin
HVDD
MUTET pin
τr =100ms(typ), 250ms(max)
= 1μF, HVDD=3.3V
(9)
: HPMTN bit = “1” → “0”
MUTET pin
HVDD
MUTET pin
τf =100ms(typ), 250ms(max)
= 1μF, HVDD=3.3V
HVSS
HVSS
2
“0”
DAC
)
C
C
(10)
: PMHPL = PMHPR bits = “1” → “0”
(11) DAC
MIN-Amp
: PMDAC = PMMIN bits = “1” → “0”
(12)
OFF: BST1-0 bits = “00”
(13) DAC Æ HP-Amp
Disable: DACH bit = “1” → “0”
MS0478-J-02
2010/11
- 91 -
[AK4343]
■
Example:
FS3-0 bits
(Addr:05H, D5&D2-0)
0,000
PLL, Master Mode
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: −8dB
LOVL=MINL bits = “0”
1,111
(1)
(1) Addr:05H, Data:27H
(10)
DACL bit
(2)
(2) Addr:02H, Data:10H
(Addr:02H, D4)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
E1H
(3) Addr:09H&0CH, Data:91H
91H
(3)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
(4) Addr:0AH&0DH, Data:28H
18H
28H
(5) Addr:03H, Data:40H
(4)
LOPS bit
(6) Addr:00H, Data:6CH
(Addr:03H, D6)
(7)
(5)
(8)
(11)
PMDAC bit
(Addr:00H, D2)
(7) Addr:03H, Data:00H
Playback
PMMIN bit
(8) Addr:03H, Data:40H
(Addr:00H, D5)
(6)
(9)
(9) Addr:00H, Data:40H
PMLO bit
(Addr:00H, D3)
>300 ms
(10) Addr:02H, Data:00H
LOUT pin
ROUT pin
>300 ms
Normal Output
(11) Addr:03H, Data:00H
Figure 82. Stereo Lineout Sequence
<
>
(1)
(FS3-0 bits)
PLL
PLL
DAC
: DACL bit = “0” Æ “1”
09H&0CH)
(5)
(2) DAC Æ
(3) ALC
(
AVL7-0 = AVR7-0 bits = “91H”(0dB)
(4)
(
0AH&0DH)
DVOLC bit = “1”(default)
DVL7-0bits(0AH) Lch
Rch
DAC
Default (0dB)
(5)
: LOPS bit = “0” Æ “1”
(6) DAC, MIN-Amp
: PMDAC = PMMIN = PMLO bits = “0” → “1”
([email protected]=44.1kHz) DAC
2’s
“0”
DAC
([email protected]=44.1kHz)
DAC
ALC bit = “1”
(1059/fs = 24ms @fs=44.1kHz) ALC
(ALC
AVL/R7-0 bits
)
ALC AVL/R7-0 bits
PMLO bit = “1” LOUT, ROUT pins
C = 1μF, AVDD=3.3V
max. 300ms
(7)
: LOPS bit = “1” Æ “0”
LOUT, ROUT pins
LOUT, ROUT pins
: LOPS bit: “0” Æ “1”
: PMDAC = PMMIN = PMLO bits = “1” → “0”
C = 1μF, AVDD=3.3V
max. 300ms
(8)
(9) DAC, MIN-Amp
LOUT, ROUT pins
(10) DAC Æ
(11)
LOUT, ROUT pins
Disable: DACL bit = “1” Æ “0”
: LOPS bit = “1” Æ “0”
MS0478-J-02
2010/11
- 92 -
[AK4343]
■
Example:
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: −8dB
LOVL = MINL bits = “0”
(1) Addr:05H, Data:27H
FS3-0 bits
(Addr:05H, D5&D2-0)
0,000
1,111
(2) Addr:21H, Data:01H
(1)
RCV bit
(3) Addr:02H, Data:10H
(2)
(Addr:21H, D0)
(10)
DACL bit
(4) Addr:03H, Data:40H
(Addr:02H, D4)
(3)
IVL/R7-0 bits
E1H
(Addr:09H&0CH, D7-0)
(5) Addr:09H & 0CH, Data:91H
91H
(5)
DVL/R7-0 bits
18H
(Addr:0AH&0DH, D7-0)
(6) Addr:0AH & 0DH, Data:28H
28H
(6)
(11)
(7) Addr:00H, Data:6CH
PMDAC bit
(Addr:00H, D2)
PMMIN bit
(8) Addr:03H, Data:00H
(Addr:00H, D5)
(7)
PMLO bit
Playback
(Addr:00H, D3)
(8)
LOPS bit
(4)
(9) Addr:03H, Data:40H
(Addr:03H, D6)
(9)
RCP pin
RCN pin
Hi-Z
Hi-Z
Normal Output
(10) Addr:02H, Data:00H
Hi-Z
VCOM Normal Output VCOM
Hi-Z
(11) Addr:00H, Data:40H
Figure 83. Receiver-Amp Output Sequence
<
>
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(FS3-0 bits)
PLL
PLL
(5) DAC
DAC Æ RCV-Amp
: DACL=LOPS bit = “0” Æ “1”
RCV-Amp
: RCV bit = “1”
DAC Æ RCV-Amp
: DACL bit = “0” Æ “1”
: LOPS bit = “0” Æ “1”
ALC
(
09H&0CH)
AVL7-0 = AVR7-0 bits = “91H”(0dB)
(
0AH&0DH)
DVOLC bit = “1”(default)
DVL7-0bits(0AH) Lch
Rch
DAC
Default (0dB)
DAC, MIN-Amp
: PMDAC = PMMIN = PMLO bits = “0” → “1”
([email protected]=44.1kHz) DAC
2’s
“0”
DAC
([email protected]=44.1kHz)
DAC
(9)
(10)
(11) DAC Æ RCV-Amp
(12) DAC, MIN-Amp
: LOPS bit = “1” → “0”
: LOPS bit = “0” → “1”
Disable: DACL bit = “1” Æ “0”
: PMDAC = PMMIN = PMLO bits = “1” → “0”
MS0478-J-02
2010/11
- 93 -
[AK4343]
■
DAC
1. PLL
Example:
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
(1)
PMPLL bit
(Addr:01H, D0)
(2)
MCKO bit
"1" or "0"
(1) (2) Addr:01H, Data:08H
(Addr:01H, D1)
(3)
External MCKI
Input
(3) Stop an external MCKI
Figure 84. Clock Stopping Sequence (1)
<
>
(1) PLL
(2) MCKO
(3)
2. PLL
: PMPLL bit = “1” → “0”
: MCKO bit = “1” → “0”
(LRCK, BICK pin)
Example
Audio I/F Format : MSB justified
PLL Reference clock: BICK
BICK frequency: 64fs
(1)
PMPLL bit
(Addr:01H, D0)
(2)
External BICK
Input
(1) Addr:01H, Data:00H
(2)
External LRCK
Input
(2) Stop the external clocks
Figure 85. Clock Stopping Sequence (2)
<
>
(1) PLL
(2)
3. PLL
: PMPLL bit = “1” → “0”
(MCKI pin)
Example
(1)
Audio I/F Format: MSB justified
PLL Reference clock: MCKI
BICK frequency: 64fs
PMPLL bit
(Addr:01H, D0)
(1)
MCKO bit
(1) Addr:01H, Data:00H
(Addr:01H, D1)
(2)
External MCKI
Input
(2) Stop the external clocks
Figure 86. Clock Stopping Sequence (3)
<
>
(1) PLL
MCKO
(2)
: PMPLL bit = “1” → “0”
: MCKO bit = “1” → “0”
MS0478-J-02
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[AK4343]
4.
(1)
External MCKI
Input
Example
(1)
External BICK
Input
External LRCK
Input
Audio I/F Format :MSB justified
Input MCKI frequency:1024fs
(1)
(1) Stop the external clocks
Figure 87. Clock Stopping Sequence (4)
<
>
(1)
5.
(1)
External MCKI
Input
Example
BICK
Output
"H" or "L"
LRCK
Output
"H" or "L"
Audio I/F Format :MSB justified
Input MCKI frequency:1024fs
(1) Stop the external MCKI
Figure 88. Clock Stopping Sequence (5)
<
>
(1) MCKI
BICK
LRCK
“H”
“L”
■
10μA)
PMVCM bit = “0”
PDN pin = “L”
MS0478-J-02
(typ.
(typ. 10μA)
2010/11
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[AK4343]
32pin QFN (Unit: mm)
5.00 ± 0.10
0.40 ± 0.10
4.75 ± 0.10
24
17
16
4.75 ± 0.10
5.00 ± 0.10
25
3.5
B
9
32
1
1
3.5
0.50
+0.07
-0.05
32
C0.42
8
A
0.23
Exposed
Pad
0.85 ± 0.05
0.10 M AB
0.08 C
:
0.04
0.01+- 0.01
0.20
C
(Exposed Pad)
(Note 7
)
■
:
:
:
MS0478-J-02
2010/11
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[AK4343]
(AK4343EN)
AKM
AK4343
XXXXX
1
XXXXX : Date code identifier (5
)
(AK4343VN)
AKM
4343VN
XXXXX
1
XXXXX : Date code identifier (5
MS0478-J-02
)
2010/11
- 97 -
[AK4343]
Date
06/04/04
06/10/24
Revision
00
01
Reason
Page
Contents
35-36
Table 20
“X”
Table 20(Handling of Line Input Pins)
53
: PMLO bit = “1” Æ PMLO bit = “0”
65
2
IC
3
Æ
“0”
2
“0”
75
HPM bit:
Æ
87
88
06/10/24
01
91
94
10/12/02
02
(Addr=0FH)
HPM bit = “1”
(L+R)/2
HPM bit = “1”
PMHPL = PMHPR bits = “1”
HPM bit = “1”
DAC
(L+R)/2
(Clock Setup: Ext Slave Mode)
MCLK Frequency: 1024fs Æ 256fs
Addr=05H: Data=27H Æ 00H
(Clock Setup: Ext Master Mode)
MCLK Frequency: 1024fs Æ 256fs
Addr=05H: Data=27H Æ 00H
(Headphone Playback)
Digital Volume Level: 0dB Æ −8dB
Addr=0EH: Data=14H Æ 19H
Figure 81: (12) Addr=0EH: Data=00H Æ 11H
(Clock Stop: PLL Master Mode)
MCKO bit = “H” or “L” Æ “1” or “0”
AK4343VN
MS0478-J-02
2010/11
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[AK4343]
z
z
z
z
z
z
MS0478-J-02
2010/11
- 99 -