Data Sheet

[AK4712]
AK4712
Stereo Cap-less LINE-Amp and HD Video-Amp
GENERAL DESCRIPTION
The AK4712 is a High Definition A/V cap-less line driver. The AK4712 integrates the audio line driver,
SD/HD video filters and video drivers. Its A/V outputs are Ground-referenced and eliminate the need for
large A/V DC-blocking capacitors with a built-in Charge-pump circuit. The AK4712 achieves excellent A/V
performance by single 3.3V power supply. The AK4712 is ideal for a wide range of consumer HD
applications, such as portable A/V players, set-top boxes, and Blu-ray/DVD player systems. The AK4712
is offered in a space saving 28pin QFN package.
FEATURES
Audio section
† THD+N: −102dB (@2Vrms)
† Dynamic Range: 108dB (@2Vrms, A-weighted)
† Full Differential (or Single-ended) input for Decoder DAC
† Stereo Output for CINCH (2Vrms)
† Ground-Referenced Output Eliminates
DC-Blocking Capacitor and Mute Circuit
Video section
† Integrated LPF
SD: [email protected]
HD: [email protected] ,[email protected] or 27MHz selectable
† 6dB Gain for Outputs
† 4ch 75ohm driver
3ch for HD: Y/Pb/Pr
1ch for CINCH: CVBS
Power supply
† 3.3V+/−5%
† Low Power Standby Mode
Package
† 28pin QFN (0.4mm pitch)
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[AK4712]
■ Block Diagram
RFB
RFB
CIN
RIN
AINLN
TVOUTL
RIN
AINLP
CIN
CINCH Audio
AMP
RFB
RIN
CIN
TVOUTR
AINRP
RIN
CIN
RIN
Audio Block
AINRN
DETN (Power Management)
ENCRCA
ENCY
Video
Detect
6dB
Video
Detect
6dB
ENCPB
6dB
ENCPR
6dB
RCAVOUT
CINCH Video
HDY
HDPB
HD Video
HDPR
Video Block
SCL
Register
Control
I2CSEL
VVD
Charge Pump
SDA/MUTEN
PDN
VD2
CP
CN
VCP VCN
VVEE
VREG
VSS
MS1509-E-00
VEE
VSS
VD1
VSS
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[AK4712]
■ Ordering Guide
AK4712EN
AKD4712
-10 ∼ +70°C (when both SD and HD video are used)
-10 ∼ +85°C (when HD Video is not used)
28pin QFN (0.4mm pitch)
Evaluation board for AK4712
AINLP
AINLN
TVOUTL
I2CSEL
TVOUTR
AINRN
AINRP
21
20
19
18
17
16
15
■ Pin Layout
VEE 22
14
PDN
CN 23
13
SCL
12
SDA/MUTEN
11
ENCY
10
ENCPR
9
ENCPB
8
ENCRCA
CP 24
AK4712
VD1 25
Top View
VD2 26
VCP 27
Exposed Pad
1
2
3
4
5
6
7
VVEE
VREG
HDY
HDPR
HDPB
RCAVOUT
VVD
VCN 28
Note 1. The exposed pad on the bottom surface of the package must be connected to VSS.
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[AK4712]
PIN/FUNCTION
No.
Pin Name
I/O
1
VVEE
O
2
VREG
O
3
4
5
6
HDY
HDPR
HDPB
RCAVOUT
O
O
O
O
7
VVD
-
8
9
10
11
ENCRCA
ENCPB
ENCPR
ENCY
I
I
I
I
12
SDA/MUTEN
I
13
SCL
I
14
PDN
I
15
16
17
AINRP
AINRN
TVOUTR
I
I
O
18
I2CSEL
I
19
20
21
TVOUTL
AINLN
AINLP
O
I
I
Function
Video Negative Voltage Output Pin
Connect to ground via a 1.0 μF low ESR (Equivalent Series Resistance) capacitor
over temperature. When this capacitor is polarized, the positive polarity pin should
be connected to the ground pin. Non-polarized capacitors can also be used.
Internal regulator output Pin for Video Charge Pump.
Connect to ground via a 1.0 μF low ESR (Equivalent Series Resistance) capacitor
over temperature. When this capacitor is polarized, the positive polarity pin should
be connected to the ground pin. Non-polarized capacitors can also be used.
Green/Y Output Pin
Red/Pr Output Pin
Blue/Pb Output Pin
Composite Output Pin for RCA
Video Power Supply Pin: 3.13V ~ 3.47V
Normally connected to ground via a 0.1μF ceramic capacitor in parallel with a 4.7μF
electrolytic capacitor.
Composite Input Pin for RCA
Blue/Pb Input Pin for Encoder
Red/Pr Input Pin for Encoder
Green/Y Input Pin for Encoder
I2CSEL= “L”: Audio Mute Pin
I2CSEL= “H”: Control Data Input Pin
Control Data Clock Input Pin
When I2CSEL=”L”, SCL pin must be connected to PDN pin.
Power-Down Mode Pin
When at “L”, the AK4712 is in the power-down mode and is held in reset. The
AK4712 should always be reset upon power-up.
Rch Positive Analog Input Pin
Rch Negative Analog Input Pin
Rch Analog Output Pin
I2C Control Enable Pin
L: Disable
H: Enable
Lch Analog Output Pin
Lch Negative Analog Input Pin
Lch Positive Analog Input Pin
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[AK4712]
Audio Negative Voltage Output Pin
Connect to ground via a 1.0 μF low ESR (Equivalent Series Resistance) capacitor
22 VEE
O
over temperature. When this capacitor is polarized, the positive polarity pin should
be connected to the ground pin. Non-polarized capacitors can also be used.
Audio Negative Charge Pump Capacitor Terminal Pin
Connect to the CP pin via a 1.0 μF low ESR (Equivalent Series Resistance)
23 CN
I
capacitor over temperature. When this capacitor is polarized, the positive polarity
pin should be connected to the CP pin. Non-polarized capacitors can also be used.
Audio Positive Charge Pump Capacitor Terminal Pin
24 CP
I
Refer to the CN pin.
Audio Power Supply Pin: 3.13V ~ 3.47V
25 VD1
Normally connected to VSS via a 0.1μF ceramic capacitor in parallel with a 4.7μF
electrolytic capacitor.
Video Charge Pump Power Supply Pin: 3.13V ~ 3.47V
26 VD2
Normally connected to VSS via a 0.1μF ceramic capacitor in parallel with a 4.7μF
electrolytic cap.
Video Negative Charge Pump Capacitor Terminal Pin
Connect to the VCN pin via a 1.0 μF low ESR (Equivalent Series Resistance)
27 VCP
I
capacitor over temperature. When this capacitor is polarized, the positive polarity pin
should be connected to the VCP pin. Non-polarized capacitors can also be used.
Video Positive Charge Pump Capacitor Terminal Pin
28 VCN
I
Refer to the VCP pin.
Analog Ground
VSS
The exposed pad on the bottom surface of the package must be connected to the
( Exposed Pad)
ground.
Note: All digital input pins must not be allowed to float.
■Handling of Unused Pin
Unused I/O pins must be connected appropriately.
Classification
Analog
Digital
Pin Name
AINLN, AINLP, AINRP, AINRN, ENCPB, ENCPR
ENCRCA, ENCY
TVOUTL, TVOUTR, RCAVOUT, HDY, HDPB, HDPR
Setting
Open
VVD
Open
SCL
Connect to PDN pin
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[AK4712]
ABSOLUTE MAXIMUM RATINGS
(VSS = 0V; Note 2)
Parameter
Power Supply
Input Current (any pins except for supplies)
Digital Input Voltage(PDN, I2CSEL pins)
Digital Input Voltage
(SCL, SDA/MUTEN pins)
Video Input Voltage
Audio Input Voltage
(Note 3)
Ambient Operating Temperature
Symbol
VD1
VD2
VVD
IIN
VIND1
min
−0.3
−0.3
−0.3
−0.3
max
4.0
4.0
4.0
±10
VVD+0.3
Unit
V
V
V
mA
V
VIND2
−0.3
4.0
V
−0.3
VEE-0.3
VVD+0.3
VD1+0.3
70
85
150
V
V
VINV
VINA
Ta
(Note 4)
Ta
(Note 5)
Tstg
−10
Storage Temperature
−65
Note 2. All voltages with respect to ground.
Note 3. VEE: VEE pin voltage.
The internal negative power supply generating circuit provides negative power supply (VEE).
The PDN pin and MUTEN bit control operation mode as shown in Table 2.
0
1
2
3
4
Mode
Full Power-down
Mute and Video power down No video
(AMP power down)
input
Mute and Video power up
Video
(AMP power down)
input
Normal operation
No video
(AMP operation)
input
Normal operation
Video
(AMP operation)
input
Table 1. VEE pin voltage
°C
°C
VEE pin Voltage
0V
0V
0V
-VD2+0.2V
-VD2+0.2V
Note 4. When both SD and HD video are used.
Note 5. When HD video is not used.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
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[AK4712]
RECOMMENDED OPERATING CONDITIONS
(VSS = 0V; Note 2)
Parameter
Power Supply
(Note 6)
Symbol
VD1
VD2
VVD
Note 2. All voltages with respect to ground.
Note 6. VVD must be connected to the same voltage.
min
3.13
3.13
3.13
typ
3.3
3.3
3.3
max
3.47
3.47
3.47
Unit
V
V
V
*AKM assumes no responsibility for the usage beyond recommended operating conditions in this datasheet.
ELECTRICAL CHARACTERISTICS
(Ta = 25°C; VD1=VD2=VVD= 3.3V)
Power Supplies
min
typ
max
Unit
Power Supply Current
Normal Operation (PDN = “H”)
mA
VD1+VD2+VVD
(With load, Note 7)
100
136
mA
VD1+VD2+VVD
(With load, Note 8)
28.0
Standby Mode (PDN = “H”)
(Note 9)
mA
VD1+VD2+VVD
1.2
1.7
Power-Down Mode (PDN = “L”)
(Note 10)
VD1+VD2
0
10
μA
VVD
0
10
μA
Note 7. MUTEN bit = “1”, SDAPW bit = HDAPW bit = “1”, Audio Output:1kHz 2Vrms output with 4.5kΩ load at all
audio output pins, 100% color bar output with 150Ω load at all video output pins..
Note 8. When HD video is not used.
Note 9. MUTEN bit = “0”, SDAPW bit = HDAPW bit = “1”, No video signal.
Note 10. All digital inputs are held at VD1 or VSS. No signal, no load.
DIGITAL CHARACTERISTICS
(Ta = 25°C; VD1=VD2=VVD= 3.13 ∼ 3.47V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%VD1
Low-Level Input Voltage
VIL
Low-Level Output Voltage
VOL
(SDA pin: Iout= 3mA)
Input Leakage Current
Iin
-
MS1509-E-00
typ
-
max
30%VD1
0.4
Unit
V
V
V
-
± 10
μA
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[AK4712]
ANALOG CHARACTERISTICS (AUDIO)
(Ta=25°C; VD1=VD2=VVD= 3.3V; Signal Frequency=1kHz; Measurement frequency=20Hz ∼ 20kHz; RL ≥4.5kΩ;
2Vrms output; RIN=10 kΩ, RFB=20 kΩ, unless otherwise specified)
Parameter
min
typ
max
Unit
Analog Input: (AINLP/AINLN/AINRN/AINRP pins)
Analog Input Characteristics (Note 11)
Input Resistance RIN
1
10
47
kΩ
4.7
20
100
Feedback Resistance RFB
kΩ
Stereo Output: (TVOUTL/TVOUTR pins)
(Note 12)
Analog Output Characteristics
Output Voltage
(Note 13)
2.0
Vrms
-80
dB
THD+N
(at 2Vrms output, Note 14, Note 15)
−102
98
108
dB
Dynamic Rang (−60dB Output, A-weighted, Note 14)
S/N
(A-weighted, Note 14, Note 17)
98
108
dB
Interchannel Isolation
(Note 14)
90
100
dB
DC offset
(Note 16)
-5
0
+5
mV
Load Resistance
TVOUTL/R
4.5
kΩ
Load Capacitance
TVOUTL/R
20
pF
Power Supply Rejection (PSRR)
(Note 18)
70
dB
Note 11. Gain setting by RIN and RFB. It must be in a rage from 0dB to 24dB.
Note 12. Measured by Audio Precision System Two Cascade.
Note 13. f = 1kHz, THD+N = -102dB
Note 14. Analog In to TVOUT. Path : AINLP/N → TVOUTL, AINRP/N → TVOUTR, RIN=10 kΩ, RFB=20 kΩ.
At 2Vrms single input, THD+N is -100dB (typ), on path AINLP → TVOUTL, AINRP → TVOUTR,
Volume=0dB
Note 15. -82dB (typ) referred to 0.5Vrms output level. RIN=4.7 kΩ, RFB=47 kΩ
: path = AINLP/N → TVOUTL, AINRP/N → TVOUTR.
Note 16. Analog In to TVOUT.
Path : AINLP/N → TVOUTL, AINRP/N → TVOUTR
Note 17. 86dB (typ), referred to 0.5Vrm output level at Gain = +20dB. RIN=4.7 kΩ, RFB=47 kΩ
: path = AINLP/N → TVOUTL, AINRP/N → TVOUTR.
Note 18. The PSRR is applied to VD1 and VD2 and VVD with 1kHz, 100mV.
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[AK4712]
ANALOG CHARACTERISTICS (SD VIDEO)
(Ta = 25°C; VD1=VD2= VVD= 3.3V; unless otherwise specified.)
Parameter
Conditions
min
External Resistance
35
External Capacitance
0.05
Gain
Input = 0.3Vp-p, 100kHz
5.5
Frequency Response
Input=0.3Vp-p, C1=C2=0pF. 100kHz to 6MHz.
-1.0
at 10MHz.
at 27MHz.
-100
Pedestal Level
Video Input
Group Delay Distortion
At 4.43MHz with respect to 1MHz.
(Note 19)
typ
-3
-40
-25
0
100
Unit
Ω
μF
dB
dB
dB
dB
mV
20
ns
0.1
6
max
1000
0.2
6.5
0.5
Input Impedance (Note 20)
Input Signal
Chrominance input (internally biased)
80
100
kΩ
f = 100kHz, maximum with distortion < 1.0%,
1.25
Vpp
gain = 6dB.
Load Resistance
150
(Figure 1)
Ω
400
pF
Load Capacitance
C1 (Figure 1)
15
pF
C2 (Figure 1)
Dynamic Output Signal
f = 100kHz, maximum with distortion < 1.0%
2.5
Vpp
Y/C Crosstalk (Note 20)
f = 4.43MHz, 1Vp-p input. Among HDY and
-50
dB
ENCPB outputs.
S/N
Reference Level = 0.7Vp-p, CCIR 567 weighting.
74
dB
BW = 15kHz to 5MHz.
Differential Gain
0.7Vpp 5steps modulated staircase.
1.3
%
chrominance &burst are 280mVpp, 4.43MHz.
Differential Phase
0.7Vpp 5steps modulated staircase.
1.4
Degree
chrominance &burst are 280mVpp, 4.43MHz.
Power Supply Rejection (PSRR)
(Note 21)
45
dB
Note 19 HDY/HDPB/HDPR Group Delay Distortion when FL1-0 bits= “00”
Note 20. When CLAMP2 bit = “0”, CLAMP1 bit = “1” for Y/C, Y signal is input to the ENCY pin and C signal is input
to the ENCPB pin.
Note 21. The PSRR is applied to VD1 and VD2 and VVD and with 100kHz, 100mV.
.
R1
75 ohm
Video Signal Output
R2
75 ohm
C1
C2
max: 15pF
max: 400pF
Figure 1. Load Resistance R1+R2 and Load Capacitance C1/C2.
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[AK4712]
ANALOG CHARACTERISTICS (HD VIDEO)
(Ta = 25°C; VD1=VD2=VVD= 3.3V, unless otherwise specified.)
Parameter
Conditions
min
External Resistance
35
External Capacitance
0.05
Gain
Input=0.3Vp-p, 100kHz
5.5
Frequency response
Input=0.3Vp-p,
FL1-0 bits = “10”
C1=C2=0pF
100kHz to 23MHz,
-1.0
(Figure 1)
at 30MHz.
at 74.25MHz.
FL1-0 bits = “01”
100kHz to 15MHz,
at 54MHz.
FL1-0 bits = “00”
100kHz to 6MHz,
at 27MHz.
Pedestal Level
Group Delay Distortion
(Note 22)
Input Signal
Video Input
At 4.43MHz with respect to 1MHz.
Crosstalk
Load Resistance
Load Capacitance
at 1MHz
Dynamic Output Signal
S/N
-100
(Figure 1)
(Figure 1)
(Figure 1)
max
1000
0.2
6.5
Unit
Ω
μF
dB
1.3
-1.0
-36
-25
dB
dB
dB
-40
1.0
-25
dB
dB
-40
0.5
-25
0
100
20
dB
dB
mV
ns
-1.0
Reference Level = 0.7Vp-p, unweighted.
BW = 100kHz to 30MHz.
Differential Gain
0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz.
FL1-0 bits = “00”
Differential Phase
0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz.
FL1-0 bits = “00”
Power Supply Rejection (PSRR)
(Note 21)
Note 22 HDY/HDPB/HDPR Group Delay Distortion when FL1-0 bits = “10”
MS1509-E-00
0.1
6
-1.0
f=100kHz, distortion < 1.0%, gain=6dB
C1
C2
f=100kHz, distortion < 1.0%
typ
-
-
1.25
Vpp
150
-60
-
-
-
400
10
2.5
dB
Ω
pF
pF
Vpp
-
61
-
dB
-
1.0
-
%
-
0.6
-
Degree
-
45
dB
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[AK4712]
SWITCHING CHARACTERISTICS
(Ta = 25°C; VD1=VD2= VVD= 3.13 ∼ 3.47V)
Parameter
Symbol
min
typ
max
Unit
Control Interface Timing (I2C Bus):
SCL Clock Frequency
fSCL
400
kHz
Bus Free Time Between Transmissions
tBUF
1.3
μs
Start Condition Hold Time
tHD:STA
0.6
μs
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
μs
Clock High Time
tHIGH
0.6
μs
Setup Time for Repeated Start Condition
tSU:STA
0.6
μs
SDA Hold Time from SCL Falling (Note 23) tHD:DAT
0
μs
SDA Setup Time from SCL Rising
tSU:DAT
0.1
μs
Rise Time of Both SDA and SCL Lines
tR
0.3
μs
Fall Time of Both SDA and SCL Lines
tF
0.3
μs
Setup Time for Stop Condition
tSU:STO
0.6
μs
Pulse Width of Spike Noise
tSP
0
50
ns
Suppressed by Input Filter
Capacitive load on bus
Cb
400
pF
Reset Timing
tPD
150
ns
PDN Pulse Width
(Note 24)
Note 23. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 24. The AK4712 should be reset once by bringing the PDN pin = “L” after all power supplies are supplied.
Note 25. I2C-bus is a trademark of NXP B.V.
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[AK4712]
■ Timing Diagram
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
I2C Bus mode Timing
tPD
PDN
VIL
Power-down Timing
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[AK4712]
OPERATION OVERVIEW
1. System Reset and Power-down Options
■ System Reset and Full Power-down Mode
The AK4712 should be reset once by bringing the PDN pin = “L” after all power supplies are supplied.
PDN pin: Power down pin
L: Full Power-down Mode. Power-down, reset and initializes control registers.
H: Device active.
■ I2C Mode and Hard Wired Mode
The AK4712 can be controlled via I2C or Hard Wired.
When the I2CSEL pin = “L”, the SDA/MUTEN pin is used for audio mute and SCL pin must be connected to PDN pin.
When the I2CSEL pin = “H”, several operation modes are selectable via the I2C-bus.
I2CSEL pin: I2C Control Enable pin
L: Disable (Hard Wired)
H: Enable (I2C)
■ Audio and Video Power Management
.
The AK4712 detects video signal inputs and power up/down video and audio blocks automatically. When DETN bit =
“1”, power management of audio block is independent from video input detector.
SD block can be powered down via the control registers.
SDAPW: SD block power-up bit (SD Video output)
0: SD block power-down, RCAVOUT pin is Hi-z
1: SD block power-up (default)
HD block can be powered down via the control registers.
HDAPW: HD block power-up bit (HD Video output)
0: HD block power-down, HDY/HDPB/HDPR pins are Hi-z.
1: HD block power-up (default)
PDN pin
L
DETN bit
*
Video Input
*
None
MUTEN pin/bit Register Control Audio block
*
Not Available
Power down
*
Power down
0
L
Power down
Detected
H
Active
L
Power down
H
Available
None
H
Active
1
L
Power down
Detected
H
Active
Note 26. When SDAPW=HDAPW bit = “0”(“1”), Video block is powered down (up).
Table 2. Status of Each Operation Modes (*: Don’t care) (Figure 2)
MS1509-E-00
Video block
Power down
Power down
Active
(Note 26)
Power down
Active
(Note 26)
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[AK4712]
When the I2CSEL pin = “L” (Hard Wired), the SDA/MUTEN pin is used for audio mute.
When the I2CSEL pin= “H” (I2C), MUTEN bit is used for audio mute. The SDA/MUTEN pin is used for Control Data
Input.
I2CSEL pin
MUTEN bit
L
*
H
0
1
MUTEN pin
L
H
Audio block
Power down
Active
Power down
*
Active
Table 3. Audio Output Status
■ Typical Operation Sequence
Figure 2 shows an example of the system timing in I2C mode. (DETN bit = “0”)
PDN pin
“1” (default)
SD/HDAPW bit
Video Signal
“0”
No Signal
“1”
Signal In
No Signal
(Note 27)
Video Output
Hi-z
Active
Hi-z
225ms(MAX)
Audio Output
(Note 28)
94ms(MAX)
94ms(MAX)
“0”
“1” (default)
(GND)
Hi-z
50ms(MAX)
94ms(MAX)
MUTEN bit
Active
Active
94ms(MAX)
“0”
“1”
“Mute”
“Mute”
Active
50ms(MAX)
(Note 29)
(Note 30)
Note 27. The RCAVOUT pin =Hi-z when SDAPW bit = “0”. HDY=HDPB=HDPR pins =Hi-z when HDAPW bit =
“0”. Video Charge pump is powered down when SDAPW bit = HDAPW bit = “0”.
Note 28. When Video signal is detected, audio output goes active after audio charge pump power up time (max.
225ms) and Mute transition time (Table 5). A click noise does not occur at this time.
Note 29. Audio charge pump is powered down after Mute transition time (Table 5). A click noise does not occur at this
time.
Note 30 When MUTEN bit changes from “1” to “0”, audio output goes active after audio charge pump power up time
(max. 50ms) and Mute transition time (Table 5). A click noise does not occur at this time.
Figure 2. Typical Operating Sequence
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[AK4712]
2. Audio Block
■ Volume Control (Gain Setting Resistors)
Voltage gain is defined as RFB/RIN. Table 4 lists the gain setting examples.
RFB
AINLN/RN
RIN
Differential
input
TVOUTL/R
RIN
AINLP/RP
RFB
Figure 3. Full Differential Stereo Input
RFB
AINLN/RN
RIN
Single-ended
input
TVOUTL/R
AINLP/RP
Figure 4. Inverting Single-ended Input
RFB
AINLN/RN
RIN
TVOUTL/R
AINLP/RP
Single-ended
input
Figure 5. Non-Inverting Single-ended Input
Input Resistors
Value, RIN
10 kΩ
10 kΩ
10 kΩ
4.7 kΩ
Feedback Resistors
Value, RFB
10 kΩ
15 kΩ
20 kΩ
47 kΩ
Figure 3
GAIN
× 1.0
× 1.5
× 2.0
× 10
Figure 4
GAIN
× -1.0
× -1.5
× -2.0
× -10
Figure 5
GAIN
× 2.0
× 2.5
× 3.0
× 11
Table 4. Gain Setting Examples
MS1509-E-00
2013/01
- 15 -
[AK4712]
■ Analog Output Block
The AK4712 has a charge pump circuit generating negative power supply rail from a 3.3V(typ) power supply. (Figure 6)
It allows the AK4712 to output audio signal centered at VSS (0V, typ) as shown in Figure 7. The negative power
generating circuit (Figure 6) needs 1.0uF low ESR (Equivalent Series Resistance) capacitors (Ca, Cb). When using
polarized capacitors, the positive pin of Ca and Cb capacitors should be connected to CP and VSS, respectively. When
MUTEN bit = “0”, the charge pump circuit is in power-down mode and its analog outputs become VSS (0V, typ).
AK4712
VD
Charge
Pump
Negative Power
VSS (exposed pad)
CP
CN
Cb
(+)
1uF
Ca
(+)
VEE
1uF
Analog Ground
Figure 6. Negative Power Generate Circuit
AK4712
2Vrms
0V
TVOUTR/TVOUTL
Figure 7. Audio Signal Output
■ Mute Control
When MOD bit = “1” (default), mute control does not cause a pop noise. When MUTEN bit (I2C mode) changes from “1”
to “0”, the audio output is muted within the transition time selected by MDT1-0 bits (Table 5). When SDA/MUTEN pin
(hard wired mode) changes from “H” to “L” , the audio output is muted within the transition time of 94.0ms (max). A
mute status switching like this operation (unmute to mute or vice versa) can not be canceled until the end of transition
time.
When MOD bit = “0”, there is no transition time and mute control may cause a pop noise.
MOD
0
1
1
1
1
MDT1
*
0
0
1
1
MDT0 Transition Time (typ)
Transition Time (max)
*
0ms
0ms
0
5.1ms
11.6ms
1
10.2ms
23.6ms
0
20.5ms
46.8ms
1
41.0ms
94.0ms
Table 5. Mute Transition Time (typ.) (*: Don’t care)
MS1509-E-00
(default)
2013/01
- 16 -
[AK4712]
3. Video Block
■ HD Video Control (05H: D1-D0)
FL1/0 bits set the HD video filter response.
FL1 bit
0
0
1
1
FL0 bit
0
1
0
1
Table 6. HD Video Filter Control
LFP response
6MHz LPF
15MHz LPF
30MHz LPF (default)
(Reserved)
■ Clamp and DC-restore Circuit Control (03H: D7-D3)
The CLAMP1 and CLAMP2 bits select the input circuit for the ENCPB pin (Encoder Blue/Pb), the ENCPR pin (Encoder
Red/Pr) and the ENCY pin (Encoder Green/Y) respectively. When CLAMP2 bit = CLAMP1 bit = “0” (setting for RGB
signal), Sync Source of DC Restore is CVBS. When CLAMP2 bit = “0”, CLAMP1 bit = “1” (setting for Y/C signal), Y
signal is input to the ENCY pin, C signal is input to the ENCPB pin and the ENCPR input circuit is powered down. When
CLAMP2 bit = “1”, CLAMP1 bit = “1” (setting for Y/Pb/Pr signal), Y signal is input to the ENCY pin, Pb signal is input
to the ENCPB pin and Pr signal is input to the ENCPR.
CLAMP2
CLAMP1
0
0
0
1
1
0
1
1
ENCY Input Circuit
DC restore clamp active
(-0.6V at sync timing/output pin)
ENCPB/PR Input Circuit
DC restore clamp active
(-0.6V at sync timing/output pin)
Biased (ENCPB)
DC restore clamp active
Power down (ENCPR)
(-0.572V at sync timing output pin)
(0.0V at sync timing/output pin)
DC restore clamp active
DC restore clamp active
(-0.6V at sync timing/output pin)
(0.0V at sync timing/output pin)
(Reserved)
(Reserved)
Table 7. DC-restore control for Encoder Input
MS1509-E-00
note
for RGB
for Y/C
for
Y/Pb/Pr
(default)
2013/01
- 17 -
[AK4712]
■ Video Output Block
The AK4712 has a video amplifier with drivability for a load resistance of 150Ω and a LPF. There are 1 channel
composite and HD inputs and outputs. The Internal negative power supply circuit supplies the negative voltage to the
video amplifier and the video amp 0V output is used for a pedestal level. Therefore, an output coupling capacitor can be
removed. (Figure 8)
AK 4712
75Ω
P edes ta l L eve l 0 V
Video
O utpu t
7 5Ω
Figure 8. Video Output Block
MS1509-E-00
2013/01
- 18 -
[AK4712]
4. Control Interface (I2C-bus Control)
1. WRITE Operations
Figure 9 shows the data transfer sequence in I2C-bus mode. All commands are preceded by a START condition. A HIGH
to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 15). After the START
condition, a slave address is sent. This address is 7bits long followed by the eighth bit that is a data direction bit (R/W).
The most significant seven bits of the slave address are fixed as “0010001”. If the slave address match that of the
AK4712, the AK4712 generates an acknowledge and the operation is executed. The master must generate an
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 17). A
“1” for R/W bit indicates that the read operation is to be executed. A “0” indicates that the write operation is to be
executed. The second byte consists of the address for control registers of the AK4712. The format is MSB first, and those
most significant 3-bits are fixed to zeros (Figure 11). The data after the second byte contain control data. The format is
MSB first, 8bits (Figure 12). The AK4712 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 15).
The AK4712 can execute more than one byte write operation per sequence. After receipt of the third byte, the AK4712
generates an acknowledge, and awaits the next data. The master can transmit more than one byte instead of terminating
the write cycle after the first data byte is transferred. After receiving of each data packet, the internal address counter is
incremented by one, and the next data is taken into the next address automatically. If the address exceeds 02H prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only be changed when the clock signal on the SCL line is LOW (Figure 17) except for the START and the STOP
conditions.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
Data(n)
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 9. Data transfer sequence at the I2C-bus mode
0
0
1
0
0
0
1
R/W
A2
A1
A0
D2
D1
D0
Figure 10. The first byte
0
0
0
A4
A3
Figure 11. The second byte
D7
D6
D5
D4
D3
Figure 12. Byte structure after the second byte
MS1509-E-00
2013/01
- 19 -
[AK4712]
2. READ Operations
Set R/W bit = “1” for READ operations. After transmission of data, the master can read the next address’s data by
generating an acknowledge instead of terminating the write cycle after the receipt the first data word. After receiving each
data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If the
address exceeds 02H prior to generating a stop condition, the address counter will “roll over” to 00H and the previous
data will be overwritten.
The AK4712 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
2-1. CURRENT ADDRESS READ
The AK4712 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would
access data from the address “n+1”. After receipt of the slave address with R/W bit set to “1”, the AK4712 generates an
acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address
counter by 1. If the master does not generate an acknowledge but generate a stop condition instead, the AK4712 ceases
transmission.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
Data(n+2)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 13. CURRENT ADDRESS READ
2-2. RANDOM READ
The Random read operation allows the master to access any memory location at random. Prior to issuing a slave address
with the R/W bit set to “1”, the master must execute a “dummy” write operation. The master issues a start condition, a
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start condition and the slave address with the R/W bit set to “1”. The AK4712 then generates an
acknowledge, 1-byte data and increments the internal address counter by 1. If the master does not generate an
acknowledge but generate a stop condition instead, the AK4712 ceases the transmission.
S
T
A
R
T
SDA
S
S
T
A
R
T
R/W= “0”
Sub
Address(n)
Slave
Address
A
C
K
S
A
C
K
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 14. RANDOM ADDRESS READ
MS1509-E-00
2013/01
- 20 -
[AK4712]
SDA
SCL
S
P
start condition
stop condition
Figure 15. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 16. Acknowledge on the I2C-bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 17. Bit Transfer on the I2C-bus
MS1509-E-00
2013/01
- 21 -
[AK4712]
■ Register Map
Addr
00H
01H
02H
Register Name
Audio Volume control
Video control
Reserve
D7
0
FLT
0
D6
0
DETN
0
D5
0
CLAMP2
0
D4
0
CLAMP1
0
D3
MOD
FL1
0
D2
MDT1
FL0
0
D1
MDT0
HDAPW
0
D0
MUTEN
SDAPW
0
When the PDN pin goes “L”, the registers are initialized to their default values.
While the PDN pin = “H” and I2CSEL pin = “H”, all registers can be accessed.
Do not write any data to the register over 02H.
■ Register Definitions
Addr
00H
Register Name
Control
R/W
Default
D7
0
D6
0
D5
0
D4
0
D3
MOD
D2
MDT1
D1
MDT0
MUTEN
D0
1
1
0
1
R/W
0
0
0
0
MUTEN: Audio output control
0: ALL Audio outputs to GND
1: Normal operation (default)
MDT1-0: The time length control of mute/unmute transition time
00: typ. 5.1 ms / max. 11.6 ms
01: typ. 10.2 ms / max. 23.6 ms
10: typ. 20.5 ms / max. 46.8 ms
11: typ. 41.0 ms / max. 94.0 ms (default)
MOD: Soft transition enable for mute/unmute control
0: Disable
The audio output is muted/unmated immediately without soft transition.
1: Enable (default)
The audio output is muted/unmuted with soft transition.
MS1509-E-00
2013/01
- 22 -
[AK4712]
Addr
01H
Register Name
Video Control
R/W
Default
D7
D6
D5
D4
D3
D0
DETN
CLAMP2
CLAMP1
FL1
D2
FL0
D1
FLT
HDAPW
SDAPW
0
0
1
0
1
0
1
1
R/W
SDAPW: SD block power-up bit(SD Video output)
0: SD block power-down, RCAVOUT pin is Hi-z.
1: SD block power-up (default)
HDAPW: HD block power-up bit(HD Video output)
0: HD block power-down, HDY/HDPB/HDPR pins are Hi-z.
1: HD block power-up. (default)
FL1-0: HD Video Filter Control
Refer to Table 6.
CLAMP2, CLAMP1: Clamp control.
Refer to Table 7
DETN: Video input detector control of audio block
0: Power management of audio block is dependent on video input detector. (default).
1: Power management of audio block is independent from video input detector.
FLT: HD Sync detection filter (500kHz band-width)
0: filter OFF (default).
1: filter ON
MS1509-E-00
2013/01
- 23 -
[AK4712]
SYSTEM DESIGN
Figure 18 shows the system connection diagram example (I2C mode). An evaluation board (AKD4712) demonstrates
application circuits, the optimum layout, power supply arrangements and measurement results.
HD Video
Audio Out
Analog
3.3
Analog
3.3
C INCH Video
4.7u
VSS
+ 4.7u
+
0.1u
VSS
0.1u
VSS
VSS
1.0u
1.0u
1.0u
22
VEE
23
25
24
CN
CP
VD1
4
HDPR
5
HDPB
I2CSEL
18
TVOUTR
17
16
AINRP
15
PDN
AINR N
14
13
SDA/ MUTEN
12
0.1u
ENCY
7
VVD
11
RCAVOUT
SCL
AK4712
6
75
75
75
75
26
19
Analog
3.3
Controller
Micro
27
TVOUTL
+
Digital
Ground
VD2
HDY
VSS
Analog Ground
VCP
3
VSS
20k
10k
10k
2.2u
2.2u
20k
330
Analog
3.3
330
20k
10k
10k
2. 2u
2.2u
20k
VSS
0.1u
4.7u
20
ENCPr
VSS
AINLN
10
0.1u
VREG
0.1u
75
2
9
75
21
ENCPb
75
AINLP
ENC RCA
VSS
75
VVEE
8
VSS 1.0u
VSS
1
0.1u
1.0u
VCN
28
VSS
Video
Encoder
DACR DACL
MPEG
decoder
Figure 18. Typical Connection Diagram (I2C Mode: the I2CSEL pin = “H”)
MS1509-E-00
2013/01
- 24 -
[AK4712]
The SCL pin must be connected to the PDN pin when the I2CSEL pin = “L”
HD Video
Audio Out
Analog
3.3
Analog
3.3
C INCH Video
4.7u
VSS
+ 4.7u
+
0.1u
VSS
0.1u
VSS
VSS
1.0u
1.0u
1.0u
22
VEE
23
25
24
CN
CP
VD1
4
HDPR
I2CSEL
18
5
HDPB
TVOUTR
17
16
AINRP
15
PDN
AINR N
14
13
SDA/ MUTEN
12
VVD
ENCY
7
11
R CAVOUT
SCL
AK4712
6
10k
10k
2.2u
2.2u
20k
330
VSS
330
20k
10k
10k
2. 2u
02.2u
20k
VSS
R 13
0.1u
75
75
75
75
26
19
Analog
3.3
Controller
Micro
27
TVOUTL
+
Digital
Ground
VD2
HDY
VSS
Analog Ground
VCP
3
VSS
20k
0.1u
4.7u
20
ENCPr
VSS
AINLN
10
0.1u
VREG
0.1u
75
2
9
75
21
ENCPb
75
AINLP
ENC RCA
VSS
75
VVEE
8
VSS 1.0u
VSS
1
0.1u
1.0u
VCN
28
VSS
Video
Encoder
DAC R DACL
MPEG
decoder
Figure 19. Typical Connection Diagram (Hard Wired Mode: the I2CSEL pin = “L”)
MS1509-E-00
2013/01
- 25 -
[AK4712]
■ Grounding and Power Supply Decoupling
VD1, VD2, VVD should be supplied from analog supply unit with low impedance and be separated from system digital
supply. A 4.7μF electrolytic capacitor parallel with a 0.1μF ceramic capacitor should be connected to each VD1 pin, VD2
pin, VVD pin, VSS (exposed pad) to eliminate the effects of high frequency noise. The 0.1μF ceramic capacitors should
be placed as near to the VD1 (VD2, VVD) pin as possible.
■ Analog Audio Outputs
The analog outputs are also single-ended and centered on 0V(typ.). The output signal ranges typically 2Vrms .
■ Attention to the PCB Wiring
AINLN and AINRN pins are the summing nodes of the Pre-Amp. Attention should be given to avoid coupling with other
signals on those nodes. This can be accomplished by making the wire length of the input resistors and the feedback
resistors as short as possible.
MS1509-E-00
2013/01
- 26 -
[AK4712]
■ External Circuit Example
The analog audio input pin must have input series resistor(RIN) and capacitor(CIN).
Analog Audio Input pin
RIN
AINRP
AINRN
AINLP
AINLN
CIN
Analog Audio Output pin
TVOUTL/R
330Ω
(Cable)
Total > 4.5kΩ
Analog Video Input pin
75Ω
(Cable)
ENCRCA, ENCY,
ENCPB, ENCPR,
0.1μF
75Ω
Analog Video Output pin
75Ω
RCAVOUT, HDY,
HDPR, HDPB
(Cable)
max
400pF
max
15pF
MS1509-E-00
75Ω
2013/01
- 27 -
[AK4712]
PACKAGE
28pin QFN (Unit: mm)
Top View
Bottom View
4.00±0.10
A
2.60±0.10
2.60±0.10
0.40±0.10
4.00±0.10
B
Exposed
Pad
0.4
0.07 M C
A
B
0.02+0.03
- 0.02
0.75 ±0.05
0.20±0.05
C
0.10
C
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS1509-E-00
2013/01
- 28 -
[AK4712]
MARKING
4712
XXXX
1
1) Pin #1 indication
2) Date Code identifier: XXXX (4 digits)
REVISION HISTORY
Date (Y/M/D)
13/01/30
Revision
00
Reason
First Edition
Page
Contents
MS1509-E-00
2013/01
- 29 -
[AK4712]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
MS1509-E-00
2013/01
- 30 -