データシート

[AK7742]
AK7742
24bit 2ch ADC + 24bit 4ch DAC with Audio DSP
AK7742
DSP
4ch
24
DAC
4ch DAC
1536step/fs (48kHz
106dB
2ch
ADC
ADC
96dB
)
74kbit
RAM
■ DSP
RAM
DSP
48pin LQFP
:
: 24-bit (24bit
)
: 13.6 ns (1536step/fs fs=48kHz; 9216step/fs fs=8kHz)
: 24 x 16 → 36-bit
: 20 / 20 → 20-bit
- ALU: 40bit
(overflow margin 4bit) 24bit
RAM: 1536 x 36-bit
RAM: 1536 x 16-bit
RAM: 1536 x 24-bit (24bit
)
RAM: 74kbit ( 3072 x 24bit )
: 8kHz ~ 96kHz
/
(4ch)
24bit/
24, 20, 16bit
I2S
2
(6ch)
24bit/
24, 16bit
IS
■ ADC: 2ch(
)
- 24bit 64 x Over-sampling delta sigma (fs=8kHz~48kHz
)
- DR, S/N: 96dB (fs=48kHz,
)
- S/(N+D): 84dB (fs=48kHz)
HPF (fc=1Hz)
-3
(24dB -103dB,0.5dB Step, Mute)
■ DAC: 4ch(
2 )
- 24bit 128 x Over-sampling advanced multi-bit (fs=8kHz~96kHz
- DR, S/N: 106dB
- S/(N+D): 92dB
(12dB -115dB,0.5dB Step, Mute)
■ DSP
■ I2C
■
■
■
)
: +3.3V ±0.3V,
: -20°C~70°C(AK7742EQ), -20°C~85°C(AK7742EN)
48pin LQFP, 0.5mm pitch (AK7742EQ)
48pin QFN, 0.4mm pitch (AK7742EN)
MS1024-J-00
2008/11
-1-
[AK7742]
■
LFLT
Hi-z
2 DVDD
3
3 VSS1
Open Drain
3 AVDD
pull down
XTO
2 VSS2
XTI
BICK
LRCK
IRESETN
CKM[2:0]
TEST1
AVDRV
ASEL[1:0]
3
DVOL
SELDO3
CLKO/SDOUT3
VCOM
REF
CLKGEN & CONT
CLKOE
ADC
0
1
SDOUTAD
DIN3
DOUT5
JX0E
0
1
2
3
DVOL
DAC2
JX1E
AIN3L,AIN3R
2
AIN2L,AIN2R
0
4
AIN1LP,AIN1LN
AIN1RP,AIN1RN
DVOL
JX0
0
1
2
3
AOUT2LP
AOUT2LN
AOUT2RP
AOUT2RN
SDINDA2
DAC1
DIN2
DOUT4
SDIN1 / JX1
2
DOUT3
SELDO5[1:0]
SDIN2 / JX0
2
1
AOUT1LP
AOUT1LN
AOUT1RP
AOUT1RN
SDINDA1
SELDO4[1:0]
JX1
DIN1
DOUT1
OUT1E
1
0
SELDO1
SELDO2[1:0]
DOUT2
GPO
3
2
MICIF
SDOUT1
RDY
SO
OUT2EN
SO/RDY/GPO/SDOUT2
1
0
I2CSEL
CAD1
SCL
CAD0
SDA
DSP
Figure 1.
MS1024-J-00
2008/11
-2-
[AK7742]
CP0,CP1
DLP0,DLP1
DP0,DP1
OFREG
64W 13-Bit
DLRAM
3072W 24-Bit
DRAM
1536W 24-Bit
CRAM
1536W 16-Bit
CBUS(16-Bit)
DBUS(24-Bit)
MPX16
Micon I/F
MPX20
X
Control
DEC
Y
16
Multiply
20
36-Bit
Serial I/F
PRAM
1536w
36-Bit
PC
Stack : 5level(max)
24-Bit
36-Bit
TMP 8
24-Bit
PTMP(LIFO) 6 24-Bit
MUL
DBUS
SHIFT
40-Bit
40-Bit
A
B
ALU
40-Bit
Overflow Margin: 4-Bit
2
24,16-Bit
DIN3 (ADC)
2
24,20,16-Bit
DIN2
2
24,20,16-Bit
DIN1
2
24,16-Bit
DOUT5 (DAC2)
2
24,16-Bit
DOUT4 (DAC1)
2
24,20,16-Bit
DOUT3
2
24,20,16-Bit
DOUT2
2
24,20,16-Bit
DOUT1
40-Bit
DR0 ∼ 3
40-Bit
Over Flow Data
Generator
Division 20÷20 20
Peak Detector
Figure 2. AK7742 DSP
MS1024-J-00
2008/11
-3-
[AK7742]
■
AK7742EQ
AK7742EN
AKD7742
-20 ∼ +70°C
-20 ∼ +85°C
48pin LQFP (0.5mm pitch)
48pin QFN (0.4mm pitch)
■
AK7742EQ
48pin LQFP
(TOP VIEW )
MS1024-J-00
2008/11
-4-
[AK7742]
AOUT1RN
AOUT1RP
AOUT1LN
AOUT1LP
37
38
VSS1
VCOM
AVDD
AIN1RN
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
39
40
AK7742EN
Top View
16
15
9
10
11
12
DVDD
VSS2
MS1024-J-00
CLKO/SDOUT3
BICK
LRCK
VSS2
DVDD
I2CSEL
IRESETN
CKM[0]
CKM[1]
SDIN2/JX0
SDIN1/JX1
SDOUT1
XTI
XTO
1
2
3
4
5
6
7
8
14
13
AIN3L
AIN2R
AIN2L
AVDD
VSS1
LFLT
TEST1
CKM[2]
AIN1RP
AIN1LN
AIN1LP
AIN3R
28
27
26
25
CAD1
CAD0
SCL
SDA
SO/RDY/GPO/SDOUT2
36
35
34
33
32
31
30
29
AOUT2LP
AOUT2LN
AOUT2RP
AOUT2RN
AVDD
AVDRV
VSS1
AK7742EN
2008/11
-5-
[AK7742]
No.
I/O
I ADC Lch
I ADC Rch
I ADC Lch
1
2
3
4
5
AIN3L
AIN2R
AIN2L
AVDD
VSS1
6
LFLT
O
7
TEST1
I
8 CKM[2]
9 DVDD
10 VSS2
I
11 XTI
I
12 XTO
O
13 SDOUT1
14
15
16
17
18
SDIN1/JX1
SDIN2/JX0
CKM[1]
CKM[0]
IRESETN
19 I2CSEL
3 pin
2 Pin
2 Pin
3.0V~3.6V
0V
PLL RC
C=12nF
VSS1
VSS2
3.0V~3.6V
0V
XTI pin
XTI pin
23 BICK
24 CLKO/SDOUT3
25
SO/RDY/GPO/
SDOUT2
26 SDA
27 SCL
XTO pin
XTIpin
XTO pin
O DSP
I/F
“L”
I
I
I
I
I
I
/ JX1
/ JX0
I/F
I/F
I2CBUS
DVDD
IF
20 DVDD
21 VSS2
22 LRCK
”L”
3.0V~3.6V
0V
I/O LR
I/F
“L”
I/O
I/F
“L”
O
/DSP
“L”
/ DSP
O
/ DSP
/
IF
“L”
I/O
I
SDA I2C
SCL I2C
IF
IF
MS1024-J-00
2008/11
-6-
[AK7742]
No.
28 CAD0
29 CAD1
30 VSS1
31 AVDRV
I/O
I I2C
I I2C
0
1
IF
IF
0V
AVDRV Pin
1μF
O
VSS1
“L”
32 AVDD
33 AOUT2RN
34 AOUT2RP
35 AOUT2LN
36 AOUT2LP
37 AOUT1RN
38 AOUT1RP
39 AOUT1LN
40 AOUT1LP
3.0V~3.6V
O DAC2 Rch
“Hi-Z”
O DAC2 Rch
“Hi-Z”
O DAC2 Lch
“Hi-Z”
O DAC2 Lch
“Hi-Z”
O DAC1 Rch
“Hi-Z”
O DAC1 Rch
“Hi-Z”
O DAC1 Lch
“Hi-Z”
O DAC1 Lch
“Hi-Z”
41 VSS1
42 VCOM
0V
O
0.1μF
2.2μF
VSS1
“L”
43
44
45
46
47
48
AVDD
AIN1RN
AIN1RP
AIN1LN
AIN1LP
AIN3R
I
I
I
I
I
ADC Rch
ADC Rch
ADC Lch
ADC Lch
ADC Rch
3.0V~3.6V
1 Pin
1 Pin
1 Pin
1Pin
3
Note:
AIN1LP, AIN1LN, AIN1RP, AIN1RN, AIN2L, AIN2R, AIN3L, AIN3R
MS1024-J-00
2008/11
-7-
[AK7742]
(VSS1=VSS2=0V: Note 1)
(AVDD=DVDD)
Analog
Digital
(
)
(Note 2)
AIN1LP, AINL1N, AIN1RP, AINR1N,
AIN2L, AIN2R, AIN3L, AIN3R
(Note 3)
AK7742EQ
AK7742EN
Note 1.
Note 2.
Note 3.
max
max
min
max
AVDD
DVDD
IIN
-0.3
-0.3
4.3
4.3
±10
V
V
mA
VINA
-0.3
(AVDD+0.3) or 4.3
V
VIND
Ta
Ta
Tstg
-0.3
-20
-20
-65
(DVDD+0.3) or 4.3
70
85
150
V
VSS1
(AVDD+0.3)V
(DVDD+0.3)V
VSS2
4.3V
4.3V
:
(VSS1=VSS2=0V: Note 1)
(AVDD=DVDD)
Analog
Digital
AVDD
DVDD
min
typ
max
3.0
3.0
3.3
3.3
3.6
3.6
V
V
:
)
ON
DVDD
AK7742
OFF
(SDA, SCL Pin
MS1024-J-00
SDA, SCL
DVDD
)
2008/11
-8-
[AK7742]
■ ADC
(
Ta=25
fs=48kHz, ADC
; AVDD=DVDD=3.3V; BICK=64fs;
, CKM mode 0 (CKM[2:0]=000))
1kHz;
min
=20Hz
typ
20kHz,
max
24
Bits
ADC
S/(N+D)
S/N
(-1dBFS)
(Note 4)
(A-weighted)
(Note 4)
(A-weighted)
(Note 4)
(f=1kHz) (Note 5)
76
88
88
90
84
96
96
105
dB
dB
dB
dB
DC
(Note 6)
(Note 7)
(Note 8)
Note 4.
Note 5. -1dBFS
Note 6.
Note 7.
Note 8.
±1.85
1.85
41
0.1
0.3
dB
±2.00
2.00
62
±2.15
2.15
Vp-p
Vp-p
kΩ
Lch-Rch
AIN1LP, AIN1LN, AIN1RP, AIN1RN
AIN2L, AIN2R, AIN3L, AIN3R
AIN1LP, AIN1LN, AIN1RP, AIN1RN, AIN2L, AIN2R, AIN3L, AIN3R
■ DAC
(
Ta=25 ; AVDD=DVDD=3.3V; BICK=64fs;
fs=48kHz, RL=5KΩ, CL= 15pF, CKM mode 0(CKM[2:0]=000))
1kHz;
min
=20Hz
typ
max
24
20kHz,
Bits
DAC
S/(N+D)
(0dBFS)
(A-weighted)
(A-weighted)
(f=1kHz)(Note 9)
S/N
80
90
90
90
3.36
5
(Note 10)
92
106
106
100
dB
dB
dB
dB
0.2
0.5
dB
3.66
3.96
Vp-p
kΩ
pF
30
Note 9.
Note 10.
DAC
Lch-Rch
AVDD
MS1024-J-00
2008/11
-9-
[AK7742]
DC
(Ta=-20°C ~70°C (AK7742EQ), Ta=-20°C ~85°C (AK7742EN); AVDD=DVDD=3.0~3.6V)
min
typ
max
VIH
80%DVDD
(Note 11)
VIL
20%DVDD
(Note 11)
VIH
70%DVDD
SCL, SDA
VIL
30%DVDD
SCL, SDA
VOH
DVDD-0.5
Iout=-100μA
VOL
0.5
Iout=100μA (Note 12)
VOL
0.4
SDA
Iout=3mA
Iin
±10
(Note 13)
Iid
22
TESTI pin
(Note 14)
Iix
26
XTI pin
Note 11. SCL, SDA pin
Note 12. SDA pin
Note 13. TEST1 pin, XTI pin
Note 14. TEST1 pin
(Typ150kΩ)
(Ta=25
; AVDD=DVDD=3.0~3.6V(typ=3.3V, max=3.6V))
min
(Note 15)
AVDD+DVDD
( IRESETN pin = “L”,
AVDD+DVDD (Note 16)
Note 15. DVDD
Note 16.
typ
max
75
122
V
V
V
V
V
V
V
μA
μA
μA
mA
)
2
mA
DSP
MS1024-J-00
2008/11
- 10 -
[AK7742]
■ ADC
(Ta=-20°C ~70°C (AK7742EQ), Ta=-20°C ~85°C (AK7742EN); AVDD=DVDD=3.0~3.6V, fs=48kHz; Note 17)
min
typ
max
PB
0
21.5
kHz
(±0.005dB)
(Note 18)
21.768
kHz
(-0.02dB)
24.00
kHz
(-6.0dB)
SB
26.5
kHz
PR
±0.005
dB
(Note 18)
SA
80
dB
(Note 19, Note 20)
0
GD
μs
GD
30
Ts
(Ts=1/fs)
±0.01
20Hz~20.0kHz
Note 17.
dB
fs
Note 18.
fs=48kHz
Note 19.
fs=48kHz
Note 20. fs=48kHz
DC
21.5kHz
26.5kHz
3.0455MHz
3.072MHz
(n x 3.072MHz ±21.99kHz; n=0,1,2,3
)
■ DAC
(Ta=-20°C ~70°C (AK7742EQ), Ta=-20°C ~85°C (AK7742EN); AVDD=DVDD=3.0~3.6V, fs=48kHz; Note 17)
min
typ
max
±0.07dB
(-6.0dB)
(Ts=1/fs)
0
Note 21.
(Note 21)
PB
(Note 21)
SB
PR
SA
GD
(Note 22)
0
26.2
24
kHz
kHz
kHz
dB
dB
Ts
±0.5
dB
24.0
21.7
±0.01
64
-
20.0kHz
fs(
)
PB=0.4535fs(@-0.05dB),
SB=0.5465fs
Note 22.
24
MS1024-J-00
2008/11
- 11 -
[AK7742]
■
(Ta=-20°C ~70°C (AK7742EQ), Ta=-20°C ~85°C (AK7742EN); AVDD=DVDD=3.0~3.6V)
min
typ
XTI
a)
Frequency(256fs)
fs=44.1KHz fXTI
11.2896
CKM[2:0]= 000
fs=48KHz
12.288
b)
Duty
40
50
Frequency(256fs)
fXTI
11.0
11.2896
fs=44.1KHz
12.288
CKM[2:0]= 000, 010
fs=48KHz
Frequency (384fs)
fs=44.1KHz fXTI
16.5
16.9344
CKM[2:0]= 001
fs=48KHz
18.432
Fs
7.35
48
LRCK
(Note 23)
BICK
a) CKM[2:0]= 001,010 (Note 24)
fBCLK
32
64
64
0.46
Duty
fBCLK
40
2.75
Duty
fBCLK
40
230
tBCLKH
tBCLKL
3.072
64
50
3.072
32
50
256
64
50
512
c) CKM[2:0]= 100 (Note 26)
d) CKM[2:0]= 101 (Note 27)
Note 23. LRCK
Note 24. 1fs
Note 25. BICK
Note 26. BICK
Note 27. BICK
BICK
)
MCLK
(BICK
MCLK
(BICK
MCLK
(BICK
64fs
-
MHz
60
12.4
%
MHz
18.6
MHz
96
kHz
64
b) CKM[2:0]= 011 (Note 25)
Duty
fBCLK
(fs)
32,48
64
max
40
460
fs
ns
ns
MHz
fs
%
MHz
fs
%
kHz
fs
%
kHz
6.144
60
3.1
60
258
60
516
(BICK
32fs,48fs,64fs
1fs
BICK
64
1fs
BICK
32
1fs
BICK
64
)
32fs
)
64fs
)
MS1024-J-00
2008/11
- 12 -
[AK7742]
■
(Ta=-20°C ~70°C (AK7742EQ), Ta=-20°C ~85°C (AK7742EN); AVDD=DVDD=3.0~3.6V)
min
typ
max
IRESET
(Note 28)
tRST
600
Note 28. “H”
ns
■
1) SDIN1, SDIN2, SDOUT1, SDOUT2, SDOUT3
(Ta=-20°C ~70°C (AK7742EQ), Ta=-20°C ~85°C (AK7742EN); AVDD=DVDD=3.0~3.6V, CL=20pF)
min
typ
max
BICK
BICK
BICK
BICK “↑”
LRCK
LRCK
BICK “↑”
LRCK
BICK “↓”
(Note 30)
fBCLK
tBCLKL
tBCLKH
tBLRD
tLRBD
tBSIDS
tBSIDH
tLRD
tBSOD
(Note 30)
fBCLK
Duty
tBLRD
tLRBD
tBSIDS
tBSIDH
tBSOD
(Note 29)
(Note 29)
BICK
BICK
BICK “↑”
LRCK
LRCK
BICK “↑”
BICK “↓”
Note 29.
Note 30.
LRCK
BICK
(SDOUT1/2/3)
BICK
(VIH)
LRCK
BICK
30ns
BICK
32
150
150
40
40
40
40
-10
-10
64
40
40
64
50
40
40
40
40
-30
BICK
(SPEC -10ns) BICK
(SPEC -10ns)
MS1024-J-00
fs
ns
ns
ns
ns
ns
ns
ns
ns
fs
ns
ns
ns
ns
ns
40
LRCK
2008/11
- 13 -
[AK7742]
■ I2CBUS
(Ta=-20°C ~70°C (AK7742EQ), Ta=-20°C ~85°C (AK7742EN); AVDD=DVDD=3.0~3.6V)
Parameter
Symbol
min
typ
max
2
I C Timing
SCL clock frequency
fSCL
400
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first Clock
tHD:STA
0.6
pulse)
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling
tHD:DAT
0
0.9
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
0.3
Fall Time of Both SDA and SCL Lines
tF
0.3
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed
tSP
0
50
by Input Filter
Capacitive load on bus
Cb
400
Note 31. I2C
Unit
KHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
Philips Semiconductors
MS1024-J-00
2008/11
- 14 -
[AK7742]
■
1/fXTI
1/fXTI
tXTI=1/fXTI
VIH
XTI
VIL
tCR
1/fs
tCF
ts=1/fs
1/fs
VIH
LRCK
VIL
tLR
1/fBCLK
1/fBCLK
tLF
tBCLK=1/fBCLK
VIH
BICK
VIL
tBCLKH
tBR tBF
tBCLKL
Figure 3.
IRESETN
tRST
VIL
Figure 4.
MS1024-J-00
2008/11
- 15 -
[AK7742]
LRCK
50%DVDD
tBLRD
tMB tMBL
tLRBD
BICK
50%DVDD
tLRD
tBSOD
SDOUT1/2/3
50%DVDD
tBSIDS
tBSIDH
SDIN1/2
50%DVDD
Figure 5.
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
Figure 6. I2C
MS1024-J-00
2008/11
- 16 -
[AK7742]
■ CKM[2:0]
AK7742
MCLK
CKM
Mode
CKM[2:0]
(Master)
ICLK
(ICLK)
CKM
[2:0]
Master
Slave
MCLK
MCLK
(ICLK)
0
1
000
001
Master
Slave
XTI
XTI
12.288MHz (Note 32)
18.432MHz (Note 32)
2
010
Slave
XTI
12.288MHz
(Note 32, Note 35)
3
4
5
6
7
011
100
101
110
111
Slave
Slave
Slave
TEST
TEST
BICK
BICK
BICK
N/A
N/A
64fs(fs=48kHz
32fs(fs=8kHz
64fs(fs=8kHz
N/A
N/A
Note 32. fs=44.1kHz
Note 33. CKM mode 6/7
Note 34. CKM mode 0
Note 35. CKM mode1/ 2
XTI(256fs)
XTI (384fs),
BICK (32fs,48fs or 64fs) ,
LRCK(fs)
XTI(256fs),
BICK(32fs,48fs or 64fs),
LRCK(fs)
BICK, LRCK
BICK, LRCK
BICK, LRCK
N/A
N/A
(N/A: Not available)
44.1/48
(fs)
XTI LRCK
CONT0
CONT0
BICK
LRCK
]
“L”
##h
CKM[2:0]
TEST
Note 36. CKM mode 3-5 fs
Note 37. CKM mode 3-5
BICK
LRCK
[
)
)
)
(Slave)
16
“H”
“0”, “1”
(# = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F)
MS1024-J-00
2008/11
- 17 -
[AK7742]
■
MCLK
(ICLK)
MCLK
ICLK
XTI Pin
CKM Mode 0/1/2
(MCLK
PLL
MCLK
)
ICLK
BICK Pin
CKM Mode 3/4/5
REFCLK
(MCLK
REFCLK
PLL
MCLK
)
MCLK73.728MHz(@fs=48kHz)
Figure 7. MCLK
1.
(ICLK)
MCLK
CKM Mode 0
fs:
CKM
Mode
0
CKM
[2:0]
000
XTI
fs:48kHz
12.288MHz
(MHz)
11.0~12.4
fs:44.1kHz
11.2896MHz
XTI
XTI
LRCK, BICK
)
CKM mode 0
XTI
AK7742
XTO
LRCK(1fs) , BICK(64fs)
(■
(IRESETN pin= “L”)
XTI pin
XTI
XTI
XTI
External Clock
XTO
Figure 8.
XTO
AK7742
(CKM Mode 0)
Figure 9.
AK7742
(CKM Mode 0)
CONT0 DFS[2:0] (D3, D2, D1)
MS1024-J-00
2008/11
- 18 -
[AK7742]
2.
XTI
CKM Mode 1/2
fs:
CKM
Mode
1
2
CKM
XTI
[2:0]
001
010
fs:48kHz
18.432MHz
12.288MHz
(MHz)
16.5~18.6
11.0~12.4
fs:44.1kHz
16.9344MHz
11.2896MHz
XTI, LRCK, BICK
3.
BICK
CKM mode 3/4/5
BICK
BICK
3
4
5
LRCK
CKM Mode 3/4/5
XTI
PLL
BICK
CKM
Mode
XTI
(MCLK)
LRCK
fs:
BICK
CKM
BICK
[2:0]
011
100
101
BICK
64fs(fs=48,44.1kHz)
32fs(fs=8kHz)
64fs(fs=8kHz)
fs:48kHz
3.072MHz
256kHz
512kHz
fs:44.1kHz
2.8224MHz
-
2.75~3.1MHz
230~258kHz
460~516kHz
XTI
0
1
XTO
External
Clock
BICK
CKM[2:0]=011, 100, 101
“1”
MCLK
BICK
CKM[2:0]
AK7742
Figure 10.
(CONT0)
XTI
DFS mode
CKM[2:0] pin
XTI
pin = “L”(VSS2)
MS1024-J-00
2008/11
- 19 -
[AK7742]
4. CKM[2:0] Pin
CKM[2:0] pin
5. CKM[2:0] Pin
Slave/
Master
CKM
Mode
CKM
[2:0]
M
0
M
0
M
0
M
0
M
0
S
1
S
1
S
1
S
1
S
1
S
2
S
2
S
2
S
2
S
2
S
3
S
4
S
5
Note 38. DFS mode
000
000
000
000
000
001
001
001
001
001
010
010
010
010
010
011
100
101
DFS
Mode
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
-
DFS
[2:0]
fs(kHz)
000(default)
48/44.1
001
32/29.4
010
16/14.7
011
8
100
96/88.2
000(default)
48/44.1
001
32/29.4
010
16/14.7
011
8
100
96/88.2
000(default)
48/44.1
001
32/29.4
010
16/14.7
011
8
100
96/88.2
48/44.1
8
8
CONT0 DFS[2:0] (D3, D2, D1)
MS1024-J-00
BICK
I2S
64fs
64fs
64fs
64fs
64fs
64fs,48fs,32fs
64fs,48fs,32fs
64fs,48fs,32fs
64fs,48fs,32fs
64fs,48fs,32fs
64fs,48fs,32fs
64fs,48fs,32fs
64fs,48fs,32fs
64fs,48fs,32fs
64fs,48fs,32fs
64fs
32fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs,48fs
64fs,48fs
64fs,48fs
64fs,48fs
64fs,48fs
64fs,48fs
64fs,48fs
64fs,48fs
64fs,48fs
64fs,48fs
64fs
32fs
64fs
2008/11
- 20 -
[AK7742]
■
AK7742
15
8bit
D0
DSP
IRESETN pin = “L”
Command
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
Code
Write
C0h
Read
40h
CONT0
C1h
41h
CONT1
C2h
42h
CONT2
C3h
43h
CONT3
C4h
44h
CONT4
C5h
45h
C6h
46h
C7h
47h
C8h
48h
D0h
DIFI2S
PCM[1]
PCM[0]
ATSPAD
ATSPDA
BANK[1]
BANK[0]
TEST
POMODE
DATARAM
BIT32FS
WAVM
WAVP[1]
DIF[1]
DIF[0]
DOF[1]
DOF[0]
CLKS[2]
CLKOE
BITCLKEN
LRCLKEN
OUT2EN
OUT1EN
CONT5
SELDO5[0]
SELDO4[0]
SELDO3
SELDO2[1]
CONT6
ADMUTE
Reseved
ASEL[1]
ASEL[0]
CONT7
DEM1[1]
DEM1[0]
DEM2[1]
DEM2[0]
TEST
TEST
CONT8
SRESETN
ADRST
DA2RST
DA1RST
DSPRST
TEST
50h
CONT10
VOLADL[7]
VOLADL[6]
VOLADL[5]
VOLADL[4]
VOLADL[3]
VOLADL[2]
D1h
51h
CONT11
VOLADR[7]
VOLADR[6]
VOLADR[5]
VOLADR[4]
VOLADR[3]
D2h
52h
CONT12
VOLDA1L[7]
VOLDA1L[6]
VOLDA1L[5]
VOLDA1L[4]
D3h
53h
CONT13
VOLDA1R[7]
VOLDA1R[6]
VOLDA1R[5]
VOLDA1R[4]
D4h
54h
CONT14
VOLDA2L[7]
VOLDA2L[6]
VOLDA2L[5]
VOLDA2L[4]
VOLDA2L[3]
VOLDA2L[2]
D5h
55h
CONT15
VOLDA2R[7]
VOLDA2R[6]
VOLDA2R[5]
VOLDA2R[4]
VOLDA2R[3]
VOLDA2R[2]
Note 39.
Note 40. TESTbit
Note 41. Default
DIFPCM
DFS[2]
DFS[1]
00h
DFS[0]
0
SS[1]
SS[0]
0
00h
WAVP[0]
EEFN
0
00h
CLKS[1]
CLKS[0]
0
00h
JX1E
JX0E
0
00h
SELDO2[0]
SELDO1
SELDO4[1]
0
00h
SELDO5[1]
DA2MUTE
DA1MUTE
0
00h
TEST
0
00h
CKRST
0
00h
VOLADL[1]
VOLADL[0]
30h
VOLADR[2]
VOLADR[1]
VOLADR[0]
30h
VOLDA1L[3]
VOLDA1L[2]
VOLDA1L[1]
VOLDA1L[0]
18h
VOLDA1R[3]
VOLDA1R[2]
VOLDA1R[1]
VOLDA1R[0]
18h
VOLDA2L[1]
VOLDA2L[0]
18h
VOLDA2R[1]
VOLDA2R[0]
18h
“0”
IRESETN pin= “L”
MS1024-J-00
2008/11
- 21 -
[AK7742]
1) CONT0 :
Command Code
Write
Read
C0h
40h
Name
CONT0
DIFPCM
0:
1: PCM
D7
D6
D5
D4
D3
D2
D1
D0
Default
DIFPCM
DIFI2S
PCM[1]
PCM[0]
DFS[2]
DFS[1]
DFS[0]
0
00h
:
I²S
(default)
Note 42. PCM
DIFI2S:
D6: DIFI2S
“0”
IF I2S
0: I²S mode
(default)
1: I²S mode
SDIN1-2, SDOUT1-3 I²S mode
DIFI2S bit = “1”
DIF[1:0], DOF[1:0]
(24bit)
DSP
I²S mode
(DIFI2S bit = “0”)
DIF[1:0], DOF[1:0]
(24bit)
Note 43. I²S
D7: DIFPCM
“0”
PCM[1:0]: PCM
DIFPCM bit = “1”
PCM[1:0]
PCM
CKM mode 3/4/5
PCM Mode PCM[1:0] LRCK
LRCK
(FRAME)
BICK
0
00
short(SF)
1
01
short(SF)
2
10
long(LF)
3
11
long(LF)
DFS[2:0]:
BIT32FS
(RE)
(FE)
(RE)
(FE)
0
Figure 21
Figure 23
Figure 25
Figure 27
1
Figure 22
Figure 24
Figure 26
Figure 28
(default)
(CKM Mode 0-2)
fs:
CKM
Mode
0-2
0-2
0-2
0-2
0-2
3
4
5
6
7
CKM
[2:0]
0XX
0XX
0XX
0XX
0XX
011
100
101
110
111
Note 44. DFS mode CKM mode 0-2
DFS mode 0-4
“0”
DFS
Mode
0
1
2
3
4
-
DFS
[2:0]
000
001
010
011
100
-
fs(kHz)
48kHz
48
32
16
8
96
48
8
8
N/A
N/A
fs(kHz)
44.1kHz
44.1
(default)
29.4
14.7
88.2
44.1
N/A
N/A
(N/A: Not available)
(fs)
“0”
MS1024-J-00
2008/11
- 22 -
[AK7742]
2) CONT1 : RAM
Command Code Name
Write Read
C1h
41h
CONT1
D7
D6
D5
D4
D3
D2
D1
ATSPA
D
ATSPD
A
BANK[1
]
BANK[0
]
TEST
SS[1]
SS[0]
Ring 8.4f
Linear 24bit
D0
Default
0
00h
ATSPAD ADC
:
0: 912LRCK(max) (fs=48kHz 19ms) (default)
1: 912LRCK×4(max) (fs=48kHz 76ms)
ATSPDA DAC1/2
0: 1/fs (default)
1: 4/fs
:
BANK[1:0]: DLRAM Mode
DLRAM Mode
0
1
2
3
BANK[1:0]
00
01
10
11
SS[1:0]: DLRAM
SS Mode
SS[1]
0
0
1
0
2
1
3
1
Note 45. SS mode 1/2/3
Note 46. DLRAM mode 1/2
TEST bit
“0”
Ring 24bit
3072word
2048word
1024word
N/A
SS[0]
0
1
0
1
Ring 8.4f
(default)
2048word
2048word
N/A
1024word
N/A
(N/A: Not available)
(default)
2
4
8
(DLRAM mode 0
Ring 20.4f
)
“0”
MS1024-J-00
2008/11
- 23 -
[AK7742]
3) CONT2 : RAM
Name
Command Code
Write
Read
C2h
42h
CONT2
D7
D6
D5
D4
D3
D2
D1
D0
POMODE
DATARAM
BIT32FS
WAVM
WAVP[1]
WAVP[0]
EEFN
0
POMODE: DLRAM
0: OFREG (default)
1: DBUS
Default
0
DATARAM: DATARAM
DATARAM Mode
A(000h-3FFh)
1024word
B(400h-5FFh)
512word
0
1
(default)
DP0
BIT32FS: BICK32fs
0: BICK64fs (default)
1: BICK32fs
BICK
64fs
CKM mode 4
WAVM: CRAM WAV Mode
0: 1/4
(default)
1: 1/2
1/4
WAVP[1:0]: CRAM
WAVP Mode
WAVP[1]
0
0
1
0
2
1
3
1
DP1
BIT32FS bit = “1”
CRAM
WAVP[0]
0
1
0
1
WAVM=0
33word
65word
129word
257word
WAVM=1
65word
129word
257word
513word
FFT
128
256
512
1024
(default)
EFEN:
0:
1:
“0”
(default)
“0”
MS1024-J-00
2008/11
- 24 -
00h
[AK7742]
4) CONT3 :
Command Code
Write
Read
C3h
43h
/
Name
CONT3
D7
D6
D5
D4
D3
D2
D1
D0
Default
DIF[1]
DIF[0]
DOF[1]
DOF[0]
CLKS[2]
CLKS[1]
CLKS[0]
0
00h
DIF[1:0]: DSP DIN1, DIN2
DIF Mode
DIF[1]
0
0
1
0
2
1
3
1
2
Note 47. I S
(DIFI2S bit = “1”)
DIF[0]
0
1
0
1
DIF mode 0
DOF[1:0]: DSP DOUT1, DOUT2, DOUT3
DOF Mode
DOF[1]
DOF[0]
0
0
0
1
0
1
2
1
0
3
1
1
2
Note 48. I S
(DIFI2S bit = “1”)
DOF mode 0
CLKS[2:0]:CLKO
CLKS Mode
0
1
2
3
4
5
6
7
“0”
CLKS[2:0]
000
001
010
011
100
101
110
111
(24bit)
24bit
20bit
16bit
(default)
(default)
(24bit)
24bit
20bit
16bit
BIT32FS bit = “1”
fs=48kHz
12.288MHz
6.144MHz
3.072MHz
8.192MHz
4.096MHz
2.048MHz
18.432MHz
N/A
DOF mode 0
fs=44.1kHz
11.2896MHz
(default)
5.6448MHz
2.8224MHz
7.5264MHz
3.7632MHz
1.8816MHz
16.9344MHz
N/A
(N/A: Not available)
“0”
MS1024-J-00
2008/11
- 25 -
[AK7742]
5) CONT4 :
Command Code
Write
Read
C4h
44h
/
Name
CONT4
D7
D6
D5
D4
D3
D2
D1
D0
CLKOE
BITCLKEN
LRCLKEN
OUT2EN
OUT1EN
JX1E
JX0E
0
CLKOE: CLKO
0: CLKO
1: CLKO
Default
(default)
BITCLKEN:
AK7742
0:
(default)
1:
(Low
)
CKM mode 1-5
LRCLKEN:
AK7742
0:
(default)
1:
(Low
)
CKM mode 1-5
BICK
AK7742
BICK
LRCK
AK7742
LRCK
OUT2EN: SO/RDY/GPO/SDOUT2
0: SO/RDY/GPO/SDOUT2
1: SO/RDY/GPO/SDOUT2
OUT1EN: SDOUT1
0: SDOUT1
1: SDOUT1
(default)
(default)
JX1E:
0: SDIN1/JX1
1: SDIN1/JX1
SDIN1
JX1
(default)
0: SDIN2/JX0
1: SDIN2/JX0
SDIN2
JX0
(default)
JX0E:
“0”
“0”
MS1024-J-00
2008/11
- 26 -
00h
[AK7742]
6) CONT5: DSP
W
R
C5h
45h
Name
D7
D6
D5
D4
D3
D2
D1
D
0
Default
CONT5
SELDO5[0]
SELDO4[0]
SELDO3
SELDO2[1]
SELDO2[0]
SELDO1
SELDO4[1]
0
00h
D7: SELDO5[0] DAC2 SDINDA2
SELDO5 Mode
SELDO5[1]
CONT6 D3
0
0
1
0
2
1
3
1
SELDO5[0]
CONT5 D7
0
1
0
1
DSP
DOUT5
SDIN2 Pin
SDIN1 Pin
ADC
SDOUTAD
(default)
D6: SELDO4[0] DAC1 SDINDA1
SELDO4 Mode
SELDO4[1]
CONT5 D1
0
0
1
0
2
1
3
1
SELDO4[0]
CONT5 D6
0
1
0
1
DSP
DOUT4
SDIN1 Pin
SDIN2 Pin
ADC
SDOUTAD
(default)
D5: SELDO3 CLKO/SDOUT3
0: CLKO (default)
1: DSP DOUT3
D4, D3: SELDO2[1:0] SO/RDY/GPO/SDOUT2
SELDO2 Mode
SELDO2[1:0]
0
00
1
01
2
10
3
11
SO
RDY
DSP GPO
DSP DOUT2
(default)
D2: SELDO1 SDOUT1
0: DSP DOUT1 (default)
1: ADC SDOUTAD
D1: SELDO4[1]
D6
D0: 0
“1”
“0”
MS1024-J-00
2008/11
- 27 -
[AK7742]
7) CONT6: ADC
SELDO5[1]
Name
W
C6
h
R
46
h
CONT6
D7
D6
D5
D4
D3
D2
D1
ADMUTE
Reserved
ASEL[1]
ASEL[0]
SELDO5[1]
DA2MUTE
DA1MUTE
D
0
Default
0
00h
D7: ADMUTE ADC SMUTE
0: ADC SMUTE
(default)
1: ADC SMUTE
D6: Reserved
0:
0
(default)
D5, D4: ASEL[1:0]
ASEL Mode
0
1
2
3
ADC
ASEL1[1:0]
00
01
10
11
pin
AIN1LP,AIN1LN,AIN1RP,AIN1RN (default)
AIN2L,AIN2R
AIN3L,AIN3R
N/A
(N/A: Not available)
MUTE
D3: SELDO5[1] DAC2 SDINDA2
CONT5 D7
D2: DA2MUTE DAC2
0: DAC2 SMUTE
1: DAC2 SMUTE
SMUTE
(default)
D1: DA1MUTE DAC1 SMUTE
0: DAC1 SMUTE
(default)
1: DAC1 SMUTE
D0: 0
1
TEST bit
0
“0”
“0”
MS1024-J-00
2008/11
- 28 -
[AK7742]
8) CONT7: TEST
Name
Command Code
Write
Read
C7h
47h
CONT7
D7
D6
D5
D4
D3
D2
D1
D0
Default
DEM1[1]
DEM1[0]
DEM2[1]
DEM2[0]
TEST
TEST
TEST
0
00h
D7, D6 DEM1[1:0] DAC1
DEM Mode
DEM1[1:0]
0
00
1
01
2
10
3
11
D5, D4 EM2[10]
DEM Mode
0
1
2
3
TEST bit
Off
48KH
44.1KHz
32KHz
DAC2
DEM1[1:0]
00
01
10
11
“0”
(50/15μs
)
fs
(default)
(50/15μs
fs
Off
48KH
44.1KHz
32KHz
)
(default)
“0”
9) CONT8:
Command Code
Write
Read
C8h
48h
Name
CONT8
D7
D6
D5
D4
D3
D2
D1
SRESET
N
ADRST
DA2RST
DA1RS
T
DSPRS
T
TEST
CKRST
D7 : SRESETN:
0:
1: DSP / ADC / DAC
SRESETN bit = “0”
DAC1, DAC2
D0
Default
0
00h
(default)
ADCRST, DA2RST, DA1RST, DSPRST
ADC, DSP,
ADCRST, DA2RST, DA1RST, DSPRST
ADRST:
0: ADC
1: ADC
(default)
DA2RST:
0: DAC2
1: DAC2
(default)
DA1RST:
0: DAC1
1: DAC1
(default)
MS1024-J-00
2008/11
- 29 -
[AK7742]
DSPRST DSP
0: DSP
1: DSP
DSP
(default)
ADC, DAC
ADC, DAC
CKRST:
0:
1:
(default)
CKM mode
TEST bit
“0”
“0”
10) CONT10-11: ADC
W
D0h
R
50h
D1h
51h
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
CONT
10
CONT
11
VOLADL
[7]
VOLADR
[7]
VOLADL
[6]
VOLADR
[6]
VOLADL
[5]
VOLADR
[5]
VOLADL
[4]
VOLADR
[4]
VOLADL
[3]
VOLADR
[3]
VOLADL
[2]
VOLADR
[2]
VOLADL
[1]
VOLADR
[1]
VOLADL
[0]
VOLADR
[0]
30h
VOLADL[7:0], VOLADR[7:0]:
; L/R
30h
0.5dB step 256 Level
(Page 58, Table 4)
11) CONT12-15: DAC1, DAC2
Name
W
D2
h
R
52
h
CONT1
2
D3
h
53
h
CONT1
3
D4
h
54
h
CONT1
4
D5
h
55
h
CONT1
5
D7
D6
D5
D4
D3
D2
D1
D0
Default
VOLD
A
1L[7]
VOLD
A
1R[7]
VOLD
A
2L[7]
VOLD
A
2R[7]
VOLD
A
1L[6]
VOLD
A
1R[6]
VOLD
A
2L[6]
VOLD
A
2R[6]
VOLD
A
1L[5]
VOLD
A
1R[5]
VOLD
A
2L[5]
VOLD
A
2R[5]
VOLD
A
1L[4]
VOLD
A
1R[4]
VOLD
A
2L[4]
VOLD
A
2R[4]
VOLD
A
1L[3]
VOLD
A
1R[3]
VOLD
A
2L[3]
VOLD
A
2R[3]
VOLD
A
1L[2]
VOLD
A
1R[2]
VOLD
A
2L[2]
VOLD
A
2R[2]
VOLD
A
1L[1]
VOLD
A
1R[1]
VOLD
A
2L[1]
VOLD
A
2R[1]
VOLD
A
1L[0]
VOLD
A
1R[0]
VOLD
A
2L[0]
VOLD
A
2R[0]
18h
VOLDA1L/R[7:0], VOLDA2L/R[7:0] :
; L/R
18h
18h
18h
0.5dB step 256 Level
(Page 59, Table 7)
MS1024-J-00
2008/11
- 30 -
[AK7742]
■
1)
AK7742
3
(RUN
)
DSP/PLL/ADC/DAC
SRESETN bit “0”
“L”
DSP/ADC/DAC
CKRSTbit “1”
CKM Mode
PLL
IRESETN pin
IRESETN pin “H”
PLL
VREF
PLL
DSP
2)
AK7742
ADC, DAC, DSP, PLL
REF
CKM[2:0] pin
(CKM mode 3/4/5)
PLL
XTI
IRESETN pin= “L”
IRESETN pin
PLL
(CKM mode 0/1/2)
“L”
“H”
BICK
CKM[2:0] pin
3)
DSP
SRESETN
ADC/DAC
DSP
LRCK,
PLL, REF
SRESETN
BICK
AK7742
“0”
“1”
4)
CKM[2:0]Pin
ICLK XTI@CKM mode 0/1/2 or BICK@CKM mode 3/4/5
(INITRSTN pin=“L”)
PLL
CKRST bit= “1”(CONT8 D1)
Pin
CKRST
1 0
50ms
DSP
PLL
PLL
DSP
SRESETN bit
MS1024-J-00
“1”
AK7742
2008/11
- 31 -
[AK7742]
CKM mode 0
CKM mode 5
XTI
BICK
600ns(min)
Command
0xC8 0x00
SRESETN bit
0xC8 0x02
0xC8 0x00
0xC8 0x80
SRESETN bit=”1”
SRESETN bit=”0”
CKRST bit=”1”
CKRST bit
CKRST bit=”0”
SRESETN bit =0:
PLL
(50ms)
SRESETN bit =1:
CKRST bit =0:
& DSP
CKRST bit =1:
Figure 11.
5)
(RUN
CKM Mode 0
CKM Mode 5
)
DSP ADC/DAC
RUN
AK7742
CRAM
CKM mode 1/2
AK7742
LRCK/BICK
LRCK
LRCK
LRCK
LRCK
DSP
4LRCK(max)
ADC
16.5ms@fs=8kHz)
130LRCK
(max)
MS1024-J-00
1LRCK(max)
(2.75ms@fs=48kHz,
2008/11
- 32 -
[AK7742]
■
/
1.
IRESETN pin “L”
AVDD DVDD
REF
(MCLK)
IRESETN pin
IRESETN pin
PLL
PLL
AK7742
Note 49.
PLL
,
,
Note 50.
XTI
IRESETN pin
Note 51. XTI pin
“H”
“H”
BICK pin
(AVDD, DVDD)
AVDD=DVDD
Initial Reset (1)
IRESETN pin
System Reset (1)
SRESETN bit
XTI(Pin)
CKM0-2
BICK(Pin)
(
CKM3-5
PLLCLK)
(
)
(1s)
PLL
OFF
DSP
IRESETN pin
>10ms
(1)
(IRESETN pin= “L”)
AVDD DVDD
(BICK)
1sec
(XTI)
Figure 12.
MS1024-J-00
2008/11
- 33 -
[AK7742]
2.
(IRESETN pin= “L”)
AVDD/DVDD
AVDD=DVDD
IRESETN pin
OFF
(“L”)
Figure 13.
■ RAM
AK7742
RAM
RAM
DSP
DRAM DLRAM
0”
PLL
200µs
RUN
RAM
RAM
RAM
■
RAM
RAM
RAM
IRESETN pin
SRESETN bit
RAM
DSP
RAM
DSP
Figure 14. RAM
MS1024-J-00
2008/11
- 34 -
[AK7742]
■
SDIN1-2, SDOUT1-3
2's
I2S
LRCK, BICK
MSB
I2S
CKM mode 4/5
2
IS
SDIN1-2
24bit
(24bit)
1.
PCM
(24bit)
16bit, I2S
20bit
SDOUT1-3
24bit,
16bit, I2S
(24bit), BICK64fs (DIFI2S= “0”)
LRCK
Left ch
Right ch
BICK
31 3029 28 27
10 9 8 7 6 5 4 3 2 1 0 31 3029 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1/2
DIF Mode 0
M 22 21 20 19
2 1 L
M 2221 20 19
2 1 L
M:MSB, L:LSB
SDOUT1/2/3
DOF Mode 0
M 22 21 20 19
2 1 L
M 2221 20 19
2 1 L
M:MSB, L:LSB
Figure 15.
2.
(24bit), BICK64fs (DIFI2S= “0”)
(24bit), BICK48fs (DIFI2S= “0”)
Left ch
LRCK
Right ch
BICK
23 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19
10 9 8 7 6 5 4 3 2 1 0
SDIN1,2
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 L M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 L
M:MSB,L:LSB
SDOUT1-3
M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 L M 22 21 20 19
10 9 8 7 6 5 4 3 2 1 L
Figure 16.
(24bit), BICK48fs (DIFI2S=“0”)
MS1024-J-00
2008/11
- 35 -
[AK7742]
3.
(24bit/20bit/16bit), BICK64fs (DIFI2S= “0”)
LRCK
Left ch
Right ch
BICK
31 30
23 22 21 20 19 18 17 16 15 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
SDIN1/2
DIF Mode 1
Don’t care M 22 21 20 19 18 17 16 15 14
1 L Don’t care M 22 21 20 19 18 17 16 15 14
1 L
SDIN1/2
DIF Mode 2
Don’t care
M 18 17 16 15 14
1 L Don’t care
M 18 17 16 15 14
1 L
SDIN1/2
DIF Mode 3
Don’t care
M 14
1 L Don’t care
M 14
1 L
M:MSB, L:LSB
SDOUT1/2/3
DOF Mode 1
MSB
22 21 20 19 18 17 16 15 14
1 L
MSB
22 21 20 19 18 17 16 15 14
1 L
SDOUT1/2/3
DOF Mode 2
MSB
18 17 16 15 14
1 L
MSB
18 17 16 15 14
1 L
SDOUT1/2/3
DOF Mode 3
MSB
14
1 L
MSB
14
1 L
Figure 17.
(24bit/20bit/16bit), BICK64fs (DIFI2S= “0”)
MS1024-J-00
2008/11
- 36 -
[AK7742]
4. I2S
(BICK=64fs)
LRCK
Left ch
Right ch
BICK
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1/2
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
SDOUT1/2/3
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
M:MSB, L:LSB
M:MSB, L:LSB
(24bit)
Figure 18. I2S
5. I2S
(BICK=48fs)
Left ch
Right ch
LRCK
BICK
SDIN1,2
SDOUT1,2,3
23 22 21 20 19
9 8 7 6 5 4 3 2 1 0 23 22 21 20 19
M 22 21 20
9 8 7 6 5 4 3 2 1 L M 22 21 20
M 22 21 20
9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 L
9 8 7 6 5 4 3 2 1 L M 22 21 20
9 8 7 6 5 4 3 2 1 L
M:MSB
L:LSB
(24bit)
Figure 19. I2S
6. BICK 32fs (CKM Mode 4)
Left ch
Right ch
LRCK
BICK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDIN1/2
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L
SDOUT1/2/3
M:MSB
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L L:LSB
Figure 20. BICK 32fs (CKM Mode 4)
MS1024-J-00
2008/11
- 37 -
[AK7742]
5. PCM
LRCK
tBCLK
SF
BICK
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
SDIN1/2
M 22 21 20 19
2 1 L
SDOUT1/2/3
M 22 21 20 19
2 1 L
M:MSB, L:LSB
Left ch
10 9 8 7 6 5 4 3 2 1 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
Right ch
Figure 21. 64fs Short-frame, Rising-edge (CKM Mode 5)
LRCK
tBCLK
SF
BICK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDIN1/2
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L
SDOUT1/2/3
M:MSB
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L L:LSB
Left ch
Right ch
tBCLK × 16
tBCLK × 16
Figure 22. 32fs Short-frame, Rising-edge (CKM Mode 4)
LRCK
tBCLK
SF
BICK
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1/2
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
SDOUT1/2/3
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
M:MSB, L:LSB
Left ch
Right ch
Figure 23. 64fs Short-frame, Falling-edge (CKM Mode 5)
MS1024-J-00
2008/11
- 38 -
[AK7742]
LRCK
tBCLK
SF
BICK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDIN1/2
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L
SDOUT1/2/3
M:MSB
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L L:LSB
Left ch
Right ch
tBCLK × 16
tBCLK × 16
Figure 24. 32fs Short-frame, Falling-edge (CKM Mode 4)
1 ≤ tBCLK ≤ 60
LF
LRCK
BICK
SDIN1/2
SDOUT1/2/3
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
tBCLK
M:MSB, L:LSB
10 9 8 7 6 5 4 3 2 1 0
M 22 2120 19
2 1 L
M 22 2120 19
2 1 L
Left ch
Right ch
tBCLK × 32
tBCLK × 32
Figure 25. 64fs Long-frame, Rising-edge
LF
1 ≤ tBCLK ≤ 28
tBCLK
LRCK
BICK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDIN1/2
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L
SDOUT1/2/3
M:MSB
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L L:LSB
Left ch
Right ch
tBCLK × 16
tBCLK × 16
Figure 26. 32fs Long-frame, Rising-edge
MS1024-J-00
2008/11
- 39 -
[AK7742]
1 ≤ tBCLK ≤ 60
LRCK
LF
BICK
SDIN1/2
SDOUT1/2/3
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
tBCLK
M:MSB,L:LSB
10 9 8 7 6 5 4 3 2 1 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
Left ch
Right ch
tBCLK × 32
tBCLK × 32
Figure 27. 64fs Long-frame, Falling-edge
LF
1 ≤ tBCLK ≤ 28
tBCLK
LRCK
BICK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDIN1/2
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L
SDOUT1/2/3
M:MSB
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L L:LSB
Left ch
Right ch
tBCLK × 16
tBCLK × 16
Figure 28. 32fs Long-frame, Falling-edge
MS1024-J-00
2008/11
- 40 -
[AK7742]
■
1.
7bit +
Bit
7
8bit
CAD[1:0] pin
CAD[1:0]= “00” :
CAD[1:0]= “01” :
CAD[1:0]= “10” :
CAD[1:0]= “11” :
bit
R/W
Chip Address
8
31h
33h
35h
37h
7bit
30h
32h
34h
36h
PRAM/CRAM/Register
Command
16 / 0
PRAM/CRAM/OFRAM
0bit
Address
16bit
Data
SCL
SDA
Str
Chip address WAck
Command
Ack Address (MSB)
Ack Address (LSB)
Ack
Data1 (MSB)
Ack
Data1 (LSB)
Ack Stp
Address 16bit, Data 16bit
2.
BIT7
R/W
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
R/W
“1”
WRITE
“0”
READ
BIT6
0
0
0
BIT5
0
0
1
BIT4
0
1
0
0
1
1
1
1
1
0
1
1
0
0
1
BIT3
0
0100/0010
1000/0100/0010
CRAM
RUN
OFRAM
RUN
CRAM, OFRAM RUN
PRAM, CRAM, OFRAM
0
0000
BIT0
0100
0110
1000
15
0
JX
@MICR
@MIR2
MS1024-J-00
2008/11
- 41 -
[AK7742]
3.
LSB
BIT[6:4]= “000”
BIT[6:4]= “100”
“011”
“111”
16bit
4.
RAM
■
80h
90h
8Fh
9Fh
A2h
A4h
B2h
B4h
B8h
C0h
CFh
F4h
16bit
16bit
16bit
16bit
16bit
16bit
16bit
16bit×(n+1)
n:
CRAM
16bit×(n+1)
n:
OFRAM
16bit×n
16bit×n
40bit×n
80h
1 81h
BIT3 BIT0
8Fh
16
2
RUN
90h
1 91h
2
BIT3 BIT0
9Fh
16
OFRAM RUN
CRAM RUN
OFRAM
CRAM
PRAM
8bit
8bit
RUN
0
15
JX
RAM
■
32h
34h
38h
40h 4Fh
60h
76h
78h
16bit
16bit
16bit
16bit×n
16bit×n
40bit×n
8bit
8bit
32bit
32bit
OFRAM
CRAM
PRAM
0~15
@MICR
24bit
@MIR2
24bit
MS1024-J-00
4bit
Validity
0000
4bit
Validity
0000
2008/11
- 42 -
[AK7742]
5.
[1]
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
(7) DATA4
(8) DATA5
RAM(PRAM)
B8h
0 0 0 0 0 A10 A9 A8
A7 A0
0 0 0 0 D35 D34 D33 D32
D31 D24
D23 D16
D15 D8
D7 D0
5byte
RAM(CRAM)
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
[2]
B4h
0 0 0 0 0 0 A9 A8
A7 A0
D15 D8
D7 D0
2byte
RAM(OFRAM)
B2h
00000000
0 0 A5 A4 A3 A2 A1 A0
0 0 0 D12 D11 D10 D9 D8
D7 D0
2byte
RUN
RUN
(1) COMMAND
(2) DATA
Note 52.
Input
C0h DFh
D7 D0
RUN
(1) COMMAND
(2) DATA
Input
F4h
D7 D0
RUN
MS1024-J-00
2008/11
- 43 -
[AK7742]
[3] RUN
RAM(CRAM)
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
RUN
Input
80h 8Fh 80h
0 0 0 0 0 0 A9 A8
A7 A0
D15 D8
D7 D0
2byte
1
8Fh
16
90h 9Fh 90h
1
00000000
0 0 A5 A4 A3 A2 A1 A0
0 0 0 D12 D11 D10 D9 D8
D7 D0
2byte
9Fh
16
Note 53. COMMAND
Input
A4h
00000000
00000000
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
RAM(OFRAM)
Input
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
RUN
Note 53. COMMAND
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
Input
A2h
00000000
00000000
MS1024-J-00
2008/11
- 44 -
[AK7742]
[4]
RAM(PRAM)
Input
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
(7) DATA4
(8) DATA5
Output
38h
0 0 0 0 0 A10 A9 A8
A7 A0
0 0 0 0 D35 D34 D33 D32
D31 D24
D23 D16
D15 D8
D7 D0
5byte
RAM(CRAM)
Input
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
Output
34h
0 0 0 0 0 0 A9 A8
A7 A0
D15 D8
D7 D0
2byte
RAM(OFRAM)
(1) COMMAND
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
Input
32h
00000000
0 0 A5 A4 A3 A2 A1 A0
Output
0 0 0 D12 D11 D10 D9 D8
D7 D0
2byte
MS1024-J-00
2008/11
- 45 -
[AK7742]
[5]
RUN
RUN
Input
(1) COMMAND
(2) DATA
40h
Output
5Fh
D7
D0
RUN
Input
(1) COMMAND
(2) DATA
Output
60h
D7
0
D6
1
D5
0
4
D4
0
D3
0
D2
0
2
D1
1
D0
0
[6] RUN
@MICR
RUN
Input
(1) COMMAND
(2) DATA1
(3) DATA2
(4) DATA3
(5) DATA4
Note 54. flag
Output
76h
D27 D20
D19 D12
D11 D4
D3 D2 D1 D0 (flag) (flag) (flag) (flag)
“0”
@MIR2
RUN
Input
(1) COMMAND
(2) DATA1
(3) DATA2
(4) DATA3
(5) DATA4
Note 54. flag
Output
78h
D27 D20
D19 D12
D11 D4
D3 D2 D1 D0 (flag) (flag) (flag) (flag)
“0”
MS1024-J-00
2008/11
- 46 -
[AK7742]
6.
[1]
RAM
RAM(PRAM)
RAM(CRAM)
RAM(OFRAM)
SCL
SDA
Str
Chip
W Ack Comm(0xB4)Ack Addr (0x00) Ack Addr (0x00) Ack D1 (MSB)
D1
D2
[2] RUN
B4h
2word
Ack D1 (LSB)
CRAM
Ack D2 (MSB)
Ack D2 (LSB)
Ack Stp
0000h
RAM
RAM(CRAM)
RAM(OFRAM)
(8bit)
1 16
(16bit),
RUN
RAM
DSP
RAM
5
16bit all0
RUN
RAM
“10”
7
RAM
“13”
8
9
10
↓
○
11
↓
○
13
↑
16
11
12
↓
○
13
↓
○
14
↓
○
15
“12”
Note 55.
Note 56. DSP
fs
CRAM
2LRCK
MS1024-J-00
2008/11
- 47 -
[AK7742]
[3]
RUN
(1) COMMAND
(2) DATA
F4h
D7 D0
RUN
8
LRCK
10
JX0 JX1 pin
“1” 1
IFCON
IFCON
IRESETN pin = “L”
00h
7
6
5
4
3
2
1
0
■
■
■
■
↑
■
■
■
IFCON
JX1
■
JX
0
□
9
8
7
□
“1”
16
↓
IFCON
Note 57.
2LRCK
[4]
RAM
RAM(PRAM)
[5]
RAM(CRAM)
RAM(OFRAM)
RUN
RUN
MS1024-J-00
2008/11
- 48 -
[AK7742]
■ I2C
(I2CSELpin= “H”)
I2C
AK7742
I 2C
DSP
(max:400kHz)
HS mode (max:3.4MHz)
1.
IC
·
1
·
IC
IC
READ
IC
WRITE
·
1-1.
SDA
SCL
“L”
“L”
“H”
“H”
“H”
SCL
“L”
SDA
SDA
SCL
·
·
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 29.
1-2.
(Start Condition)
SCL
“H”
(Stop Condition)
SDA
“H”
“L”
·
SDA
“L”
“H”
·
·
SCL
“H”
·
SCL
SDA
START CONDITION
Figure 30.
STOP CONDITION
·
·
MS1024-J-00
2008/11
- 49 -
[AK7742]
1-3.
Repeated Start Condition
SCL
SDA
START CONDITION
Repeated Start CONDITION
Figure 31.
1-4.
(Acknowledge)
IC
1
SDA
IC
AK7742
WRITE
AK7742
SDA
HIGH
“L”
·
·
READ
SDA
SDA
AK7742
·
AK7742
Not Acknowledge
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
9
not acknowledge
acknowledge
START
CONDITION
Figure 32.
acknowledge
MS1024-J-00
2008/11
- 50 -
[AK7742]
1-5.
IC
IC
“00110”
7
2
IC
CAD pin
·
IC
R/W
8
READ
5
R/W bit=“0”
R/W bit= “1”
WRITE
R/W bit= “0”
R/W bit=”1”
0
0
1
1
0
CAD1
CAD0
R/W
(CAD1, CAD0
)
Figure 33.
1-6.
I2C
AK7742
8
I2C
MSB
8
A1B2C3(hex)
24bit
2
IC
2
(1)
(1)I C
A1
B2
C3
A1
B2
A
24BIT
8BIT
C3
A
8BIT
8BIT
A …Acknowledge
Figure 34.
Write
Read
Write
Read
MS1024-J-00
2008/11
- 51 -
[AK7742]
2. Write
AK7742
Write
Figure 35
Write
*1
Table 1. Write
S
SLAD
W
A
Cmd
A
Data
A
Write
Stp
repeat N times (*1)
Figure 35. Write
80h
90h
8Fh
9Fh
A2h
A4h
B2h
B4h
B8h
C0h CFh
F4h
Note 58.
2byte
2byte
2byte
2byte
2byte
2byte
2byte
2byte
n:
×(n+1)
2byte
n:
×(n+1)
2byte
2byte
5byte
1byte
1byte
CRAM
RUN
80h
OFRAM
2
BIT3
8Fh
2
BIT3 BIT0
9Fh
16
RUN
90h
×n
×n
×n
1 81h
1 91h
BIT0
16
OFRAM RUN
CRAM RUN
OFRAM
CRAM
PRAM
0 15
JX
RAM
Table 1. Write
Write
MS1024-J-00
2008/11
- 52 -
[AK7742]
3. Read
AK7742
Read
Read
Figure 36
*2
Figure 36
*3
Read
AK7742
Read
Table 2. Read
S
SLAD
W
A
Cmd
A
Data
A
rS
SLAD
R
Read
A
Repeat N times ( *2 )
Data
A
Data
Na
Stp
Repeat N-1 times ( *3 )
Figure 36. Read
32h
34h
38h
40h 4Fh
60h
76h
78h
2byte
2byte
2byte
2byte×n
2byte×n
5byte×n
1byte
1byte
4byte
4byte
OFRAM
CRAM
PRAM
0
15
@MICR
28bit
@MIR2
28bit
Note 59.
4bit
Validity
0000
4bit
Validity
0000
RAM
Table 2. Read
Read
MS1024-J-00
2008/11
- 53 -
[AK7742]
Read
Read
AK7742
Read
Read
AK7742
RDY
2
IC
Read
Low
S
Read
High
SLAD
W Na
Cmd
Na
xxx
Na
rS
SLAD
R Na
Read
N
RDY
Read
RDY
“H”
Figure 37. Read
MS1024-J-00
2008/11
- 54 -
[AK7742]
Note: I2C
SLAD
…SlaveAddress (7 bits)
Cmd
…Command Code (8 bits)
S
…StartCondition
rS
…Repeated StartCondition
Stp
…StopCondition
W
…
R/W
Write(=0)
Write (1 bit)
R
…
R/W
Read(=1)
Read (1 bit)
A
…Acknowledge (1 bit)
Na
…NotAcknowledge (1 bit)
(Gray)
(White)
…
AK7742
MS1024-J-00
2008/11
- 55 -
[AK7742]
■ ADC
1. ADC
AK7742
HPF
ADC
DC
(HPF)
1Hz(fs=48kHz)
(fs)
48kHz
0.93Hz
(fs)
44.1kHz
0.86Hz
8kHz
0.16Hz
Table 3.
2.
ADC
ADMUTE
1
-∞ (0)
ADMUTE
-∞
ATT
0
ATT
Attenuation 0dB
-∞
-∞
ATT
ATT
-∞
×ATT
×ATT
ATT
Attenuation 0dB
912LRCLK(828+GD(30))
ADC
INITRSTN pin = “L”
ADMUTE bit
GD
0dB
Attenuation
GD
912LRCK(max)
-∞dB
912LRCK(max)
AOUT
Figure 38.
MS1024-J-00
2008/11
- 56 -
[AK7742]
3.
(2)
200ms
<
(3)
>
A DMUTE bi t
( 2)
( 1)
DA TT Le ve l
( 1)
( 3)
A tte nu a ti on
-∞
A IN 2L /AIN2 R
Ch an n el
A IN3L /AIN3 R
Figure 39.
(1)
-∞
DATT
Attenuation 0dB
ATSPAD bit
(CONT1 D7)
0
1
LRCK
912LRCK
912LRCK x 4
Figure 40.
ATSPAD
fs=48kHz
19ms
76ms
MS1024-J-00
0dB
Attenuation 0dB
(1)
(max)
fs=44.1kHz
20.68ms
82.72ms
-∞
fs=8kHz
114ms
456ms
2008/11
- 57 -
[AK7742]
4. ADC
AK7742
ADC
Lch,Rch
(256
0.5dB
)
ADC Lch
ADC Rch
Attenuation Level
VOLADL [7:0] VOLADR [7:0]
00h
00h
+24.0dB
01h
01h
+23.5dB
02h
02h
+23.0dB
:
:
:
2Fh
2Fh
+0.5dB
30h
30h
0.0dB
(default)
31h
31h
-0.5dB
:
:
:
FDh
FDh
-102.5dB
FEh
FEh
-103.0dB
FFh
FFh
Mute (-∞)
Table 4.
ATSPADbit
Mode
ATSPAD bit
0
0
1
1
Table 5. ADC
ATT
Attenuation speed
1/fs
4/fs
1021
00h-FF(Mute)
30h
ADC
MS1024-J-00
(default)
Mode0
1021/fs(21.3ms fs48KHz)
2008/11
- 58 -
[AK7742]
■ DAC
1.
DAC
IIR
DAC1
DEM Mode
0
1
2
3
48KHz
DEM1[1:0] bits, DAC2
DEM[1:0] bit
00
01
10
11
Table 6.
(50/15μs
)
DEM2[1:0]bits
fs
Off
48KHz
44.1KHz
32KHz
(default)
2. DAC
AK7742
DAC
DAC1
VOLDA2R[7:0]bits
VOLDA1L[7:0] bits
(256
0.5dB
VOLDA1R[7:0]bits
DAC2
VOLDA2L[7:0] byte
VOLDA2R[7:0] byte
VOLDA1L[7:0] byte
VOLDA1R[7:0] byte
00h
01h
02h
:
17h
18h
19h
:
FDh
FEh
FFh
Table 7. DAC1, DAC2
)
DAC
VOLDA2L[7:0] bits
Attenuation Level
+12dB
+11.5dB
+11.0dB
:
+0.5dB
0.0dB
-0.5dB
:
-114.5dB
-115dB
Mute
(default)
ATSPDAbit
Mode
ATSPDA bit
0
0
1
1
Table 8. DAC1, DAC2
ATT
Attenuation speed
1/fs
4/fs
1021
(default)
Mode0
1021/fs(21.3ms fs48KHz)
00h-FF(Mute)
DAC1,DAC2
MS1024-J-00
18h
2008/11
- 59 -
[AK7742]
3.
DAC1,DAC2
×ATT
-∞
DA1MUTE, DA2MUTE
-∞ (0)
×ATT
ATT
ATT
“1”
DAC
DA1RST bit= “1”, DA2RST bit= “1”
SRESETN bit= “0”
ATT
ATT
DA1MUTE, DA2MUTE “0”
-∞
ATT
dB
DAC
INITRSTN pin= “L”
DA1MUTE bit
DA2MUTE bit
+2/fs(max)
+2/fs(max)
0dB
Attenuation
-
dB
GD
GD
Figure 41.
MS1024-J-00
2008/11
- 60 -
[AK7742]
Figure 42
AKD7742
0.1μ
Digital +3.3V
0.1μ
10μ
CLOCK
CONTROL
8,16,17
22
I2CSEL
LRCK
23
SDA
BICK
24
CLKO
CLOCK
CKM[2:0]
DVDD
9
20
DVDD x 2
SCL
CLKO/SDOUT3
CAD0
CAD1
SDOUT3
GPO/SDOUT2
13
SDOUT1
Audio I/F
19
26
27
28
Micom
29
25
I/F
GPO
AK7742
SDOUT2
14
Jump
SDIN1/JX1
15
SDIN2/JX0
IRESETN
TESTI
47,46
45,44
3
2
1
48
1μF
C1
31
6
12nF
10μ
0.1μ
10μ
0.1μ
Analog +3.3V
4
43
32
10μ
0.1μ
10,21
18
RESET
CONTROL
7
AIN1LP,AIN1LN
AIN1RP,AIN1RN
XTO
AIN2L
12
CL
Rd
AIN2R
XTI
AIN3L
11
CL
AIN3R
AOUT1LP,AOUT1LN
AVDRV
AOUT1RP,AOUT1RN
LFLT
AVDD
AOUT2LP,AOUT2LN
AOUT2RP,AOUT2RN
40,39
38,37
36,35
34,33
AVDD
VCOM
AVDD
VSS1
VSS2
42
0.1μ
2.2μ
5,30,41
Rd
Figure 42.
MS1024-J-00
2008/11
- 61 -
[AK7742]
(2)
1)
AK7742
AVDD
DVDD
AVDD
PC
AK7742
2)
AVDD
VCOM pin
AVDD/2
Pin
0.1μF
2.2μF
VSS1
Pin
VCOM pin
VCOM pin
3)
±FS=±(AVDD)×2.0/3.3
AVDD=3.3V
FS=(AVDD)×2.0/3.3
±2.00Vpp(typ)
2’s
2.00Vpp(typ)
AK7742
64fs
64fs
AK7742
(RC
64fs
)
AK7742
+3.3V(typ)
AVDD+0.3V
VSS1-0.3V
10mA
IC
±15V
10k
10k
Signal
22μ
+
10k
68p +10V
+
10k
-10V
2.00Vpp
68p
+
NJM5532D
+
+
AINLP
AINLN
2.00Vpp
Figure 43.
MS1024-J-00
2008/11
- 62 -
[AK7742]
4)
AVDD/2
7FFFFFH(@24bit)
000000H(@24bit)
VAOUT
2’s
800000H(@24bit)
AVDD/2 +
mV
DC
4.7k
1.1k +
3.6k
33u
33u
+
AOUT+
1.83Vpp
0V
DC
1.83Vpp
AOUT-
±1.83Vpp(typ.)
1.1k
3.66Vp
180
8.2n
8.2n
3.6k
+10V
+
180
4.7k
470p
470p
22u
+
NJM5532D
VAOUT
220
10k
-10V
Figure 44.
1.1kΩ
5)
AK7742
XTI pin
XTO pin
XTI XTO
CKM Mode
0
XTI, XTO pin
R1 (max)
70Ω
C0 (max)
5pF
Table 9.
(CL)
22pF
6) LFLT Pin
AK7742
LFLT pin
C
C1
12nF± 30%
MS1024-J-00
2008/11
- 63 -
[AK7742]
(AK7742EQ)
48pin LQFP (Unit: mm)
1.70Max
9.0 ± 0.2
0.13 ± 0.13
7.0
1.4± 0.05
25
24
48
13
7.0
37
9.0 ± 0.2
36
1
12
0.09 ∼ 0.20
0.5
0.22 ± 0.08
0.10 M
0° ∼ 10°
0.10
0.3 ∼ 0.75
■
(
MS1024-J-00
)
2008/11
- 64 -
[AK7742]
(AK7742EN)
48pin QFN (Unit: mm)
6.20 ± 0.10
0.45 ± 0.10
B
Exposed
Pad
48
1
0.18
0.20 ± 0.05
4.40TYP
6.00 ± 0.05
6.20 ± 0.10
6.00 ± 0.05
4-C0.5
12
A
1
4.40TYP
0.40
±0.05
48
0.22 ±0.05
0.85 ± 0.05
0.05 M
0.45 ±0.10
:
0.05 C
0.02TYP
0.005MIN 0.04MAX
C
(Exposed Pad)
■
(
MS1024-J-00
)
2008/11
- 65 -
[AK7742]
(AK7742EQ)
AKM
AK7742EQ
XXXXXXX
1
XXXXXXX: Date code identifier (7 digits)
(AK7742EN)
AKM
AK7742EN
XXXXXXX
48
1
XXXXXXX: Date code identifier (7 digits)
MS1024-J-00
2008/11
- 66 -
[AK7742]
Date (YY/MM/DD)
08/11/07
Revision
00
Reason
Page
Contents
•
•
•
•
•
•
MS1024-J-00
2008/11
- 67 -