AK8996 Data Sheets

[AK8996/W]
AK8996/W
Pressure Sensor Interface IC
The AK8996 is a pressure sensor interface IC that features compensation for temperature drift and sensor
variation. It is designed to excite and interface to a bridge sensor. Variations in the sensor can be
corrected via compensation values stored in integrated non-volatile memory (EEPROM). Compensation
values are obtained from measurement results for a set of offset voltages and temperature drift, along with
a set of bridge voltages and temperature drift, including characteristics of the AK8996. The AK8996 is
available in either a 16-pin QFN package or in wafer form.
Features
 Pressure sensor compensation and excitation IC (Analog output)
 Low power consumption:
350µA typ. @ 100Hz sampling
 Standby function:
1µA max.
 Low-voltage operation:
2.2 to 3.6V, 5V±10%
 Operating temperature range: -40 to 105ºC
 Integrated span voltage switching function (by a factor of 5, typ.)
Resolution:
Gain Amp. 1: 3-bits; Gain Amp. 2:1-bit
Adjustment step: factor of 1/step (by a factor of 2 to 9);
factor of 1/step (by a factor of 1 and 2)
 Integrated sensor output compensation
 Offset voltage adjustment
- Resolution:
Rough: 4-bits; Fine: 7-bits
- Adjustment step: Rough: 7.5%/step; Fine 0.125%/step @VDD: 5.0V
 Offset voltage temperature drift adjustment (1st/2nd order coefficient)
- Resolution:
10-bits; 8-bits
- Adjustment step: 0.196%/step; 0.787%/step
 Output span voltage adjustment
Resolution:
9-bits
Adjustment value: 100/[100+0.25*N](%)
N: -256 to +255
 Sensitivity temperature drift adjustment (1st/2nd order coefficient)
Resolution:
10-bits; 8-bits
Adjustment step: 0.196%/step; 0.787%/step
 Integrated output reference voltage switching function
Resolution:
Rough 5-bits; Fine 6-bits
Adjustment step: 0.0005*VDD/step (0.0785*VDD to 0.9215*VDD) @VO
 Integrated criteria adjustment function for determining positive/negative pressure
Resolution:
10-bits
Adjustment step: 0.001*VDD/step (0.05*VDD to 0.95*VDD)
 Integrated output gain (buffer gain) switching function (by a factor of 4, typ.)
Resolution:
3-bits
Adjustment step: factor of 0.5/step (by a factor of 2 to 4)
 Integrated sampling frequency switching function:
100Hz, 1kHz, 2kHz, 10.24kHz
 Ratiometric voltage output
 Integrated constant voltage source for pressure sensor
: 2.0V @VDD: 2.2 to 3.6V; 4.0V @VDD: 5.0V±10%
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 Integrated reference voltage & reference current generator
- VREF voltage adjustment control
Resolution:
3-bits
Adjustment step: 1%/step
- IREF current adjustment control
Resolution:
4-bits
- Adjustment step: 2.7%/step typ.
 Integrated temperature sensor
Temperature range:
-40 to 105C
- Temperature sensor output voltage adjustment control
Resolution:
6-bits
Adjustment step: 0.2%/step
 Integrated timer oscillator for intermittent operation (1024 kHz typ.)
- Oscillating frequency adjustment control
Resolution:
4-bits
Adjustment step: 5%/step
 Integrated EEPROM for compensation values and control data storage
Size:
157 bits
Endurance:
1,000 times or more
Retention time:
10 years or more @Ta: 105C
 Integrated pressure detection/self-diagnosis function
 Supply type:
Wafer PKG (UQFN16)
Product name
AK8996
AK8996W
Supply Type
PKG (UQFN16)
Wafer
Note
Block Diagram
Oscillator
Regulator
VS
Timing
Logic
V_Bandgap
V_Reference
I_Reference
Pressure
Judge
VDD track
Gain Temp.
track
STV
V_Temp.
Offset_Temp.
VSS
VSSO
V_
Common
VOUT
EEPROM
Gain Amp.1
Gain Amp.2
Offset
Gain Amp.3
PTH
DET
Buffer
S/H1&
Level
Shift
Gain
S/H2
EEPROM
&
Control
Register
Gain Amplifier Block
2
AGND
Pressure Detector
Gain_Temp.
LPF
MS1055-E-02
VDD
VOUT
Offset Temp.
track
VP
VN
Power ON
Delay
VOUT
VO
32kohm
Serial I/F
SDI/O
SCLK
CS
STBYN
2011/12
[AK8996/W]
Overview
The AK8996 is a pressure sensor interface IC that features compensation for temperature drift and sensor
variation. It is designed to excite and interface to a bridge sensor. Variations in the sensor can be
corrected via compensation values stored in integrated non-volatile memory (EEPROM). Compensation
values are obtained from measurement results for a set of offset voltages and temperature drift, along with
a set of bridge voltages and temperature drift, including characteristics of the AK8996.
The internal compensation circuit is accomplished through DACs, with 4-bit and 7-bit resolution to adjust
offset voltage of the sensor, and the secondary characteristics compensator for the associated
temperature drift, coupled with 9-bit resolution to adjust the span voltage and another secondary
characteristics compensator for its associated temperature drift. Depending on the application, the internal
EEPROM values can be pre-configured to enable adjustment of the reference sensitivity and the output
reference voltage. For the adjustment procedure, see the sections on "Adjustment Sequence" and
"Functional Description".
Depending on the application, the AK8996’s internal EEPROM values can be preconfigured to enable
adjustment of the reference sensitivities and output reference voltages. Sampling frequencies can be
switched between 100Hz, 1kHz, 2kHz and 10.24kHz using the internal EEPROM data.
The AK8996 is provided with a pressure detection circuit. If the applied pressure exceeds the defined
voltage threshold at the PTH terminal, a high-level signal is output on the DET pin. The threshold can be
adjusted by the internal EEPROM data. The AK8996 is also provided with a self-diagnostic function. Upon
power-up or at initial operation immediately after exiting standby mode, this self-test feature checks for the
required value at the output (VOUT pin), and if an expected value is not available, the output is assumed to
be anomalous and a high-level signal is output on the DET pin, in the same manner as with the pressure
detection.
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Pin Configuration
1. Wafer Configuration
For the detail, please contact your local sales office or authorized distributor.
2. Package Outline (UQFN16)
NC
VDD
VSS
D ET
12
11
10
9
VOUT
13
8
SDI/O
VO
14
7
SC LK
PTH
15
6
CS
AGND
16
5 STBYN
4
VS
VN
VP
4
3
2
1 VSSO
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Adjustment Characteristics
1) Adjustable Sensor Characteristics (Reference Example)
Item
Drive voltage
Temperature range
Sensor resistance
Voltage input span
range
Symbol
Svs1
Svs2
Sta
Sres1
Min.
Typ.
4
2
Max.
-40
3
5
Units
V
V
C
k
Sres2
1
2
k
Sspnin
1
Sspnin
2
Sspn
22.22
80
200
mV
VDD: 2.2 to 3.6V
& 5V±10%
VDD: 2.7 to 3.6V
& 5V±10%
VDD: 5V±10% Note)
11.11
40
100
mV
VDD: 2.2 to 3.6V
105
Comments
Note)
Voltage span
100/164 100/100 100/36.25 times Note)
adjustment range
Offset voltage
Soff1
-48
48
mV
VDD: 5V±10% Note)
adjustment range
Soff2
-24
24
mV
VDD: 2.2 to 3.6V Note)
nd
Sensitivity temp. drift 2
Sst21
-0.0016
+0.0016
VDD: 5V±10% Note)
order coefficient
Sst22
-0.0008
+0.0008
VDD: 2.2 to 3.6V Note)
Sensitivity temp. drift 1st Sst11
-0.32
+0.32
VDD: 5V±10% Note)
order coefficient
Sst12
-0.3
+0.3
VDD: 2.2 to 3.6V Note)
nd
Offset temp. drift 2
Sot21
-0.0016
+0.0016
VDD: 5V±10% Note)
order coefficient
Sot22
-0.0008
+0.0008
VDD: 2.2 to 3.6V Note)
st
Offset temp. drift 1
Sot11
-0.6
+0.6
VDD: 5V±10% Note)
order coefficient
Sot12
-0.3
+0.3
VDD: 2.2 to 3.6V Note)
Note) Equivalent input values assumed from the output. See 5) Registers Description 5.1.1) Adjustment
block register. This adjustment range includes variations in the AK8996.
2) Adjustment Accuracy
Item
Symbol
Min.
Typ.
Note2)
Max.
Note3)
Units
Comments
Offset adjustment accuracy
Cof
0.063
%FS

Offset temp. drift adjustment accuracy
Coft
0.101
%FS

Output span adjustment accuracy
Csn
0.125
%FS

Sensitivity temp. adjustment accuracy
Csnt
0.003
%FS

Sensitivity temp. variation step
Csts
0.268
%FS

Sensitivity supply voltage variation step Csvs
0.236
%FS

Note1)
Final adjustment accuracy
Call
0.397
1.0
%FS
Note1) Call=(Cof^2+Coft^2+Csn^2+Csnt^2+Csts^2+Csvs^2)^(1/2)
Note2) Temp.=105ºC, VDD=4.5V, G1=5x, G3=1.25x, BufG=4x, Offset temp. drift 1st/2nd order
coefficient=Min./Max., Sensitivity temp. drift 1st/2nd order coefficient=Min.*1/2, VOUT output
band-limited (≤500Hz @Fs=10kHz, [email protected]=2kHz, [email protected]=1kHz, [email protected]=100Hz)
effective
Note3) Temp.=-40 to 105ºC, VDD=5V±10%, 3.3V±10%, 3.0V±10%, 2.5V±10%,
G1/G3/BufG=Min. to Max., Each temperature coefficient=Min. to Max., VOUT output band-limited
(≤500Hz @Fs=10kHz, [email protected]=2kHz, [email protected]=1kHz, [email protected]=100Hz) effective
* The calculation of adjustment accuracy is based on our definition as a reference. The accuracy of
product depends on your sensor characteristics and adjustment method.
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Description of Blocks
Gain Amplifier Block, LPF & S/H1 & Level Shifter, S/H2 & Buffer
The set of these blocks amplifies, compensates and outputs the pressure sensor level with a
normal gain ratio of 50:1. This set of blocks intermittently amplifies, compensates, samples and
holds the pressure sensor output. The output stage, with an internal resistor of 32k, is band-limited
with a combination of external capacitors, providing a low impedance output through a buffer. A
percentage designator is used, benchmarked with 4000mVdc output at 100%, reflecting the 50x increase
in differential input from 80mVdc.
Block
Gain Amp. 1
(G1)
Functions
A low-noise high-gain amplifier at the front end. The differential signal is increased
by a factor of 5 (typically) (with factors of 2 to 9, in single-factor steps).
The G1 differential output is converted to single-ended with reference to AGND
Gain Amp. 2 and typically amplified by a factor of 1 (1 or 2). The preloaded compensation data
Offset_Temp. in the EEPROM enables the pressure sensor offset voltage and offset temperature
Offset
secondary characteristics to be compensated.
Offset Temp. Offset adj.
Resolution:
Rough: 4-bits; Fine: 7-bits
track
Adj. step: Rough: 7.5%; Fine: 0.125% @VDD: 5V
(G2)
Offset temp. drift.Resolution: 1 st order coeff: 10-bits; 2 nd order coeff: 8-bits
Adj. step: 1 st order coeff: 0.196%; 2 nd order coeff: 0.787%
Amplifies the G2 output by a factor of 1.25 (typically). The preloaded compensation
Gain Amp. 3
data in the EEPROM enables the pressure sensor span voltage and sensitivity
Gain_Temp.
temperature secondary characteristics to be compensated.
Gain
Span adj.
Resolution:
9-bits
(G3)
Adj. value: 100/[100+0.25*N](%)
N: -256 to +255
Supply voltage and sensitivity temperature variation compensation circuit.
Monitors the AGND voltage to detect the magnitude of supply voltage variation; the
STV
pressure sensor sensitivity temperature secondary characteristics compensation
VDD track
values are calculated for entry into G3 using the temperature sensor output voltage
Gain Temp.
and preloaded compensation data (EEPROM data).
track
Sensitivity temperature drift
(STV)
Resolution:
1 st order coeff: 10-bits; 2 nd order coeff: 8-bits
Adj. step: 1 st order coeff: 0.196%; 2 nd order coeff: 0.787%
Compares the pressure sensor VOUT pin output voltage to the threshold voltage to
define the sensitivity temperature secondary characteristics compensation
coefficient.
Pressure determination threshold adj.
Resolution: 10-bits
Adj. step: 0.001*VDD (0.05*VDD – 0.95*VDD)
Note that upon powering up and exiting standby (STBYN pin from low to high), the
precise pressure cannot be determined until the VOUT pin output settles, depending on
the external capacitance value of the VO pin.
Pressure
When the VOUT pin output voltage is more than the output reference voltage, the
Judge
positive (+) sensitivity temperature secondary characteristic compensation
coefficient is selected; but when the VOUT pin output voltage is less than the
output reference voltage, the negative (-) sensitivity temperature secondary
characteristic compensation coefficient is selected.
Note) If the output reference voltage is half of VDD, pressure threshold adjustment
is unnecessary. Even if the compensation coefficient +/- is not used,
pressure threshold adjustment is required if the output reference voltage is
set to a value other than half of VDD.
Anti-aliasing filter to eliminate the fold-back noise generated in the
LPF
sample-and-hold circuit (S/H 1&2) in the later stage. The cutoff frequency is
fc=60kHz.
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Block
S/H1&
Level shift
Functions
Doubles the LPF output for the sample and hold. It also modifies the output
reference voltage.
Output ref. voltage adj. Resolution:
Rough: 5-bits; Fine: 6-bits
Adj. step: 0.0005*VDD (0.0785*VDD – 0.9215*VDD)
Description is with reference to VO pin.
Note) If the output reference voltage is half of VDD, output reference voltage adjustment is
unnecessary.
S/H2
Buffer
Timing
Logic
Regulator
Pressure
Detector
MS1055-E-02
Sample-and-hold circuit.
A 32k resistor is connected to the output stage. The combination with an external
capacitor creates the LPF characteristics.
Change the external capacitance value according to the desired signal band for
detection using the following equation:
fc=1/(2*π*32k*C) (Hz)
If the application does not require a low-impedance output, the VO pin output can
be used as an alternative. In this case, set the EEPROM data to disable the buffer.
Disabling the buffer allows for lower power dissipation. However, since the VO pin
has a 32k output impedance, connecting a resistive load will cause output
voltage inaccuracies. Note also that the gain retained in the buffer cannot be
achieved.
Buffer to produce a band-limited output with low impedance. Typically provides a
fourfold output (2x to 4x, in 0.5 steps).
Reprogramming the EEPROM allows the buffer to be disabled for low power
dissipation. (See S/H2.)
Generates timing sync signals for internal operation and sampling frequencies for
sensor output signals. Sampling frequencies can be selected from the EEPROM.
Sampling frequency (fs): 100Hz (default); 1 kHz; 2kHz; 10.24kHz
Constant voltage generator circuit to drive the sensor. The drive voltage can be
selected from the EEPROM depending on the supply voltage being used.
Drive voltage: 4.0V @VDD: 5V±10% (default); 2.0V @VDD: 2.2 to 3.6V
Pressure detection circuit and self-diagnosis circuit.
The pressure range can be selected depending on the EEPROM data for the pressure
detector.
•
Pressure above a certain value is detected (determined by threshold).
•
Pressure below a certain value is detected (determined by inverted threshold).
•
Pressure above or below a certain value is detected (determined both by a
threshold and an inverted threshold).
The DET pin goes high when the detected pressure exceeds the threshold. The
detection threshold value can be set by entering it via the PTH pin or using the EEPROM
data in the AK8996. Note that upon powering up and exiting standby (STBYN pin from
low to high) the precise pressure cannot be determined until the VOUT pin output settles,
depending on the setup and external capacitance value of the VO pin.
The self-diagnostic circuit ensures that the output (VOUT pin) produces a given value by
fixing the VP and VN pins at half of VDD upon power-up, or only at initial operation
immediately after exiting the standby mode. In the event of any anomalies, signals go
high at the DET pin. To reset the self-diagnostic circuit, set the STBYN low or recycle the
power. Bear in mind that the self-diagnostic circuit does not detect all of the failure
modes of the AK8996.
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Reference Section & Others
Block
Functions
Generates the reference voltage or bias current required for each circuit.
V_Bandgap
Adjust the VREF voltage so that it is equivalent to 1.0V.
(VBG)
VREF voltage adj.
Resolution:
3-bits
V_Reference
Adj. step:
1% step
(VREF)
Adjust the IREF current so that it is equivalent to 20µA.
I_Reference
IREF current adj.
Resolution:
4-bits
(IREF)
Adj. step:
2.7% steps typically
Oscillator to generate timing sync signals for internal operation and sampling
Oscillator
frequencies for sensor output signals. Adjust the oscillating frequency to 1024kHz.
(OSC)
OSC adj.
Resolution:
4-bits
Adj. step:
5% steps
Temperature sensor for converting the ambient temperature to voltage. Adjust the
temperature sensor output voltage (VTMP voltage) so that it is equivalent to VREF
V_temp.
voltage at 25ºC.
(VTMP)
VTMP voltage adj.
Resolution:
6-bits
Adj. step:
0.2% (0.67C) steps
Generates analog circuit reference voltage 1/2VDD. Connect 10nF capacitance to
this pin for stabilization.
V_Common
Since the output cannot drive current, do not connect a resistive load.
(VCOM)
The internal power-up circuit causes it to start up within the settling time for stable
analog operation (Start Up valid time).
Upon power-up or exit from standby mode (low to high at the STBYN pin), this
circuit generates the settling time for stable analog operation using the internal
Power Up circuit. This circuit oversees the startup time for VREF or IREF and
disables the OSC to prevent improper operation. When the settling time for stable
analog operation expires, the OSC is enabled.
Power ON
Start up the supply voltage within 200 µsec (0.8*VDD<). If power-up is not started
Delay
within 200 µsec, the AK8996 may enter the test mode. Note that the AK8996 may not
(PODLY)
function properly in the test mode (For the description of the function, refer to the
Functional Description 9) Note on the AK8996 Power-up).
When recycling the power with the VDD pin and STBYN pin interconnected, it should be
monitored to ensure that the supply voltage is below 0.1*VDD to enable the power-on
reset.
Serial I/F
Serial interface for accessing EEPROM.
EEPROM & EEPROM and control register (volatile memory).
Control
Used to store compensation values and measurement modes and to set up the
Register
measurement modes for adjustment.
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Pin Assignments and Functions
PAD Name
1
VSSO
2
VP
VS
3
4
I/O
O
I
O
C load max.
R load min.
30pF
1k
3k
Type
GND
Analog
Analog
VN
STBYN
I
I
Analog
CMOS
CS
SCLK
SDI/O
DET
VSS
VDD
NC
VOUT
I
I
I/O
O
CMOS
CMOS
CMOS
CMOS
GND
Power
O
50pF
VO
O
3µF
PTH
AGND
I
O
5
6
7
8
9
10
11
12
13
Analog
10k
20k
Analog
14
15
16
MS1055-E-02
Analog
Analog
9
Comments
VDD > 2.7V
VDD > 2.2V
Schmitt trigger input
Connected to VDD when not in
use.
Pull-down resistor (100k) included
Pull-down resistor (100k) included
Pull-down resistor (100k) included
Do not connect
VDD > 2.7V
VDD > 2.2V
Due to the internal 32k output
resistor, resistive load connection
is prohibited
10nF connection; resistive load
connection prohibited
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Pin Descriptions
Pin conditions
DET: “H”
STBYN:
Start up
Note)
EOUT[0]: EOUT[0]:
“L”
“L”
“H”
1
VSSO Reference voltage output pin
2
VP
Sensor differential signal input pin (+ve)
Hi-Z
Hi-Z
Constant voltage supply pin for sensor
3
VS
Hi-Z
Hi-Z
drive
4
VN
Sensor differential signal input pin (-ve)
Hi-Z
Hi-Z
5 STBYN Standby pin ("L": Standby)
VSS
VDD
VDD
VDD
6
CS
Chip select pin
7
SCLK Serial clock pin
8
SDI/O Data I/O pin
Output pin for pressure detection (high
at detection) and output pin for
9
DET
VSS
VDD
VDD
VSS
abnormal self-diagnostic detection
(high at detection)
10
VSS
Reference voltage pin
11
VDD
+ Power supply pin
12
NC
13 VOUT Sensor signal pin
Hi-Z
Hi-Z
AGND
Capacitance connection pin for sensor
14
VO
Hi-Z
AGND
signal band-limiting
Pin for pressure detection and
15
PTH
self-diagnosis threshold input
Analog ground with external
16 AGND
Hi-Z
AGND
capacitance for stabilization
Note) See "Operation Sequence."
PAD Name
MS1055-E-02
Functions
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Level Diagram
VP
G1
G2(D2S)
G3
S/H1
Level
S/H2
VN
G=5
G=1
G=0.5*2.5
G=2
Shift
G=1
R=32k
BUF
VOUT
G=4
VO
ING=2 - 18
LVs=0.1*VDD - 0.9*VDD
BUFG=2 - 4
1) Level Shift : 0.1*VDD, Pressure : Positive
+/-200mV
400mV
200mV
500mV
1000mV
Level
G=4
Shift
VP-VN=80mV
4000mV
0.5*VDD
1000mV
0.1*VDD
2) Level Shift : 0.9*VDD, Pressure : Negative
+/-200mV
400mV
200mV
500mV
1000mV
Level
Shift
VP-VN=80mV
G=4
1000mV
0.9*VDD
0.5*VDD
4000mV
3) Level Shift : 0.5*VDD, Pressure : Positive & Negative
+/-200mV
400mV
200mV
500mV
1000mV
G=2
2000mV
0.5VDD
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Electrical Characteristics
1) Absolute Maximum Ratings
Item
Symbol
Min.
Supply voltage
VDD
-0.3
Input voltage
VDIN
VSS-0.3
Input current
IIN
-10
Output current
IOUT
-10
Max.
6.5
VDD+0.3
10
10
Units
V
V
mA
mA
Comments
EEPROM retention characteristics
< 105ºC
Note) Operation at or beyond these limits may result in permanent damage to the device.
Storage temp.
TST
-55
125
2) Recommended Operating Conditions
Item
Symbol Min.
Typ.
Operating temp.
Ta
-40
VDD1
2.2
3.0
Supply voltage
VDD2
4.5
5.0
Max.
105
3.6
5.5
C
Units
Comments
C
V EVD[0]=1
V EVD[0]=0
3) Supply Voltage Current (See Functional Description)
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Symbol Min.
Typ.
Max.
Comments
Item
Units
Note1)
Supply voltage
IDD0
1
µA At standby
current 0 note )
Supply voltage
IDD1
350
450
µA Sampling frequency: 100Hz
current 1 note )
Supply voltage
IDD2
250
340
µA Sampling frequency: 100Hz
current 2 note )
Buffer OFF (EBU[0]=1)
Supply voltage
IDD3
570
680
µA Sampling frequency: 1kHz
current 3 note )
Supply voltage
IDD4
820
980
µA Sampling frequency: 2kHz
current 4 note )
Supply voltage
IDD5
2550
2850
µA Sampling frequency: 10.24kHz
current 5 note )
Note )
At the time of measurement, a 3k resistor load is applied to the VS pin, no load is applied to
the VO&VOUT pin, and AGND is applied to the VP&VN pin.
Note1) Supply voltage current when VDD = 5.0V (EVD[0]=0).
4) EEPROM Characteristics
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Min.
Typ.
Max.
Units
EEPROM write voltage
Evdd
2.7
V
EEPROM write temp.
Eta
-40
85
C
EEPROM endurance
Etime
1000
times
EEPROM data retention
Ehold
10
years
time
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5) Digital DC Characteristics
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol Pin
Conditions
Min.
Typ.
Max.
Units
High level input
VIH
1, 2
0.7*VDD
V
voltage
Low level input
VIL
1, 2
0.3*VDD
V
voltage
High level input
IIH1
1
+10
+200
µA
current 1
High level input
IIH2
2
-10
+10
µA
current 2
Low level input
IIL
1, 2
-10
+10
µA
current
High level output VOH
3
IOH= -200µA
0.9*VDD
V
voltage
Low level output
VOL
3
IOL= +200µA
0.1*VDD
V
voltage
1 SDI(/O), SCLK, CS (integrated 100k pull-down resistor )
2 STBYN (Schmitt trigger)
3 SD(I/)O, DET
6) Digital AC Characteristics
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Min.
Typ.
Max.
Units
Write time (EEPROM address write)
Twr_EEP1
5
100
msec
Write time (EEPROM batch write)
Twr_EEP1
10
100
msec
Write time (register)
Twr_REG
300
nsec
CS setup time
Tcs
100
nsec
Data setup time
Ts
100
nsec
Data hold time
Th
100
nsec
SCLK high time
Twh
500
nsec
SCLK low time
Twl
500
nsec
SCLK → SDO delay time
Td
200
nsec
Idle time
Ti
100
nsec
SCLK rising time Note)
Tr
10
nsec
SCLK falling time Note)
Tf
10
nsec
Note) Design reference value; no production test performed.
[Serial I/F timing (Write)]
[SCLK Raising/Falling timing]
Twr_EEP1/2, Twr_REG
Tcs
Ti
Tr
Tf
0.7VDD
CS
Ts
Twh
Th
Twl
SCLK
1
SCLK
SDI/O
0.3VDD
16
A0
D0
[Serial I/F timing (Read) ]
CS
Td
SCLK
SDI/O
8
A0
MS1055-E-02
Td
9
Hi-Z
16
D7
D0
Hi-Z
13
2011/12
[AK8996/W]
7) Power-Up and Standby Exit Time
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol Min. Typ. Max. Units
Comments
See Functional Description 9)
Power-up time
Tvdd
200
µsec Note
on
the
AK8996
Power-up
Standby exit time
Tvdst
10
nsec
Standby rise time
Tstbr
10
nsec
Standby fall time
Tstbf
10
nsec
Tidle1
1
msec
Standby valid time
Tidle2
30
msec VDD pin voltage<0.1*VDD
VOUT output rise
VO pin external
Tvout
20
µsec
time
capacitance<0.1µF
AGND output rise
AGND pin external
Tvgnd
150
250
µsec
time
capacitance: 10nF
Settling time for
Tenable1
280
465
µsec
stable analog
Tenable2
350
495
µsec
operation
Note) Design reference value; no production test performed.
STBYN pin unused (STBYN=VDD) Note)
STBYN pin used
0.8*VDD
0.8*VDD
0.8*VDD
VDD pin voltage
(=STBYN pin voltage)
0.1*VDD
0.1*VDD
Normal
operation
Tvdd
Tenable1
VDD pin voltage
Tstbf
Tidle2
Tvdst
0.7*VDD
0.7*VDD
0.3*VDD
0.3*VDD
0.7*VDD
STBYN pin voltage
Tvout
VOUT pin voltage
AGND pin voltage
Hi-Z
0.45*VDD
Tvgnd
0.45*VDD
0.5*VDD
Tstbr
Tenable2
Normal
operation
Tidle1
0.5*VDD
Note) When recycling the power with the VDD and
STBYN pins connected, ensure that the supply voltage is
below 0.1*VDD to enable the power on reset.
8) Pressure Determination Circuit (Pressure Judge)
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Conditions
Min.
Typ.
Max.
Units Comments
Unadjusted
Pressure judge
Vjudi AM[3:0]:9h DET
0.48*VDD 0.5*VDD 0.52*VDD V
DET pin
threshold
output
With respect to Vjudi
Pressure judge Vjud+ Max:
0.95*VDD
V
DET pin
EPJLV[9:0]=23Eh
threshold
adjustment
With respect to Vjudi
Vjud- Min:
0.05*VDD
V
DET pin
range
EPJLV[9:0]=1C2h
0.001
Adj. Step
Vjstp
V
DET pin
*VDD
Output ref. voltage=
Pressure judge
threshold
VOUT
Selected ST2N, ST1NS, ST1N
Registers
MS1055-E-02
ST2P, ST1PS, ST1P
14
ST2N, ST1NS, ST1N
2011/12
[AK8996/W]
9) Pressure Detector
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Conditions
Min.
Typ.
Max.
Units Comments
Pressure
Vdeto5+ EINT1[1:0]=01
0.5*VDD
0.95*VDD V
EINT2[0]=0
detection
VDD=5V±5%
threshold
External input Vdeto3+ EINT1[1:0]=01
0.5*VDD
0.90*VDD
range
EINT2[0]=0
Pressure
detection
threshold
Internal set
value
Vdeti
EVD[0]=1
VDD=2.2 - 3.6V
Unadjusted
AM[3:0]:5h DET out
EINT1[1:0]=01
EINT2[0]=1
0.72*VDD 0.74*VDD 0.76*VDD
V
0.95*VDD
V
Vdet5+ With respect to Vdeti
Pressure
detection
threshold
Internal set
value
Adjust. width
Vdet3+
VdetAdjust. step
Hysteresis
voltage
Vdstp
Vhysi
Hysteresis
voltage
Adjust. width
Vhys+
Adjust. step
Vhstp
Pressure
detection time
Pressure
non-detection
time
Pressure
detector
Disable time
Adjust. width
Tdetr
Tdetf
Vhys-
Max: EPT[3:0]=7h
VDD=V±5%
EINT1[1:0]=01
EINT2[0]=0
EVD[0]=1
EPT[3:0]=6,7h
prohibited
VDD=2.2 - 3.6V
With respect to Vdeti
Min: EPT[3:0]=8h
0.89*VDD
0.50*VDD
0.008
*VDD
Unadjusted
AM[3:0]:7h DET out
EINT1[1:0]=01
With respect to Vhysi
Max: EHYS[2:0]=0h
With respect to Vhysi
Min: EHYS[2:0]=7h
0.03*VDD
0.020
*VDD
V
0.032
*VDD
V
V
0.0
V
V
EINT1[1:0]=01
-0.0175
*VDD
-0.0025
*VDD
450
600
µsec
EINT1[1:0]=01
450
600
µsec
Tasdis+ EAS[2:0]=7h
V
12.5
msec
ESF[1:0]=3h
EINT1[1:0]=01
0.1
msec
PTH
Vhys
VOUT
0.5*VDD
0.5*VDD
DET
Tdetr
MS1055-E-02
Tdetf
15
2011/12
[AK8996/W]
10) Self-Diagnostic Circuit
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Conditions
Min.
Typ.
Max.
Units Comments
Self-diagnostic
normal
0.48*VDD
0.52*VDD
EINT1[1:0]=10
Vself
V
operation
-0.1
+0.1
judgment range
Self-diagnostic
EINT1[1:0]=10
Tself
450
600
µsec
detection time
11) Analog Characteristics
11-1) Reference Section
11-1-1) Reference Section Characteristics
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Conditions
Min.
Typ.
Max.
Units Comments
VREF voltage
Vr0
Unadjusted
0.97
1.0
1.04
V
AM[3:0]:1h DET out
Vr+
With respect to Vr0
+30
mV
Max: EVR[2:0]=3h
VREF adj. width
VrWith respect to Vr0
-40
mV
Min: EVR[2:0]=4h
VREF adj. step Vrstp
10
mV
VS voltage
VS51 After VREF adj.
V
VS pin out
3.88
4.00
4.12
Load resistance: 3k
VS52 Load resistance: 1k
VDD>2.7V
3.88
4.00
4.12
VS31 After VREF adj.
V
VS pin out
1.94
2.00
2.06
Load resistance: 3k
VS32 Load resistance: 1k
VDD>2.7V
1.94
2.00
2.06
IREF current
Ir0
Unadjusted
16.15
20
24.98
µA
AM[3:0]:2h DET out
Ir+
With respect to Ir0
+4.81
µA
Max: EIR[3:0]=7h
IREF adj. width
IrWith respect to Ir0
-3.40
µA
Min: EIR[3:0]=8h
IREF adj. step
Irstp
0.547
µA
OSC freq.
Fr0
Unadjusted
768
1024
1288
kHz
AM[3:0]:3h DET out
OSC adj. width
Fr+
With respect to Fr0
204.8
kHz
Max: EFR[3:0]=4h
FrWith respect to Fr0
-204.8
kHz
Min: EFR[3:0]=Ch
OSC adj. step
Frstp
51.2
kHz
MS1055-E-02
16
2011/12
[AK8996/W]
11-1-1) Reference Section Characteristics (Continued)
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Conditions
Min.
Typ.
Max.
Units Comments
Unadj. (Temp = 25C)
VTMP voltage
Vt0
0.936
1.0
1.062
V
AM[3:0]:4h DET out
With respect to Vt0
Vt0+
+62
mV
Max: ETM[5:0]=1Fh
VTMP adj. width
With respect to Vt0
Vt0-64
mV
Min: ETM[5:0]=20h
VTMP adj. step Vt0stp
2.0
mV
VTMP temp
Note)
Vt
3.0
Temp = -40 to 105C
mV/C
variation
0.5*VDD
0.5*VDD
AGND voltage
Vag
0.5*VDD
V
-0.06
+0.06
Note) Design reference value; no production test performed.
11-1-2) Reference Section (packaged version only) Characteristics (note)
Unless otherwise specified, VDD = 4.5 to 5.5V, Temperature = -40 to 105ºC
Item
Symbol
Conditions
Min.
Typ.
Max.
Units Comments
VREF voltage
Vr0P
AM[3:0]:1h DET out
0.99
1.0
1.01
V
After adj.
After adj.
VS51P Load resistance: 3k
3.88
4.00
4.12
V
VS voltage
After adj.
VS52P Load resistance: 1k 3.88
4.00
4.12
IREF current
Ir0P
AM[3:0]:2h DET out
18
20
22
µA After adj.
OSC freq.
Fr0P
AM[3:0]:3h DET out
921.6
1024
1126.4
kHz After adj.
After adj.
VTMP voltage
Vt0P
AM[3:0]:4h DET out
0.994
1.0
1.006
V
@25C
Note) Factory default adjustment is referenced to 5V mode (EVD[0]=0). If 3V mode (EVD[0]=1) is
used, readjustment is required
11-2) Gain Amplifier and Other Blocks
Unless otherwise specified, the following requirements apply.
• Reference Section is complete with adjustment.
• For supply voltage of 5V (3V), the level diagram includes G1 gain of 5x, Level shift 0.1*VDD
and BUFF gain of 4x (see level diagram 1) and the output voltage 4000mV (2000mV) is set as
100% based on a differential input of 80mV (40mV).
11-2-1) Overall Characteristics
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Conditions
Min.
Typ.
Max.
Units Comments
Std. gain
Gtyp VP/VN → VOUT
50
times
Input common
Vicom
0.45VS 0.5*VS 0.55VS
V
voltage
Output common
VP/VN → VOUT
Vcom0
0.1*VDD
V
voltage
VP=VN=0.5*VS
Vmax+ VP/VN → VOUT
0.9*VDD
V
Max. output
range
Vmax- VP-VN=VSS or VDD
0.1*VDD
V
VP/VN → VOUT
@1Hz VP=VN=Open
Non-input noise Nout
1,000 µVrms
100kHz
VO external
Note)
capacitance: 10nF
Note) Value for 50x nominal gain. Design reference value; no production test performed.
MS1055-E-02
17
2011/12
[AK8996/W]
11-2-2) G1/2 Gain Adjustment Circuit
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Conditions
Min.
Typ.
Max.
Units Comments
Measurement in test mode
Unadjusted
Vg10
VP-VN=80mV
145
160
175
mV
G1/2 output
VDD=5V±5%
voltage
EIG[2:0]=0h, EIG[3]=0
Vg02
VP-VN=40mV
73.0
80
87.0
mV
VDD=2.2 - 3.6V
EIG[2:0]=0h, EIG[3]=0
EVD[0]=1
G1 adjustment
G1sc+ EIG[2:0]=7h
9
times
range
G1scEIG[2:0]=0h
2
times
Adj. step
G1sc stp
1
times
G2 adj.
G2sc+ EIG[3]=1
2
times
G2scEIG[3]=0
1
times
11-2-3) Offset Voltage Adjustment Circuit
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Conditions
Min.
Typ.
Max.
Units Comments
Measurement in test mode
Unadjusted output Vo01 VDD=5V±5%
0.5*VDD 0.5*VDD 0.5*VDD
mV
voltage
–30
+30
Vo02 VDD=2.2-3.6V 0.5*VDD 0.5*VDD 0.5*VDD
mV
EVD[0]=1
–15
+15
Offset rough adj. Ocmp+ EOC[10]=0h
+52.5
%
DAC adj. range
EOC[9:7]=7h
Ocmn+ EOC[10]=1h
-52.5
%
EOC[9:7]=7h
Adj. step
Ocm stp
7.5
%
Offset fine adj.
Ocl+
EOC[10]=0h
+7.875
%
DAC adj. range
EOC[6:0]=3Fh
OclEOC[10]=1h
-7.875
%
EOC[6:0]=3Fh
Adj. step
Ocl stp
0.125
%
11-2-4) Span Voltage Adjustment Circuit
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Conditions
Min.
Typ.
Max. Units Comments
Measurement in test mode after offset voltage adjustment
Unadjusted
Vs01 VP-VN=80 [email protected]
480
500
520
mV
Span voltage
Vs02 VP-VN=40 [email protected]
240
250
260
mV
EVD[0]=1
Span adj. range Sc+ ESC[8:0]=0FFh
100/36.25
times
Sc- ESC[8:0]=100h
100/164
times
Adj. Step
Sc stp N=-256 - +255
100/(100+0.25*N)
times
MS1055-E-02
18
2011/12
[AK8996/W]
11-2-5) Offset Temperature Drift & Sensitivity Temperature Drift Adjustment Circuit
11-2-5-1) Quadratic Function Generator (a*Temp^2+b*Temp+c)
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Conditions
Min.
Typ.
Max.
Units Comments
Measurement in test mode after offset voltage and span voltage adjustment
2 nd order coeff. a
A2nd5+
VDD=5V±5%
+0.0016
Adj. range 1
A2nd5-0.0016
Adj. step 1 A2nd5 stp
1.260E-5
2 nd order coeff. a
A2nd3+
VDD=2.2 - 3.6V
+0.0008
Adj. range 2
A2nd3-0.0008
Adj. step 2 A2nd3 stp
0.630E-5
Note) Design reference value; no production test performed.
11-2-5-2) Offset Linear Function Generator (d*Temp+e)
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Conditions
Min.
Typ.
Max.
Units Comments
Measurement in test mode after offset voltage and span voltage adjustment
1 st order coeff. d
D2ndO5+ VDD=5V±5%
+0.60
Adj. range 1
D2ndO5-0.60
Adj. step 1 D2ndO5 stp
0.0012
1 st order coeff. d
D2ndO3+ VDD=2.2 - 3.6V
+0.30
Adj. range 2
D2ndO3-0.30
Adj. step 2 D2ndO3 stp
0.00060
Note) Design reference value; no production test performed.
11-2-5-3) Sensitivity Linear Function Generator (d*Temp+e)
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Conditions
Min.
Typ.
Max.
Units Comments
Measurement in test mode after offset voltage and span voltage adjustment
1 st order coeff. d
D2ndS5+
VDD=5V±5%
+0.32
Adj. range 1
D2ndS5-0.32
Adj. step 1 D2ndS5 stp
0.000626
st
1 order coeff. d
D2ndS3+
VDD=2.2 - 3.6V
+0.30
Adj. range 2
D2ndS3-0.30
Adj. step 2 D2ndS3 stp
0.00060
Note) Design reference value; no production test performed.
MS1055-E-02
19
2011/12
[AK8996/W]
11-2-6) Supply Voltage & Temperature Sensitivity Variation Adjustment Circuit (ST & SV)
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Conditions
Min.
Typ.
Max. Units Comments
Measurement in test mode after offset voltage and span voltage adjustment
Unadjusted SV circuit
With respect
Sensitivity
SV1
initial operation
5.0
%
to target
variation
value
characteristics
SV circuit 2 nd
With respect
to supply voltage SV2
±0.25
%
operation
to SV1
Unadjusted ST initial
With respect
Sensitivity
ST1
operation
5.0
%
to target
variation
value
characteristics
to operating
ST circuit 2 nd operation
With respect
ST2
±0.25
%
temperature
to ST1
11-2-7) LPF, S/H1&2, & Buffer
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Conditions
Min.
Typ.
Max.
Units Comments
Measurement in test mode after offset voltage and span voltage adjustment
LPF freq.
Fc1
40
60
80
kHz
response
S/H1&2 gain
SHG
1.935
2
2.065 times
S/H1&2 out
SHerr
-20
0
20
mV
pre-adj. error
S/H2 output
resistance
Rout
24.6
32
39.4
k
post-adj. error
Bufg+
EOG[2:0]=4h
4
times
BUF gain adj.
width
BufgEOG[2:0]=0h
2
times
Adj. step
Bufgstp
0.5
times
10k
Rbuf1+ Load resistance:
0.9*VDD
V
BUF output
Rbuf10.1*VDD V
20 k
(VOUT) drive
Rbuf2+ Load resistance:
0.9*VDD
V
VDD>2.7V
characteristics
Rbuf20.1*VDD V
VDD>2.7V
10 k
MS1055-E-02
20
2011/12
[AK8996/W]
11-2-8) Level shift
Unless otherwise specified, VDD = 2.2 to 5.5V, Temperature = -40 to 105ºC, register default
Item
Symbol
Conditions
Min.
Typ.
Max.
Units Comments
Measurement in test mode after offset voltage and span voltage adjustment
Unadjusted
Vlv0
0.5*VDD
0.5*VDD
AM[3:0]:9h
0.5*VDD
V
VO pin
–0.02
+0.02
VS input → VO out
Output reference
Vlv0 reference
Vlvr+
0.890
V
VO pin
voltage
Max: ELV[10:6]=1Fh
*VDD
Rough adj. width
Vlvo reference
Vlvr0.110
V
VO pin
(Level shift)
Min: ELV[10:6]=0Fh
*VDD
Vlrstp
0.026
V
VO pin
*VDD
Vlv0 reference
Vlvf+
0.0315
Max: ELV[10]=1h,
V
VO pin
*VDD
ELV[5:0]=3Fh
Output reference
Vlv0 reference
voltage
Vlvf-0.0315
Min: ELV[10]=0h,
V
VO pin
Fine adj. width
*VDD
ELV[5:0]=3Fh
(Level shift)
Vlfstp
0.0005
V
VO pin
*VDD
MS1055-E-02
21
2011/12
[AK8996/W]
Operation Sequence
1. Normal Operation Timing (Pressure Detector Valid)
Self-Diagnosis OFF (First time) Initial operation for STV
CLK (1=512 kH z)
NO.
Status
Approx. 400 sec
0
00
Start Up
5
Pressure measurement period
8
10
20
ST0
PJ0
18
30
50 51
3
Idling period
100 Hz: 5,070 1 kH z: 462
2 kHz: 206
10.24 kHz: 0
13
STV0
MSR
ST3
VDD or STBYN
Press judge
P. supply & sens.
variation adj.
STV
(First) Initial
Operation
S/H1&2
1/2*VDD for output ref. voltage
VOUT
VOUT·(1)
DET
Self-Diagnosis OFF (2nd time & after) Normal operation for STV
CLK (1=512kHz)
0
Idling Period
100 Hz: 5,070 1 kHz: 462
NO.
2 kHz: 206
10.24 kH z: 11
0
Status
ST1
5
8
21
18
31
PJ1
50 51
3
13
STV1
MSR
ST3
VDD or STBYN
Press judge
STV
P. Supply & sens.
variation adj.
(2nd time & after)
Normal Operation
S/H1&2
VOUT
DET
MS1055-E-02
VOUT·(n-1)
VOUT·(n)
Abnormal: “H ” (Initial judge)
22
2011/12
[AK8996/W]
2. Operation Timing when the Self-Diagnosis Circuit is Valid (Pressure Detector Valid)
Self-Diagno sis ON (1 st tim e) P ower supp ly va riation adjusted and sen sitivity variation unad juste d for STV
CLK (1=5 12 kHz )
A ppro x.4 0 0s ec
NO.
Status
0
00
Start Up
5
8
10
20
ST0
PJ0
Self-diagno sis perio d
18
34
50
51
4
14
STV4
MSR4
ST4
VDD or STB YN
Press ju dge
P. S up ply var. adj.
STV
(1st tim e) P. S up ply var ad j., sen s. tem p. var
una djusted.
S/H1 &2
Outp ut ref. vo ltag e ne ar 1/2 *VDD
VOUT
VOUT·(1)
DET
Abnorm al:
”H”
Self-Diagno sis ON (2 nd t im e) Init ial op eration fo r STV
P re ssure m easurem ent period
CLK (1=5 12 kHz )
0
5
8
NO.
15
20
Status
ST5
PJ0
18
30
50
3
51
13
STV0
MSR
ST3
VDD o r STB YN
Press ju dge
STV
P. S upp ly & Sen s
var. adj.
(2nd tim e) In itial ope ra tio n, (3rd time & a fter)
Norma l op eration
S/H1 &2
VOUT
DET
MS1055-E-02
VOUT·(n-1)
VOUT·(n)
Ab norma l: ”H”
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3. Description of Operation Timing Status
3.1 Normal Operation Timing
No.
State
00
Start Up
10
ST0
20
30
3
13
PJ0
STV0
MSR
ST3
11
ST1
21
PJ1
31
:
STV1
:
MS1055-E-02
CLK
Operations
Analog circuit settling time for stable operation.
Analog reference circuits as VREF & IREF start up and
configured output reference voltage is provided at VOUT pin.
Clock count start
Analog circuit startup
CLK=5
Pressure judge circuit not in operation
CLK=8
STV initial operation
CLK=18
Output pressure (VP-VN) to VOUT
CLK=51
Idling
With fs=10.24kHz setup, no idling and in continuous
operation.
Idling period
100Hz
5,070 CLK
1kHz
482 CLK
2kHz
206 CLK
10.24kHz 0 CLK
CLK1=51 or 256 Pressure detection operation and analog circuit startup
or 512 or 5120
CLK=5+CLK1
Pressure judge circuit operation
(Positive/negative pressure determination)
CLK=8+CLK1
STV normal operation
:
:
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3.2 Self-Diagnostic Circuit in Operation
No.
State
00
Start Up
10
ST0
20
PJ0
CLK=5
34
4
14
STV4
MSR4
ST4
CLK=8
CLK=18
CLK=51
15
20
30
3
:
ST5
PJ0
STV0
MSR
:
CLK=100
CLK=105
CLK=108
CLK=118
:
MS1055-E-02
Trigger
Operations
Analog circuit settling time for stable operation.
Analog reference circuits VREF & IREF start up and
configured output reference voltage is provided at VOUT
pin.
Clock count start
Analog circuit startup
Pressure judge circuit not in operation
SV initial operation (ST not in operation)
VP&VN pin fixed to 1/2*VS; given value output to VOUT
Self-diagnostic circuit operation & idling
Back to normal operation on completing self-diagnosis in
50 CLK.
Analog circuit startup
Pressure judge circuit not in operation
STV initial operation
Output pressure (VP-VN=0V) to VOUT
:(Same as operation after ST3 in 3.1 Normal Operation
Timing)
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Adjustment Sequence
■ Main Routine
Power ON
( & STBYN : “H” )
EEPROM:ON
(CAdd 00h D[0] set)
note2)
EEPROM initialize
(Add 19h D[7:0] set)
Measurement
mode routine
Sensor & AK8996
temperature
characteristic
measurement
routine
Offset & Span
temperature
coefficient set
(Add 04h D[7:0]=7f
Add 05h D[2:0]=3
Add 06h D[7:0]=ff
Add 07h D[7:0]=7f
Add 08h D[7:0]=7f
Add 09h D[2:0]=3
Add 0Ah D[7:0]=ff
Add 0Bh D[2:0]=3
Add 0Ch D[7:0]=ff )
VREF adjustment
routine
EEPROM:OFF
(CAdd 00h D[0] set)
Sensor & AK8996
temperature
characteristic
measurement
routine
ex. Pressure:100kPa
ex. Ta:-40C
ex. Pressure:0kPa
Sensor & AK8996
temperature
characteristic
measurement
routine
Offset rough/fine
adjustment routine
ex. Pressure:100kPa
ex. Ta:25C
IREF adjustment
routine
OSC adjustment
routine
VTMP adjustment
routine
DET pin normal
operation set
(CAdd 00h D[4:1] set)
Offset rough/fine
adjustment routine
ex. Ta:105C
ex. Ta:25C
note2)
Level shift &
Pressure judge set
routine
Span rough/fine
adjustment routine
Span rough/fine
adjustment routine
Pressure & damage
check routine
Power OFF
EEPROM:ON
(CAdd 00h D[0] set)
EEPROM:ON
(CAdd 00h D[0] set)
Offset & Span
temperature
coefficient calculate
(Add 04h D[7:0]
Add 05h D[2:0]
Add 06h D[7:0]
Add 07h D[7:0]
Add 08h D[7:0]
Add 09h D[2:0]
Add 0Ah D[7:0]
Add 0Bh D[2:0]
Add 0Ch D[7:0] set)
Offset & Span
temperature
coefficient set
(Add 04h D[7:0]=0
Add 05h D[2:0]=0
Add 06h D[7:0]=0
Add 07h D[7:0]=0
Add 08h D[7:0]=0
Add 09h D[2:0]=0
Add 0Ah D[7:0]=0
Add 0Bh D[2:0]=0
Add 0Ch D[7:0]=0)
EEPROM:OFF
(CAdd 00h D[0] set)
EEPROM:OFF
(CAdd 00h D[0] set)
note) EEPROM Address is indicated by “Add”,
Control Register Address is indicated by “CAdd”.
note2) In case of Package, each items are unused.
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■ Sub Routine
Measurement mode
routine
VREF adjustment
routine
IREF adjustment
routine
Press ure J udge set
(Add 17h D[5:4] set)
VREF
measurement set
(CAdd 00h D[4:1] set)
I REF
meas urement set
(CAdd 00h D[4:1] set)
Supply voltage set
(Add 17h D[3] set)
VR EF measurement
& check
IREF measurement
& c heck
OK
OK
Sampling f req. set
(Add 17h D[2:1] set)
NG
NG
VREF adjus tment
(Add 12h D[2:0] set)
IREF adjus tment
(Add 13h D[3:0] set)
VR EF measurement
& check
IREF measurement
& chec k
Buffer ON/OFF set
(Add 17h D[0] set)
Input Gain (GA1/2) set
(Add 0Dh D[ 3:0] set)
NG
NG
OK
END
END
OK
END
note) EEPRO M Addres s is indicated by “Add”,
Control Regist er Address is indicated by “CAdd”.
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■ Sub Routine
OSC adjus tment
routine
VTMP adjustment
routine
O ffset rough/fine
adjus tment routine
OSC
measurement set
(CAdd 00h D[4:1] set)
VTMP
measurement s et
(CAdd 00h D[4:1] set)
Offs et meas urement
& c heck
OK
NG
OSC meas urement
& c heck
VTMP measurement
& check
OK
OK
EEPRO M:ON
(CAdd 00h D[0] set)
NG
NG
OSC adjus tment
(Add 14h D[3:0] set)
OSC measurement
& check
VT MP adjustment
(Add 15h D [5:0] s et)
VTMP meas urement
& check
NG
NG
OK
OK
O ffset adjustment
(Add 00h D[3:0] &
01h D[6:0] set)
EEPRO M:OFF
(CAdd 00h D[0] set)
Offset measurement
& check
NG
END
END
note) EEPROM Address is indicated by “Add”,
Control Register Addres s is indicated by “CAdd”.
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■ Sub Routine
Span rough/fine
adjustment routine
Span measurement
& c heck
Lev el s hift &
Pressure judge set
routine
EEPRO M:O N
(CAdd 00h D[0] set)
OK
NG
Buffer gain s et
(Add 0Eh D[2:0] set)
EEPRO M:O N
(CAdd 00h D[0] s et)
Span adjustment
(Add 02h D[0] & 03h
D[8:0] set)
EEPROM:OF F
(CAdd 00h D [0] set)
Span measurement
& c heck
EEPRO M:O FF
(CAdd 00h D[0] set)
Pres sure Judge
measurement s et
(CAdd 00h D[4:1] set)
Pres sure Judge
level measurement
& check
Lev el shift
measurement & check
OK
NG
OK
NG
NG
OK
END
EEPROM:ON
(CAdd 00h D[0] set)
Press ure J udge
level adjustment
(Add 1Dh D[1:0] &
1Eh D[7:0] set)
EEPROM:OFF
(CAdd 00h D[0] set)
Pressure Judge
level measurement
& c heck
NG
OK
EEPR OM:ON
(CAdd 00h D[0] set)
Lev el shift set
(Add 1Bh D [4:0] &
1Ch D[5:0] s et)
EEPRO M:O FF
(CAdd 00h D[0] set)
Level shift
measurement & c heck
NG
OK
END
note) EEPROM Address is indic ated by “Add”,
Control Register Address is indicated by “C Add”.
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■ Sub Routine
Sensor & AK8996
temperature
charac teris tic
meas urement
routine
Pressure & damage
check routine
ex. Press ure:0kPa
EEPR OM:ON
(CAdd 00h D[ 0] set)
CAdd 01h D[3,2] set
nd
Sensor temperature
offset voltage
meas urement
AK8996 2 order
temperat ure offset
voltage measurement
CAdd 01h D[1:0] set
ex. Pres sure:100kPa
st
Sensor temperature
posit ive span v oltage
meas urement
ex. Press ure:-100k Pa
Function ON/OF F set
(Add 18h D[4: 3] set)
D[4:3] : 1, 3h
Function select
(Add 18h D[2] set)
D[ 2] : 0h
D[2] : 1h
AK8996 1
order
temperat ure offset
voltage measurement
Pres sure lev el set
(Add 10h D[3:0] set)
CAdd 01h D[5:4, 3, 2,
1:0] set
Pressure level set
(Add 11h D[ 2:0] &
0Fh D [2:0] s et)
nd
Sensor temperature
negative s pan voltage
meas urement
AK8996 2 order
t emperature span
voltage measurement
Pressure lev el check
(CAdd 00h D[4:1] set )
CAdd 01h D[1:0] set
ex. Pressure: 0k Pa
st
CAdd 01h D[ 5: 4, 3, 2,
1:0] set
Lev el function set
(Add 18h D[1:0] set)
AK8996 1
order
t emperature span
voltage measurement
END
VO UT output control
(Add 18h D[5] set)
END
note) EEPROM Address is indicated by “Add”,
Control Register Address is indicated by “CAdd”.
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Functional Description
1) Adjustment Procedure Description (Example)
The adjustment procedure for the AK8996 follows (See "Adjustment Sequence.").
Note) When shipped in package form, the adjustments for the items 1-4 below have been completed. It is
necessary to read the data (items 1-4 below) from a chip first and after initializing the EEPROM,
rewrite the readout data. Note that depending on the required accuracy and implementation status,
there could be some cases where items 1-4 should be readjusted. The factory default adjustment is
with reference to 5V mode (EVD[0]=0).If 3V mode (EVD[0]=1) is used, readjustment is required.
The EEPROM register address is referred to as "address," while the control register (volatile memory)
address is referred to as "C address."
1. VREF Adjustment (completed when shipped in package form)
The reference voltage is adjusted to 1.0V. Adjusting the VREF voltage also means adjustment of the
sensor drive voltage (VS).
Configuring the adjustment mode 1 register (C address: 00h data AM[3:0]:1h) allows the VREF
voltage to be output at the DET pin (See recommended connection examples for components).
2. IREF Adjustment (completed when shipped in package form)
The reference current is adjusted to 20.0µA.
Configuring the adjustment mode 1 register (C address: 00h data AM[3:0]:2h) allows the IREF voltage
to be output at the DET pin (See recommended connection examples for components).
3. OSC Adjustment (completed when shipped in package form)
The intermittent operation control clock is adjusted to 1024kHz.
Configuring the adjustment mode 1 register (C address: 00h data AM[3:0]:3h) allows the OSC output
to be output at the DET pin (See recommended connection examples for components).
4. VTMP Adjustment (completed when shipped in package form)
Temperature sensor output (VTMP) voltage is adjusted to match the VREF voltage.
Configuring the adjustment mode 1 register (C address: 00h data AM[3:0]:4h) allows the VTMP
voltage to be output at the DET pin (See recommended connection examples for components).
Since a quadratic function generator is used to compensate for the sensor characteristics, the VTMP
output should be matched with the VREF voltage.
5. Offset Voltage Adjustment
The offset voltage for the pressure sensor is adjusted, including the AK8996 internal error.
The offset voltage is adjusted using the offset voltage rough adjustment register (Address: 00h data
EOC[10:7]) and offset voltage fine adjustment register (Address: 01h data EOC[6:0]).
Since the offset voltage temperature drift is to be compensated for afterwards, the complete
adjustment cannot be performed. Final readjustment is required including the level shift voltage error
(See Section 11).
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■ Offset Voltage Adjustment Example
EOC[10]: Offset voltage rough adjustment sign bit
If unadjusted output is more than 0.5*VDD, set EOC[10]=0.
If unadjusted output is less than 0.5*VDD, set EOC[10]=1.
EOC[9:7]: Offset voltage rough adjustment: Adjust in 300mV steps (@VDD: 5V).
When EOC[10] = 0, adjust within -150 to +150mV (0.5*VDD reference).
When EOC[10] = 1, adjust within -150 to +150mV (0.5*VDD reference).
EOC[6]: Offset voltage fine adjustment sign bit
If unadjusted output is more than 0.5*VDD, set EOC[6]=0.
If unadjusted output is less than 0.5*VDD, set EOC[6]=1.
EOC[5:0]: Offset voltage fine adjustment: Adjust in 5mV steps (@VDD: 5V). For example,
When EOC[6] = 0 and the rough adjustment result is -150mV, set 30 dec = 1E hex.
When EOC[6] = 1 and the rough adjustment result is +150mV, set 30 dec = 1E hex.
Fine-tune the offset to within ±2.5mV (@VDD: 5V).
6. Output Span Voltage Adjustment
The output span voltage for the connected pressure sensor is adjusted, including the AK8996 inherent
error.
The output span voltage is adjusted using the output span voltage adjustment register (Address: 02h
data ESC[8], address: 03h data ESC[7:0]).
Since the sensitivity temperature drift is to be compensated for afterwards, the complete adjustment
cannot be performed. Final readjustment is required, including the level shift voltage error (See
Section 12).
■ Output Span Voltage Adjustment Example
When the output is 2400mV (@VDD: 5V), set ESC[8:0] = 160 dec.
2400 [mV]*100/60 = 4000 [mV]
When the output is 5600mV (@VDD: 5V), set ESC[8:0] = -160 dec.
5600 [mV]*100/140 = 4000 [mV]
Fine-tune the above output span voltage error so that it is within ±5mV (@VDD: 5V).
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7. Secondary Characteristics Adjustment for Pressure Sensor & AK8996 Offset and Sensitivity
Temperature
Specific procedures for adjusting the pressure sensor's temperature drift (secondary characteristics)
follow the sequence illustrated on this page.
Note) For enhanced adjustment accuracy, make an adjustment for both maximum operation
temperature and minimum operation temperature.
2nd order function
generation block
AC[1:0]
2ND[1:0]
Offset Temp.
OT2, OT1S,
OT1
ST2P, ST2N,
ST1PS, ST1P,
ST1NS, ST1N
+40mV
+/- Gain
Temp.
STV
OTSW [0]
STSW[0]
VP
0.5*VS
VN
Gain Amp.1
Gain Amp.2
Gain Amp.3
ING
OCR, OCF
SCS, SC
-40mV
INSW [1:0]
EOT2[7:0]
nd
Temperature
Sensor
EST2P[7:0]
EST2N[7:0]
nd
2 order
characteristic
generator
2 order
characteristic
tuning
st
1
order
characteristic
tuning
2nd order function generation block
EOT1[9:0]
EST1P[9:0]
EST1N[9:0]
2ND[1:0]
Secondary temperature characteristics for pressure sensor offset and sensitivity as shown in this equation
can be cancelled out with the AK8996's corresponding characteristics.
Secondary temperature characteristics for pressure sensor offset and sensitivity Vsen (T):
Vsen (T) = αT^2+βT+γ
Secondary temperature characteristics for AK8996 offset and sensitivity Vic (T):
Vic = [(g*a)T^2+(g*b)T+(g*c)]+[dT+e]=(g*a)T^2+(g*b+d)T+(g*c+e)
Quadratic function Linear function
In order to cancel the secondary temperature characteristics, the following measurements should be
conducted for at least three different temperatures (e.g., 25ºC, -40ºC, +105ºC).
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7.1 Pressure Sensor Offset Temperature Drift Measurement
Configure adjustment mode 2 register (C address: 01h data INSW[1:0]:0h, data OTSW[0]:1h,
data STSW[0]:1h).
Measure the VOUT pin voltage at a pressure of 0kPa.
7.2 Pressure Sensor Sensitivity Temperature Drift Measurement
Configure adjustment mode 2 register (C address: 01h data INSW[1:0]:0h, data OTSW[0]:1h,
data STSW[0]:1h).
Measure the VOUT pin voltage (Vp72) at pressure e.g., +100kPa.
As necessary, measure the VOUT pin voltage at pressure e.g., -100kPa.
7.3 AK8996 Offset Secondary Temperature Characteristics Measurement (g*aT^2+g*bT+g*c)
Configure adjustment mode 2 register (C address: 01h data INSW[1:0]:1h, data OTSW[0]:0h,
data STSW[0]:1h, 2ND[1:0]:1h).
Measure the VOUT pin voltage.
7.4 AK8996 Offset Primary Temperature Characteristics Measurement (dT + e)
Configure adjustment mode 2 register (C address: 01h data INSW[1:0]:1h, data OTSW[0]:0h,
data STSW[0]:1h, 2ND[1:0]:2h).
Measure the VOUT pin voltage.
7.5 AK8996 Sensitivity Secondary Temperature Characteristics Measurement
(g*aT^2+g*bT+g*c)
Configure adjustment mode 2 register (C address: 01h data INSW[1:0]:2h, data OTSW[0]:1h,
data STSW[0]:0h, 2ND[1:0]:1h).
Measure the VOUT pin voltage.
7.6 AK8996 Sensitivity Primary Temperature Characteristics Measurement (dT + e)
Configure adjustment mode 2 register (C address: 01h data INSW[1:0]:2h, data OTSW[0]:1h,
data STSW[0]:0h, 2ND[1:0]:2h).
Measure the VOUT pin voltage.
8. Calculating the Secondary Characteristics from the Section 7 Measurement Results
Calculate α off, β off and γ off values from the pressure sensor offset temperature measurement
results.
Calculate α ga, β ga, and γ ga values from the pressure sensor sensitivity temperature
measurement results.
Values for g*a, g*b+d and g*c+e are known from the AK8996 temperature drift measurement
results.
Zero order coefficient γ and g*c + e are already adjusted in Sections 5 and 6, so no further
adjustment is required here.
For offset and sensitivity,
Make an adjustment to achieve α = g*a.
Make an adjustment to achieve β = g*b + d.
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Explanations for "Calculating Sensitivity Temperature Characteristics 2nd Order Coefficients", "Offset
Temperature Secondary Characteristics Calculation Example" and "Sensitivity Temperature Secondary
Characteristics Calculation Example." are described in the following section.
■ Calculating Sensitivity Temperature Characteristics 2nd Order Coefficients
The difference between the values measured at the VOUT pin for three temperature points and the
reference values at the reference voltage (Vbase = 0.8 V) is calculated to obtain the following coefficients
for the sensitivity:
Sensor: α ga, β ga, γ ga
AK8996: a, b, c (quadratic function output), d, e (linear function output)
For example, assume:
Sensitivity temperature drift measurement result for a sensor alone:
Vsenc (25ºC), Vsenn (low temp), Vsenp (high temp)
Sensitivity temperature drift measurement result for AK8996:
Vicc2 (25ºC), Vicn2 (low temp), Vicp2 (high temp) quadratic function
Vicc1 (25ºC), Vicn1 (low temp), Vicp1 (high temp) linear function
Note) These values are for the span from which the offset voltages are subtracted for each temperature.
1) The gain values (gc, gn, gp) for compensating the sensitivity temperature drift are obtained from the
sensitivity temperature drift results of a sensor alone:
gc=Vsenc/Vsenc=1, gn=Vsenc/Vsenn, gp=Vsenc/Vsenp
For the gain values (gc, gn, gp) obtained, find the voltage that should be output from the AK8996
quadratic function generator.
Vsenc1=Vbase/gc, Vsenn1=Vbase/gn, Vsenp1=Vbase/gp
Vbase: AK8996's quadratic function generator reference voltage (Vbase = 0.8V)
Find the coefficients (α ga, β ga, γ ga) as the secondary characteristics of the sensitivity temperature
drift of a sensor alone from the voltages for Vsenc1, Vsenn1 and Vsenp1.
2) From the AK8996's sensitivity temperature drift measurement result, find the gain values (gicc2, gicn2,
gicp2) which are compensated for by the quadratic function generator.
Depicted in this example is the AK8996's quadratic function sensitivity temperature drift
measurement result (same is also true with that of a linear function).
gicc2=Vicc2/Vicc2=1, gicn2=Vicn2/Vicc2, gicp2=Vicp2/Vicc2
For the gain values (gicc2, gicn2, gicp2) obtained, find the voltage which is output from the AK8996
quadratic function generator.
Vicc21=Vbase/gicc2, Vicn21=Vbase/gicn2, Vicp21=Vbase/gicp2
Vbase: AK8996's quadratic function generator reference voltage (Vbase = 0.8V)
Find the coefficients (a, b, c) as the secondary characteristics of the AK8996's sensitivity temperature
drift from the voltages for Vicc21, Vicn21 and Vicp21. In the same way, find the coefficients (d, e) as
the primary characteristics of the AK8996's sensitivity temperature drift from the voltages for Vicc11,
Vicn11 and Vicp11.
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Specific calculation examples are described here.
■ Offset Temperature Secondary Characteristics Calculation Example (See 5) Register Description in
"Serial Interface Description" Section)
Assume the AK8996's secondary characteristics (quadratic function and linear function) as:
Vic=[(g*a)T^2+(g*b)T+(g*c)]+[dT+e]=(g*a)T^2+(g*b+d)T+(g*c+e)
Quadratic function
Linear function
For example, the contents of an adjustment register corresponding to the sensor's secondary
characteristics is measured by:
Assume the secondary characteristic of the measured sensor is Vsen = 0.0003T^2 - 0.0237T+ 0.0.
If the temperature secondary characteristic of the measured AK8996's offset voltage is
Vic2=0.0016T^2 - 0.16T + 0.0 and the primary characteristic is Vic1=0.6T + 0.0, set the coefficient
so that the sensor's secondary characteristic is canceled out (i.e., AK8996's secondary
characteristic becomes Vic=-0.0003T^2 + 0.0237T - 0.0).
EOT2[7]: Second-order coefficient adjustment sign bit for the offset voltage temperature drift
To make the measured AK8996's second-order coefficient (g*a) positive, EOT[7]=0.
To make the measured AK8996's second-order coefficient (g*a) negative, EOT[7]=1.
In this example, set "1" because the second-order coefficient (g*a) is -0.0003.
EOT2[6:0]: Second-order coefficient adjustment bit for the offset voltage temperature drift
Adjust the coefficient in 0.7874% steps.
For example, set EOT2[6:0]=103dec and g*a=-0.000302 for the measured AK8996's
second-order coefficient (g*a). That is, the AK8996's secondary characteristic is
Vic2=-0.000302T^2 + 0.0302T - 0.0.
0.000302=0.0016*|1-0.7874/100*103|
0.0302=0.16*|1-0.7874/100*103|
Next, adjust the first-order coefficient so that the AK8996's first-order coefficient (g*b + d) equals
+0.0237.
EOT1[9]: First-order coefficient adjustment sign bit for the offset voltage temperature drift
Set EOT[9]=0 if the adjustment first-order coefficient d is for addition.
Set EOT[9]=1 if the adjustment first-order coefficient d is for subtraction.
In this example, set "1" because the first-order coefficient (g*b + d) is subtracted from
+0.0302 after secondary characteristic adjustment.
EOT1[8:0]: First-order coefficient adjustment bit for the offset voltage temperature drift
Since the first-order coefficient is +0.0237 (=0.0302-0.0065), set EOT1[8:0]=456dec
and d=-0.00646. That is, the AK8996's primary characteristic is Vic1=-0.00646T+0.0.
0.00646=0.6*|1-0.1957/100*456|
Now the adjustment of the second-order and first-order coefficients is completed with the
adjustment (Vic=0.0003T^2-0.0237T+0.0). The zero order coefficient is, ideally, 0.0, but it could
remain as an offset voltage. If that is the case, fine-tune according to the offset voltage fine
adjustment procedure after finishing the offset and sensitivity temperature drift adjustment.
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■ Sensitivity Temperature Secondary Characteristics Calculation Example (See 5) Register
Description in the "Serial Interface Description" section)
Assume the AK8996's secondary characteristics (quadratic function and linear function) as:
Vic=[(g*a)T^2+(g*b)T+(g*c)]+[dT+e]=(g*a)T^2+(g*b+d)T+(g*c+e)
Quadratic function
Linear function
For example, the content of the adjustment register corresponds to the sensor's secondary
characteristic in the positive pressure is measured by:
Assume the secondary characteristic of the measured sensor is Vsen = 0.00051T^2 - 0.2345T + 0.0.
If the secondary characteristic of the measured AK8996's sensitivity temperature is Vic2=0.0016T^2
- 0.16T + 0.0 and the primary characteristic is Vic1=0.32T + 0.0, set the coefficient to match the
sensor's secondary characteristic (i.e., AK8996's secondary characteristic becomes Vic=
0.00051T^2 - 0.2345T + 0.0).
ST2P[7]:
Second-order coefficient adjustment sign bit for the sensitivity temperature secondary
characteristics
Set EST2P[7]=0 to make the measured AK8996's second-order coefficient (g*a)
positive.
Set EST2P[7]=1 to make the measured AK8996's second-order coefficient (g*a)
negative.
In this example, set "0" because the second-order coefficient (g*a) is 0.00051.
ST2P[6:0]: Coefficient adjustment bit for sensitivity temperature secondary characteristics
Adjust the coefficient in 0.7874% steps.
For example, set EST2P[6:0]=123dec and g*a=0.0005039 for the measured AK8996's
second-order coefficient (g*a). That is, the AK8996's secondary characteristic is Vic2
= 0.0005039T^2 - 0.05039T + 0.0.
0.0005039=0.0016*|1-0.7874/100*123|
0.05039=0.16*|1-0.7874/100*123|
Next, adjust the first-order coefficient so that the AK8996's first-order coefficient (g*b + d) equals
-0.2345.
ST1P[9]: First-order coefficient adjustment sign bit for the sensitivity temperature secondary
characteristics
Set EST1P[9]=0 if the adjustment first-order coefficient d is for addition.
Set EST1P[9]=1 if the adjustment first-order coefficient d is for subtraction.
In this example, set "1" because the first-order coefficient (g*b + d) is subtracted from
-0.05039 after secondary characteristics adjustment.
ST1P[8:0] : First-order coefficient adjustment bit for the sensitivity temperature secondary
characteristics
Since a first-order coefficient is -0.2345 (=-0.05039-0.18411), set EST1P[8:0]=354dec
and d=-0.18434. That is, the AK8996's primary characteristic is Vic1=-0.18434T+0.0.
Now the adjustment of the second-order and first-order coefficients is completed with the
adjustment (Vic=0.00051T^2-0.2345T+0.0). The zero order coefficient is, ideally, 0.0, but it could
remain as a span voltage. If that is the case, fine-tune according to the span voltage adjustment
procedure after finishing the offset and sensitivity temperature drift adjustment.
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9. Offset Voltage Fine Adjustment
Adjusts the error caused when the offset voltage temperature drift are compensated for. Offset voltage
is adjusted using the offset voltage rough adjustment register (Address: 00h data EOC[10:7]) and
offset voltage fine adjustment register (Address: 01h data EOC[6:0]).
10. BUFF Gain Adjustment
Adjusts the output buffer gain. The output buffer gain is adjusted using the BUF gain adjustment
register (Address: 0Eh data EOG[2:0]).
11. Pressure Determination Threshold and Output Reference Voltage Adjustment
Specific adjustment procedures for the output reference voltage are shown based on this block
diagram.
S/H1 &
Level Shifter
VO
S/H2
32kohm
ELV[10:6]
ELV[5:0]
Buffer
VOUT
EOG[2:0]
EPJLV[9:0]
Pressure
judge
Adjust the pressure determination threshold values (adjust the pressure determination threshold
value first, followed by the output reference voltage). Pressure determination threshold values are
adjusted using the pressure judgment threshold adjustment registers 1 and 2 (Address: 1D, 1Eh data:
EPJLV[9:0]).
As shown in the diagram, the buffer circuit and pressure judgment circuit are tuned for the pressure
determination threshold adjustments. Thus, the VO pin voltage after the pressure determination
threshold adjustment is almost equal to 2.5V (@VDD: 5V) as a result of the offset voltage adjustment
in Section 5. So, after adjusting the pressure determination threshold, some pressure determination
threshold values may cause the VOUT pin voltage to get stuck at the supply voltage. For example, if
the pressure determination threshold is adjusted to 1.0V with a supply voltage of 5V EOG[2:0]=4hex
(set to 4x), the VOUT pin voltage is 1.0 + 4*(2.5 - 1.0) = 7.0V, stuck at the supply voltage.
Adjust the output reference voltage. The output reference voltage is adjusted using the register for the
output reference voltage’s rough and fine adjustments (Address: 1B, 1Ch data: ELV[10:0]).
First, calculate the adjustment value for the output reference voltage rough adjustment (ELV[10:6]).
Specifically, since it is known that the VO pin voltage is 2.5V (@VDD: 5V) and the buffer reference
voltage is the pressure determination threshold, calculate so that the difference between the two
values is as small as possible. Next, adjust the VOUT pin voltage to the desired output reference
voltage using the output reference voltage fine adjustment (ELV[5:0]).
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12. Output Span Voltage Fine Adjustment
Adjusts the error caused when the sensitivity temperature drift is compensated for. The output span
voltage is adjusted using the output span voltage adjustment register (Address: 02h data ESC[8],
address: 03h data ESC[7:0]).
2) Finding the VO Pin External Capacitance (Cap)
This section explains how the VO pin external capacitance is defined. The requirements for
determining the VO pin external capacitance value are, the stabilization time of the VOUT pin output
voltage on power-up and after exiting the standby mode (STBYN pin "L" to "H") and SINAD
(Signal/[Noise + Distortion]).
1. VOUT Pin Output Voltage Stabilization Time
Note that depending on the VO pin external capacitance values, the measurement values (VOUT pin
voltage) may contain errors upon power-up or after exiting STBYN. Stabilization time is not dependent
on the sampling clock.
Here is an example with the aid of a diagram and tables. "99.5% Settling time (+ in the figure)" in
the table below represents the time required for the voltage to settle to the output reference voltage X
(0.5*VDD in this case) during the period  in the figure and the voltage to settle down to 99.5% of the
output voltage Y (0.1*VDD in this case) according to the pressure applied during the period (+ in
the figure). Note)
Under the conditions where the VO pin has an external capacitance of 3µF (sampling frequency
100Hz), the VOUT pin voltage will settle down to 16.4% (0.0815*VDD with respect to the expected
0.5*VDD value) of the output reference voltage during the period  in the figure. The period  in the
figure is fixed to 0.3 msec.
Settling factor A=(1-e^(-0.3[msec]/(560[]*3[µF]))*100=16.4[%]
Subsequently, the output voltage will settle to 99.5% according to the pressure during period  in the
figure. During period  in the figure below, the output will settle down to from 0.0815*VDD to 99.5% of
0.1*VDD in 345.2 msec.
Settling factor B=(0.995*0.1*VDD-0.164*0.5*VDD)/(0.1*VDD-0.164*0.5*VDD)*100=97.2[%]
Settling time D (period  in the figure) =-32[k]*3[µF]*ln(1-B/100)=345.2 [msec]
Therefore, the settling time up to 99.5% (period + in the figure) will be as follows:
99.5% settling time (period + in the figure) = 0.3 [msec] + D = 345.5 [msec]
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Referring to the previous calculation example, determine the stabilization time based on actual
requirements:
Prerequisites: Output reference voltage:
X
Output voltage (VOUT pin): Y
VO pin external capacitance: Cap (Cap[µF] typ., Cap*1.1[µF] worst)
Internal resistance 1:
Res1 (560[] typ., 689.5[] worst)
VO pin internal resistance 2: Res2 (32[k] typ., 39.4[k] worst)
Item C:
Y>A*X C=99.5[%]; Y<A*X C=100.5[%]
Period  in the figure:
Time (0.3[msec] typ., 0.2 or 0.5[msec] worst)
Settling factor A=(1-e^(-Time/(Res1*Cap)))*100
Settling factor B=(C[%]/100*Y-A/100*X)/(Y-A/100*X)*100
Settling time D (period  in the figure) =-Res2*Cap*ln(1-B/100)
99.5% settling time (period + in the figure) = Time + D
VDD pin voltage

Sample timing

e.g. Level shift voltage 0.5VDD  Final value 0.1*VDD
When sampling frequency is 100 Hz,
VO pin capacitance 3 μF

VO&VOUT pin voltage

 -  Reference designators
: Sampling timing; this diagram represents 100 Hz (10 msec).
: Powe r-up rise t ime (Tvdd), specified as less than 200 μs.
: Sett ling time for stable analog operation (Tenable 1, 2).
Specified as either less than 465µs or 495µs depending on whether STBYN pin is used or not.
: Pressure signal detection time. On power-up or after exiting t he STBYN mode, this signal rapidly settles down to the reference voltage.
This time finally settles down depending on the VO pin e xternal cap acita nce an d the int ernal 32kΩ resistance dependan t time consta nt.
In this case, this period is typically 345.2 msec as shown in the table below.
VO pin
Ext. cap
Cutoff
Freq.
(typical)
99.5% Settling time
(Fig )
Worst
Typical
case
case
Note)
Fig Time (fixed)
Typical
case
Worst
case
Note)
3μF
1.658Hz 0.3 msec
0.2 msec 345.2 msec 617.9 msec
1μF
4.974Hz 0.3 msec
0.5 msec 171.8 msec 244.6 msec
100nF
49.74Hz 0.3 msec
0.5 msec 21.37 msec 28.96 msec
10nF
497.4Hz 0.3 msec
0.5 msec 2.139 msec 2.897 msec
1nF
4.97kHz 0.3 msec
0.5 msec 0.214 msec 0.290 msec
500pF
9.95kHz 0.3 msec
0.5 msec 0.107 msec 0.145 msec
Note) Worst case for external capacitance ±10% and lot variations.
MS1055-E-02
40
99.5% Settling time
(Fig +)
Typical
case
Worst case
345.5 msec
172.1 msec
21.67 msec
2.439 msec
0.514 msec
0.407 msec
618.1 msec
245.1 msec
29.46 msec
3.397 msec
0.790 msec
0.645 msec
Note)
2011/12
[AK8996/W]
Note)
The output reference voltage X (VO pin output) that is settled to during the period  in the diagram,
which is dependent on the output reference voltage rough & fine adjustment register (Address: 1B,
1Ch data: ELV[10:0]), is given by:
ELVR[9: 6]
VO pin
Dec
Hex
Bin
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ELVR[10]=0
(*VDD)
0.5
0.4
0.4
0.4
0.4
0.3
0.3
0.3
0.3
0.2
0.2
0.2
0.2
0.1
0.1
0.1
ELVR[10]=1
(*VDD)
0.5
0.5
0.5
0.5
0.6
0.6
0.6
0.6
0.7
0.7
0.7
0.7
0.8
0.8
0.8
0.8
Comments
Default
2. VOUT pin SINAD
Summarized in this table is the relationship between the VO pin’s external capacitance and SINAD.
Note that the SINAD should be 46dB or larger if 0.5% FS adjustment accuracy is required.
SINAD characteristics
Cutoff
Sampling
VO pin
Freq.
Worst case
Freq.
Ext. cap
Typical case
Note)
(typical)
5μF
0.995Hz
49.59dB
46.39dB
3μF
1.658Hz
45.15dB
41.95dB
100Hz
1μF
4.974Hz
35.61dB
32.41dB
100nF
49.74Hz
15.73dB
12.66dB
1μF
4.974Hz
55.61dB
52.41dB
1kHz
100nF
49.74Hz
35.61dB
32.41dB
10nF
497.4Hz
15.73dB
12.66dB
100nF
49.74Hz
55.82dB
52.62dB
10nF
497.4Hz
35.82dB
32.62dB
10.24kHz
1nF
4.97kHz
15.93dB
12.85dB
500pF
9.95kHz
10.23dB
7.46dB
Note) Worst case for external capacitance ±10% and lot variations.
As mentioned in Sections "1. VOUT pin output voltage stabilization time" and "2. VOUT pin SINAD",
the VO pin external capacitance value should be reduced to decrease the measurement time. For
increased SINAD, the VO pin external capacitance value should be greater.
On determining the VO pin external capacitance value, the various conditions should be thoroughly
reviewed according to the application requirements.
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3) Pressure Detection & Determination Circuit Operation at Power-Up and Standby Exit (STBYN pin
"L" to "H")
Use caution when operating the pressure detection and pressure determination circuits on power-up
and after exiting the standby mode (STBYN pin "L" to "H").
1. Pressure detection circuit operation
For proper operation of the pressure detection circuit, it is necessary to settle the VOUT pin output
voltage to within ±0.5% of the output reference voltage configured in the "Settling time for stable
analog operation" (See "Operation Sequence" Section).
The VOUT pin output voltage settles in the time constant determined by the 32k internal resistance
and VO pin external capacitance. To understand settling time, see 2) Finding the VO pin external
capacitance (Cap). If the Cap value is 0.1µF or less, the VOUT pin output voltage settles to within
±0.5% of the output reference voltage, while with the use of capacitance greater than 0.1µF, errors
may be detected because it does not settle to within ±0.5%.
In order to avoid this problem, the pressure detector should be left disabled for a short time at
power-up and at exiting the STBYN mode. Calculate the disable time based on 2) Finding the VO pin
external capacitance (Cap). There is a simplified equation to determine the worst-case value:
Disable time = -39400[] * 1.1*C[F] |* ln (1-0.995)
2. Pressure Detection Circuit Disable Time
Pressure detection circuit Disable time is the time from exit of the settling time for stable analog
operation to the pressure detection output. Pressure detection circuit Disable time with
pressure detection valid and both pressure detection and self-diagnosis valid is shown below.
2.1 Pressure detection valid (EINT1[1:0]=1h)
EAS[2: 0]
Dec Hex
Bin
0
0
000
1
1
001
2
2
010
3
3
011
4
4
100
5
5
101
6
6
110
7
7
111
Pressure Detector Disable Time (msec)
fs: 100Hz
fs: 1kHz
fs: 2kHz
fs: 10kHz
10
1.0
0.5
0.1
10
1.0
0.5
0.2
20
2.0
1.0
0.4
60
6.0
3.0
0.8
140
14.0
7.0
1.6
300
30.0
15.0
3.1
620
62.0
31.0
6.3
1260
126.0
63.0
12.5
Comments
Default
VDD
Settling time for
stable analog operation
DET pin output
Pressure detector disable time
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2.2 Pressure detection & self diagnosis valid (EINT1[1:0]=3h)
Dec
0
1
2
3
4
5
6
7
EAS[2: 0]
Hex
Bin
0
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
Pressure Detector Disable Time (msec)
fs: 100Hz
fs: 1kHz
fs: 2kHz
fs: 10kHz
10.2
1.2
0.7
0.3
10.2
1.2
0.7
0.3
40.2
4.2
2.2
0.6
80.2
8.2
4.2
1.0
160.2
16.2
8.2
1.8
320.2
32.2
16.2
3.3
640.2
64.2
32.2
6.5
1280.2
128.2
64.2
12.7
Comments
Default
VDD
Settling time for
stable analog operation
DET pin output
Pressure detector disable time
(Including self diagnosis time)
3. Pressure determination circuit operation
The settling time for the VOUT pin voltage is, as with the pressure detector, determined by the 32k
internal resistor and VO pin external capacitance C. Current specifications (C≤0.1µF) do not cause
any problem with the pressure determination results, whereas misinterpretation may occur in the
pressure determination circuit if a capacitance of more than 0.1µF is used. These matters should be
carefully considered before use.
4) Power Consumption
Current values described in 3) Power Consumption in the Electrical Characteristics are those for the
average current. The maximum current is shown in the table below. Use a power supply with sufficient
supply capacity by referring to this table:
Max. Current
MS1055-E-02
Unit
VDD: 3.6V
VDD: 5.5V
mA
2.4
3.5
43
Note
Reference value
for design
2011/12
[AK8996/W]
5) Note on the Use of Output Reference Voltage Switching Circuit (Level Shift)
S/H1 & Level Shift circuit is configured as shown here:
ELVR[9:6]=0h, ELVF[5:0]=0 0h: SW O FF
ELVR[9:6]
ELVF[5:0]
Rough adj.
DAC
Fine adj .
DAC
Le vel Shi ft
R =3 2k
LPF
VO
S/H 2
S/H 1
From this diagram, the switching operation inside the S/H1 differs between the code setup for
ELVR[9:6]=0h, ELVF[5:0]=00h (register LVR, LVF Address 1Bh, 1Ch) and otherwise. If the data is set
up as shown, both switches are turned off, while in other situations they are turned on.
In some circumstances, an adjustment step for the fine adjustment DAC on the VO pin or VOUT pin
cannot maintain the monotonicity between the ELVF[5:0]=00h and the other codes. Use adequate
care, especially when the output reference voltage is set around 0.5VDD.
6) Data Reproducibility at Measuring the Temperature Drift
AK8996 temperature drift data reproducibility experiments have been conducted. The
experimental result shown here indicates that the AK8996 temperature drift data reproducibility
is within ±0.3 mV. Note that the experimental result shown here is for reference:
Experiment conditions
Supply voltage:
5V
Input voltage:
40 mV (=VP-VN)
Output reference voltage:
0.5*VDD
Gain:
25 times
VO pin external capacitance:
10nF
Environmental temperature sweep: 25C → -40C → 25C → 125C → 25C
Measurement pin:
VO pin, VOUT pin
Experiment result: The graph shows that the resulting variations are within ±0.3mV.
VOUT pin
VO pin
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7) Offset Temperature Primary Characteristics (Compensation Procedure)
If the offset temperature drift first order coefficient is left over after adjustment of the sensor
characteristics, follow the readjustment procedure. Ensure that this procedure is conducted before
9. Offset Voltage Fine Adjustment.
Readjustment Procedure (See the figure below)
1. On the most recent setup of the adjustment temperature (e.g., at 50ºC), calculate the coefficient to
be applied to the AK8996.
2. After setup, measure the VOUT pin voltage (Voff50) with the pressure set to 0kPa.
3. Store the measured value in the memory (e.g., address 16 hex EUE[7:0]).
4. Restore the temperature to 25ºC (last adjustment phase).
5. Measure the VOUT pin voltage (Voff25) with the pressure set to 0kPa.
The adjustment procedure is normally completed with the adjustments of the offset voltage, pressure
determination threshold, output reference voltage and output span voltage fine adjustment. If,
however, offset temperature characteristic first-order coefficient needs to be adjusted, the following
adjustments should be performed first:
6. Calculate the remaining offset temperature characteristic first-order coefficients.
Remaining offset temperature characteristic 1st order coeff. =
(Voff50-Voff25)/(50-25)[mV/ºC]···(A)
7. Calculate a gradient per step from the offset temperature drift first-order coefficient (e.g.,
0.04[mV/ºC]).
Adjustment code = (A)/0.04
8. Apply the calculated adjustment code to the OT1 register (address 06 hex).
Output level for 0 kPa
Output
with coeff. being applied
Voff50
Output level with coeff
being applied
 fine
tuning
Voff25
0
50C Temperature
25C
Output level first set up
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8) Pressure Detector's Detection Threshold
Information about the setup of the pressure detector's detection threshold and the setup range of the
detection threshold based on the mode setup is summarized.
Block diagram of the pressure detector:
EINT2[0]
0.5*VDD<
PTH
Threshold
EEPROM
: EPT[3:0]
+ side
comparator
LOGIC
DET
-1
- side
comparator
0.5*VDD>
VOUT
EINT3[1:0]
The pressure detector's detection threshold can be set up, as shown in the block diagram, either
through the external input (PTH pin) or internal setup (EEPROM setup EPT[3:0]). Selecting the
external input or internal setup can be performed using the EEPROM (EINT2[0]).
As shown in the block diagram, the pressure detector's detection threshold is limited by the setup
range depending on the mode setup. Setup range limitations are summarized here; use care when
using the pressure detector.
EINT3 [1:0]
Symbol
00
INT<
01
INT>
10
INT><
11
INT<>
Mode setup
Detect pressure above
threshold
Detect pressure below
threshold
Detect pressure either
above or below threshold
Detect pressure within a
certain range
Detection threshold setup range
0.5*VDD~0.95*VDD @VDD: 5V
0.05*VDD~0.5*VDD @VDD: 5V
~(0.5*VDD~0.95*VDD),
(0.05*VDD~0.5*VDD)~ @VDD: 5V
(0.5*VDD~0.95*VDD)
~(0.05*VDD~0.5*VDD) @VDD: 5V
For example, if EINT3[1:0]: 0hex is set, the detection threshold range is, as shown in the table,
0.5*VDD to 0.95*VDD @VDD: 5V. This means that setup below 0.5*VDD cannot be achieved, so due
consideration must be given when using it.
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9) Note on the AK8996 Power-up
When applying the power to the AK8996, use caution to the following.
On power up the AK8996, keep the rise time below 200µs (0.1*VDD -> 0.8*VDD). If the rise time on
power up exceeds 200µs, this section may enter the test mode. The AK8996 may not function
properly in the test mode. To exit from the test mode, reset at the STBYN pin or recycle the power.
If the AK8996 cannot be powered up in less than 200µs, connect the STBYN pin to the resistor (R) and
capacitor (C) as shown below. Determine the resistance (R) and capacitance (C) values so that the
STBYN pin voltage is 0.3*VDD or less when the supply voltage reaches the VDD to ensure the
AK8996 digital circuit is reset on power up.
The following equation is used to calculate the resistance (R) and capacitance (C) values.
Vstbyn = VDD * [1-exp(-t/R*C)]
Vstbyn : STBYN pin voltage
t
: Time required to reach Vstbyn voltage
VDD
R
EEPROM &
Control Register
Serial I/F
STBYN
C
VSS
10) Note on the pressure detection circuit hysteresis voltage setup
Use caution to the following when setting up the pressure detection circuit hysteresis voltage.
The hysteresis voltage is normally used as negative with respect to the pressure detection threshold value
reference. If, however, the hysteresis voltage is set to a low value (e.g. 0.0025*VDD), the hysteresis
voltage may be positive with respect to the pressure detection threshold reference. In that case, the
pressure detection circuit may not function properly.
To avoid the above situations, be sure to adjust the hysteresis voltage in the adjustment phase before
using the pressure detection circuit hysteresis voltage. Also note that the hysteresis voltage varies with
the supply voltage.
The hysteresis voltages for four different supply voltages (2.5V, 3.0V, 3.3V, 5V) are shown in the table
below. Regions in the table where hysteresis voltage is likely to be inverted are shaded in red and the
regions the voltage is the least likely to be inverted are shaded in blue. Note that the table in the below is
for reference purpose only; do not use it as being guaranteed.
Address : 11 hex D[2:0]=EHYS[2:0]
EHYS[2:0]
Hysteresis voltage (mV)
VDD
Reference
Dec Hex Bin
VDD:2.5V
VDD:3V
VDD:3.3V
0
0
000 0.0200*VDD
-50.00
-60.00
-66.00
1
1
001 0.0175*VDD
-43.75
-52.50
-57.75
2
2
010 0.0150*VDD
-37.50
-45.00
-49.50
3
3
011 0.0125*VDD
-31.25
-37.50
-41.25
4
4
100 0.0100*VDD
-25.00
-30.00
-33.00
5
5
101 0.0075*VDD
-18.75
-22.50
-24.75
6
6
110 0.0050*VDD
-12.50
-15.00
-16.50
7
7
111 0.0025*VDD
-6.25
-7.50
-8.25
MS1055-E-02
47
VDD:5V
-100.0
-87.5
-75.0
-62.5
-50.0
-37.5
-25.0
-12.5
units
mV
mV
mV
mV
mV
mV
mV
mV
2011/12
[AK8996/W]
11) VOUT Output
The AK8996 VOUT output shows four kinds of output waveforms below according to the condition.
Please use the AK8996 understanding of those output waveforms may come.
No
Item
Content
Sensitivity temperature variation characteristic (ST operation) :
Description
When temperature changes, VOUT output shows sawtooth waveform within ST
adjustment step, according to the pressure applied.
VOUT(V)
Target voltage
1
Output
Waveform
-40
105
Temp(ºC)
ST adjustment step
Description
Sensitivity supply voltage variation characteristic (SV operation) :
When supply voltage changes, VOUT output shows stepwise waveform within SV
adjustment step , according to the pressure applied.
VOUT(V)
Target voltage
2
Output
Waveform
5.5
4.5
Supply
Voltage(V)
SV adjustment step
MS1055-E-02
48
2011/12
[AK8996/W]
N
o
Item
Content
VOUT output time change 1 :
When the band is not limited, a VOUT output shows stepwise change for every
Description
sampling period in the following figures. Since its change occurs for every
sampling period, it can be reduced by using bandwidth shaping filter.
ST or SV 1 step
VOUT(V)
3
Output
Waveform
1 cycle (Fs)
Time(msec)
VOUT output time change 2 :
When temperature changes slowly to compare with the band-limited time, a VOUT
Description
output shows stepwise change with temperature change in the following figures. For
example, it occurs when the temperature in a thermostat chamber changes slowly.
ST 1 step
VOUT(V)
4
Output
Waveform
Temp
Temperature change
Time(min)
MS1055-E-02
49
2011/12
[AK8996/W]
Serial Interface Description
The AK8996 writes data to and reads data from the EEPROM and control register (volatile memory) through a
three-wire synchronous serial interface, consisting of SCLK, SDI/O and CS. The serial interface circuit in its
input standby state detects the CS high signal and captures data from SDI/O in sync with the rising edge of the
SCLK, and outputs data from SDI/O synchronous with the rising edge of SCLK. Input data contains three
instruction bits (12 - 10), five address bits (A4 - A0) and eight data bits (D7 - D0). Provide the data in the order
of I2 → I0 → A4 → A0 → D7 → D0.
On the WRITE instruction, allow 5msec or more write time for EEPROM and 300nsec or more write time for
the control register (see Twr in 6) Digital AC Characteristics in the Electrical Characteristics section). For the
READ instruction, data is written up to 8CLK for SCLK (any values are acceptable because the data is
ignored) and the data output starting at the rising edge of 9CLK is read out.
1) Data Configuration
Configuration of data written to or read out through the serial interface is shown below. There are 16 specific
bits of data in total comprised of three instruction bits, five address bits and eight data bits.
Instruction
I2
I1
Address
I0
A4
A3
A2
Data
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Data input direction
2) Description of Instructions
Instruction codes are summarized below.
Code Note)
Instruction
I2
I1
I0
1
1
0
EEPROM read
(Read Mode)
1
0
1
EEPROM write
(Write Mode)
EEPROM batch
write
(Write Mode)
0
1
0
Control reg. read
(Read Mode)
0
0
1
Control reg. write
(Write Mode)
Description
Reads out the data written in the EEPROM
Writes data to the EEPROM. Write time (from 16th SCLK
rising edge to CS falling edge) requires 5msec or more.
If the 19h address is written, input data is written to all
addresses. Write time (from 16th SCLK rising edge to CS
falling edge) requires 10msec or more.
Reads out the data written in the control register.
Writes the data to the control register. Write time (from
16th SCLK rising edge to CS falling edge) requires
300nsec or more.
Note) Instructions other than this are prohibited.
MS1055-E-02
50
2011/12
[AK8996/W]
3) Register Map
3.1) EEPROM Register Map
Content
Name
OCR
Offset voltage rough adj.
Address
(hex)
Offset voltage fine adj.
01h
SCS
Output span voltage adj.
02h
Output span voltage adj.
03h
OT2
Offset voltage temp. drift
adj. (2nd order coeff.)
04h
OT1S
Offset voltage temp. drift
adj. (1st order coeff.)
05h
OT1
Offset voltage temp. drift
adj. (1st order coeff.)
ST2P
Sens. temp. drift adj.
(2nd order coeff. +ve)
ST2N
Sens. temp. drift adj.
(2nd order coeff. -ve)
ST1PS
Sens. temp. drift adj.
(1st order coeff. +ve)
ST1P
Sens. temp. drift adj.
(1st order coeff. +ve)
ST1NS
ST1N
ING
BUFG
AS
Sens. temp. drift adj.
(1st order coeff. -ve)
06h
07h
08h
0Ah
Input gain adj.
0Dh
10h
HYS
Pressure detector
comparator hysteresis
voltage adj.
11h
IREF *
OSC *
VTMP *
IREF current adj.
OSC frequency adj.
VTMP adj.
MS1055-E-02
D1
D0
EOC[8]
EOC[7]
0
0
0
0
EOC[6]
EOC[5]
EOC[4]
EOC[3]
EOC[2]
EOC[1]
EOC[0]
0
0
0
0
0
0
0
ESC[8]
0
ESC[7]
ESC[6]
ESC[5]
ESC[4]
ESC[3]
ESC[2]
ESC[1]
ESC[0]
0
0
0
0
0
0
0
0
EOT2[7]
EOT2[6]
EOT2[5]
EOT2[4]
EOT2[3]
EOT2[2]
EOT2[1]
EOT2[0]
0
0
0
0
0
0
0
0
EOT1[9]
EOT1[8]
EOT1[7]
EOT1[6]
EOT1[5]
EOT1[4]
EOT1[3]
EOT1[2]
0
0
EOT1[1]
EOT1[0]
0
0
0
0
0
0
0
0
EST2P[7]
EST2P[6]
EST2P[5]
EST2P[4]
EST2P[3]
EST2P[2]
EST2P[1]
EST2P[0]
0
0
0
0
0
0
0
0
EST2N[7]
EST2N[6]
EST2N[5]
EST2N[4]
EST2N[3]
EST2N[2]
EST2N[1]
EST2N[0]
0
0
0
0
0
0
EST1P[7]
EST1P[6]
EST1P[5]
EST1P[4]
EST1P[3]
EST1P[2]
0
0
0
0
0
0
0
0
EST1P[9]
EST1P[8]
0
0
EST1P[1]
EST1P[0]
0
0
EST1N[9]
EST1N[8]
0
0
EST1N[7]
EST1N[6]
EST1N[5]
EST1N[4]
EST1N[3]
EST1N[2]
EST1N[1]
EST1N[0]
0
0
0
0
0
0
0
0
EIG[3]
EIG[2]
EIG[1]
EIG[0]
0
0
0
0
EOG[2]
EOG[1]
EOG[0]
0Fh
Pressure detector
threshold
VREF voltage adj.
D2
EOC[9]
0Eh
PTH
VREF *
D3
EOC[10]
0Bh
0Ch
Pressure detector disable
time adj.
D5
Note 1)
09h
Sens. temp. drift adj.
st
(1 order coeff. -ve)
BUF gain adj.
D6
00h
OCF
SC
D7
Data
D4
15h
51
0
EAS[0]
0
0
0
EPT[2]
EPT[1]
EPT[0]
0
0
0
0
EHYS[2]
EHYS[1]
EHYS[0]
0
0
0
EVR[2]
EVR[1]
EVR[0]
EIR[3]
14h
0
EAS[1]
EPT[3]
12h
13h
0
EAS[2]
0
0
0
EIR[2]
EIR[1]
EIR[0]
0
0
0
0
EFR[3]
EFR[2]
EFR[1]
EFR[0]
0
0
0
0
ETM[5]
ETM[4]
ETM[3]
ETM[2]
ETM[1]
ETM[0]
0
0
0
0
0
0
2011/12
[AK8996/W]
UE
Customer data write use
MM
Measurement mode
INT
Pressure detection &
self-diagnosis mode
AW
LVR
Reserved
1Ah
Out reference voltage
rough adj.
(Level shift rough)
1Bh
PJLV2
Pressure judge threshold
adj. 2
EUE[6]
EUE[5]
EUE[4]
EUE[3]
EUE[2]
EUE[1]
0
0
0
0
0
0
0
0
EAC[1]
EAC[0]
EVD[0]
ESF[1]
ESF[0]
EBU[0]
18h
19h
Out reference voltage fine
adj. (Level shift fine)
EUE[7]
17h
EEPROM batch write
mode
LVF
PJLV1
16h
0
0
0
0
0
0
EOUT[0]
EINT1[1]
EINT1[0]
EINT2[0]
EINT3[1]
EINT3[0]
0
0
0
0
0
0
EAW[7]
EAW[6]
EAW[5]
EAW 4]
EAW[3]
EAW[2]
EAW[1]
EAW[0]
-
-
-
-
-
-
-
-
ELV[10]
ELV[9]
ELV[8]
ELV[7]
ELV[6]
0
0
0
0
0
ELV[5]
ELV[4]
ELV[3]
ELV[2]
ELV[1]
ELV[0]
0
0
0
0
1Ch
1Dh
Pressure judge threshold
adj. 1
1Eh
Reserved
1Fh
EUE[0]
0
0
EPJLV[9]
EPJLV[8]
0
0
EPJLV[7]
EPJLV[6]
EPJLV[5]
EPJLV[4]
EPJLV[3]
EPJLV[2]
EPJLV[1]
EPJLV[0]
0
0
0
0
0
0
0
0
Note 1) Lower line of each data represents the factory settings written to EEPROM.
Note 2) Access to addresses other than the above is prohibited.
Note 3) Write "0" to the unused D[7:0].
Note 4) For a packaged device, registers marked with * are adjusted before shipment.
Therefore, defaults are not "0".
3.2) Control Register (Volatile Memory) Map
Content
Name
CM1
CM2
Adjustment mode 1
Adjustment mode 2
Reserved
Address
(hex)
00h
D7
D6
D5
AC[1]
AC[0]
0
01h
Data
D4
AM[3]
Note 1)
D3
D2
D1
D0
AM[2]
AM[1]
AM[0]
AEPEN[0]
0
0
0
0
0
0
INSW[1]
INSW[0]
OTSW[0]
STSW[0]
2ND[1]
2ND[0]
0
0
0
0
0
0
02h –
1Fh
Note 1) Lower line of each data represents the control register data at power-up and STBYN "L".
Note 2) Access to addresses other than the above is prohibited.
Note 3) Write "0" to the unused D[7:0].
MS1055-E-02
52
2011/12
[AK8996/W]
4) Serial Interface Timing Diagram
[WRITE Mode]
Twr_EEP, Twr_REG
CS
1
4
9
16
SCLK
SDI/O
I2
I1
I0
A4
A3
A2
A1
A0
D7
D0
[READ Mode]
CS
1
4
9
16
SCLK
Hi-Z
SDI/O
MS1055-E-02
I2
I1
I0
A4
A3
A2
A1
A0
53
Hi-Z
D7
D0
2011/12
[AK8996/W]
5) Register Description
5.1) Description of EEPROM Register
5.1.1) Adjustment Section Register
Offset and span adjustment should be made after mode setup and adjustment of the reference
generator section including VREF, IREF, OSC and VTMP.
***** CAUTION *****
At the time of adjustment, set the EEPROM control mode to EEPROM Always Operating mode
(Control register Address 01 hex AEPEN[0]:1).
a) Offset voltage adjustment (Register names: OCR, OCF)
Rough adjustment should be performed first, followed by a fine adjustment for the offset voltage.
The content of the adjustment registers are shown here.
a-1) Offset voltage rough adjustment (OCR)
The offset voltage is coarsely tuned.
The offset adjustment voltage varies ratiometrically with respect to the supply voltage.
The ratio in the table below is benchmarked to a VOUT output of 4000 mV (@VDD: 5V) as 100%
(ratio = (Offset voltage @VDD: 5V)/4000[mV]*100[%]).
Address: 00 hex D[3:0]=ECO[10:7]
EOC[9: 7]
Ratio
VDD:
EOC
Dec Hex
Bin
(%)
[10]=0
(mV)
0
0
000
0.00
0
1
1
001
7.50
150
2
2
010
15.00
300
3
3
011
22.50
450
4
4
100
30.00
600
5
5
101
37.50
750
6
6
110
45.00
900
7
7
111
52.50
1050
MS1055-E-02
3V
EOC
[10]=1
(mV)
0
-150
-300
-450
-600
-750
-900
-1050
54
VDD:
EOC
[10]=0
(mV)
0
300
600
900
1200
1500
1800
2100
5V
EOC
[10]=1
(mV)
0
-300
-600
-900
-1200
-1500
-1800
-2100
Comments
Default
2011/12
[AK8996/W]
a-2) Offset voltage fine adjustment (OCF)
The offset voltage is fine-tuned.
The offset adjustment voltage varies ratiometrically with respect to the supply voltage.
The ratio in the table below is benchmarked to a VOUT output of 4000mV (@VDD: 5V) as 100%
(ratio = (Offset voltage @VDD: 5V)/4000[mV]*100[%]).
Address: 01 hex D[6:0]=ECO[6:0]
EOC [5:0]
Ratio
Dec
Hex
Bin
(%)
0
1
:
10
11
:
20
21
:
30
31
:
40
41
:
50
51
:
62
63
00
01
:
0A
0B
:
14
15
:
1E
1F
:
28
29
:
32
33
:
3E
3F
000000
000001
:
001010
001001
:
010100
010101
:
011110
011111
:
101000
101001
:
110010
110011
:
111110
111111
0.0000
0.1250
MS1055-E-02
1.2500
1.3750
2.5000
2.6250
3.7500
3.8750
5.0000
5.1250
6.2500
6.3750
7.7500
7.8750
VDD:
EOC
[6]=0
(mV)
0
2.5
:
25.0
27.5
:
50.0
52.5
:
75.0
77.5
:
100.0
102.5
:
125.0
127.5
:
155.0
157.5
3V
EOC
[6]=1
(mV)
0
-2.5
:
-25.0
-27.5
:
-50.0
-52.5
:
-75.0
-7.5
:
-100.0
-102.5
:
-125.0
-127.5
:
-155.0
-157.5
55
VDD:
EOC
[6]=0
(mV)
0
5
:
50
55
:
100
105
:
150
155
:
200
205
:
250
255
:
310
315
5V
EOC
[6]=1
(mV)
0
-5
:
-50
-55
:
-100
-105
:
-150
-155
:
-200
-205
:
-250
-255
:
-310
-315
Comments
Default
2011/12
[AK8996/W]
b) Output span voltage adjustment (Register names: SCS, SC)
Adjusts the span voltage.
The magnification factor in this table represents an adjustment factor benchmarked to a VOUT output of
4000mV (@VDD: 5V) as 1 (factor) = 100[%]/100[%].
The output and sensitivity describes the adjustable output voltages with the assumed reference
output ([email protected]: 3V, [email protected]: 5V) when ESC[8:0] = 0 dec.
Address: 02 hex - 03 hex D[8:0]=ESC[8:0]
Magnification
ESC[8:0]
Dec
Hex
Bin
(Factor)
-256
-255
:
-160
-159
:
-41
-40
:
-2
-1
0
1
2
:
40
41
:
159
160
:
254
255
100
101
:
160
161
:
1D7
1D8
:
1FE
1FF
000
001
002
:
028
029
:
09F
0A0
:
0FE
0FF
100000000
100000001
:
101100000
101100001
:
111010111
111011000
:
111111110
111111111
000000000
000000001
000000010
:
000101000
000101001
:
010011111
010100000
:
011111110
011111111
100/164.00
100/163.75
:
100/140.00
100/139.75
:
100/110.25
100/110.00
:
100/100.50
100/100.25
100/100.00
100/99.75
100/99.50
:
100/90.00
100/89.75
:
100/60.25
100/60.00
:
100/36.50
100/36.25
MS1055-E-02
VDD: 3V
Sens.
(mV)
(Factor)
1220
30.488
1221
30.534
:
:
1429
35.714
1431
35.778
:
:
1814
45.351
1818
45.455
:
:
1990
49.751
1995
49.875
2000
50.000
2005
50.125
2010
50.251
:
:
2222
55.556
2228
55.710
:
:
3320
82.988
3333
83.333
:
:
5479
136.99
5517
137.93
Output
56
VDD: 5V
Output Sens.
(Factor)
(mV)
2439
30.488
2443
30.534
:
:
2857
35.714
2862
35.778
:
:
3628
45.351
3636
45.455
:
:
3980
49.751
3990
49.875
4000
50.000
4010
50.125
4020
50.251
:
:
4444
55.556
4457
55.710
:
:
6639
82.988
6667
83.333
:
:
10959 136.99
11034 137.93
Comments
Default
2011/12
[AK8996/W]
c) Offset voltage temperature drift adjustment
Adjusts the offset voltage temperature secondary characteristics inherent to a sensor and the
AK8996. After performing the offset voltage adjustment at 25ºC, use the register's offset voltage
temperature characteristic coefficients for adjustment so that the absolute values of the AK8996's
coefficient are matched to those of the sensor's coefficient. (See 1) Adjustment Procedure
Description in "Functional Description" in the "Adjustment Sequence" section)
c-1) Offset voltage temperature drift 2 nd order coefficient adjustment (Register name: OT2)
Address: 04 hex D[7:0]=EOT2[7:0]
EOT2[6:0]
Ratio
Dec Hex
Bin
(%)
EOT2[7]:0
VDD: 5V / 3V
0.00160000
/0.00080000
0.0015874
/0.0007937
EOT2[7]:1
VDD: 5V / 3V
-0.00160000
/-0.00080000
-0.0015874
/-0.0007937
0
00
0000000
100.000
1
01
0000001
99.213
10
0010000
87.402
0.00139842
/0.00069921
-0.00139842
/-0.00069921
20
0100000
74.803
0.00119685
/0.000598425
-0.00119685
/-0.000598425
40
1000000
49.606
0.0007937
/0.00039685
-0.0007937
/-0.00039685
126
3E
1111110
0.7874
127
3F
1111111
0.0
0.0000126
/0.000006299
0.0
-0.0000126
/-0.000006299
0.0
Comments
Default
…..
16
…..
32
…..
64
…..
MS1055-E-02
57
2011/12
[AK8996/W]
c-2) Offset voltage temperature drift 1 st order coefficient adjustment (Register names: OT1S,
OT1)
Address: 05 hex - 06 hex D[9:0]=EOT1[9:0]
EOT1[8:0]
Ratio
EOT1[9]:0
Dec Hex
Bin
(%)
VDD: 5V / 3V
0.6000
0
000 000000000 100.000
/0.3000
0.5988
99.804
1
001 000000001
/0.2994
…..
0.5249
64
030 001000000 87.4755
/0.2624
…..
0.4497
128 040 010000000 74.9511
/0.2249
…..
0.2994
256 100 100000000 49.9022
/0.1497
…..
0.001174
0.1957
510 1FE 111111110
/0.0005871
0.0
0.0
511 1FF 111111111
MS1055-E-02
58
EOT1[9]:1
VDD: 5V / 3V
-0.6000
/-0.3000
-0.5988
/-0.2994
Comments
Default
-0.5249
/-0.2624
-0.4497
/-0.2249
-0.2994
/-0.1497
-0.001174
/-0.0005871
0.0
2011/12
[AK8996/W]
d) Sensitivity temperature drift adjustment (Register names: ST2P, ST2N, ST1PS, ST1P,
ST1NS, ST1N)
Adjusts the sensitivity temperature secondary characteristics inherent to a sensor and the AK8996.
After performing the span voltage adjustment at 25ºC, use the register's sensitivity temperature drift
coefficients for adjustment so that the absolute values of the AK8996's coefficient are matched to
those of the sensor's coefficient. (See 1) Adjustment Procedure Description in "Functional
Description" in the "Adjustment Sequence" section)
d-1) Sensitivity temperature drift 2 nd order coefficient adjustment (Register names: ST2P,
ST2N)
Address: 07 hex D[7:0]=EST2P[7:0], 08 hex D[7:0]=EST2N[7:0]
EST2P/N2[6:0]
Ratio
EST2P/N[7]:0
EST2P/N[7]:1
Comments
Dec Hex
Bin
(%)
VDD: 5V / 3V
VDD: 5V / 3V
0.00160000
-0.00160000
Default
0
00
0000000 100.000
/0.00080000
/-0.00080000
0.0015874
-0.0015874
99.213
1
01
0000001
/0.0007937
/-0.0007937
…..
0.00139842
-0.00139842
16
10
0010000 87.402
/0.00069921
/-0.00069921
…..
0.00119685
-0.00119685
32
20
0100000 74.803
/0.000598425
/-0.000598425
…..
0.0007937
-0.0007937
64
40
1000000 49.606
/0.00039685
/-0.00039685
…..
0.0000126
-0.0000126
0.7874
126
3E
1111110
/0.000006299
/-0.000006299
0.0
0.0
0.0
127
3F
1111111
MS1055-E-02
59
2011/12
[AK8996/W]
d-2) Sensitivity temperature drift 1 st order coefficient adjustment (Register names: ST1PS,
ST1P, ST1NS, ST1N)
Address: 09 hex – 0A hex D[9:0]=EST1P[9:0], 0B hex – 0C hex D[9:0]=EST1N[9:0]
EST1P/N1[8:0]
Ratio
EST1P/N[9]:0
EST1P/N[9]:1
Comments
Dec Hex
Bin
(%)
VDD: 5V / 3V
VDD: 5V / 3V
0.32
-0.32
Default
0
000 000000000 100.000
/0.30
/-0.30
0.3194
-0.3194
99.804
1
001 000000001
/0.2994
/-0.2994
…..
0.2799
-0.2799
64
030 001000000 87.4755
/0.2624
/-0.2624
…..
0.2398
-0.2398
128 040 010000000 74.9511
/0.2249
/-0.2249
…..
0.1597
-0.1597
256 100 100000000 49.9022
/0.1497
/-0.1497
…..
0.0006262
-0.0006262
0.1957
510 1FE 111111110
/0.0005871
/-0.0005871
0.0
0.0
0.0
511 1FF 111111111
e) Input gain (G1/2) adjustment (Register name: ING)
Register for setting the total gain.
The input gain is adjusted according to the full-scale voltage of the pressure sensor.
Adjust the input gain so that the internal gain amp 2 output voltage is 400mV (@VDD: 5.0V) or less.
Address: 0D hex D[3:0]=EIG[3: 0]
EIG[2:0]
G1 Gain
(times)
Dec Hex
Bin
0
0
000
2
1
1
001
3
2
2
010
4
3
3
011
5
4
4
100
6
5
5
101
7
6
6
110
8
7
7
111
9
MS1055-E-02
Total Gain (times)
EIG[3]=0
20
30
40
50
60
70
80
90
60
EIG[3]=1
40
60
80
100
120
140
160
180
Comments
Default
2011/12
[AK8996/W]
f)
BUF gain adjustment (Register name: BUFG)
Sets up the buffer circuit's gain.
After the level shift voltage is determined by the VOUT voltage, use EOG[2:0] for gain adjustment so
that the detection maximum output is 4000mV (@VDD: 5.0V) with Vop (level shift voltage is
uppermost or lowermost) or Vpp (± output centered on the level shift voltage).
Address: 0E hex D[2:0]=EOG[2:0]
EOG[2: 0]
Ratio
(%)
Dec Hex
Bin
0
0
000
100
1
1
001
125
2
2
010
150
3
3
011
175
4
4
100
200
Note 1) Dec 5 to 7 are unavailable.
BUFF gain
(times)
2.0
2.5
3.0
3.5
4.0
Total
(times)
25.00
31.25
37.50
43.75
50.00
Comments
Default
g) Pressure detector disable time (Register name: AS)
Sets up the pressure detector disable time.
In order for the pressure detector to accurately detect the pressure at power-up or standby exit ("L" to "H" at
STBYN pin), it must wait until the VOUT pin output reference voltage is stabilized (See Section 3 Pressure
Detection & Determination Circuit Operation at Power-Up and Standby Exit (STBYN pin "L" to "H") in
"Functional Description").
g-1) Pressure detection valid (EINT1[1:0]=1h)
Address : 0F hex D[2:0]=EAS[2:0]
Dec
0
1
2
3
4
5
6
7
EAS[2: 0]
Hex
Bin
0
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
Pressure Detector Disable Time (msec)
fs: 100Hz
fs: 1kHz
fs: 2kHz
fs: 10kHz
10
1.0
0.5
0.1
10
1.0
0.5
0.2
20
2.0
1.0
0.4
60
6.0
3.0
0.8
140
14.0
7.0
1.6
300
30.0
15.0
3.1
620
62.0
31.0
6.3
1260
126.0
63.0
12.5
Comments
Default
g-2) Pressure detection & self diagnosis valid (EINT1[1:0]=3h)
Address : 0F hex D[2:0]=EAS[2:0]
Dec
0
1
2
3
4
5
6
7
MS1055-E-02
EAS[2: 0]
Hex
Bin
0
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
Pressure Detector Disable Time (msec)
fs: 100Hz
fs: 1kHz
fs: 2kHz
fs: 10kHz
10.2
1.2
0.7
0.3
10.2
1.2
0.7
0.3
40.2
4.2
2.2
0.6
80.2
8.2
4.2
1.0
160.2
16.2
8.2
1.8
320.2
32.2
16.2
3.3
640.2
64.2
32.2
6.5
1280.2
128.2
64.2
12.7
61
Comments
Default
2011/12
[AK8996/W]
h) Pressure detector threshold (Register name: PTH)
Sets up the pressure detector's detection threshold values.
The detector threshold voltage varies ratiometrically with respect to the supply voltage. The
thresholds for positive (+) and negative (-) comparators cannot be defined independently.
Address: 10 hex D[3:0]=EPT[3:0]
EPT[3:0]
Detection threshold (V)
Comments
ex. VDD: 5V
Detection
Dec Hex
Bin
threshold
+ve side
-ve side
-8
8
1000
0.50*VDD
2.50
2.50
-7
9
1001
0.53*VDD
2.65
2.35
-6
A
1010
0.56*VDD
2.80
2.20
-5
B
1011
0.59*VDD
2.95
2.05
-4
C
1100
0.62*VDD
3.10
1.90
-3
D
1101
0.65*VDD
3.25
1.85
-2
E
1110
0.68*VDD
3.40
1.60
-1
F
1111
0.71*VDD
3.55
1.45
0
0
0000
0.74*VDD
3.70
1.30
Default
1
1
0001
0.77*VDD
3.85
1.15
2
2
0010
0.80*VDD
4.00
1.00
3
3
0011
0.83*VDD
4.15
0.85
4
4
0100
0.86*VDD
4.30
0.70
5
5
0101
0.89*VDD
4.45
0.55
Note)
6
6
0110
0.92*VDD
4.60
0.40
Note)
7
7
0111
0.95*VDD
4.75
0.25
Note) When EVD[0]:1 is used, setup of VDD: 2.2 to 3.6 V and EPT[3:0]:6h, 7h is prohibited.
i)
Comparator hysteresis voltage adjustment for pressure detection (Register name: HYS)
The hysteresis voltage of the comparator for the pressure detector is set up.
The hysteresis voltage varies ratiometrically with respect to the supply voltage. The hysteresis
voltages for positive (+) and negative (-) comparators cannot be defined independently.
Address: 11 hex D[2:0]=EHYS[2:0]
EHYS[2:0]
Hysteresis voltage (mV)
Comments
Dec
Hex
Bin
Hysteresis voltage
ex. VDD: 5V
0
0
000
0.0200*VDD
-100.0
Default
1
1
001
0.0175*VDD
-87.5
2
2
010
0.0150*VDD
-75.0
3
3
011
0.0125*VDD
-62.5
4
4
100
0.0100*VDD
-50.0
5
5
101
0.0075*VDD
-37.5
6
6
110
0.0050*VDD
-25.0
7
7
111
0.0025*VDD
-12.5
Note) See Functional Description 10) Note on the pressure detection circuit hysteresis voltage
setup
MS1055-E-02
62
2011/12
[AK8996/W]
5.1.2) Reference Voltage Generator Register
j)
VREF voltage adjustment (Register name: VREF)
Register for adjusting the AK8996 reference voltage. Perform an adjustment to attain the reference
voltage of 1000 mV (See Recommended Connection Example for Components).
ΔVREF3/5 in the table below indicates a value varying with the setup values of the register. ΔVS3/5
represents the values of ΔVREF3/5 multiplied by two and four, respectively. The ratio is
benchmarked to 1000mV (VREF ideal value) as 100% (Ratio = ΔVREF/1000[mV]*100[%]).
Address: 12 hex D[2:0]=EVR[2:0]
EVR[2:0]
Ratio VDD: 3V, 3.3V mode
ΔVREF3
ΔVS3
Dec Hex Bin
(%)
(mV)
(mV)
-4
4
100
96
-40
-80
-3
5
101
97
-30
-60
-2
6
110
98
-20
-40
-1
7
111
99
-10
-20
0
0
000
100
0
0
1
1
001
101
+10
+20
2
2
010
102
+20
+40
3
3
011
103
+30
+60
VDD: 5V
ΔVREF5
ΔVS5
(mV)
(mV)
-40
-160
-30
-120
-20
-80
-10
-40
0
0
+10
+40
+20
+80
+30
+120
Comments
Default
k) IREF current adjustment (Register name: IREF)
Register for adjusting the AK8996 reference current. Perform an adjustment to attain the reference
voltage of 20.0µA (See Recommended Connection Example for Components).
ΔIREF in the table below indicates a value varying with the setup values of the register.
ΔVIREF (= ΔIREF*47[k]) is a voltage value varying with the external resistance (47k) at the time of
adjustment.
The ratio is benchmarked to 20.0µA (IREF ideal value) as 100% (Ratio = ΔIREF/20[µA]*100[%]).
Address: 13 hex D[3:0]=EIR[3:0]
EIR[3:0]
Ratio
Dec Hex
Bin
(%)
-8
8
1000
83.0
-7
9
1001
84.7
-6
A
1010
86.6
-5
B
1011
88.5
-4
C
1100
90.5
-3
D
1101
92.7
-2
E
1110
95.0
-1
F
1111
97.4
0
0
0000
100
1
1
0001
102.8
2
2
0010
105.7
3
3
0011
108.8
4
4
0100
112.2
5
5
0101
115.9
6
6
0110
119.8
7
7
0111
124.1
MS1055-E-02
ΔIREF
(µA)
-3.40
-3.05
-2.68
-2.30
-1.89
-1.46
-1.00
-0.52
0
+0.55
+1.14
+1.77
+2.45
+3.17
+3.96
+4.81
ΔVIREF
(V)
-0.220
-0.203
-0.186
-0.168
-0.149
-0.129
-0.107
-0.084
-0.060
-0.034
-0.006
+0.023
+0.055
+0.089
+0.126
+0.166
63
Comments
Default
2011/12
[AK8996/W]
l)
OSC frequency adjustment (Register name: OSC)
Register for adjusting the AK8996 operation clock. Perform an adjustment to attain a frequency of
1.024kHz. Frequency Δf in the table below indicates a value varying with the setup values of the
register. The ratio is benchmarked to 1.024kHz (OSC ideal value) as 100%
(Ratio = Frequency Δf/1024[kHz]*100[%]).
Address: 14 hex D[3:0]=EFR[3:0]
EFR[3:0]
Dec
Hex
Bin
-4
C
1100
-3
D
1101
-2
E
1110
-1
F
1111
0
0
0000
1
1
0001
2
2
0010
3
3
0011
4
4
0100
Note 1) Hex 5 to B are unavailable.
Ratio
(%)
80
85
90
95
100
105
110
115
120
Frequency Δf
(kHz)
-204.8
-153.6
-102.4
-51.2
0
+51.2
+102.4
+153.6
+204.8
Comments
Default
m) VTMP voltage adjustment (Register name: VTMP)
Compensates the offset values for the AK8996's internal temperature sensor. Adjusts the values so
that the difference between VTMP voltage and VREF voltage is close to 0 mV (If VREF is 1005mV,
adjust so that VTMP is also 1005mV).
ΔVTMP in the table below indicates a value varying with the setup values of the register. The ratio is
benchmarked to 1000mV (VREF ideal value) as 100% (Ratio = ΔVTMP/1000[mV]*100[%]).
Address: 15 hex D[5:0]=ETM[5:0]
ETM[5:0]
Dec
Hex
Bin
-32
20
100000
…..
-16
32
110000
…..
-8
38
111000
…..
-4
3C
111100
…..
-1
3F
111111
0
00
000000
1
01
000001
…..
4
04
000100
…..
8
08
001000
…..
16
10
010000
…..
31
1F
011111
MS1055-E-02
Ratio
(%)
-6.4
ΔVTMP
(mV)
-64
-3.2
-32
-1.6
-16
-0.8
-8
-0.2
0.0
+0.2
-2
0
+2
+0.8
+8
+1.6
+16
+3.2
+32
+6.2
+62
64
Comments
Default
2011/12
[AK8996/W]
5.1.3) Register Available to Users
n) User-writable data space (Register name: UE)
Free area (EEPROM) available to the user.
Address: 16 hex D[7:0]=EUE[7:0]
Name
Content
Address
UE
User-writable data
16 hex
Default
Data
D7
D6
D5
D4
D3
D2
D1
D0
EUE7 EUE6 EUE5 EUE4 EUE3 EUE2 EUE1 EUE0
0
0
0
0
0
0
0
0
5.1.4) Mode Setup Register
o) Measurement mode (Register name: MM)
Sets up the measurement mode such as the selection of the AK8996 supply voltages and
sampling frequencies.
Address: 17 hex D[5:0]= EAC[1:0], EVD[0], ESF[1:0], EBU[0]
D[5:0]
Symbol
Mode setup
Pressure judge circuit control register (adj. mode 1 CM1 D[6.5]
D[5:4]
EAC[1:0]
prioritized)
00
NRM1
Pressure judge circuit functions valid (default)
01
APP
Pressure judge circuit invalid, fixed to positive pressure judge
10
APN
Pressure judge circuit invalid, fixed to negative pressure judge
11
Reserved
D[3]
EVD[0]
Supply voltage setup register
0
VD5
Supply voltage at 5V (default)
1
VD3
Supply voltage at 3V
D[2:1]
ESF[1:0]
Sampling frequency setup register
00
SF0
Sampling frequency 100 Hz (default)
01
SF1
Sampling frequency 1kHz
10
SF2
Sampling frequency 2kHz
11
SF3
Sampling frequency 10.24kHz
D[0]
EBU[0]
BUFFER Block ON/OFF register
0
BU0
BUFFER Block enable (default)
1
BU1
BUFFER Block disable
MS1055-E-02
65
2011/12
[AK8996/W]
p) Pressure detection and self-diagnosis modes (Register name: INT)
Sets up the pressure detector and self-diagnosis circuit integrated with the AK8996.
Address: 18 hex D[5:0]= EOUT[0], EINT1[1:0], EINT2[0], EINT3[1:0]
D[7:0]
Symbol
Mode setup
D[7:6]
Reserved
D[5]
EOUT[0]
VOUT pin output status setup register when DET pin is high
0
VOUTE
Normal state (default)
1
VOUTD
VOUT pin Hi-Z output (indeterminate)
D[4:3]
EINT1[1:0] Pressure detection & self-diagnosis setup register 1
00
INTOFF
Pressure detection & self-diagnosis turned off (default)
01
INTPON
Pressure detection valid
10
INTSON
Self diagnosis valid
11
INTON
Pressure detection & self diagnosis valid
D[2]
EINT2[0]
Pressure detection & self-diagnosis setup register 2
0
INT1OUT
Pressure detection valid (PTH pin reference is used) (default)
1
INT1IN
Pressure detection valid (Internal register reference is used)
D[1:0]
EINT3[1:0] Pressure detection & self-diagnosis setup register 3
00
INT<
Detect pressure above threshold (default)
01
INT>
Detect pressure below threshold
10
INT><
Detect pressure either above or below threshold
11
INT<>
Detect pressure within a certain range
q) EEPROM batch write mode (Register name: AW)
Initializes the addresses in the EEPROM register map all at once or writes identical data. This
address is not available in the EEPROM.
Address: 19 hex D[7:0]=EAW[7:0]
Name
Content
Address
AW
EEPROM batch write
19 hex
MS1055-E-02
Data
D7
D6
D5
D4
D3
D2
D1
D0
EAW7
EAW6
EAW5
EAW4
EAW3
EAW2
EAW1
EAW0
66
2011/12
[AK8996/W]
5.1.5) Output Reference Voltage and Pressure Judge Threshold Setup Register
r) Output reference voltage adjustment (Register names: LVR, LVF)
Rough adjustment should be performed first, followed by a fine adjustment for the output reference
voltage. The content of the adjustment registers is shown here.
r-1) Output reference voltage rough adjustment (LVR)
The output reference voltage is coarsely tuned.
The adjustment voltage varies ratiometrically with respect to the supply voltage.
Address: 1B hex D[4:0]=ELVR[10:6]
ELVR[9: 6]
VO pin
VOUT pin
ELVR
ELVR
ELVR
ELVR
Comments
Dec Hex Bin
[10]=0 [10]=1
[10]=0
[10]=1
(*VDD) (*VDD)
(*VDD)
(*VDD)
0
0
0000
0.000
0.000
0.000*OG Note)
0.000*OG
Default
1
1
0001 -0.026
+0.026
-0.026*OG
+0.026*OG
2
2
0010 -0.052
+0.052
-0.052*OG
+0.052*OG
3
3
0011 -0.078
+0.078
-0.078*OG
+0.078*OG
4
4
0100 -0.104
+0.104
-0.104*OG
+0.104*OG
5
5
0101 -0.130
+0.130
-0.130*OG
+0.130*OG
6
6
0110 -0.156
+0.156
-0.156*OG
+0.156*OG
7
7
0111 -0.182
+0.182
-0.182*OG
+0.182*OG
8
8
1000 -0.208
+0.208
-0.208*OG
+0.208*OG
9
9
1001 -0.234
+0.234
-0.234*OG
+0.234*OG
10
A
1010 -0.260
+0.260
-0.260*OG
+0.260*OG
11
B
1011 -0.286
+0.286
-0.286*OG
+0.286*OG
12
C
1100 -0.312
+0.312
-0.312*OG
+0.312*OG
13
D
1101 -0.338
+0.338
-0.338*OG
+0.338*OG
14
E
1110 -0.364
+0.364
-0.364*OG
+0.364*OG
15
F
1111 -0.390
+0.390
-0.390*OG
+0.390*OG
Note) OG: Indicates the value of the BUF gain (Register name: BUFG) being set.
MS1055-E-02
67
2011/12
[AK8996/W]
r-2) Output reference voltage fine adjustment (LVF)
The output reference voltage is fine-tuned.
The adjustment voltage varies ratiometrically with respect to the supply voltage.
Address: 1C hex D[5:0]=ELVF[5:0]
ELVF[5:0]
VO pin
VOUT pin
ELVR
ELVR
ELVR
ELVR
Dec Hex
Bin
[10]=0
[10]=1
[10]=0
[10]=1
(*VDD) (*VDD)
(*VDD)
(*VDD)
0
00 000000
0
0
0*OG
0*OG
1
01 000001 -0.0005 0.0005
-0.0005*OG
0.0005*OG
2
02 000010 -0.0010 0.0010
-0.0010*OG
0.0010*OG
:
:
:
:
:
:
:
30
1E 011110 -0.0150 0.0150
-0.0150*OG
0.0150*OG
31
1F 011111 -0.0155 0.0155
-0.0155*OG
0.0155*OG
32
20 100000 -0.0160 0.0160
-0.0160*OG
0.0160*OG
:
:
:
:
:
:
:
61
3D 111101 -0.0305 0.0305
-0.0305*OG
0.0305*OG
62
3E 111110 -0.0310 0.0310
-0.0310*OG
0.0310*OG
63
3F 111111 -0.0315 0.0315
-0.0315*OG
0.0315*OG
Note) OG: The value of the BUF gain (Register name: BUFG) being set.
Comments
Default
s) Pressure judge threshold adjustment (Register names: PJLV1, PJLV2)
The pressure judge threshold voltage is adjusted.
The adjustment threshold value varies ratiometrically with respect to the supply voltage.
Address: 1D hex D[1:0]=EPJLV[9:8], 1E hex D[7:0]=EPJLV[7:0]
DET pin
EPJLV[9:0]
Comments
VDD: 3V
VDD: 5V
Dec Hex
Bin
(mV)
(mV)
-450 23E
1000111110
1350
2250
-450 23F
1000111111
1347
2245
:
:
:
:
:
-401 26F
1001101111
1203
2005
-400 270
1001110000
1200
2000
-399 271
1001110001
1197
1995
:
:
:
:
:
-1
3FF
1111111111
3
5
0
0
0000000000
0
0
Default
1
1
0000000001
-3
-5
:
:
:
:
:
399 18F
0110001111
-1197
-1995
400 190
0110010000
-1200
-2000
401 191
0110010001
-1203
-2005
:
:
:
:
:
449 1C1
0111000001
-1347
-2245
450 1C2
0111000010
-1350
-2250
MS1055-E-02
68
2011/12
[AK8996/W]
5.2) Description of Control Register (Volatile Memory)
a) Adjustment mode 1 (Register name: CM1)
This register is used to adjust the AK8996 reference voltage and pressure sensor's offset, span,
offset temperature drift and sensitivity temperature drift including those of the AK8996.
Address: 00 hex D[6:0]=AC[1:0], AM[3:0], AEPEN[0]
(This is not a nonvolatile EEPROM, but a volatile register.)
D[7:0]
Symbol
Mode setup
Description
D[7]
Reserved
Pressure judge circuit
D[6:5]
AC[1:0]
Controls pressure judge circuit
control
00
NRM2
Normal operation
(Default)
Positive pressure
01
APP
Pressure determination result is positive pressure.
output
Negative pressure
10
APN
Pressure determination result is negative pressure.
output
11
Reserved
D[4:1] AM[3:0]
IC adjustment mode Adjustment signal is output at the DET pin.
0000
NRM1
Normal operation
(Default)
0001
AVR
VREF adjustment
Outputs the VREF voltage
0010
AIR
IREF adjustment
Outputs the IREF current
0011
AFR
OSC adjustment
Outputs the OSC signal
Outputs the VTMP voltage
Adjust this voltage so that it matches the VREF
0100
ATO
VTMP adjustment
voltage at 25C.
Positive judge
Outputs internally set positive determination
0101
ADT+
threshold adjustment threshold value
Negative judge
Outputs internally set negative determination
0110
ADTthreshold adjustment threshold value
Positive hysteresis
Outputs hysteresis voltage of the positive
0111
AHY+
voltage
comparator
Negative hysteresis
Outputs hysteresis voltage of the negative
1000
AHYvoltage
comparator
Pressure judge
1001
APJ
Outputs output determination threshold value
threshold adjustment
1010Reserved
1111
EEPROM control
D[0]
AEPEN[0]
Controls the EEPROM operation
mode
Intermittent EEPROM EEPROM normal operation (intermittent operation)
0
NRM0
operation
(Default)
EEPROM is always turned on.
1
AEPD
EEPROM always on
Always turn on when adjusting the module.
Note) When using the IC adjustment mode for setting the VTMP output, make an additional setup
of AEPEN[0] = 1. In any other setup, the circuit is automatically always turned on.
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b) Adjustment mode 2 (Register name: CM2)
This register is used to adjust the AK8996 and pressure sensor's offset, span, offset temperature
drift and sensitivity temperature drift.
Address: 01 hex D[5:0]=INSW[1:0], OTSW[0], STSW[0], 2ND[1:0]
(This is not a nonvolatile EEPROM, but a volatile register.)
D[7:0]
Symbol
Mode setup
Description
D[7:6]
Reserved
D[5:4] INSW[1:0]
Input mode control Controls the input mode
00
NRM6
Normal operation
Enables the sensor input (Default)
Reference voltage
Internally generated AK8996 reference
01
AIN0
mode
voltage fed to the input
Internally generated AK8996 80mV voltage
10
AIN80
80mV voltage mode
fed to the input
Reserved
11
Temperature offset Controls offset temperature drift adjustment
D[3]
OTSW[0]
circuit control
circuit
0
NRM5
Enable
Enables temperature offset circuit (Default)
1
ASTOF
Disable
Disables temperature offset circuit
D[2]
STSW[0]
ST circuit control
Controls the ST circuit
0
NRM4
Enable
Enables the ST circuit (Default)
1
ASVOF
Disable
Disables the ST circuit
Secondary
D[1:0]
2ND[1:0]
characteristic
measurement
00
NRM3
Normal operation
(Default)
Secondary
Outputs secondary characteristic (primary
01
A2ND
characteristic output characteristic off)
Primary
Outputs primary characteristic (secondary
10
A1ST
characteristic output characteristic off)
Reserved
11
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Recommended Connection Example for Components
1) VO pin connection example
VO
S/H2
32 k
0 F Š3 F
Inside AK8996/W
2) Power supply and AGND pin connection example
VDD
1.0 F±10%
AGND
10 nF±10%
VSS
Inside AK8996/W
3) DET pin connection examples for adjustment
1) VREF & VTMP adjustment
Control register (AVR, ATO)
VREF/VTMP
DET
Voltage
meter
1k
Inside AK8996/W
2) IREF adjustment
Control register (AIR)
IREF
Inside AK8996/W
DET
Voltage
meter
1k
47 k
3) Oscillator adjustment
Control register (AFR)
Oscillator
DET
Frequency
counter etc.
Inside AK8996/W
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4) PTH pin connection example
VDD
User control
PTH
User control
VSS
Inside AK8996/W
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Package Information
1. Marking
9
(1) Pin Number 1 indication mark
(2) Asahi-Kasei Microdevices
Logo
AK M
13
(2)
(3) Part Number
8 9 96
(4)
(4) Date Code (3 digits)
(3)
X1 X2 X3
5
(1)
1
2. External Dimensions
The rear-side TAB is recommended to be mounted
on the substrate to ensure strength. Do not connect
to the power supply, GND or any signal.
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IMPORTANT NOTICE
 These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales
office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current
status of the products.
 AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the
application or use of any information contained herein.
 Any export of these products, or devices or systems containing them, may require an export
license or other official approval under the law and regulations of the country of export pertaining to
customs and tariffs, currency exchange, or strategic materials.
 AKM products are neither intended nor authorized for use as critical componentsNote1) in any
safety, life support, or other hazard related device or systemNote2), and AKM assumes no
responsibility for such use, except for the use approved with the express written consent by
Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the
device or system containing it, and which must therefore meet very high standards of
performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other
fields, in which its failure to function or perform may reasonably be expected to result in loss of
life or in significant injury or damage to person or property.
 It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or
otherwise places the product with a third party, to notify such third party in advance of the above
content and conditions, and the buyer or distributor agrees to assume any and all responsibility
and liability for and hold AKM harmless from any and all claims arising from the use of said product
in the absence of such notification.
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