AK8448

ASAHI KASEI
[AK8448]
AK8448
6-Channel Linear Sensor compatible
10 Bit 40 MSPS x 3 Analog Pre-Processor
Features
…
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…
…
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…
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Maximum Processing Speed
In CDS mode and Clamp mode
1ch, 2ch and 3ch mode:
40M samples/sec per channel
4ch and 6ch mode:
20M sample/sec per channel
In DC Direct-coupled mode
1ch, 2ch and 3ch mode:
15M sample/sec per channel
4ch and 6ch mode:
15M sample/sec per channel
Maximum Input Level: 1.35Vpp (typ.)@CDS mode and DC connection mode
1.19Vpp (typ.)@Clamp mode
Compatible with both CCD and CIS Signal Polarities
Simultaneously Sampling 6-Channel CDS circuits ( Correlated Double Sampling )
Offset DACs: Adjustable Range : ±298.7 mV (typ.), Independent 6-channel 8 Bit DACs
PGA:
Adjustable Gain Range : 0 dB ~ 18.75 dB (typ.)
Independently adjustable 6-channel 8 Bit PGAs.
Linearity:
DNL = -1LSB (min.), +1LSB (max.) with guaranteed no missing code.
5 bit Output Bus:
Enables to output 10 Bit Data in 5 Bit x 2 cycles
4-Wire Serial Interface
Supply:
3.3V±0.3V
Power Dissipation:
T.B.D(typ.)@6ch mode, at 20M samples/sec per channel
Package:
64 Pin LQFP, Pin pitch 0.5 mm, Mold size 10 mm x 10 mm
DAREFP
DAREFN
VCLP
VCOM
VRP
VRN
AVDD
AISET
AVSS
DVDD
Reference Voltage
DVSS
CCDIN0
CCDIN1
DAC
Clamp
CDS
DAC
Clamp
CDS
10
DA0～4
5
DB0～4
PGA
Clamp
CDS
DAC
DAC
Clamp
CDS
5
DC0～4
PGA
Timing Control
SHD
ADC
10bit
40MSPS
PGA
REFIN5
CCDIN5
10
5
Output Control
DAC
CCDIN4
REFIN4
ADC
10bit
40MSPS
PGA
Clamp
CDS
REFIN3
CCDIN3
10
PGA
CCDIN2
REFIN2
ADC
10bit
40MSPS
MUX
DAC
REFIN1
MUX
Clamp
CDS
MUX
REFIN0
PGA
SHR
ADCK
RESETB
Serial I/F Control
CLPB
SDIN
MS1513-E-00
SDOUT SDENB SDCLK
CE0
CE1
2013/02
1
ASAHI KASEI
[AK8448]
Functional Description of Each Block
…
Clamp / CDS Sensor Interface Circuit
It samples the Image signal level from the sensor.
The AK8448 has 3 sampling modes – CDS mode, Clamp mode and DC direct-coupled mode.
There are 5 ,number of channel select modes – 1, 2, 3, 4 and 6 channels. Channel(s) to be used
is selected by the number of channel mode.
CDS circuits, DACs, PGAs and ADCs of the un-used channels are automatically powered-down.
…
DAC
Offset addition D/A converter
This is a D/A converter to generate an offset voltage which is added to the sampled signal level at
the Sensor Interface part. Voltage range of DAC is ±298.7mV (typ.) and its resolution is 8 Bit. An
independent offset voltage can be set to each channel by register setting.
…
PGA ( Programmable Gain Amplifier )
This is a programmable Gain amplifier to adjust signal amplitude of each channel. Adjustable
range is from 0 dB to 18.75 dB (typ.), and its resolution is 8 Bit.
An independent gain can be set to each channel by register setting.
…
This
MUX
is
Channel Multiplexer
an
Analog
Switch
to
input
in
the
time-division-multiplexed
fashion
the
simultaneously-sampled 2 channel signals to an ADC, in 4 channel mode and 6 channel mode.
In 4 channel mode and 6 channel mode, 10 Bit ADCs process dual channels in time-divisionmultiplexed method.
…
ADC
A/D Converter
This is a 10 Bit, 40 MSPS A/D converter to convert an Image signal level into digital data after
offset adjustment and gain adjustment are made. There are 3 ADCs and 2 channels are
connected to each ADC through a channel multiplexer.
…
Output Control
ADC Output Data Control
Digital circuit to control the Output Form of ADC data. ADC data can be output in either 5 Bit-wide
or 10 Bit-wide by register setting.
In case of 5 Bit-wide data operation, the upper 5 Bit of the ADC data is output at the rising edge of
ACDK clock, and the lower 5 Bit data ,at the falling edge of ADCK.
In case of 10 Bit-wide data operation, ADC data from two different data channels are
output at
the rising edge and at the falling edge of ADCK respectively.
It is also possible to output ADC data at only the falling edge of ADCK clock by register setting in
10 Bit-wide data operation.
MS1513-E-00
2013/02
2
ASAHI KASEI
…
Reference Voltage
[AK8448]
Reference Voltage Generation Circuit
Circuit to generate internal Clamp level VCLP, Analog Common Level VCOM, ADC Reference
Voltages VRP & VRN and DAC Reference Voltages DAREFP & DAREFN.
…
Timing Control
Timing Generating Circuit
Digital circuit to generate internal timing pulses from those input clocks, ADCK, SHR, SHD and
CLPB.
ADCK is a clock which is used for ADC operation and for operation of ADC Output Data Control
part.
SHR is a timing pulse which is used to sample Reference level of Sensor signal.
SHD is a timing pulse which is used to sample Data level of Sensor signal.
CLPB is a timing pulse to show Clamp period.
…
Serial I/F Control
Serial Register Interface Circuit
A 4-Wire Interface to set values at the Control registers.
Control registers also can be read out.
By assigning specific address to individual devices by chip enable pins CE0 and CE1, up to 4.
AK8448 devices can be connected on the same, 4-wires.
MS1513-E-00
2013/02
3
ASAHI KASEI
[AK8448]
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AVDD
CCDIN0
REFIN0
DAREFN
DAREFP
AISET
AVDD
AVSS
RESETB
CE1
CE0
SDCLK
SDENB
SDIN
AVDD
AVSS
Pin Assignment
AVSS
CCDIN1
REFIN1
VCLP
VCOM
CCDIN2
REFIN2
REFIN3
CCDIN3
VRP
VRN
CCDIN4
REFIN4
REFIN5
CCDIN5
AVDD
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SDOUT
NC
DA4 (D9)
DA3 (D8)
DA2 (D7)
DA1 (D6)
DA0 (D5)
DVDD
DVSS
DB4 (D4)
DB3 (D3)
DB2 (D2)
DB1 (D1)
DB0 (D0)
NC
DVDD
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DVSS
DC4
DC3
DC2
DC1
DC0
NC
DVDD
DVSS
AVSS
AVDD
CLPB
ADCK
SHD
SHR
AVSS
Figure 1
Pin Layout
MS1513-E-00
2013/02
4
ASAHI KASEI
[AK8448]
Pin Function
No.
Name
Type
Description
1
AVSS
PWR
Analog ground
2
SHR
I
Reference level sampling pulse input
3
SHD
I
Data level sampling pulse input
4
ADCK
I
ADC sampling clock input
5
CLPB
I
Clamp control input
Low : Clamp operation “ON”
High : Clamp operation “OFF”
This should be fixed to Low during CDS mode
6
AVDD
PWR
Analog power supply
7
AVSS
PWR
Analog ground
8
DVSS
PWR
Digital ground
9
DVDD
PWR
Digital power supply
10
NC
11
DC0
O
ADC output in a straight binary code( DC0 : LSB side , DC4 : MSB
12
DC1
O
side )
13
DC2
O
In 5 Bit-wide output operation in 3-channel and 6 channel modes,
14
DC3
O
Data output corresponds to CCDIN4 and CCDIN5.
15
DC4
O
In 10 Bit-wide output operation and in 5 Bit-wide output operation in 1
left open or should be connected to VSS
channel, 2
channel and 4 channel modes, these outputs are not used.
When these modes are selected, low level is output in normal operation
and either low level or high-Z output is programmable in power-down
mode by register setting.
16
DVSS
PWR
Digital ground
17
DVDD
PWR
Digital power supply
18
NC
19
DB0 (D0)
O
ADC output in a straight binary code.
20
DB1 (D1)
O
Signal name with parenthesis means a signal name in 10 Bit-wide
21
DB2 (D2)
O
output operation ( in 5 Bit-wide output operation, DB0 : LSB side, DB4 :
22
DB3 (D3)
O
MSB side and in 10 Bit-wide output operation, D0 : LSB ).
23
DB4 (D4)
O
When in 5 Bit-wide output operation in 1 channel mode, these outputs
left open or should be connected to AVSS
are not used. They become low level output in normal operation and
either low level or high-Z output is programmable by register setting in
power-down mode.
24
DVSS
PWR
Digital ground
25
DVDD
PWR
Digital power supply
MS1513-E-00
2013/02
5
ASAHI KASEI
[AK8448]
No.
Name
Type
Description
26
DA0 (D5)
O
ADC output in a straight binary code.
27
DA1 (D6)
O
Signal name with parenthesis means a signal name in 10 Bit-wide
28
DA2 (D7)
O
output operation ( in 5 Bit-wide output operation, DA0 : LSB side, DA4 :
29
DA3 (D8)
O
MSB side and in 10 Bit-wide output operation, D9 : MSB ).
30
DA4 (D9)
O
31
NC
32
SDOUT
O
Serial I/F Data output, Pull up or pull down please.
33
AVSS
PWR
Analog ground
34
AVDD
PWR
Analog power supply
35
SDIN
I
Serial I/F Data input
36
SDENB
I
Serial I/F Data enable
37
SDCLK
I
Serial I/F clock
38
CE0
I
Chip Enable
39
CE1
I
40
RESETB
I
Reset
41
AVSS
PWR
Analog ground
42
AVDD
PWR
Analog power supply
43
AISET
I
Internal Bias current
left open or should be connected to AVSS.
Connect a 8.2Kohm resistor between AVSS and this pin.
44
45
NC
TEST
I
left open or should be connected to AVSS.
For test , connect to AVSS.
46
REFIN0
I
Reference input
Connect a same value capacitor as CCDIN0 input capacitor between
AVSS and this pin. In DC direct-coupled mode, an externally-fed signal
reference level should be input.
47
CCDIN0
I
Sensor signal input
48
AVDD
PWR
Analog power supply
49
AVSS
PWR
Analog ground
50
CCDIN1
I
Sensor signal input
51
REFIN1
I
Reference input
Connect a same value capacitor as CCDIN1 input capacitor between
AVSS and this pin.
In DC direct-coupled mode, an externally-fed signal reference level
should be input.
52
VCLP
O
Clamp level output
Connect a stabilizing capacitor between AVSS and this pin.
MS1513-E-00
2013/02
6
ASAHI KASEI
No.
53
Name
VCOM
[AK8448]
Type
O
Description
Internal Reference voltage
Connect a stabilizing capacitor between AVSS and this pin
54
CCDIN2
I
Sensor signal input
55
REFIN2
I
Reference input
Connect a same value capacitor as CCDIN2 input capacitor between
AVSS and this pin.
In DC direct-coupled mode, an externally-fed signal reference level
should be input.
56
REFIN3
I
Reference input
Connect a same value capacitor as CCDIN3 input capacitor between
AVSS and this pin.
IN DC direct-coupled mode, an externally-fed signal reference level
should be input.
57
CCDIN3
I
Sensor signal input
58
VRP
O
ADC reference voltage positive side
Connect a stabilizing capacitor between AVSS and this pin.
59
VRN
O
ADC reference voltage negative side
Connect a stabilizing capacitor between AVSS and this pin.
60
CCDIN4
I
Sensor signal input
61
REFIN4
I
Reference input
Connect a same value capacitor as CCDIN4 input capacitor between
AVSS and this pin.
In DC direct-coupled mode, an externally-fed signal reference level
should be input.
62
REFIN5
I
Reference input
Connect a same value capacitor as CCDIN5 input capacitor between
AVSS and this pin.
In DC direct-coupled mode, an externally-fed signal reference level
should be input.
63
CCDIN5
I
Sensor signal input
64
AVDD
PWR
Analog power supply
Type description
Note )
I : input pin
O : output pin
PWR : power supply pin
AVDD is a power supply for Analog part and Digital part.
DVDD is a power supply for the Digital output bufferes.
MS1513-E-00
2013/02
7
ASAHI KASEI
[AK8448]
Absolute Maximum Ratings
AVSS = DVSS = 0 V. All voltages are referenced to ground.
Parameter
Symbol
Min.
Max.
Power Supplies
Input Current
Analog Input Voltage
Digital Input Voltage
(Input Pins)
Digital Input Voltage
(Output Pins)
Ambient Operating
Temperature
Storage Temperature
Unit
AVDD
−0.3
4.5
V
DVDD
−0.3
4.5
V
IIN
−10
10
mA
VINA
−0.3
AVDD+0.3
V
VINL
−0.3
AVDD+0.3
V
VONL
−0.3
DVDD+0.3
V
Ta
0
70
°C
Tstg
−65
150
°C
Notes
Except Supply
Pins
Restriction on the
over input
Operation under a condition exceeding above limits may cause permanent damage to the device.
Normal operation is not guaranteed under the above extreme conditions.
Recommended Operating Conditions
AVSS = DVSS = 0 V. All voltages are referenced to ground.
Parameter
Symbol
Min.
Typ.
Max.
Power Supplies
Analog
AVDD
3.0
3.3
3.6
Output buffer
DVDD
3.0
3.3
3.6
REFINn ( n = 0 ~ 5 )
VREFIN
0
AVDD−1.3
Input voltage at DC
direct-coupled mode
MS1513-E-00
Unit
V
V
V
Notes
Positive Polarity
2013/02
8
ASAHI KASEI
[AK8448]
Electrical Characteristics
„ DC Characteristics
Parameter
High level input
voltage
Low level input
voltage
High level output
voltage 1
Low level output
voltage 1
High level output
voltage 2
Low level output
voltage 2
Input leakage
current
High-Z leakage
current
Symbol
( AVDD = 3.0 ~ 3.6 V, DVDD = 3.0 ~ 3.6 V, Ta = 0 ~ 70 °C)
Pin
Min.
Max.
Unit
Notes
VIH
Note 1
VIL
Note 1
VOH1
Note 2
VOL1
Note 2
VOH2
Note 3
VOL2
Note 3
ILIKG
Note 1
IOZ
Note 2
0.7AVDD
V
0.3AVDD
V
V
IOH= −1mA
V
IOL= 1mA
V
IOH= −0.25mA
0.2DVDD
V
IOL= 0.25mA
−10
10
μA
−10
10
μA
0.8DVDD
0.2DVDD
0.8DVDD
( note 1 ) SHD, SHR, ADCK, CLPB, SDCLK, SDENB, SDIN, CE0, CE1,RESETB
( note 2 ) DA0 ~ DA4, DB0 ~ DB4, DC0 ~ DC4
( note 3 ) SDOUT
MS1513-E-00
2013/02
9
ASAHI KASEI
[AK8448]
„ Analog Characteristics
( AVDD = 3.3 V, DVDD = 3.3 V, Ta = 25 °C, ADCK at 40MHz unless otherwise specified )
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Reference Voltage part
Clamp Voltage
VCLP
Positive Polarity
0.94
1.04
1.14
V
Negative Polarity
2.15
2.3
2.45
Common Voltage VCOM
1.1
1.2
1.3
V
ADC Reference
Voltage
Positive
VRP
1.5
1.6
1.7
V
Negative
VRN
0.7
0.8
0.9
Clamp / CDS part
Input Range
VI
At PGA Gain= 0dB
CDS mode
1.20
1.35
1.50
Vpp
Clamp mode
1.04
1.19
1.34
DC direct-coupled mode
1.20
1.35
1.50
Input Capacitance CIN
CCDIN
10
pF
Input Bandwidth
CBW
CCDIN~ADC
1
( note 1 )
At PGA Gain= 0dB
pixel
CDS Effect
CDS
noise 0.4Vpp 150kHz
-35
dB
signal 0.8Vpp 1MHz
Offset Adjust DAC
Resolution
DRES
8
Bit
Range
DRNG
Input referred value
±252.0 ±298.7 ±366.6
mV
Differential
DNL
Guaranteed monotonicity
−1.0
+1.5
LSB
Non-Linearity
PGA
Maximum Gain
GMAX
CCDIN~ADC
18.25 18.75 19.25
dB
Relative value to 0dB
Step Width
GSTA
Resolution
Differential
Non-Linearity
RES
DNL
Input Idle State
Noise ( note 2 )
Internal Offset
( note 3 )
Cross-Talk
NI
Guaranteed monotonicity
0.001
0.03
～0.26
dB
ADC
VOFST
CCDIN~ADC
−1.0
Guaranteed no-missing code
Noise, Internal Offset, Cross-talk
At PGA Gain=0dB
At PGA Gain=18dB
At PGA Gain=0dB
−50
XTALK1
XTALK2
( note 4 )
( note 5 )
−3
MS1513-E-00
10
+1.0
0.4
1.0
bit
LSB
LSBrms
50
±1
mV
LSB
+3
2013/02
10
ASAHI KASEI
[AK8448]
( AVDD = 3.3 V, DVDD = 3.3 V, Ta = 25 °C, ADCK at 40MHz unless otherwise specified )
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Current Consumption
Analog Part
In Normal
IA
6 channel mode
160
202
mA
Operation
Digital Output
Part
ID
At Power-Down
IPD
6 channel mode, a full scale
minus 2 dB 1 MHz
sine-wave input signal,
CL = 10 pF
Analog part + Digital part
14.5
30
mA
0.1
mA
Characteristics above are when same external components and time-constant are used as
shown in the recommended , external circuit configuration examples.
( note 1 )
Time till the ADC output settles within +/− 1 LSB of the final value when a full-scale minus 2 dB
step signal is input.
( note 2 )
Defined as a sigma of ADC output code variations.
( note 3 )
It defines that the Offset DAC setting value in no input signal condition exists between Offset DAC
setting value of A0h ( equivalent to an input-referred, – 50 mV ) and 60h ( equivalent to an
input-referred, + 50 mV ) where ADC output code changes from 000h to 001h.
Since a total adjustable range of Offset Adjust DAC includes this internal Offset adjust range, a
practical adjustable range of input signal is reduced by the internal Offset amount.
( note 4 )
Definition at ADCK = 40 MHz, A/D conversion rate mode, 6 channels, CDS mode. PGA gain of
the channel to be measured is set at its maximum value, all other channels’ PGA gains are set at
minimum values.
Then measure how much the output code of the target channel to be measured fluctuates when
input to the measured channel is fixed and a full-scale minus 1 dB step signal is input on all other
channels.
( note 5 )
Definition at ADCK = 10 MHz, A/D conversion rate mode, all channels’ PGA gains at minimum
values.
Then measure how much the output code of the target channel to be measured fluctuates when
input to the measured channel is fixed and a full-scale minus 1 dB step signal is input on all other
channels.
MS1513-E-00
2013/02
11
ASAHI KASEI
[AK8448]
„ Switching Characteristics 1 : in ADC conversion rate mode, DC direct-coupled mode
z
Timing Diagrams ( 1 )
5 Bit wide, 1 channel, 2 channel, 3 channel modes
z
Timing Diagrams ( 3 )
5 Bit wide, 4 channel, 6 channel modes
z
Timing Diagrams ( 5 )
10 Bit wide, 1 channel mode
z
Timing Diagrams ( 7 )
10 Bit wide, 2 channel mode
z
Timing Diagrams ( 9 )
10 Bit wide, 4 channel mode
No.
1
Parameter
ADCK Cycle Time ( T )
2
ADCK Low Level Width
3
ADCK High Level Width
4
5
6
ADCK Rise Time
ADCK Fall Time
SHD Cycle Time
7
8
SHD Pulse Width
SHD Set-up Time
( time to ADCK to rise )
SHD Delay Time
( time from ADCK to fall )
SHD Aperture Delay
Output Data Delay Time
( time from ADCK edge )
9
10
11
12
Pipe Line Delay
( AVDD = 3.0 ~ 3.6 V, DVDD = 3.0 ~ 3.6 V, Ta = 0 ~ 70 °C)
Pin
Min.
Typ. Max. Unit
Condition
ADCK
33.3
2000 ns
4, 6ch mode
66.6
2000
1, 2, 3 ch mode
ADCK
15.0
ns
4, 6 ch mode
31.7
1, 2, 3 ch mode
ADCK
15.0
ns
4, 6 ch mode
31.7
1, 2, 3 ch mode
ADCK
6
ns
ADCK
6
ns
SHD
2T
ns
4, 6 ch mode
T
1, 2, 3 ch mode
SHD
12
ns
SHD
0
ns
SHD
SHD
DA4~DA0
DB4~DB0
DC4~DC0
DA4~DA0
DB4~DB0
DC4~DC0
14
ns
2.5
1
9
9
ns
ns
unit:
# of
ADCK
cycles
8.5
13
SHD = “ H “ inhibit period
( time till the first ADCK
to rise after SHD to fall )
SHD
T+1
MS1513-E-00
ns
C=10pF
2, 3, 4, 6 ch mode
and
1 ch 5 bits Width
mode
1 ch 10 bits
Width mode
4, 6ch mode
2013/02
12
ASAHI KASEI
[AK8448]
„ Switching Characteristics 2 : in ADC conversion rate mode, CDS, Clamp modes
z
Timing Diagrams ( 2 )
5 Bit wide,1 channel, 2 channel, 3 channel modes
z
Timing Diagrams ( 4 )
5 Bit wide, 4 channel, 6 channel modes
z
Timing Diagrams ( 6 )
10 Bit wide, 1 channel mode
z
Timing Diagrams ( 8 )
10 Bit wide, 2 channel mode
z
Timing Diagrams ( 10 ) 10 Bit wide, 4 channel mode
No.
1
2
3
4
Parameter
ADCK Cycle Time ( T )
ADCK Low Level Width
ADCK High Level Width
SHR, SHD Cycle Time
5
6
7
SHR Pulse Width
SHD Pulse Width
SHD Set-up Time
( time to ADCK to rise )
SHD Delay Time
( time from ADCK to fall )
SHR Aperture Delay
SHD Aperture Delay
Output Data Delay Time
( time from ADCK edge )
8
9
10
11
12
Pipe Line Delay
( AVDD = 3.0 ~ 3.6 V, DVDD = 3.0 ~ 3.6 V, Ta = 0 ~ 70 °C)
Pin
Min.
Typ. Max. Unit
Condition
ADCK
25
2000 ns
ADCK
10.9
ns
ADCK
10.9
ns
SHR, SHD
2T
ns
4, 6ch mode
T
1, 2, 3ch mode
SHR
8
ns
SHD
8
ns
SHD
0
ns
SHD
SHR
SHD
DA4~DA0
DB4~DB0
DC4~DC0
DA4~DA0
DB4~DB0
DC4~DC0
10
ns
3.0
2.5
1
9
9
ns
ns
ns
unit:
# of
ADCK
cycles
8.5
13
SHD
SHD = “ H “ inhibit period
( time till the first ADCK to
rise after SHD to fall )
T+1
MS1513-E-00
ns
C=10pF
2, 3, 4, 6ch mode
and
1CH 5 bits Width
mode
1CH 10 bits
Width mode
4, 6ch mode
2013/02
13
ASAHI KASEI
[AK8448]
„ Switching Characteristics 3 : in total pixel rate mode, DC direct-coupled mode
z
Timing Diagrams ( 11 )
10 Bit wide, 2 channel mode
z
Timing Diagrams ( 13 )
10 Bit wide, 3 channel mode
z
Timing Diagrams ( 15 )
10 Bit wide, 4 channel mode
z
Timing Diagrams ( 17 )
10 Bit wide, 6 channel mode
No.
1
Parameter
ADCK Cycle Time ( T )
2
ADCK Low Level Width
3
ADCK High Level Width
4
SHD Cycle Time
6
7
SHD Pulse Width
SHD Set-up Time
( time to ADCK to rise )
SHD Delay Time
( note 1 )
SHD Aperture Delay
Output Data Delay Time
( time from ADCK edge )
Pipe Line Delay
8
9
10
11
( AVDD = 3.0 ~ 3.6 V, DVDD = 3.0 ~ 3.6 V, Ta = 0 ~ 70°C)
Pin
Min.
Typ.
Max. Unit
Condition
ADCK
12.5
333
ns
6ch mode
16.6
500
4ch mode
22.2
666
3ch mode
33.3
1000
2ch mode
ADCK
4.6
ns
6ch mode
6.7
4ch mode
9.5
3ch mode
15.0
2ch mode
ADCK
4.6
ns
6ch mode
6.7
4ch mode
9.5
3ch mode
15.0
2ch mode
SHD
6T
ns
6ch mode
4T
4ch mode
3T
3ch mode
2T
2ch mode
SHD
12
ns
SHD
0
T/2-2
ns
SHD
SHD
DA4~DA0
DB4~DB0
DA4~DA0
DB4~DB0
14
ns
2.5
1
9
30
20
12
SHD
SHD = “ H “ inhibit period
( time till the first ADCK to
rise after SHD to fall )
3T+1
2T+1
ns
ns
C=10pF
unit: 3ch,6ch mode
# of
ADC 2ch,4ch mode
K
cycle
s
ns
6ch mode
4ch mode
( note 1 )
Time from the ADCK edge where a falling edge of the internal A / D clock is generated.
In 2 channel, 4 channel modes, it is from ADCK to rise.
In 3 channel, 6 channel modes, it is from ADCK to fall.
MS1513-E-00
2013/02
14
ASAHI KASEI
[AK8448]
„ Switching Characteristics 4 : in total pixel rate mode, CDS, Clamp modes
z
Timing Diagrams ( 12 ) 10 Bit wide, 2 channel mode
z
Timing Diagrams ( 14 ) 10 Bit wide, 3 channel mode
z
Timing Diagrams ( 16 ) 10 Bit wide, 4 channel mode
z
Timing Diagrams ( 18 ) 10 Bit wide, 6 channel mode
No.
1
Parameter
ADCK Cycle Time ( T )
2
3
4
ADCK Low Level Width
ADCK High Level Width
SHR, SHD Cycle Time
5
6
7
SHR Pulse Width
SHD Pulse Width
SHD Set-up Time
( time to ADCK to rise )
SHD Delay Time
( note 1 )
SHR Aperture Delay
SHD Aperture Delay
Output Data Delay Time
( time from ADCK edge )
Pipe Line Delay
8
11
12
11
12
( AVDD = 3.0 ~ 3.6 V, DVDD = 3.0 ~ 3.6 V, Ta = 0 ~ 70°C)
Pin
Min.
Typ.
Max. Unit
Condition
ADCK
12.5
333
ns
6ch mode
12.5
500
4ch mode
12.5
666
3ch mode
12.5
1000
2ch mode
ADCK
4.6
ns
ADCK
4.6
ns
SHR, SHD
6T
ns
6ch mode
4T
4ch mode
3T
3ch mode
2T
2ch mode
SHR
8
ns
SHD
8
ns
SHD
0
T/2-2
ns
SHD
SHR
SHD
DA4~DA0
DB4~DB0
DA4~DA0
DB4~DB0
10
ns
3.0
2.5
1
9
30
20
13
SHD
SHD = “ H “ inhibit period
( time till the first ADCK to
rise after SHD to fall )
3T+1
2T+1
ns
ns
ns
C=10pF
unit: 3ch,6ch mode
# of
ADC 2ch,4ch mode
K
cycle
s
ns
6ch mode
4ch mode
( note 1 )
Time from the ADCK edge where a falling edge of the internal A / D clock is generated.
In 2 channel, 4 channel modes, it is from ADCK to rise.
In 3 channel, 6 channel modes, it is from ADCK to fall.
Timings are specified at the points where specified levels by the DC Characteristics are
intersected.
MS1513-E-00
2013/02
15
ASAHI KASEI
[AK8448]
„ Timing Diagrams (1) : ADCK frequency = A/D conversion rate mode ( 5 Bit-wide output )
z
1 channel, 2 channel, 3 channel modes ( DC direct-coupled, positive polarity )
Please refer to Switching Characteristics 1 table.
CCDIN0
CCDIN2
CCDIN4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
ADCK
SHR
SHD
DA4～0
M L M L M L M L M L M L M L M L M L M L M L M L M L M L M L
CCDIN0
0
1
2
3
DB4～0
M L M L M L M L M L M L M L M L M L M L M L M L M L M L M L
CCDIN2
0
1
2
3
DC4～0
M L M L M L M L M L M L M L M L M L M L M L M L M L M L M L
CCDIN4
0
1
2
3
9 ADCK cycles
(Pipeline Delay)
M: MSB 5bit
L: LSB 5bit
Timing Diagrams in 1 channel, 2 channel, 3 channel modes
CCDIN0
CCDIN2
CCDIN4
n
n+1
12
SHR
10
9
8
SHD
6
1(T)
ADCK
4
DA4～0
DB4～0
DC4～0
LSB
3
5
2
MSB
0.5*AVDD
0.5*AVDD
13
13
0.5*DVDD
LSB
n－10
0.5*DVDD
MSB
LSB
n－9
Detailed Timing Diagrams in 1 channel, 2 channel, 3 channel modes
MS1513-E-00
2013/02
16
ASAHI KASEI
[AK8448]
„ Timing Diagrams (2) : ADCK frequency = A/D conversion rate mode ( 5 Bit-wide output )
1 channel, 2 channel, 3 channel modes
z
( CDS mode & Clamp modes, negative polarity )
Please refer to Switching Characteristics 2 table.
CCDIN0
CCDIN2
CCDIN4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
ADCK
SHR
SHD
DA4~0
M L M L M L M L M L M L M L M L M L M L M L M L M L M L M L
CCDIN0
0
1
2
3
DB4~0
M L M L M L M L M L M L M L M L M L M L M L M L M L M L M L
CCDIN2
0
1
2
3
DC4~0
M L M L M L M L M L M L M L M L M L M L M L M L M L M L M L
CCDIN4
0
1
2
3
9 ADCK cycles
(Pipeline Delay)
M: MSB 5bit
L: LSB 5bit
Timing Diagrams in 1 channel, 2 channel, 3 channel modes
CCDIN0
CCDIN2
CCDIN4
11
n-2
n-1
n
12
n+1
SHR
6
7
10
9
SHD
4
8
6
5
0.5*AVDD
ADCK
3
DA4~0
DB4~0
DC4~0
2
1 (T)
LSB
MSB
13
LSB
n－12
MSB
LSB
n－11
MSB
13
LSB
n－10
0.5*DVDD
MSB
LSB
n－9
MSB
n－8
Detailed Timing Diagrams in 1 channel, 2 channel, 3 channel modes
MS1513-E-00
2013/02
17
ASAHI KASEI
[AK8448]
„ Timing Diagrams (3) : ADCK frequency = A/D conversion rate ( 5 Bit-wide output )
z
4 channel, 6 channel modes ( DC direct-coupled mode, positive polarity )
Please refer to Switching Characteristics 1 table.
CCDINn
(n=0~5)
0
1
2
3
4
5
6
7
ADCK
SHR
SHD
DA4~0
M L M L M L M L M L M L M L M L M L M L M L M L M L M L M L
1
1
2
0
0
even= CCDIN0
even odd even odd even
odd= CCDIN1
DB4~0
M L M L M L M L M L M L M L M L M L M L M L M L M L M L M L
1
1
0
0
2
even= CCDIN2
even odd even odd even
odd= CCDIN3
DC4~0
M L M L M L M L M L M L M L M L M L M L M L M L M L M L M L
1
1
0
0
2
even= CCDIN4
even odd even odd even
odd= CCDIN5
9 ADCK cycles
(Pipeline Delay)
M: MSB 5bit
L: LSB 5bit
Timing Diagrams in 4 channel, 6 channel modes
CCDINn
(n=0~5)
n
12
SHR
10
8
9
SHD
6
1(T)
ADCK
0.5*AVDD
13
4
DA4~0
DB4~0
DC4~0
LSB
3
5
13
2
MSB
LSB
n−6
odd
MSB
0.5*DVDD
LSB
n−5
even
Detailed Timing Diagrams in 4 channel, 6 channel modes
MS1513-E-00
2013/02
18
ASAHI KASEI
[AK8448]
„ Timing Diagrams (4) : ADCK frequency = A/D conversion rate mode ( 5 Bit-wide output )
z
4 channel, 6 channel modes ( CDS mode & Clamp mode, negative polarity )
Please refer to Switching Characteristics 2 table.
CCDINn
(n=0~5)
0
1
2
3
4
5
6
7
ADCK
SHR
SHD
DA4~0
M L M L M L M L M L M L M L M L M L M L M L M L M L M L M L
1
1
2
0
0
even= CCDIN0
even odd even odd even
odd= CCDIN1
DB4~0
M L M L M L M L M L M L M L M L M L M L M L M L M L M L M L
1
1
0
0
2
even= CCDIN2
even odd even odd even
odd= CCDIN3
DC4~0
M L M L M L M L M L M L M L M L M L M L M L M L M L M L M L
1
1
0
0
2
even= CCDIN4
even odd even odd even
odd= CCDIN5
9 ADCK cycles
(Pipeline Delay)
M: MSB 5bit
L: LSB 5bit
Timing Diagrams in 4 channel, 6 channel modes
CCDINn
(n=0~5)
n-1
11
12
n
n+1
SHR
6
7
10
9
SHD
8
6
0.5*AVDD
ADCK
4
DA4~0
DB4~0
DC4~0
5
2
1 (T)
LSB
n-7
odd
MSB
13
LSB
n-6
even
MSB
LSB
n-6
odd
MSB
13
LSB
MSB
LSB
n-5
n-5
even 0.5*DVDD odd
MSB
n-4
even
Detailed Timing Diagrams in 4 channel, 6 channel modes
MS1513-E-00
2013/02
19
ASAHI KASEI
[AK8448]
„ Timing Diagrams(5): ADCK frequency = A/D conversion rate mode ( 10 Bit-wide output )
z
1 channel mode ( DC direct-coupled mode, positive polarity )
Please refer to Switching Characteristics 1 table.
CCDIN0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADCK
SHR
SHD
DA4~0
(D9~5)
DB4~0
(D4~0)
MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB
0
1
2
3
4
LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB
0
1
2
3
4
DC4~0
8.5 ADCK cycles
(Pipeline Delay)
Timing Diagrams in 1 channel mode
CCDIN0
12
n-1
n
n+1
n+2
n+3
SHR
10
9
SHD
8
6
0.5*AVDD
ADCK
4
DA4~0
(D9~5)
DB4~0
(D4~0)
3
5
2
1 (T)
n-11
13
n-10
n-9
n-8
n-7
0.5*DVDD
Detailed Timing Diagrams in 1 channel mode
MS1513-E-00
2013/02
20
ASAHI KASEI
[AK8448]
„ Timing Diagrams(6): ADCK frequency = A/D conversion rate mode ( 10 Bit-wide output )
z
1 channel mode ( CDS mode & Clamp mode, negative polarity )
Please refer to Switching Characteristics 2 table.
CCDIN0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADCK
SHR
SHD
DA4~0
(D9~5)
DB4~0
(D4~0)
MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB
4
0
1
2
3
LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB
4
0
1
2
3
DC4~0
8.5 ADCK cycles
(Pipeline Delay)
Timing Diagrams in 1 channel mode
11
12
CCDIN0
n-1
n
n+1
n+2
n+3
SHR
6
7
10
9
SHD
8
6
0.5*AVDD
ADCK
4
DA4~0
(D9~5)
DB4~0
(D4~0)
3
5
2
1 (T)
n-11
13
n-10
n-9
n-8
n-7
0.5*DVDD
Detailed Timing Diagrams in 1 channel mode
MS1513-E-00
2013/02
21
ASAHI KASEI
[AK8448]
„ Timing Diagrams(7): ADCK frequency = A/D conversion rate mode ( 10 Bit-wide output )
z
2 channel mode ( DC direct-coupled mode, positive polarity )
Please refer to Switching Characteristics 1 table.
CCDIN0
CCDIN2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADCK
SHR
SHD
DA4~0
(D9~5)
DB4~0
(D4~0)
DC4~0
0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2
MSB
4
0
1
2
3
0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2
LSB
0
1
2
3
4
CCDIN0
CCDIN2
9 ADCK cycles
(Pipeline Delay)
Timing Diagrams in 2 channel mode
CCDIN0
CCDIN2
n-2
n-1
12
n
n+1
SHR
10
9
SHD
6
8
ADCK
4
DA4~0
(D9~5)
DB4~0
(D4~0)
3
5
2
0.5*AVDD
1 (T)
2
13
2
0
n-12
0
2
n-11
0
13
2
n-10
0.5*DVDD
0
2
n-9
CCDIN0
0
n-8
CCDIN2
Detailed Timing Diagrams in 2 channel mode
MS1513-E-00
2013/02
22
ASAHI KASEI
[AK8448]
„ Timing Diagrams(8): ADCK frequency = A/D conversion rate mode ( 10 Bit-wide output )
z
2 channel mode ( CDS mode & Clamp mode, negative polarity )
Please refer to Switching Characteristics 2 table.
CCDIN0
CCDIN2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADCK
SHR
SHD
DA4~0
(D9~5)
DB4~0
(D4~0)
DC4~0
0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2
MSB
4
0
1
2
3
0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2
LSB
0
1
2
3
4
CCDIN0 CCDIN2
9 ADCK cycles
(Pipeline Delay)
Timing Diagrams in 2 channel mode
11
CCDIN0
CCDIN2
n-2
n-1
n
12
n+1
SHR
6
7
10
9
SHD
6
8
ADCK
4
DA4~0
(D9~5)
DB4~0
(D4~0)
3
5
2
0.5*AVDD
1 (T)
2
0
13
2
n-12
0
2
n-11
0
13
2
n-10
0.5*DVDD
0
2
n-9
CCDIN0
0
n-8
CCDIN2
Detailed Timing Diagrams in 2 channel mode
MS1513-E-00
2013/02
23
ASAHI KASEI
[AK8448]
„ Timing Diagrams(9): ADCK frequency = A/D conversion rate mode ( 10 Bit-wide output )
z
4 channel mode ( DC direct-coupled mode, positive polarity )
Please refer to Switching Characteristics 1 table.
CCDINn
(n=0~3)
0
1
2
3
4
5
6
7
ADCK
SHR
SHD
DA4~0
(D9~5)
DB4~0
(D4~0)
0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2
1
1
0
0
2
MSB
0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2
0
0
1
1
2
LSB
DC4~0
9 ADCK cycles
(Pipeline Delay)
Timing Diagrams in 4 channel mode
CCDINn
(n=0~3)
n-1
12
n
n+1
SHR
10 9
15
SHD
8
6
0.5*AVDD
ADCK
4
DA4~0
(D9~5)
DB4~0
(D4~0)
3
5
2
1 (T)
3
n-7
0
13
2
1
3
n-6
0
13
2
0.5*DVDD
1
n-5
3
0
n-4
Detailed Timing Diagrams in 4 channel mode
MS1513-E-00
2013/02
24
ASAHI KASEI
[AK8448]
„ Timing Diagrams(10):ADCK frequency = A/D conversion rate mode ( 10Bit-wide output )
z
4 channel mode ( CDS mode & Clamp mode, negative polarity )
Please refer to Switching Characteristics 2 table.
CCDINn
(n=0~3)
0
1
2
3
4
5
6
7
ADCK
SHR
SHD
DA4~0
(D9~5)
DB4~0
(D4~0)
0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2
1
1
0
0
2
MSB
0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2
0
0
1
1
2
LSB
DC4~0
9 ADCK cycles
(Pipeline Delay)
Timing Diagrams in 4 channel mode
CCDINn
(n=0~3)
n-1
12
n
9
n+1
SHR
6
7
10
9
15
SHD
6
8
0.5*AVDD
ADCK
4
DA4~0
(D9~5)
DB4~0
(D4~0)
3
5
2
13
1 (T)
3
n-7
0
2
1
3
n-6
0
13
2
0.5*DVDD
1
n-5
3
0
n-4
Detailed Timing Diagrams in 4 channel mode
MS1513-E-00
2013/02
25
ASAHI KASEI
[AK8448]
„ Timing Diagrams(11): ADCK frequency = total pixel rate mode ( 10 Bit-wide output )
2 channel mode ( DC direct-coupled mode, positive polarity )
z
Please refer to Switching Characteristics 3 table.
CCDINn
(n=0,2)
0
1
2
3
4
5
6
7
8
9
10
11
ADCK
SHR
SHD
Internal
A/D Clock
DA4~0
(D9~5)
DB4~0
(D4~0)
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
MSB
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
LSB
CCDIN0
DC4~0
2
0
1
2
0
1
0
2
0
0
CCDIN2
20 ADCK cycles
(Pipeline Delay)
Timing Diagrams in 2 channel mode
CCDIN0
CCDIN2
n-2
n-1
12
n
n+1
SHR
10
9
SHD
8
6
0.5*AVDD
ADCK
4 3 52
1 (T)
Internal
A/D Clock
DA4~0
(D9~5)
DB4~0
(D4~0)
13
0.5*DVDD
2
0
2
n-13
0
2
n-12
0
2
n-11
0
2
n-10
0
n-9
Detailed Timing Diagrams in 2 channel mode
MS1513-E-00
2013/02
26
ASAHI KASEI
[AK8448]
„ Timing Diagrams(12): ADCK frequency = total pixel rate mode ( 10 Bit-wide output )
2 channel mode ( CDS mode & Clamp mode, negative polarity )
z
Please refer to Switching Characteristics 4 table.
CCDINn
(n=0,2)
0
1
2
3
4
5
6
7
8
9
10
11
ADCK
SHR
SHD
Internal
A/D Clock
DA4~0
(D9~5)
DB4~0
(D4~0)
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
0
2
MSB
2
0
2
0
2
0
2
0
2
0
2
0
2
CCDIN0
2
0
1
2
0
1
0
2
0
2
0
2
0
2
0
2
LSB
DC4~0
0
0
0
CCDIN2
20 ADCK cycles
(Pipeline Delay)
Timing Diagrams in 2 channel mode
11
CCDIN0
CCDIN2
n-3
n-2
n-1
12
n
n+1
SHR
7
6
10
9
SHD
8
6
0.5*AVDD
ADCK
4 3 52
1 (T)
Internal
A/D Clock
DA4~0
(D9~5)
DB4~0
(D4~0)
13
0.5*DVDD
2
0
2
n-13
0
2
n-12
0
2
n-11
0
2
n-10
0
n-9
Detailed Timing Diagrams in 2 channel mode
MS1513-E-00
2013/02
27
ASAHI KASEI
[AK8448]
„ Timing Diagrams(13): ADCK frequency = total pixel rate mode ( 10 Bit-wide output )
3 channel mode ( DC direct-coupled mode, positive polarity )
z
Please refer to Switching Characteristics 3 table.
CCDINn
(n=0,2,4)
0
1
2
3
4
5
6
7
8
9
10
11
ADCK
SHR
SHD
Internal
A/D Clock
DA4~0
(D9~5)
DB4~0
(D4~0)
2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0
0
1
MSB
2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0
0
1
LSB
CCDIN0
DC4~0
CCDIN4
CCDIN2
30 ADCK cycles
(Pipeline Delay)
Timing Diagrams in 3 channel mode
CCDINn
(n=0,2,4)
n-1
n
n+1
12
SHR
10
8
9
SHD
6
1 (T)
0.5*AVDD
ADCK
4 3 5 2
Internal
A/D clock
DA4~0
(D9~5)
DB4~0
(D4~0)
13
0
2
n-12
4
0
0.5*DVDD
2
4
n-11
0
2
n-10
4
0
2
n-9
Detailed Timing Diagrams in 3 channel mode
MS1513-E-00
2013/02
28
ASAHI KASEI
[AK8448]
„ Timing Diagrams(14): ADCK frequency = total pixel rate mode ( 10 Bit-wide output )
3 channel mode ( CDS mode & Clamp mode, negative polarity )
z
Please refer to Switching Characteristics 4 table.
CCDINn
(n=0,2,4)
0
1
2
3
4
5
6
7
8
9
11
10
ADCK
SHR
SHD
Internal
A/D Clock
DA4~0
(D9~5)
DB4~0
(D4~0)
0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4
MSB
0
0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4 0 2 4
CCDIN0
DC4~0
LSB
CCDIN4
CCDIN2
0
30 ADCK cycles
(Pipeline Delay)
Timing Diagrams in 3 channel mode
12
CCDINn
n
n-1
(n=0,2,4)
n+1
9
SHR
7
6
10
9
8
SHD
6
1 (T)
0.5*AVDD
ADCK
4 3 5 2
Internal
A/D Clock
DA4~0
(D9~5)
DB4~0
(D4~0)
13
0.5*DVDD
0
2
4
0
2
4
0
2
4
n-10
n-11
0
2
n-9
Detailed Timing Diagrams in 3 channel mode
MS1513-E-00
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29
ASAHI KASEI
[AK8448]
„ Timing Diagrams(15): ADCK frequency = total pixel rate mode ( 10 Bit-wide output )
4 channel mode ( DC direct-coupled mode, positive polarity )
z
Please refer to Switching Characteristics 3 table.
CCDINn
(n=0~3)
0
1
2
3
4
5
ADCK
SHR
SHD
Internal
A/D Clock
DA4~0
(D9~5)
3
DB4~0
(D4~0)
3
0
2
1
3
0
2
1
3
0
2
1
3
0
2
1
3
0
2
1
3
0
MSB
0
2
1
3
0
2
1
CCDIN0
DC4~0
3
0
2
1
LSB
2
0
3
0
2
1
3
0
2
1
3
0
2
0
CCDIN3
CCDIN2
CCDIN1
20 ADCK cycles
(Pipeline Delay)
Timing Diagrams in 4 channel mode
CCDINn
(n=0~3)
10
n
SHR
n+1
10
9
8
15
SHD
6
1 (T)
0.5*AVDD
ADCK
43 5 2
Internal
A/D Clock
DA4~0
(D9~5)
DB4~0
(D4~0)
13
0
n-6
2
1
3
0.5*DVDD
0
2
1
n-5
3
0
2
n-4
Detailed Timing Diagrams in 4 channel mode
MS1513-E-00
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30
ASAHI KASEI
[AK8448]
„ Timing Diagrams(16): ADCK frequency = total pixel rate mode ( 10 Bit-wide output )
4 channel mode ( CDS mode & Clamp mode, negative polarity )
z
Please refer to Switching Characteristics 4 table.
CCDINn
(n=0~3)
0
1
2
3
4
5
ADCK
SHR
SHD
Internal
A/D Clock
DA4~0
(D9~5)
3
DB4~0
(D4~0)
3
0
2
1
3
0
2
1
3
0
2
1
3
0
2
1
3
0
2
1
3
0
MSB
0
2
1
3
0
2
1
3
0
2
1
3
0
2
1
3
0
2
1
LSB
CCDIN0
DC4~0
2
0
3
0
2
0
CCDIN3
CCDIN2
CCDIN1
20 ADCK cycles
(Pipeline Delay)
Timing Diagrams in 4 channel mode
CCDINn
(n=0~3)
12
n
n+1
7 11
SHR
6
10
8 9
15
SHD
6
1 (T)
0.5*AVDD
ADCK
43 5 2
Internal
A/D Clock
DA4~0
(D9~5)
DB4~0
(D4~0)
13
0
n-6
2
1
3
0
2
n-5
1
3
0
2
n-4
Detailed Timing Diagrams in 4 channel mode
MS1513-E-00
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31
ASAHI KASEI
[AK8448]
„ Timing Diagrams(17): ADCK frequency = total pixel rate mode ( 10 Bit-wide output )
6 channel mode ( DC direct-coupled mode, positive polarity )
z
Please refer to Switching Characteristics 3 table.
-CCDINn
(n=0~5)
0
1
2
3
4
5
ADCK
SHR
SHD
Internal
A/D Clock
DA4~0
(D9~5)
DB4~0
(D4~0)
3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 5 1 3 5 0 2 4 1
MSB
0
3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1
LSB
CCDIN0
DC4~0
CCDIN4
CCDIN2
0
CCDIN3
CCDIN1
CCDIN5
30 ADCK cycles
(Pipeline Delay)
Timing Diagrams in 6 channel mode
CCDINn
(n=0~5)
SHR
n+2
n+1
n
12
10
8
9
15
SHD
6
1 (T)
ADCK
3
0.5*AVDD
2
4
5
Internal
A/D Clock
13
DA4~0
(D9~5)
DB4~0
(D4~0)
0
n-6
2
4
1
3
5
0
0.5*DVDD
2
4
n-5
1
3
5
0
2
4
n-4
1
3
5
0
2
n-3
Detailed Timing Diagrams in 6 channel mode
MS1513-E-00
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32
ASAHI KASEI
[AK8448]
„ Timing Diagrams(18): ADCK frequency = total pixel rate mode ( 10 Bit-wide output )
6 channel mode ( CDS mode & Clamp mode, negative polarity )
z
Please refer to Switching Characteristics 4 table.
-CCDINn
(n=0~5)
0
1
2
3
4
5
ADCK
SHR
SHD
Internal
A/D Clock
DA4~0
(D9~5)
DB4~0
(D4~0)
3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1
MSB
0
3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1
LSB
CCDIN0
DC4~0
CCDIN4
CCDIN2
0
CCDIN3
CCDIN1
CCDIN5
30 ADCK cycles
(Pipeline Delay)
Timing Diagrams in 6 channel mode
12
CCDINn
(n=0~5)
n-1
n
9
n+1
n+2
7
SHR
10
6
8
9
15
SHD
6
1 (T)
ADCK
3
0.5*AVDD
2
4
5
Internal
A/D Clock
DA4~0
(D9~5)
DB4~0
(D4~0)
13
0
n-6
2
4
1
3
5
0
2
4
0.5*DVDD n-5
1
3
5
0
2
n-4
4
1
3
5
0
2
n-3
Detailed Timing Diagrams in 6 channel mode
MS1513-E-00
2013/02
33
ASAHI KASEI
[AK8448]
„ Switching Characteristics : Serial I / F
Parameter
Clock Cycle
Clock Pulse Width
( “ H “ period )
Clock Pulse Width
( “ L “ period )
Set-up Time
( time to SDCLK )
Hold Time
( time from SDCLK )
Rise Time of SDCLK,
SDENB
Fall Time of SDCLK,
SDENB
SDENB High Level Pulse
Width
Data delay time
( time from SDCLK )
Data Hold Time
( time from SDENB )
Number of Serial Data
( AVDD = 3.0 ~ 3.6 V, DVDD = 3.0 ~ 3.6 V, Ta = 0 ~ 70 °C)
Pin
Min.
Typ. Max. Unit
Condition
Symb
ol
Scyc
Shi
SDCLK
SDCLK
40
MHz
ns
Slo
SDCLK
40
ns
Ssu
20
ns
20
ns
Sdw
SDIN
SDENB
SDIN
SDENB
SDCLK
SDENB
SDCLK
SDENB
SDENB
Sdly
SDOUT
Shld
SDOUT
Snum
SDCLK
Sh
Sr
Sf
10
SDCLK
Ssu
6
ns
0.3 AVDD
→0.7 AVDD
0.3 AVDD
→0.7 AVDD
ns
30
0
ns
ns
16
Scyc
Slo
Shi
1
ns
40
Scyc
Slo
6
2
15
16
Shi
1
Sh
Ssu
2
8
9
10
16
Sh
SDIN
SDOUT
Ssu
High-Z
Sh Sdw
Ssu
High-Z
Shld
Sdly
SDENB
Sh
Sdw
Figure 2
Write to AK8448
Read from AK8448
MS1513-E-00
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34
ASAHI KASEI
[AK8448]
Control Registers
Address
Data
(Hex)
Initial
D7
D6
D5
D4
D3
D2
D1
D0
ADCK
Power
Freq.
Down
(Hex)
0
00
Sensor
Interface Signal
Mode
1
00
Channel Number
Polarity
SHR
Output
Test
SHD
as
pattern
Data
Channel Channel Channel
Polarity
Power
output
Width
0 and 1
0
Output Order of Order of Order of
2 and 3
3 and 4
Down
2
80
Offset Data for CCDIN0
3
80
Offset Data for CCDIN1
4
80
Offset Data for CCDIN2
5
80
Offset Data for CCDIN3
6
80
Offset Data for CCDIN4
7
80
Offset Data for CCDIN5
8
00
PGA Gain Data for CCDIN0
9
00
PGA Gain Data for CCDIN1
A
00
PGA Gain Data for CCDIN2
B
00
PGA Gain Data for CCDIN3
C
00
PGA Gain Data for CCDIN4
D
00
PGA Gain Data for CCDIN5
E
08
TEST
F
00
TEST
In this data sheet, R0 indicates a register at address 0, for example.
R0, D0 description means, D0 bit of register at address 0.
Each bit of registers to be described in the following is set to a condition as noted to be default
after the reset.
…
R0 Register
„ R0, D7-D6
D7
0
0
1
Sensor I/F mode
D6
0
1
0
Sensor Interface Mode
DC direct-coupled ( default )
CDS
Clamp
MS1513-E-00
2013/02
35
ASAHI KASEI
[AK8448]
„ R0, D5
Signal polarity
D5
0
Signal
Polarity
Negative
1
Positive
„ R0, D4 ~ D2
D4
0
0
0
0
1
Sensor Type
Signal swings to low voltage side from the reference level. CCD
sensors etc. ( default )
Signal swings to high voltage side from the reference level. CIS
sensors etc.
Cannel Number
D3
0
0
1
1
0
D2
0
1
0
1
0
Cannel
Number
1( default )
2
3
4
6
0
{
{
{
{
{
1
{
{
CCDIN
2
3
{
{
{
{
{
{
4
{
{
5
{
{: denotes input channel( s ) to be used in the selected # of channel mode.
Un-used functional blocks, CDS, DAC, PGA and ADC are automatically powered-down.
No capacitor connection is required on CCDINn & REFINn pins for the un-used channels.
Those, un-used pins should be connected to AVSS.
„ R0, D1
ADCK Frequency
D1
0
1
ADCK Input Frequency
A/D Conversion Rate
( default )
Note
Either 5 Bit-wide or 10 Bit-wide output data is
output both at the rising edge and the falling
edge of ADCLK.
10 Bit-wide output data is output at the rising
edge of ADCK.
Total Pixel Rate
In the default mode, ADCK at the same frequency as ADC conversion rate should be
input.
ADC data is output both at the rising edge and the falling edge of ADCK.
In total pixel rate mode, ADCK at the same frequency as a total sum of pixel rate of
effective channels should be input. ADC data is output at the rising edge of ADCK.
„ R0, D0
D0
0
1
Power-Down
Operation
Normal Operation ( default )
Power-Down
In Power-down mode, clock feed to the Digital part is stopped while Analog part is
powered-down.
ADC data output conditions ( DA0 ~ DA4, DB0 ~ DB4, DC0 ~ DC4 ) at power-down can
be selected to be either fixed low or high-Z output by D6 bit of register R1.
MS1513-E-00
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36
ASAHI KASEI
…
[AK8448]
R1 Register
„ R1, D7
D7
0
1
SHR, SHD Polarity Select
Polarity
Active High ( default )
Active Low
All diagrams shown in this data sheet are when SHR and SHD polarities are set at
default conditions ( active high ).
„ R1, D6
D6
0
1
Output Conditions at Power-Down
Output conditions
Fixed to low ( default )
High Z
R1, D5 Test pattern output
D5
0
1
Output
Normal (default)
Test pattern output
10-bit increment pattern is outputted at test pattern output.
（0,1,2,3,･･･,1022,1023,0,1,2,3,･･･）
„ R1, D3
D3
0
1
Output Data width
Output Data width
5 Bit ( default )
10 Bit
When the setting of ADCK frequency is equal to total pixel rate mode ( R0, D1 = 1 ),
output data is output in 10 Bit-wide mode, regardless of output data width setting.
MS1513-E-00
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37
ASAHI KASEI
[AK8448]
„ R1, D2-D0
Channel Processing Order
D2
0
1
Channels 0, 1 Processing Order
CCDIN0 → CCDIN1 → CCDIN0 → CCDIN1 ( default )
CCDIN1 → CCDIN0 → CCDIN1 → CCDIN0 …
D1
0
1
Channels 2, 3 Processing Order
CCDIN2 → CCDIN3 → CCDIN2 → CCDIN3 ( default )
CCDIN3 → CCDIN2 → CCDIN3 → CCDIN2 …
D0
0
1
Channels 4, 5 Processing Order
CCDIN4 → CCDIN5 → CCDIN4 → CCDIN5 ( default )
CCDIN5 → CCDIN4 → CCDIN5 → CCDIN4 …
This is to select the processing order of corresponding input channel pair of the selected,
single ADC. Processing order can be individually set at every pair.
This register is valid either in 4 channel mode / 5 Bit-wide output or 6 channel mode / 5
Bit-wide output.
All diagrams shown in this data sheet are when the channel processing order is set at
default condition.
MS1513-E-00
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38
ASAHI KASEI
…
[AK8448]
R2~R7 Registers
„ D7-D0
Offset Data
D7-D0
( Straight Binary )
11111111
11111110
:
10000001
10000000 ( default )
01111111
:
00000001
00000000(Inhibition)
Offset ( x) =
Offset Voltage
−298.7mV
-296.3mV
:
−2.4mV
0mV
2.4mV
:
298.7mV
(298.7mV)
298.7
× (128 − x) mV
127
At Negative Mode
At Positive
Mode
Maximum Shift to Maximum Shift to
Black level side
White Level Side
( ADC code small )
( ADC code large )
↑
|
|
|
|
↓
Maximum Shift to
Black Level Side
( ADC code small )
Maximum Shift to
White Level Side
( ADC code large )
0≤ x ≤255
Default x=128
…
R8~RD Registers
„ D7-D0
PGA Gain Data
Setting code and gain ( ideal value ) relation is expressed in the following equation.
Gain( x) =
2 × 208
Where x is register set value ( 0 < = x < = 255 )
33.3 + 255 − x
At default
x=0
0.12
20
18
0.1
16
Gain Ste p[dB]
Gain[dB]
14
12
10
8
6
4
0.08
0.06
0.04
0.02
2
0
0
0
64
128
192
256
0
64
Figure 3
128
192
256
Code
Code
PGA Gain Curves ( ideal values )
MS1513-E-00
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39
ASAHI KASEI
[AK8448]
Operations
„ Sensor I/F Mode
AK8448 has three sensor interface modes: CDS, Clamp and DC connect. The sensor
interface mode is selected by Sensor Interface Mode register R0, D7~D6.
CDS mode
z
A mode to process the difference Vpix as its pixel level which is between the reference
level Vprec of each pixel from the sensor output signal and its data level Vdata.
Reference level of the sensor signal is sampled at SHR and data level of the sensor
signal is sampled at SHD respectively.
Sampling point is at the falling edge of SHR and SHD respectively.
When polarity of SHR and SHD is inverted by register ( R1, D7 = 1 ), the sampling point
becomes at the rising edge.
Vprec
CCDINn
Vpix
Vdata
SHR
SHD
CLPB
Low
Figure 4 CDS Mode Timing Outline
Clamp mode
z
A mode to process the difference Vpix as its pixel level which is between the internally
generated Clamp level Vclamp and data level Vdata of the sensor output signal.
Data level of the sensor signal is sampled at SHD.
Internal Clamp
Level
Vclamp
CCDINn
Vpix
Vdata
SHR
SHD
CLPB
Figure 5 Clamp Mode Timing Outline
MS1513-E-00
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40
ASAHI KASEI
[AK8448]
DC direct-coupled mode
z
A mode to process a difference Vpix as its pixel level which is between a reference level
fed on REFINn pin externally, and data level Vdata of the sensor output signal.
When no reference level exists in sensor output signal, this mode is used as an example.
Data level of the sensor signal is sampled at SHD. Since SHR is not used, connect it to
either Low or High.
Vdata
CCDINn
Vpix
REFINn(Input)
SHR
CLPB
Low( or High)
SHD
Figure 6 DC Direct-coupled Mode Timing Outline
MS1513-E-00
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41
ASAHI KASEI
[AK8448]
„ Clamp Operation
In CDS mode and Clamp mode, Clamping is made in order to adjust the reference DC
level of sensor signal to match the internal reference level of the AK8448.
Clamp operation is controlled by CLPB and SHR.
Clamp switch closes during CLPB = Low and SHR = High ( “ Low “ when SHR, SHD
polarities are inverted ), and CCDINn ( n = 0 ~ 5 ) pin signal is pulled toward the internal
clamp level.
REFINn ( n = 0 ~ 5 ) is also clamped in the same way.
In CDS mode, fix CLPB to low so that clamping is always enabled.
CCDINn Clamp Level
CLPB .AND. SHR
0: Open
1: Close
CCDINn
Sensor
CDS
(Sample
& Hold)
Figure 7 Clamp Circuit Outline
CCD
Effective Pixel
Optical Black
Effective Pixel
SHR
Clamp is active
CLPB
Internal Clamp Level
CCDINn
Pull in reference level to clamp level
Figure 8 Clamp Operation Timing Outline
MS1513-E-00
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42
ASAHI KASEI
[AK8448]
„ Signal Polarity
The AK8448 accepts both positive and negative input polarities.
Either signal polarity is selected by setting Signal Polarity register ( R0,D5 ) to meet
sensor types to be used.
In general, CCD exhibits negative polarity characteristics and CIS exhibits positive
polarity characteristics. Either polarity can be selected, regardless of sensor I/F mode
setting.
Negative polarity characteristics
z
Reference Level
Black (ADC code 000h
White (ADC code 3FFh
Data Level
Positive polarity characteristics
z
Data Level
White (ADC code 3FFh
Black (ADC code 000h
Reference Level
Figure 9 Signal Polarities
„ Output Data Control
ADC output data is output in either 5 Bit-wide or 10 Bit-wide by setting Data Width
register ( R1, D3 ).
When 5 Bit-wide data mode is selected, data is output on each of three 5 Bit buses –
DA4 ~ DA0, DB4 ~ DB0 and DC4 ~ DC0 respectively which correspond to each ADC.
When 10 Bit-wide data mode is selected, data is output on 10 pins – DA4 ( MSB ) ~ DA0
and DB4 ~ DB0 ( LSB ).
In 5 Bit-wide data mode, the upper 5 Bit of data is output at the rising edge of ADCK, and
the lower 5 Bit at the falling edge of ADCK.
In 10 Bit-wide data mode, two different channel data are output at the rising edge and at
the falling edge of ADCK respectively.
It is also possible to output data at only the falling edge of ADCK in 10 Bit-wide data
mode, by setting ADCK Frequency register ( R0, D1 ).
In this operation, it is required to input ADCK at the frequency of a total sum of pixel rate
of all channels ( total pixel rate ). Un-used buses DB4 ~ DB0 and DC4 ~ DC0 such as a
case in 1 channel mode with 5 Bit-wide output, will output Low levels.
MS1513-E-00
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43
ASAHI KASEI
[AK8448]
„ ADCK
A/D Conversion Rate mode and Total Pixel Rate mode
ADCK generates ADC conversion timing and ADC data output timing.
Whether to output data at both the rising edge and the falling edge of ADCK or to output
data at only the rising edge can be selected by ADCK Frequency mode register.
A/D conversion rate mode is a mode where data is output at both the rising edge and the
falling edge of ADCK.
In A/D conversion rate mode, input an ADCK clock of same frequency as ADC
conversion rate.
Total pixel rate mode is a mode where data is output at only the ADCK rising edge. In
this mode, input an ADCK clock of same frequency as a total sum of effective channels’
pixel rates.
For example, when to process a 20 MHz / channel sensor signal in 3 channel mode, a 20
MHz ADCK is input in A/D conversion rate mode which is equal to ADC conversion rate.
Maximum Conversion Rate
Maximum operating speed of ADC data output buffers DA0 ~ DA4, DB0 ~ DB4, DC0 ~
DC4 is designed to be 80 Mbps.
When a total pixel rate mode is selected as ADCK frequency mode, maximum sampling
rate per channel in 3 channel and 6 channel modes is limited by this output buffer speed.
For example, maximum conversion rate in 6 channel mode is 80 MSPS / 6 = 13.3 MSPS
per channel, and not 20 MSPS.
MS1513-E-00
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44
ASAHI KASEI
[AK8448]
Number of channels and its ADCK frequency, a possible data width combination and its
maximum conversion rate per channel are listed in the following table.
[CDS, Clamp mode]
# of
Channels
A/D Conversion Rate Mode
Maximum
5 bits
10 bits
Conversion
Width
Width Rate [SPS/CH]
Total Pixel Rate Mode
Maximum
5 bits
10 bits
Conversion
Width
Width
Rate
[SPS/CH]
1
{
{
40M
-
{Note1
40M
2
{
{
40M
-
{
40M
3
{
-
40M
-
{
26.6M
4
{
{
20M
-
{
20M
6
{
-
20M
-
{
13.3M
[DC Direct mode]
# of
Channels
A/D Conversion Rate Mode
Maximum
5 bits
10 bits
Conversion
Width
Width
Rate
[SPS/CH]
Total Pixel Rate Mode
Maximum
5 bits
10 bits
Conversion
Width
Width
Rate
[SPS/CH]
1
{
{
15M
-
{Note1
15M
2
{
{
15M
-
{
15M
3
{
-
15M
-
{
15M
4
{
{
15M
-
{
15M
6
{
-
15M
-
{
13.3M
Note1: A/D conversion rate mode and total pixel rate mode have same timing waveforms
in 1 channel / 10 Bit-wide output operation. Please use A/D conversion rate mode at the
default state.
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ASAHI KASEI
[AK8448]
„ SHR/SHD Polarity
CCDINn
SHR
Active High
(Default)
SHD
SHR
Active Low
SHD
SHR/SHD polarity can be changed by register R1 Register.
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ASAHI KASEI
Serial
[AK8448]
I/F
Write operation into and Read operation from Control registers are executed via a 4 –
wire Serial Interface.
SDIN data while SDENB is at low is taken at the rising edge of SDCLK.
When the starting bit of SDIN data is “ zero “, writing into register is made and when it is
“ one “, reading from register is made.
The second and the third bits ( C1, C0 ) correspond to CE1 and CE0 pin data
respectively and only when logical levels are at C1 = CE1 and C0 = CE0, either write in
or read out operation is enabled.
The fourth bit must be zero.
Bits from the fifth to the eighth are for register address. MSB is the fifth bit and LSB is the
eighth bit.
Bits from ninth to sixteenth are data for register. MSB ( = D7 ) is the ninth bit and LSB ( =
D0 ) is the sixteenth bit.
„ Reset
Register values at the power-up are indeterminate including registers for test.
In order to avoid test registers from disturbing normal operation, a reset should be made
right after the power-up.
When RESETB pin is set to low, each register is set to its default value while test
registers are set to necessary values for normal operation.
Low duration time of RESETB should be 100 ns and longer.
Return RESETB pin to high after the reset, and necessary value should be written to
each register. When reset is not made after power-up, write default values into test
registers.
„ Power-Down
The AK8448 enters power-down mode when operation mode register R0,D1 is set at “ 1
“. In power-down mode, supplying operation clock to Digital part is also stopped while
current supply to Analog part is ceased.
When returning to normal operation from power-down mode ( R0, D0 = 0 ), a wait time is
required so that VCOM ( reference voltage ) is stabilized to its normal voltage since
VCOM is made to 0 V at power-down.
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ASAHI KASEI
[AK8448]
Serial Interface
„ Writing into the AK8448
SDCLK
SDIN
W C1 C0 0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
High Z
SDOUT
SDENB
Figure 10 Write Into Register
„ Reading from the AK8448
SDCLK
SDIN
SDOUT
R C1 C0 0 A3 A2 A1 A0
High Z
D7 D6 D5 D4 D3 D2 D1 D0
SDENB
Figure 11 Read From Register
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ASAHI KASEI
[AK8448]
Package Outline Dimensions
1.60 Max
12.00±0.20
1.40±0.05
10.00
0.10±0.05
48
33
32
10.00
12.00±0.20
49
17
64
1
0.50
16
0.145±0.055
0.22±0.05
0.10 M
1.00
S
0°~7°
Unit: mm
0.60±0.15
0.10 S
Package Marking
( 1 ) Pin # 1 identifier (The chamfered corner indicates pin number 1)
( 2 ) Marketing code : AK8448VQ
( 3 ) Date code : xxxxxxx ( 7 digits )
Upper 4 digits : week code
Lower 3 bits : AKM’s control code
AK8448VQ
XXXXXXX
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ASAHI KASEI
[AK8448]
External Circuit Examples
1μF
1μF
0.1μF
0.1μF
0.1μF
0.1μF
1μF
1μF
0.1μF
0.1μF
0.1μF
0.1μF
AVSS
SDIN
AVDD
SDCLK
SDENB
CE0
CE1
AVSS
RESETB
AVDD
NC
TEST
10 kΩ±20%
SDOUT
NC
REFIN1
DA4
VCLP
DA3
VCOM
DA2
CCDIN2
DA1
REFIN2
DA0
REFIN3
DVDD
CCDIN3
DVSS
VRP
DB4
VRN
DB3
CCDIN4
DB2
REFIN4
DB1
REFIN5
DB0
CCDIN5
NC
DVSS
DC4
DC3
DC2
DC1
DC0
NC
AVSS
DVSS
CLPB
AVDD
ADCK
SHR
SHD
AVSS
AVDD
3.3V
DVDD
0.1μF
CCDIN1
AISET
0.1μF
0.1μF
REFIN0
AVSS
CCDIN0
0.1μF
AVDD
0.1μF
3.3V
0.1μF
0.1μF
8.2kΩ±1%
„ CDS Mode
0.1μF
0.1μF
DVDD
0.1μF
0.1μF
0.1μF
Above example is for reference. Please select optimum capacitor values for a target system.
Figure 12 CDS Mode
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ASAHI KASEI
[AK8448]
8.2kΩ±1%
1μF
3.3V
1μF
1μF
1μF
1μF
1μF
1μF
1μF
1μF
1μF
1μF
1μF
AVSS
SDIN
AVDD
SDCLK
SDENB
CE0
CE1
AVSS
RESETB
AVDD
NC
TEST
SDOUT
NC
DA4
VCLP
DA3
VCOM
DA2
CCDIN2
DA1
REFIN2
DA0
REFIN3
DVDD
CCDIN3
DVSS
VRP
DB4
VRN
DB3
CCDIN4
DB2
REFIN4
DB1
REFIN5
DB0
CCDIN5
NC
DVSS
DC4
DC3
DC2
DC1
DC0
NC
AVSS
DVSS
CLPB
AVDD
ADCK
SHR
SHD
AVSS
AVDD
10 kΩ±20%
REFIN1
DVDD
1μF
CCDIN1
AISET
1μF
1μF
REFIN0
AVSS
AVDD
0.1μF
CCDIN0
1μF
0.1μF
3.3V
0.1μF
„ Clamp Mode
0.1μF
0.1μF
DVDD
0.1μF
0.1μF
0.1μF
Above example is for reference. Please select optimum capacitor values for a target system.
Figure 13 Clamp Mode
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ASAHI KASEI
[AK8448]
8.2kΩ±1%
3.3V
1μF
1μF
0.1μF
0.1μF
1μF
1μF
0.1μF
0.1μF
AVSS
SDIN
AVDD
SDCLK
SDENB
CE0
CE1
AVSS
AVDD
NC
AISET
10 kΩ±20%
SDOUT
NC
REFIN1
DA4
VCLP
DA3
VCOM
DA2
CCDIN2
DA1
REFIN2
DA0
REFIN3
DVDD
CCDIN3
DVSS
VRP
DB4
VRN
DB3
CCDIN4
DB2
REFIN4
DB1
REFIN5
DB0
CCDIN5
NC
DVSS
DC4
DC3
DC2
DC1
DC0
NC
DVDD
AVSS
DVSS
CLPB
AVDD
ADCK
SHR
SHD
AVSS
AVDD
RESETB
CCDIN1
0.1μF
TEST
AVSS
REFIN0
AVDD
0.1μF
CCDIN0
0.1μF
0.1μF
3.3V
0.1μF
„ DC Direct-coupled Mode
0.1μF
0.1μF
DVDD
0.1μF
0.1μF
0.1μF
Above example is for reference. Please select optimum capacitor values for a target system.
Figure 14 DC Direct-Coupled Mode
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ASAHI KASEI
[AK8448]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales
office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current
status of the products.
z AKM assumes no liability for infringement of any patent, intellectual property, or other rights in
the application or use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export
license or other official approval under the law and regulations of the country of export
pertaining to customs and tariffs, currency exchange, or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any
safety, life support, or other hazard related device or systemNote2), and AKM assumes no
responsibility for such use, except for the use approved with the express written consent by
Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or damage
to person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of,
or otherwise places the product with a third party, to notify such third party in advance of the
above content and conditions, and the buyer or distributor agrees to assume any and all
responsibility and liability for and hold AKM harmless from any and all claims arising from the
use of said product in the absence of such notification.
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