AK1547

[AK1547]
AK1547
4GHz Low Noise Integer-N Frequency Synthesizer
1. Overview
The AK1547 is an Integer-N PLL (Phase Locked Loop) frequency synthesizer, covering a wide range of frequency
from 500MHz to 4GHz. Consisting of a highly accurate charge pump, a reference divider, a programmable divider
and a dual-modulus prescaler (P/P+1), this product provides high performance, very low Phase Noise and small
footprints.
An ideal PLL can be achieved by combining the AK1547 with the external loop filter and VCO (Voltage Controlled
Oscillator). Access to the registers is controlled via a 3-wire serial interface. The operating supply voltage is from
2.7V to 5.5V, and the charge pump circuit and the serial interface can be driven by individual supply voltage.
2. Features

Operating frequency :
500MHz to 4GHz

Programmable charge pump current :
650A to 5200A typical with 8steps
The current range can be controlled by an external resistor.

Fast lock mode for improved lock time :
The programmable timer can switch two charge pump
current setting.

Supply Voltage :
2.7 to 5.5 V (PVDD, AVDD pins)

Separate Charge Pump Power Supply :
PVDD to 5.5V (CPVDD pin)

Excellent Phase Noise :
-218dBc/Hz

On-chip lock detection feature of PLL :
Selectable Phase Frequency Detector (PFD) Output or
Digital filtered lock detect

Package :
20pin QFN (0.5mm pitch, 4mm4mm0.75mm)

Operating temperature :
-40°C to 85°C
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[AK1547]
- Table of Contents -
1.
Overview __________________________________________________________________________ 1
2.
Features ___________________________________________________________________________ 1
3.
Block Diagram ______________________________________________________________________ 3
4.
Pin Functional Description and Assignments ____________________________________________ 4
5.
Absolute Maximum Ratings ___________________________________________________________ 6
6.
Recommended Operating Range ______________________________________________________ 6
7.
Electrical Characteristics _____________________________________________________________ 7
8.
Block Functional Descriptions ________________________________________________________ 11
9.
Register Map ______________________________________________________________________ 17
10.
Function Description - Registers _____________________________________________________ 19
11.
IC Interface Schematic ______________________________________________________________ 28
12.
Recommended Connection Schematic of Off-Chip Component ____________________________ 30
13.
Power-Up Timing Chart (Recommended Flow) __________________________________________ 32
14.
Frequency setting Timing Chart (Recommended Flow) ___________________________________ 33
15.
Typical Evaluation Board Schematic __________________________________________________ 34
16.
Outer Dimensions __________________________________________________________________ 35
17.
Marking __________________________________________________________________________ 36
In this specification, the following notations are used for specific signal and register names.
[Name]
: Pin name
<Name> : Register group name (Address name)
{Name}
: Register bit name
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VBG
BIAS
R COUNTER
14 bit
REFIN
CPVSS
CPVDD
NC
PVDD
PVSS
AVDD
NC
AVSS
3. Block Diagram
PHASE
FREQENCY
DETECTOR
CHARGE
PUMP
CP
CLK
REGISTER
24 bit
DATA
LE
LOCK DETECT
SWALLOW
COUNTER
6 bit
FAST
COUNTER
PROGRAMABLE
COUNTER
13 bit
N DIVIDER
RFINN
-
8/9,16/17,32/33,64/65
LD
PDN
PRESCALER
TEST2
+
TEST1
RFINP
Fig. 1 Block Diagram
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4. Pin Functional Description and Assignments
Table 1 Pin Functions
Power down
(Note 1)
No.
Name
I/O
1
CPVSS
G
Charge pump ground
2
TEST1
DI
Test pin 1
3
AVSS
G
Analog ground
4
RFINN
AI
Complementary input to the RF Prescaler
5
RFINP
AI
Input to the RF Prescaler
6
AVDD
P
Power supply for analog blocks
7
NC
8
REFIN
AI
Reference signal input
9
PVSS
G
Peripherals ground
10
TEST2
DI
Test pin 2
Internal pull-down,
Schmidt trigger input
11
PDN
DI
Power down
Schmidt trigger input
12
CLK
DI
Serial clock input
Schmidt trigger input
13
DATA
DI
Serial data input
Schmidt trigger input
14
LE
DI
Load enable input
Schmidt trigger input
15
LD
DO
Lock detect output
16
PVDD
P
Power supply for peripherals
17
NC
18
CPVDD
P
Power supply for charge pump
19
BIAS
AIO
Resistance pin for setting charge pump current
20
CP
AO
Charge pump output
Note 1)
Pin Functions
Remarks
Internal pull-down,
Schmidt trigger input
“Low”
“Hi-Z”
“Power Down” means the state of [PDN]=”Low” after power on.
The following table shows the meaning of abbreviations used in the “I/O” column.
AI: Analog input pin
AO: Analog output pin
AIO: Analog I/O pin
DO: Digital output pin
P: Power supply pin
G: Ground pin
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DI: Digital input pin
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[AK1547]
CP
BIAS
CPVDD
NC
PVDD
2. Pin Assignments
20
19
18
17
16
CPVSS
1
15 LD
TEST1
2
14 LE
AVSS
3
TOP
13 DATA
VIEW
RFINP
5
11 PDN
NC
7
AVDD
6
8
9
10
TEST2
12 CLK
PVSS
4
REFIN
RFINN
20pin QFN (0.5mm pitch, 4mm4mm)
Fig. 2
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Pin Assignments
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5. Absolute Maximum Ratings
Table 2 Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Unit
Remarks
VDD1
-0.3
6.5
V
[AVDD], [PVDD] (Note 1)
VDD2
-0.3
6.5
V
[CPVDD] (Note 1)
VSS1
0
0
V
[AVSS], [PVSS]
VSS2
0
0
V
[CPVSS]
Analog Input Voltage
VAIN
VSS1-0.3
VDD1+0.3
V
[RFINN], [RFINP], [REFIN] (Notes 1 & 2)
Digital Input Voltage
VDIN
VSS1-0.3
VDD1+0.3
V
Supply Voltage
Ground Level
[CLK], [DATA], [LE], [PDN], [TEST1],
[TEST2] (Notes 1 & 2)
Input Current
IIN
-10
10
mA
Storage Temperature
Tstg
-55
125
°C
Note 1)
0V reference for all voltages.
Note 2)
Maximum must not be over 6.5V.
Exceeding these maximum ratings may result in damage to the AK1547. Normal operation is not guaranteed at
these extremes.
6. Recommended Operating Range
Table 3 Recommended Operating Range
Parameter
Operating Temperature
Symbol
Min.
Ta
-40
VDD1
2.7
VDD2
VDD1
Typ.
5.0
Max.
Unit
Remarks
85
C
5.5
V
Applied to the [AVDD],[PVDD] pins
5.5
V
Applied to the [CPVDD] pin
Supply Voltage
Note 1)
VDD1 and VDD2 can be driven individually within the Recommended Operating Range.
Note 2)
All specifications are applicable within the Recommended Operating Range (operating temperature /
supply voltage).
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7. Electrical Characteristics
1. Digital DC Characteristics
Table 4 Digital DC Characteristics
Parameter
Symbol
Conditions
Min.
High level input voltage
Vih
Low level input voltage
Vil
High level input current 1
Iih1
Vih = VDD1=5.5V
-1
High level input current 2
Iih2
Vih = VDD1=5.5V
27
Low level input current
Iil
Vil = 0V, VDD1=5.5V
-1
High level output voltage
Voh
Ioh = -500A
Low level output voltage
Vol
Iol = 500A
Max.
55
0.2VDD1
V
Note 1)
1
A
Note 2)
110
A
Note 3)
1
A
Note 1)
V
Note 4)
V
Note 4)
0.4
Note 2)
Applied to the [CLK], [DATA], [LE] and [PDN] pins.
Note 3)
Applied to the [TEST1] and [TEST2] pins.
Note 4)
Applied to the [LD] pin.
7
Remarks
Note 1)
VDD1-0.4
Applied to the [CLK], [DATA], [LE], [PDN], [TEST1] and [TEST2] pins.
Unit
V
0.8VDD1
Note 1)
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2. Serial Interface Timing
<Write-In Timing>
Tlesu Tle
Tc s u
LE
(Input)
Tc h Tc l
CLK
(Input)
Ts u T h d
DATA
(Input)
D21
D2
D20
Fig. 3
D1
D0
A1
A0
Serial Interface Timing Chart
Table 5 Serial Interface Timing
Parameter
Symbol
Min.
Typ.
Max.
Unit
Clock L level hold time
Tcl
25
ns
Clock H level hold time
Tch
25
ns
Clock setup time
Tcsu
10
ns
Data setup time
Tsu
10
ns
Data hold time
Thd
10
ns
LE setup time
Tlesu
10
ns
LE pulse width
Tle
25
ns
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Remarks
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[AK1547]
3. Analog Circuit Characteristics
The resistance of 27kΩ is connected to the [BIAS] pin.
VDD1=2.7V to 5.5V, VDD2=VDD1 to 5.5V, –40°C≤Ta≤85°C, unless otherwise specified.
Parameter
Min.
Typ.
Max.
Unit
Remarks
RF Characteristics
Input Sensitivity
-10
0
dBm
Input Frequency
500
4000
MHz
REFIN Characteristics
Input Sensitivity
0.4
VDD1
Vpp
Input Frequency
5
104
MHz
125
MHz
55
MHz
Maximum Allowable Prescaler Output
Frequency
Phase Detector
Phase Detector Frequency
Charge Pump
Charge Pump Maximum Value
5200
A
Charge Pump Minimum Value
650
A
Icp TRI-STATE Leak Current
1
nA
0.6≤Vcpo≤VDD2-0.7, Ta=25°C
Mismatch between Source and Sink Currents
(Note 1)
10
%
Vcpo=VDD2/2, Ta=25°C
Icp vs. Vcpo (Note 2)
15
%
0.5≤Vcpo≤VDD2-0.5, Ta=25°C
10
A
[PDN]=“0” or {PD1}=1
Current Consumption
IDD1
IDD2 (Note3, Note4)
12
18
mA
[PDN]=”1”, {PD1}=0, IDD for VDD1
IDD3 (Note3)
0.8
1.6
mA
[PDN]=”1”, {PD1}=0, IDD for VDD2
Note 1) Mismatch between Source and Sink Currents : [(|Isink|-|Isource|)/{(|Isink|+|Isource|)/2}]100 [%]
Note 2) See “Charge Pump Characteristics - Voltage vs. Current”. Vcpo is the output voltage at [CP].
Icp vs. Vcpo : [{1/2(|I1|-|I2|)}/{1/2(|I1|+|I2|)}]100 [%]
Note 3) When [PDN] = ”1” and {PD1}=0, the total power supply current of the AK1547 is “IDD2+IDD3+ Charge
pump current”.
Note 4) RFIN=4GHz,5dBm input, REFIN=100MHz, 10dBm input, PRESCALER=32,
Phase Detector Frequency=1MHz
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Resistance Connected to the BIAS Pin for Setting Charge Pump Output Current
Parameter
BIAS resistance
Min.
Typ.
Max.
Unit
22
27
33
kΩ
Remarks
Icp
I1
I2
I2
I1
Isink
Isource
0.5
CPVDD/2
CPVDD-0.5
Vcpo
Fig. 4
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Charge Pump Characteristics - Voltage (Vcpo) vs. Current (Icp)
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[AK1547]
8. Block Functional Descriptions
1. Frequency Setup
The following formula is used to calculate the frequency setting for the AK1547.
Frequency setting (external VCO output frequency) = FPFD  N
Where :
N
: Dividing number N = [ (P  B) + A ]
FPFD
: Phase detector frequency FPFD = [REFIN] pin input frequency / R counter dividing number
P
: Prescaler Value (See < Address2>:{Pre[1:0]})
B
: B (Programmable) counter value (See <Address1>:{B[12:0]})
A
: A (Swallow) counter value (See <Address1>:{A[5:0]})
Calculation example
The output frequency of external reference frequency oscillator is 10MHz, and FPFD is 200kHz and VCO
frequency is 2460MHz.
AK1547 setting :
R (Reference counter)=10000000/200000 = 50 (<Address0>:{R[13:0]}= “50”)
P=32 (<Address2>:{PRE[1:0]}=”10Bin”)
B=384 (<Address1>:{B[12:0]}=”384”)
A=12 (<Address1>:{A[5:0]}=”12”)
Frequency setting = 200kHz  [ (32384) + 12] = 2460MHz
Lower limit for setting consecutive dividing numbers
In AK1547, it is impossible to set consecutive dividing numbers below the lower limit. The lower limit, Nmin,
depends on the Prescaler setting, and can be calculated by the following formula;
2
Nmin=P -P
The dividing number below Nmin can’t be set for succession. For example, in the case of P=16, 240 and over
can be set as consecutive dividing number.
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2.Charge Pump, Loop Filter
The current setting of charge pump can switch with the built-in timer for Fast Lock.
Phase Detector
Loop Filter
up
R3
CP
VCO
C1
down
R2
C3
Timer
C2
Fig. 5
Loop Filter Schematic
The charge pump current for normal operation (CP1) is determined by the setting in {CP1[2:0]}, which is a 3-bit
address of {D[15:13]} in <Address2> and a value of the resistance connected to the [BIAS] pin. The charge pump
current for the Fast Lock Up mode operation (CP2) is determined by the setting in {CP2[2:0]}, which is a 3-bit
address of D[18:16] in <Address2> and a value of the resistance connected to the [BIAS] pin.
The following formula shows the relationship among the resistance value, the register setting and the electric
current value.
charge pump minimum current (Icp_min) [A] =17.46 / Resistance connected to the BIAS pin [Ω]
charge pump current (Icp) [A] = Icp_min [A]  ({CP1} or {CP2} setting +1)
The allowed value range for the resistance connected to the [BIAS] pin is from 22 to 33kΩ for both normal and
Fast Lock Up mode operations.
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3. Fast Lock Up Mode
Setting {FAST[1:0]} in <Address2> to “11Bin” and {CPGAIN} in <Address1> to “1” enables the Fast Lock Up mode
for the AK1547.
The Fast Lock Up mode is enabled only during the time period set by the timer according to the counter value in
{TIMER[3:0]} in <Address2>. The charge pump current is set to the value specified by {CP2}. When the specified
time period elapses, the Fast Lock Up mode operation is switched to the normal operation. And {CPGAIN} in
<Address1> is reset to “0”.
{TIMER[3:0]} in <Address2> is used to set the time period for this mode. The following formula is used to calculate
the time period :
Switchover time = 1 / FPFD  Counter Value
Counter Value = 3 + (Timer[3:0] setting  4)
Fast Lock Up time
specified by the timer
Operation mode
Normal
Fast Lock Up
Normal
Charge pump current
CP1
CP2
CP1
Loop filter Switch
OFF
ON
OFF
Frequency setting (Write “1” into {CPGAIN} in <Address1>.)
Fig. 6
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Fast Lock Up Mode Timing Chart
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4.Lock Detect
Lock detect output can be selected by {LD[2:0]} in <Address2>. When {LD} is set to “101Bin", the phase detector
outputs an un-manipulated phase detection(comparison) result. (This is called “analog lock detect”.) When {LD} is
set to “001Bin”, the lock detect signal is output according to the on-chip logic. (This is called “digital lock detect”.)
The lock detect can be done as following (Case of R>1):
The [LD] pin is in unlocked state (which outputs “Low”) when a frequency setup is made.
In the digital lock detect, the [LD] pin outputs “High” (which means the locked state) when a phase error smaller
than a cycle of [REFIN] clock (T) is detected for N times consecutively. When a phase error larger than T is
detected for N times consecutively while the [LD] pin outputs “High”, then the [LD] pin outputs “Low” (which means
the unlocked state). The counter value N can be set by {LDP} in <Address0>. The N is different between
“unlocked to locked” and “locked to unlocked”.
Table 6 Lock Detect Precision
{LDP}
unlocked to locked
locked to unlocked
0
N=15
N=3
1
N=31
N=7
The lock detect signal is shown below:
Reference clock
PFD frequency signal
Divided clock of RF input signal
PFD output signal
This is ignored
because it cannot
be sampled.
ignored
Valid
Valid
ignored
The [LD] pin outputs “High” when
a phase error smaller than T is
detected for N times consecutively.
LD Output
Case of “R = 1”
Reference clock
PFD frequency signal
Divided clock of RF input signal
Valid
PFD output signal
This is ignored
because it cannot
be sampled.
ignored
Valid
ignored
The [LD] pin outputs HIGH when
a phase error smaller than T is
detected for N times consecutively.
LD Output
Case of “R > 1”
Fig. 7
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Digital Lock Detect Operations
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[AK1547]
Unlock ([LD]=Low)
Flag=0
Phase Error < T
No
Yes
Flag = Flag+1
No
Flag > N
Yes
Lock ([LD]=High)
Fig. 8 Unlock to Lock Operation Flow
Lock ([LD]=High)
PDN=0 or {PD1}=1
Flag=0
Phase Error > T
No
Yes
Flag = Flag+1
No
Flag > N
Yes
Unlock ([LD]=Low)
Fig. 9 Lock to Unlock Operation Flow
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5.Reference counter
The reference input can be set with a dividing number in the range of 1 to 16383 using {R [13:0]}, which is a 14-bit
address of {D[13:0]} in <Address0>. 0 cannot be set as a dividing number.
6.Prescaler
The dual modulus prescaler (P/P + 1) and the swallow counter are used to provide a large dividing ratio.
The prescaler is set by {PRE[1:0]}, which is a 2-bit latch of {D[21:20]} in <Address2>.
{PRE[1:0]}=”00Bin”, P=8, Dual modulus prescaler 8/9
{PRE[1:0]}=”01Bin”, P=16, Dual modulus prescaler 16/17
{PRE[1:0]}=”10Bin”, P=32, Dual modulus prescaler 32/33
{PRE[1:0]}=”11Bin”, P=64, Dual modulus prescaler 64/65
The Maximum Allowable Prescalor Output Frequency is 125MHz. “P” must be set as “RF Input Frequency/P≦
125MHz”.
7.Power-down and Power-save mode
It is possible to operate in the power-down or power-save mode if necessary by using the external control pin.
Power On
Follow the power-up sequence.
Normal Operation
Table 7 Power-down and Power-save mode
<Address2>
[PDN]
Function
{PD2}
{PD1}
“Low”
X
X
Power Down
“High”
X
0
Normal Operation
“High”
0
1
Asynchronous Power Down
“High”
1
1
Synchronous Power Down
X : Don’t care (“0” is recommended)
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9. Register Map
Name
Data
Address
R Counter
0
0
0
1
Function
1
0
Initialization
1
1
N Counter (A and B)
D21 - D0
Name
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Addr
ess
R
Count
0
0
0
LDP
0
0
0
0
R
[13]
R
[12]
R
[11]
R
[10]
R
[9]
R
[8]
R
[7]
R
[6]
R
[5]
R
[4]
R
[3]
R
[2]
R
[1]
R
[0]
0x0
N
Count
0
0
CP
GAIN
B
[12]
B
[11]
B
[10]
B
[9]
B
[8]
B
[7]
B
[6]
B
[5]
B
[4]
B
[3]
B
[2]
B
[1]
B
[0]
A
[5]
A
[4]
A
[3]
A
[2]
A
[1]
A
[0]
0x1
Func.
PRE
[1]
PRE
[0]
PD2
CP2
[2]
CP2
[1]
CP2
[0]
CP1
[2]
CP1
[1]
CP1
[0]
TIME TIME
R
R
[3]
[2]
TIME TIME
FAST FAST
R
R
[1]
[0]
[1]
[0]
CP
HiZ
CP
POLA
LD
[2]
LD
[1]
LD
[0]
PD1
CNTR
0x2
RST
Initial.
PRE
[1]
PRE
[0]
PD2
CP2
[2]
CP2
[1]
CP2
[0]
CP1
[2]
CP1
[1]
CP1
[0]
TIME TIME
R
R
[3]
[2]
TIME TIME
FAST FAST
R
R
[1]
[0]
[1]
[0]
CP
HiZ
CP
POLA
LD
[2]
LD
[1]
LD
[0]
PD1
CNTR
0x3
RST
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[AK1547]
Notes for writing into registers
After powers on AK1547, the initial registers value are not defined. It is required to write the data in all addresses
in order to commit it.
[Examples of writing into registers]
(Ex. 1) Power-On
-
Bring [PDN] to ”0 (Low)”
-
Apply VDD
-
Program Address0, Address1 and Address2 ({PD1}=”1” is recommended)
-
Bring [PDN] to ”1 (High)”
-
Program {PD1} in Address2 to “0”
(Ex. 2) Changing frequency settings : Initialization
-
Program Address3
-
Program Address1
(Ex. 3) Changing frequency settings : Counter reset
-
Program Address2.
-
Program Address1
-
Program Address2.
As part of this, load “1” to both {PD1} and {CNTR_RST}.
As part of this, load “0” to both {PD1} and {CNTR_RST}.
(Ex. 4) Changing frequency settings : PDN pin method
-
Bring [PDN] to ”0 (Low)”
-
Program Address1
-
Bring [PDN] to ”1 (High)”
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10. Function Description - Registers
< Address0 : R Counter >
D[21:19]
D18
D[17:14]
D[13:0]
Address
0
LDP
0
R[13:0]
00
D[21:19], D[17:14] : These bits are set to the following for normal operation
D21
D20
D19
D17
D16
D15
D14
0
0
0
0
0
0
0
LDP : Lock Detect Precision
The counter value for digital lock detect can be set.
D18
Function
Remarks
15 times Count
unlocked to locked
3 times Count
locked to unlocked
31 times Count
unlocked to locked
7 times Count
locked to unlocked
0
1
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[AK1547]
R[13:0] : Reference clock division number
The following settings can be selected for the reference clock division.
The allowed range is 1 (1/1 division) to 16383 (1/16383 division). 0 cannot be set.
The maximum frequency for FPFD is 55MHz.
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
Remarks
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Prohibited
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1/1 division
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1/2 division
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1/3 division
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1/4 division
1/16381
division
1/16382
division
1/16383
division
DATA
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MS1464-E-00
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2012/9
[AK1547]
< Address1 : N Counter >
D[21:20]
D19
D[18:6]
D[5:0]
Address
0
CPGAIN
B[12:0]
A[5:0]
01
D21, D20 : These bits are set to the following for normal operation
D21
D20
0
0
CPGAIN : Sets the charge pump current
When {FAST[1:0]} is NOT ”11Bin” :
D19
Function
Remarks
0
CP1 is enabled
1
CP2 is enabled
When {FAST[1:0]} is ”11Bin” :
D19
Function
Remarks
0
CP1 is enabled
CP2 is enabled during
1
Fast Lock Up Mode
switchover time
B[12:0] : B (Programmable) counter value
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
Function
Remarks
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Prohibited
0
0
0
0
0
0
0
0
0
0
0
0
1
1 Dec
Prohibited
0
0
0
0
0
0
0
0
0
0
0
1
0
2 Dec
Prohibited
0
0
0
0
0
0
0
0
0
0
0
1
1
3 Dec
DATA
1
1
1
1
1
1
1
1
1
1
1
0
1
8189 Dec
1
1
1
1
1
1
1
1
1
1
1
1
0
8190 Dec
1
1
1
1
1
1
1
1
1
1
1
1
1
8191 Dec
MS1464-E-00
21
2012/9
[AK1547]
A[5:0] : A (Swallow) counter value
D5
D4
D3
D2
D1
D0
Function
0
0
0
0
0
0
0
0
0
0
0
0
1
1 Dec
0
0
0
0
1
0
2 Dec
0
0
0
0
1
1
3 Dec
Remarks
DATA
1
1
1
1
0
1
61 Dec
1
1
1
1
1
0
62 Dec
1
1
1
1
1
1
63 Dec
* Requirements for A[5:0] and B[12:0]
The data at A[5:0] and B[12:0] must meet the following requirements:
A[5:0] ≥ 0, B[12:0] ≥ 3, B[12:0] ≥ A[5:0]
See “Frequency Setup” in section “Block Functional Descriptions” for details of the relationship
between a frequency division number N and the data at A[5:0] and B[12:0].
MS1464-E-00
22
2012/9
[AK1547]
< Address2 : Function >
D[21:20]
D19
D[18:16]
D[15:13]
D[12:9]
D[8:7]
PRE[1:0]
PD2
CP2[2:0]
CP1[2:0]
TIMER[3:0]
FAST[1:0]
D6
D5
D[4:2]
D1
D0
Address
CPHIZ
CPPOLA
LD[2:0]
PD1
CNTR_RST
02
PRE[1:0] : Selects a dividing ratio for the prescaler
The prescaler value should be chosen so that the prescaler output frequency is always less than or
equal to 125MHz.
D21
D20
Function
Remarks
0
0
P=8, Dual modulus prescaler 8/9
0
1
P=16, Dual modulus prescaler 16/17
1
0
P=32, Dual modulus prescaler 32/33
1
1
P=64, Dual modulus prescaler 64/65
PD2, PD1 : Power Down Select
<Address2>
[PDN]
Function
{PD2}
{PD1}
“Low”
X
X
Power Down
“High”
X
0
Normal Operation
“High”
0
1
Asynchronous Power Down
“High”
1
1
Synchronous Power Down
X : Don’t care ( “0” is recommended)
{PD2}=1 and {PD1}=1 : All circuits powers down at the timing when the Phase detector frequency
signal reverses.
{PD2}=0 and {PD1}=1 :
All circuits goes into Power Down during the rise up of LE signal that latches
“1” into {PD1}.
The registers can be written even in [PDN]=0.
MS1464-E-00
23
2012/9
[AK1547]
CP2[2:0] : Charge pump current setting 2
CP1[2:0] : Charge pump current setting 1
AK1547 provides two setting for charge pump current. They can be set by {CP1} and {CP2}.
The following formula shows the relationship among the resistance value, the register setting and the
electric current.
Charge pump minimum current (Icp_min)[A] = 17.46 / Resistance connected to the BIAS pin [Ω]
Charge pump current (Icp) [A] = Icp_min [A]  ({CP1} or {CP2} setting +1)
The following table shows the typical Icp for each status.
Icp (typical)
D18
D17
D16
Bias Resistance
D15
D14
D13
33 kΩ
27 kΩ
22 kΩ
0
0
0
529
647
794
0
0
1
1058
1293
1587
0
1
0
1587
1940
2381
0
1
1
2116
2587
3175
1
0
0
262.7
3233
3968
1
0
1
3175
3880
4762
1
1
0
3704
4527
5555
1
1
1
4233
5173
6349
Remarks
[Unit : A]
TIMER[3:0] : Sets the switchover time for CP2-to-CP1
This is enabled when {FAST[1:0]} is ”11Bin” and {[CPGAIN}=”1”.
The charge pump current is set into value {CP2[2:0]} designate during switchover time. It goes to be
{CP1[2:0]} setting value after the time out.
The following formula shows the relationship between the switchover time and the counter value.
Switchover time = 1 / FPFD  Counter Value
Counter Value = 3 + Timer[3:0]  4
MS1464-E-00
24
2012/9
[AK1547]
The following table shows the relationship between counter value and {TIMER[3:0]}.
D12
D11
D10
D9
Function
0
0
0
0
3 Counts
0
0
0
1
7 Counts
0
0
1
0
11 Counts
0
0
1
1
15 Counts
0
1
0
0
19 Counts
0
1
0
1
23 Counts
0
1
1
0
27 Counts
0
1
1
1
31 Counts
1
0
0
0
35 Counts
1
0
0
1
39 Counts
1
0
1
0
43 Counts
1
0
1
1
47 Counts
1
1
0
0
51 Counts
1
1
0
1
55 Counts
1
1
1
0
59 Counts
1
1
1
1
63 Counts
Remarks
FAST[1:0] : Enables or disables the Fast Lock mode
When {FAST[1:0]} is ”11Bin”, {CPGAIN} of function latch is the Fast Lock mode bit. When Fast Lock is
enabled, charge pump current is set to the value of {CP2} setting during the switchover time under the
control of the timer counter. After the timeout, {CPGAIN} is reset into “0” and charge pump current goes
to be {CP1} setting value.
D8
D7
X
0
0
1
{CPGAIN}
Function
0
CP1 is enabled
1
CP2 is enabled
0
CP1 is enabled
1
CP2 is enabled
0
CP1 is enabled
1
1
CP2 is enabled during
1
switchover time
MS1464-E-00
Remarks
25
Fast Lock Up Mode. {CPGAIN}
is reset to “0” after timeout.
2012/9
[AK1547]
CPHIZ : TRI-STATE output setting for charge pump
D6
Function
0
Charge pumps are activated.
1
TRI-STATE
Note 1)
Remarks
Use this setting for normal operation.
Note 1)
The charge pump output is turned OFF and put in the high-impedance (Hi-Z)
state.
CPPOLA : Selects positive or negative output polarity for CP1 and CP2
D5
Function
0
Negative
1
Positive
Remarks
High
VCO frequency
Positive
Negative
Low
Low
Charge pump output voltage
High
LD : Selects output from [LD] pin
MS1464-E-00
D4
D3
D2
Function
0
0
0
DVSS
0
0
1
Digital lock detect
0
1
0
N divider output
0
1
1
DVDD
1
0
0
R divider output
1
0
1
Analog lock detect
1
1
0
DVSS
1
1
1
DVSS
26
Remarks
Open Drain
2012/9
[AK1547]
CNTR_RST : Counter Reset
D0
Function
Remarks
0
Normal operation
1
R and N counters are reset.
< Address3 : Initialization >
This function is same as <Address2>.
When this register is accessed, the following occurs :
-
Address2 is loaded.
-
An internal pulse resets the R counter, N counter and {TIMER} settings to load-state conditions, and also
charge pump to Tri-state.
-
Writing Address1 activates the R and N counter, {TIMER} and charge pump. {TIMER} is enabled when
{FAST}=”11Bin” and {CPGAIN}=“1”.
MS1464-E-00
27
2012/9
[AK1547]
11. IC Interface Schematic
No.
Pin name
I/O
R0()
11
PDN
I
300
12
CLK
I
300
13
DATA
I
300
14
LE
I
300
2
TEST1
I
300
10
TEST2
I
300
Function
Cur(A)
Digital input pin
R0
Digital input pin (Pull-Down)
R0
100k
15
LD
O
8
REFIN
I
Digital output pin
300
Analog input pin
R0
19
BIAS
IO
300
Analog input/output pin
R0
MS1464-E-00
28
2012/9
[AK1547]
No.
Pin name
I/O
20
CP
O
4
RFINN
I
12k
20
5
RFINP
I
12k
20
R0()
Function
Cur(A)
Analog output pin
Analog input pin (RF input pin)
R0
MS1464-E-00
29
2012/9
[AK1547]
12. Recommended Connection Schematic of Off-Chip Component
1.
Power Supply Pins
LSI
PVDD
0.01F
100pF
10F
CPVDD
0.01F
100pF
10F
AVDD
0.01F
100pF
10F
2.
TEST1, TEST2
LSI
TEST1,2
3.
REFIN
LSI
REFIN
100pF±10%
MS1464-E-00
30
2012/9
[AK1547]
4.
RFINP、RFINN
LSI
VCO Output
RFINP
51Ω
100pF±10%
RFINN
100pF±10%
5.
BIAS
LSI
BIAS
22kΩ~33kΩ
MS1464-E-00
31
2012/9
[AK1547]
13. Power-Up Timing Chart (Recommended Flow)
VDD1, VDD2
PDN
Internal register values are set
Address
Register Write-in
0~2
Hi-z
CP
Output
op
Note1)
After VDD1 and VDD2 is powered up, the initial setting of registers is undefined.
It is required to write in Address0, 1 and 2.
Fig. 10 Power Up Sequence (Recommended)
VDD1, VDD2
PDN
Internal sequence circuit is initialized
Address 2
{PD1}=1
Register Write-in
Undefined
Internal register values are set
Address 0,1
Address 2
{PD1}=0
Hi-z
CP
Output
Note2) When VDD1,VDD2 and PDN are synchronously powered up, internal sequence circuit is not
initialized. So the circuit starts working on undefined status. Therefore, register {PD1} must be
set to “1” before register setting.
Fig. 11 Power Up Sequence (VDD1/VDD2/PDN synchronous power-up)
MS1464-E-00
32
2012/9
[AK1547]
14. Frequency Setting Timing Chart (Recommended Flow)
VDD1, VDD2
PDN
Address 2
Register Write-in
Power down
{PD1}=1
Address 0 Address 1
setting
setting
Address 2
Power up
{PD1}=0
Hi-z
CP
Output 1
Output 2
Fig. 102 Frequency settings (controlled by {PD1})
VDD1, VDD2
PDN
Address 3 Address 0 Address 1
Register Write-in
{PD1}=0
setting
setting
Hi-z
CP
Output 1
Output 2
Fig. 113 Frequency settings (controlled by INITIAL register)
注)
The function of Address3 is the same as Address2. Before writing in Address3, be sure to set
{PD1}=0. Access to Address3 resets CP to Hi-Z, then set Address0 and 1. Access to
Address1 restarts CP to operating.
MS1464-E-00
33
2012/9
[AK1547]
15. Typical Evaluation Board Schematic
RFOUT
AK1547
Loop Filter
18
R3
18
VCO
CP
C1
100pF
R2
C3
REFIN
100pF
18
C2
BIAS
27k
100pF
RFINP
100pF
RFINN
51
Fig. 124 Typical Evaluation Board Schematic
Note1)
Although it is no problem that both of [TEST1] and [TEST2] are open, it is recommended that they should
be connected to ground.
Note2)
Although it is no problem that exposed pad at the center of the backside is open, it is recommended that it
should be connected to ground.
MS1464-E-00
34
2012/9
[AK1547]
16. Outer Dimensions
Fig. 135 Outer Dimensions
MS1464-E-00
35
2012/9
[AK1547]
17. Marking
a.
Style
:
QFN
b.
Number of pins
:
20
c.
A1 pin marking
:
●
d.
Product number
:
1547
e.
Date code
:
YWWL (4 digits)
Y
: Lower 1 digit of calendar year
(Year 2012-> 2, 2013-> 3 ...)
WW : Week
L
: Lot identification, given to each product lot which is made in a week
(A, B, C…)
→ LOT ID is given in alphabetical order
1547
YWWL
(d)
(e)
●(c)
MS1464-E-00
36
2012/9
[AK1547]
IMPORTANT NOTICE
 These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi
Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
 Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor
products. You are fully responsible for the incorporation of these external circuits, application circuits,
software and other related information in the design of your equipments. AKM assumes no responsibility for
any losses incurred by you or third parties arising from the use of these information herein. AKM assumes
no liability for infringement of any patent, intellectual property, or other rights in the application or use of
such information contained herein.
 Any export of these products, or devices or systems containing them, may require an export license or
other official approval under the law and regulations of the country of export pertaining to customs and
tariffs, currency exchange, or strategic materials.
 AKM products are neither intended nor authorized for use as critical components Note1) in any safety, life
support, or other hazard related device or system Note2), and AKM assumes no responsibility for such use,
except for the use approved with the express written consent by Representative Director of AKM. As used
here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or damage
to person or property.
 It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold
AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
MS1464-E-00
37
2012/9
Related Parts
Part#
Mixer
Discription
Comments
AK1220
100MHz~900MHz High Linearity Down Conversion Mixer
IIP3:+22dBm
AK1222
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IDD:2.9mA
AK1224
100MHz~900MHz
NF:8.5dB, IIP3:+18dBm
AK1228
10MHz~2GHz Up/Down Conversion Mixer
3V Supply, NF:8.5dB
AK1221
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IIP3:+25dBm
AK1223
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Low Noise, High Liniarity Down Conversion Mixer
High Linearity Down Conversion Mixer
IIP3:+13dB, NF:15dB
PLL Synthesizer
AK1541
20MHz~600MHz Low Power Fractional-N Synthesizer
IDD:4.6mA
AK1542A
20MHz~600MHz Low Power Integer-N Synthesizer
IDD:2.2mA
AK1543
400MHz~1.3GHz Low Power Fractional-N Synthesizer
IDD:5.1mA
AK1544
400MHz~1.3GHz Low Power Integer-N Synthesizer
IDD:2.8mA
AK1590
60MHz~1GHz Fractional-N Synthesizer
IDD:2.5mA
AK1545
0.5GHz~3.5GHz Integer-N Synthesizer
16-TSSOP
AK1546
0.5GHz~3GHz Low Phase Noise Integer-N Synthesizer
Normalized C/N:-226dBc/Hz
AK1547
0.5GHz~4GHz Integer-N Synthesizer
5V Supply
AK1548
1GHz~8GHz Low Phase Noise Integer-N Synthesizer
Normalized C/N:-226dBc/Hz
100~300MHz Analog Signal Control IF VGA w/ RSSI
Dynamic Range:30dB
IFVGA
AK1291
integrated VCO
AK1572
690MHz~4GHz Down Conversion Mixer with Frac.-N PLL and VCO
IIP3:24dBm,
[email protected]
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690MHz~4GHz Up Conversion Mixer with Frac.-N PLL and VCO
IIP3:24dBm,
[email protected]
IF Reciever (2nd Mixer + IF BPF + FM Detector)
AK2364
Built-in programmable AGC+BPF, FM detector IC
IFBPF:10kHz ~ 4.5kHz
AK2365A
Built-in programmable AGC+BPF, IFIC
IFBPF:7.5kHz ~ 2kHz
Analog BB for PMR/LMR
AK2345C
AK2360/
AK2360A
CTCSS Filter, Encoder, Decoder
24-VSOP
Inverted frequency(3.376kHz/3.020kHz) scrambler
8-SON
AK2363
MSK Modem/DTMF Receiver
24-QFN
AK2346B
0.3-2.55/3.0kHz Analog audio filter,
Emphasis, Compandor, scrambler, MSK Modem
24-VSOP
0.3-2.55/3.0kHz Analog audio filter
Emphasis, Compandor, scrambler, CTCSS filter
24-VSOP
AK2346A
AK2347B
AK2347A
24-QFN
24-QFN
Function IC
AK2330
8-bit 8ch Electronic Volume
VREF can be selected for each
channel
AK2331
8-bit 4ch Electronic Volume
VREF can be selected for each
channel
Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without
notice. When you consider any use or application of AKM product stipulated in this document, please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
2014/10