Data Sheet

[AK4611]
AK4611
4/8-Channel Audio CODEC
GENERAL DESCRIPTION
The AK4611 is a single chip audio CODEC that includes four ADC channels and eight DAC channels.
The converters are designed with Enhanced Dual Bit architecture for the ADC’s, and Advanced Multi-Bit
architecture for the DAC, enabling very low noise performance. Fabricated on a low power process, the
AK4611 operates off of a +3.3V analog supply and a +1.8V digital supply. The AK4611 supports both
single-ended and differential inputs and outputs. A wide range of applications can be realized, including
home theater, pro audio and car audio. The AK4611 is available in an 80-pin LQFP package.
FEATURES
1. 4channel 24bit ADC
- 128x Oversampling
- Linear Phase Digital Anti-Alias Filter
- Analog Anti-Alias Filter for Single-Ended Input and Differential Input
- ADC S/(N+D)
92dB: Single-Ended Input
97dB: Differential Input
- ADC DR, S/N
103dB: Single-Ended Input
104dB: Differential Input
- Digital HPF for offset cancellation
- I/F format: MSB justified, I2S or TDM
- Overflow flag
2. 8channel 24bit DAC
- 128x Oversampling
- Linear Phase 24bit 8 times Digital Filter
- Analog Smoothing Filter for Single-Ended Output
- DAC S/(N+D)
94dB: Single-Ended Output
100dB: Differential Output
- DAC DR, S/N
105dB: Single-Ended Output
108dB: Differential Output
- Individual channel digital volume with 256 levels and 0.5dB steps
- Soft mute
- De-emphasis for 32kHz, 44.1kHz and 48kHz
- Zero Detect Function
- I/F format: MSB justified, LSB justified (16bit, 20bit, 24bit), I2S or TDM
3. Sampling Frequency
- Normal Speed Mode: 32kHz to 48kHz
- Double Speed Mode: 64kHz to 96kHz
- Quad Speed Mode: 128kHz to 192kHz
4. Master / Slave mode
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[AK4611]
5. Master clock
- Slave mode: 256fs, 384fs or 512fs (Normal Speed Mode: fs=32kHz  48kHz)
256fs
(Double Speed Mode: fs=64kHz  96kHz)
128fs
(Quad Speed Mode: fs=128kHz  192kHz)
- Master mode: 256fs or 512fs
(Normal Speed Mode: fs=32kHz  48kHz)
256fs
(Double Speed Mode: fs=64kHz  96kHz)
128fs
(Quad Speed Mode: fs=128kHz  192kHz)
6. 4-wire Serial and I2C Bus µP I/F for mode setting
7. Power Supply
- Analog Power Supply: AVDD1, AVDD2 = 3.0  3.6V
- Digital Power Supply: DVDD = 1.6  2.0V
- I/O Buffer Power Supply: TVDD1, TVDD2 = 1.6  3.6V
8. Power Supply Current : 81 mA (fs=48kHz)
9. Ta = -20 ~ 85ºC (AK4611EQ), - 40  105ºC (AK4611VQ)
10. Package: 80pin LQFP (0.5mm pitch)
MS1050-E-05
2015/06
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[AK4611]
■ Block Diagram
M/S
LIN1+ / LIN1
ADC1
LIN1-
HPF1
PDN
DVMPD
RIN1+ / RIN1
ADC1
RIN1-
HPF1
XTI / MCKI
LIN2+ / LIN2
LIN2RIN2+ / RIN2
RIN2-
ADC2
HPF2
ADC2
HPF2
X’tal
Oscillation
Audio
I/F
XTO
Divider
MCKO
XATL
MCLK
LOUT1+ / LOUT1
LOUT1-
LRCK
LRCK
BICK
BICK
SCF1
DAC1
DATT1
DEM1
SCF1
DAC1
DATT1
DEM1
TST3
DATT2
DEM2
TST5
TST1
TST2
ROUT1+ / ROUT1
ROUT1-
TST4
LOUT2+ / LOUT2
LOUT2-
SCF2
DAC2
ROUT2+ / ROUT2
ROUT2-
SCF2
DAC2
DATT2
DEM2
SCF3
DAC3
DATT3
DEM3
LOUT3+ / LOUT3
LOUT3-
SCF3
DAC3
LOUT4+ / LOUT4
LOUT4-
SCF4
ROUT4+ / ROUT4
ROUT4-
SDTO1
SDOUT2
SDTO2
TST6
OVF1 / DZF1
OVF2 / DZF2
VCOM
ROUT3+ / ROUT3
ROUT3-
SDOUT1
SCF4
DAC4
DAC4
DATT3
DEM3
DATT4
DEM4
DATT4
DEM4
SDIN1
SDTI1
SDIN2
SDTI2
SDIN3
SDTI3
SDIN4
SDTI4
TST7
TST8
CAD0
CAD1
uP I/F
I2C
CSN
CCLK / SCL
CDTI / SDA
CDTO
VREFH1
VREFH2
AVDD1
VSS1 AVDD2
VSS2
DVDD
VSS3
TVDD1
VSS4
TVDD2
Figure 1. Block Diagram
MS1050-E-05
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[AK4611]
■ Ordering Guide
-20  +85C
80pin LQFP (0.5mm pitch)
-40  +105C
80pin LQFP (0.5mm pitch)
Evaluation Board for AK4611
AK4611EQ
AK4611VQ
AKD4611
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
TST12
1
TST11
1
TST10
1
TST9
1
ROUT41
ROUT4+ / ROUT4
1
LOUT41
LOUT4+ / LOUT4
1
VREFH2
1
AVDD2
1
VSS2
1
ROUT31
ROUT3+ / ROUT3
1
LOUT31
LOUT3+ / LOUT3
1
ROUT21
ROUT2+ / ROUT2
1
LOUT21
1
58
56
1
TST13
59
57
TST14
60
■ Pin Layout
TST15
61
40
LOUT2+ / LOUT2
TST16
62
39
ROUT1-
OVF1 / DZF1
63
38
ROUT1+ / ROUT1
OVF2 / DZF2
64
37
LOUT1-
LIN1+ / LIN1
65
36
LOUT1+ / LOUT1
LIN1-
66
35
DVMPD
RIN1+ / RIN1
67
34
TST8
RIN1-
68
33
TST7
LIN2+ / LIN2
69
32
SDTI4
LIN2-
70
31
SDTI3
RIN2+ / RIN2
71
30
SDTI2
RIN2-
72
29
SDTI1
TST17
73
TST18
80 pin LQFP
(TOP VIEW)
28
BICK
74
27
LRCK
8
9
10
11
12
13
14
15
16
17
18
19
20
CCLK / SCL
CSN
CDTI / SDA
CDTO
TVDD2
VSS3
DVDD
NC
TST2
M/S
MCKO
PDN
XTO
XTI / MCKI
7
TVDD1
21
I2C
22
80
6
79
TST20
5
TST19
CAD1
VSS4
CAD0
SDTO1
23
4
24
78
3
77
VCOM
TST5
VREFH1
TST4
SDTO2
2
TST6
25
1
26
76
TST3
75
TST1
VSS1
AVDD1
Figure 2. Pin Layout
MS1050-E-05
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[AK4611]
■ Compatibility with AK4628
1.
Functions
Function
Number of ADC channel
Number of DAC channel
Input
Output
I/F Format
TDM512
XTAL OSC
Parallel / Serial Select Pin
Control Data Output Pin
Ta
Package
AK4628
2-channel
8-channel
Single
Single
I2S, LJ, RJ(20/24bit), TDM
No
No
Yes
No
-40  +85C
44pinLQFP
AK4611
4-channel
8-channel
Single or Diff
Single or Diff
I2S, LJ, RJ(16/20/24bit), TDM
Fs=48kHz
Yes
No
Yes
-40  +105C
80pinLQFP
AK4628
4.5  5.5V
No
No
4.5  5.5V
2.7  5.5V
No
No
AK4611
No
3.0  3.6V
3.0  3.6V
1.6  2.0V
No
1.6  3.6V
1.6  3.6V
AK4628
96k / 192k
Single: 92 / 90
Differential : - / Single: 102 / 106
Differential : - / 128 level
100k I2C, 3wire
AK4611
192k / 192k
Single: 92 / 94
Differential : 97 / 100
Single: 103 / 105
Differential: 104 / 108
256 level
400k I2C, 4wire
2. Power Supply
Voltage Name
AVDD
AVDD1
AVDD2
DVDD
TVDD
TVDD1
TVDD2
3. Specification
Parameter
Fs (AD/DA)
THD+N (AD/DA)
S/N (AD/DA)
Output DATT
µP I/F
MS1050-E-05
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[AK4611]
PIN/FUNCTION
No.
Pin Name
I/O
1
TST1
I
2
TST3
I
3
TST4
I
4
TST5
I
5
6
CAD0
CAD1
I
I
7
I2C
I
CCLK
I
SCL
I
CSN
I
CDTI
I
SDA
I/O
8
9
10
11
12
13
14
CDTO
TVDD2
VSS3
DVDD
O
-
15
NC
-
16
TST2
I
17
M/S
I
18
MCKO
O
19
PDN
I
20
22
23
24
25
XTO
XTI
MCKI
TVDD1
VSS4
SDTO1
SDTO2
O
I
I
O
O
26
TST6
O
27
28
29
30
31
32
LRCK
BICK
SDTI1
SDTI2
SDTI3
SDTI4
I/O
I/O
I
I
I
I
33
TST7
I
21
-
Function
Test Pin
This pin must be connected to VSS4.
Test Pin
This pin must be connected to TVDD2.
Test Pin
This pin must be connected to VSS4.
Test Pin
This pin must be connected to VSS4.
Chip Address 0 Pin
Chip Address 1 Pin
µP I/F Mode Select Pin
“L”: 4-wire Serial, “H”: I2C Bus
Control Data Clock Pin in serial control mode
I2C = “L”: CCLK (4-wire Serial)
Control Data Clock Pin in serial control mode
I2C = “H”: SCL (I2C Bus)
Chip Select Pin in 4-wire serial control mode
This pin must be connected to TVDD2 at I2C bus control mode
Control Data Input Pin in serial control mode
I2C = “L”: CDTI (4-wire Serial)
Control Data Input Pin in serial control mode
I2C = “H”: SDA (I2C Bus)
Control Data Output Pin in 4-wire serial control mode
Input / Output Buffer Power Supply 1 Pin, 1.6V3.6V
Ground Pin, 0V
Digital Power Supply Pin, 1.6V2.0V
No Connection.
No internal bonding. This pin must be connected to the ground.
Test Pin
This pin must be connected to VSS4.
Master Mode Select Pin
“L”: Slave Mode “H”: Master Mode
Master Clock Output Pin
Power-Down & Reset Pin
When “L”, the AK4611 is powered-down and the control registers are reset to default
state. If the state of CAD1-0 changes, then the AK4611 must be reset by PDN.
X’tal Output Pin
X’tal Input Pin
External Master Clock Input Pin
Input / Output Buffer Power Supply 1 Pin, 1.6V3.6V
Digital Ground Pin, 0V
Audio Serial Data Output 1 Pin
Audio Serial Data Output 2 Pin
Test Pin
This pin must be open.
Input /Output Channel Clock Pin
Audio Serial Data Clock Pin
Audio Serial Data Input 1 Pin
Audio Serial Data Input 2 Pin
Audio Serial Data Input 3 Pin
Audio Serial Data Input 4 Pin
Test Pin
This pin must be connected to VSS4.
MS1050-E-05
2015/06
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[AK4611]
No.
Pin Name
34
TST8
I
35
DVMPD
I
54
LOUT1+
LOUT1
LOUT1ROUT1+
ROUT1
ROUT1LOUT2+
LOUT2
LOUT2ROUT2+
ROUT2
ROUT2LOUT3+
LOUT3
LOUT3ROUT3+
ROUT3
ROUT3VSS2
AVDD2
VREFH2
LOUT4+
LOUT4
LOUT4ROUT4+
ROUT4
ROUT4-
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
O
O
O
O
O
O
55
TST9
O
56
TST10
O
57
TST11
O
58
TST12
O
59
TST13
O
60
TST14
O
61
TST15
O
62
TST16
O
OVF1
O
DZF1
O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
I/O
63
Function
Test Pin
This pin must be connected to VSS4.
DAC output VCOM voltage power down pin
“L”: DAC outputs are VCOM voltage “H”: DAC outputs are Hi-Z.
Lch Analog Positive Output 1 Pin (DOE1 bit = “H”)
Lch Analog Output 1 Pin (DOE1 bit = “L”)
Lch Analog Negative Output 1 Pin (When DOE1 bit = “L”, this pin must be open.)
Rch Analog Positive Output 1 Pin (DOE1 bit = “H”)
Rch Analog Output 1 Pin (DOE1 bit = “L”)
Rch Analog Negative Output 1 Pin (When DOE1 bit = “L”, this pin must be open.)
Lch Analog Positive Output 2 Pin (DOE2 bit = “H”)
Lch Analog Output 2 Pin (DOE2 bit = “L”)
Lch Analog Negative Output 2 Pin (When DOE2 bit = “L”, this pin must be open.)
Rch Analog Positive Output 2 Pin (DOE2 bit = “H”)
Rch Analog Output 2 Pin (DOE2 bit = “L”)
Rch Analog Negative Output 2 Pin (When DOE2 bit = “L”, this pin must be open.)
Lch Analog Positive Output 3 Pin (DOE3 bit = “H”)
Lch Analog Output 3 Pin (DOE3 bit = “L”)
Lch Analog Negative Output 3 Pin (When DOE3 bit = “L”, this pin must be open.)
Rch Analog Positive Output 3 Pin (DOE3 bit = “H”)
Rch Analog Output 3 Pin (DOE3 bit = “L”)
Rch Analog Negative Output 3 Pin (When DOE3 bit = “L”, this pin must be open.)
Ground Pin, 0V
Analog Power Supply Pin, 3.0V3.6V
Positive Voltage Reference Input Pin, AVDD2
Lch Analog Positive Output 4 Pin (DOE4 bit = “H”)
Lch Analog Output 4 Pin (DOE4 bit = “L”)
Lch Analog Negative Output 4 Pin (When DOE4 bit = “L”, this pin must be open.)
Rch Analog Positive Output 4 Pin (DOE4 bit = “H”)
Rch Analog Output 4 Pin (DOE4 bit = “L”)
Rch Analog Negative Output 4 Pin (When DOE4 bit = “L”, this pin must be open.)
Test Pin
This pin must be open.
Test Pin
This pin must be open.
Test Pin
This pin must be open.
Test Pin
This pin must be open.
Test Pin
This pin must be open.
Test Pin
This pin must be open.
Test Pin
This pin must be open.
Test Pin
This pin must be open.
Analog Input Overflow Detect 1 Pin (Note 1)
This pin goes to “H” if the analog input of Lch or Rch overflows.
Zero Input Detect 1 Pin
( Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”. And when RSTN bit is “0”, PMDAC bit is “0”, this pin goes to “H”.
MS1050-E-05
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[AK4611]
No.
Pin Name
I/O
Function
Analog Input Overflow Detect 2 Pin (Note 1)
OVF2
O
This pin goes to “H” if the analog input of Lch or Rch overflows.
64
Zero Input Detect 2 Pin
( Note 2)
DZF2
O
When the input data of the group 2 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”. And when RSTN bit is “0”, PMDAC bit is “0”, this pin goes to “H”.
LIN1+
I
Lch Analog Positive Input 1 Pin (DIE1 bit = “H”)
65
LIN1
I
Lch Analog Input 1 Pin (DIE1 bit = “L”)
Lch Analog Negative Input 1 Pin (When DIE1 bit = “L”, this pin must be open.)
66 LIN1(Note 3)
RIN1+
I
Rch Analog Positive Input 1 Pin (DIE1 bit = “H”)
67
RIN1
I
Rch Analog Input 1 Pin (DIE1 bit = “L”)
Rch Analog Negative Input 1 Pin (When DIE1 bit = “L”, this pin must be open.)
68 RIN1(Note 3)
LIN2+
I
Lch Analog Positive Input 2 Pin (DIE2 bit = “H”)
69
LIN2
I
Lch Analog Input 2 Pin (DIE2 bit = “L”)
Lch Analog Negative Input 2 Pin (When DIE2 bit = “L”, this pin must be open.)
70 LIN2(Note 3)
RIN2+
I
Rch Analog Positive Input 2 Pin (DIE2 bit = “H”)
71
RIN2
I
Rch Analog Input 2 Pin (DIE2 bit = “L”)
Rch Analog Negative Input 2 Pin (When DIE2 bit = “L”, this pin must be open.)
72 RIN2(Note 3)
Test Pin
73 TST17
I
This pin must be open.
Test Pin
74 TST18
I
This pin must be open.
75 VSS1
Ground Pin, 0V
76 AVDD1
Analog Power Supply Pin, 3.0V3.6V
77 VREFH1
I
Positive Voltage Reference Input Pin, AVDD1
Common Voltage Output Pin, AVDD1x1/2
78 VCOM
O
Large external capacitor around 2.2µF is used to reduce power-supply noise.
Test Pin
79 TST19
I
This pin must be open.
Test Pin
80 TST20
I
This pin must be open.
Note 1. This pin becomes OVF pin when OVFE bit is set to “1”.
Note 2. This pin becomes DZF pin when OVFE bit is set to “0”.
Note 3. This pin becomes analog negative input pin in differential input mode, and becomes output pin invert the positive
input pin in single-end input mode. This pin must be open in single-end input mode.
Note 4. All digital input pins except for pull-down must not be left floating.
MS1050-E-05
2015/06
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[AK4611]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=VSS3=VSS4=0V; Note 5)
Parameter
Power Supplies
Analog
Digital
Output buffer
Input Current (any pins except for supplies)
Analog Input Voltage
Digital Input Voltage
(TST2,M/S,PDN,XTI/MCKI,LRCK,BICK,
SDTI1,SDTI2,SDTI3,SDTI4,TST7,TST8,
DVMPD pins)
(TST1,TST3,TST4,TST5,CAD0,CAD1,I2C,
CCLK/SCL,CSN,CDTI/SDA pins)
Ambient Temperature (power applied)
Symbol
AVDD1,2
DVDD
TVDD1,2
IIN
VINA
min
-0.3
-0.3
-0.3
-0.3
max
4.2
2.2
4.2
10
AVDD1,2+0.3
Unit
V
V
V
mA
V
VIND1
-0.3
TVDD1+0.3
V
VIND2
-0.3
TVDD2+0.3
V
Ta
Ta
-20
-40
85
105
C
C
AK4611EQ
AK4611VQ
Storage Temperature
Tstg
-65
150
C
Note 5. All voltages with respect to ground. VSS1, VSS2, VSS3 and VSS4 must be connected to the same analog ground
plane. AVDD1 and AVDD2 must be the same voltage.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=VSS3=VSS4=0V; Note 5)
Parameter
Symbol
min
typ
max
Unit
Power Supplies Analog
AVDD1,2
3.0
3.3
3.6
V
(Note 6)
Digital
DVDD
1.6
1.8
2.0
V
I/O buffer 1
TVDD1
DVDD
3.3
3.6
V
(Stereo Mode & Normal Speed Mode)
I/O buffer 1
TVDD1
3.0
3.3
3.6
V
(Except Stereo Mode & Normal Speed Mode)
I/O buffer 2
TVDD2
DVDD
3.3
3.6
V
Note 6. The power up sequence between AVDD1, AVDD2, DVDD, TVDD1 and TVDD2 is not critical. Each power
supplies should be powered up during the PDN pin = “L”. The PDN pin should be “H” after all power supplies are
powered up. All power supplies should be powered on, only a part of these power supplies cannot be powered off.
(Power off means power supplies equal to ground or power supplies are floating.) Do not turn off only the
AK4611 under the condition that a surrounding device is powered on and the I2C bus is in use.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS1050-E-05
2015/06
-9-
[AK4611]
ANALOG CHARACTERISTICS
(Ta=25C; AVDD1=AVDD2=TVDD1=TVDD2=3.3V, DVDD =1.8V; VSS1=VSS2=0V; VREFH1=AVDD1,
VREFH2=AVDD2; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement
Frequency=20Hz20kHz at 48kHz, 20Hz~40kHz at fs=96kHz, 20Hz~40kHz at fs=192kHz; unless otherwise specified)
Parameter
min
typ
max
Unit
ADC Analog Input Characteristics (single inputs)
Resolution
24
Bits
S/(N+D)
fs=48kHz
-1dBFS
84
92
dB
BW=20kHz
-60dBFS
40
fs=96kHz
-1dBFS
83
91
dB
BW=40kHz
-60dBFS
37
fs=192kHz
-1dBFS
91
BW=40kHz
-60dBFS
37
DR
(-60dBFS with A-weighted)
95
103
dB
S/N
(A-weighted)
95
103
dB
Interchannel Isolation
90
110
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Gain Drift
40
ppm/C
Input Voltage
AIN=0.65xVREFH1
1.94
2.15
2.37
Vpp
Input Resistance
7
9
k
Power Supply Rejection
(Note 7)
50
dB
ADC Analog Input Characteristics (differential inputs)
S/(N+D)
fs=48kHz
-1dBFS
88
97
dB
BW=20kHz
-60dBFS
40
dB
fs=96kHz
-1dBFS
86
94
BW=40kHz
-60dBFS
37
fs=192kHz
-1dBFS
94
BW=40kHz
-60dBFS
37
DR
(-60dBFS with A-weighted)
96
104
dB
S/N
(A-weighted)
96
104
dB
Interchannel Isolation
90
110
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Gain Drift
40
ppm/C
Input Voltage
AIN=0.65xVREFH1
(Note 8)
±1.94
±2.15
±2.37
Vpp
Input Resistance
11
13
k
Power Supply Rejection
(Note 7)
50
dB
Common Mode Rejection Ratio (CMRR)
(Note 9)
74
dB
DAC Analog Output Characteristics (single outputs)
Resolution
24
Bits
S/(N+D)
fs=48kHz
0dBFS
84
94
dB
BW=20kHz
-60dBFS
44
fs=96kHz
0dBFS
86
92
BW=40kHz
-60dBFS
41
fs=192kHz
0dBFS
92
BW=40kHz
-60dBFS
41
DR
(-60dBFS with A-weighted)
97
105
dB
S/N
(A-weighted)
97
105
dB
Interchannel Isolation
90
110
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Gain Drift
20
ppm/C
Output Voltage
AOUT=0.63xVREFH2
1.87
2.08
2.29
Vpp
Load Resistance
(AC Load)
5
k
Load Capacitance
30
pF
Power Supply Rejection
(Note 7)
50
dB
MS1050-E-05
2015/06
- 10 -
[AK4611]
DAC Analog Output Characteristics (differential outputs)
S/(N+D)
fs=48kHz
0dBFS
90
100
dB
BW=20kHz
-60dBFS
45
fs=96kHz
0dBFS
88
98
BW=40kHz
-60dBFS
42
fs=192kHz
0dBFS
98
BW=40kHz
-60dBFS
42
DR
(-60dBFS with A-weighted)
100
108
dB
S/N
(A-weighted)
100
108
dB
Interchannel Isolation
90
110
dB
Interchannel Gain Mismatch
0
0.5
dB
Gain Drift
20
ppm/C
Output Voltage
AOUT=0.63xVREFH2
(Note 8)
±1.87
±2.08
±2.29
Vpp
Load Resistance
(Note 10)
2
k
Load Capacitance
30
pF
Power Supply Rejection
(Note 7)
50
dB
Note 7. PSR is applied to AVDD1, AVDD2, DVDD, TVDD1 and TVDD2 with 1kHz, 50mVpp. VREFH1 and VREFH2
pins are held a constant voltage +3.3V.
Note 8. This value is (LIN+) – (LIN-) and (RIN+) – (RIN-). The voltage is proportional to VREFH1, VREFH2 voltage.
Note 9. VREFH1 and VREFH2 are held +3.3V, the input bias voltage is set to AVDD1, 2 x 0.5. The 1kHz, 0.96Vpp
signal is applied to LIN- and LIN+ with same phase (e.g. shorted) or RIN- and RIN+. The CMRR is measured as
the attenuation level from 0dB = -7dBFS (since the normal 0.96Vpp = -7dBFS). This value is guaranteed but not
tested.
Note 10. For AC-load. In the case of DC-load is 5kΩ.
Note 11. This value is Load Capacitance for output pin to GND. In differential mode, this value should be estimated to be
twice, because Load Capacitance exists to GND and between the differential pin.
Parameter
min
typ
max
Unit
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
AVDD1+AVDD2
fs=48kHz, 96kHz, 192kHz
63.0
125.0
mA
DVDD
fs=48kHz
12.0
24.0
mA
fs=96kHz
17.0
35.0
mA
fs=192kHz
28.0
55.0
mA
TVDD1+TVDD2
fs=48kHz
6.0
8.0
mA
fs=96kHz
7.0
9.5
mA
fs=192kHz
7.0
9.5
mA
Power-down mode
(PDN pin = “L”, DVMPD = “L”)
(Note 12)
AVDD1+AVDD2+DVDD+TVDD1+TVDD2
200
550
µA
(PDN pin = “L”, DVMPD = “H”)
(Note 12)
AVDD1+AVDD2+DVDD+TVDD1+TVDD2
10
200
µA
Note 12. In the power-down mode, all digital input pins including clock pins are held VSS3 (TST1, TST3, TST4, TST5,
CAD0, CAD1, I2C, CSN, CCLK, CDTI pins), VSS4 (TST2, M/S, MCKI, LRCK, BICK, SDTI1, SDTI2, SDTI3,
SDTI4,TST7, TST8).
MS1050-E-05
2015/06
- 11 -
[AK4611]
FILTER CHARACTERISTICS (fs=48kHz)
(Ta= Tmin  Tmax; AVDD1=AVDD2=3.0 3.6V, DVDD=1.6 2.0V, TVDD1=TVDD2=1.6 3.6V; DEM=OFF)
Parameter
Symbol
min
typ
max
Unit
ADC Digital Filter (Decimation LPF):
Passband
(Note 13) 0.1dB
PB
0
18.9
kHz
0.2dB
20.0
kHz
3.0dB
23.0
kHz
Stopband
(Note 13)
SB
28
kHz
Passband Ripple
PR
0.1
dB
Stopband Attenuation
SA
68
dB
Group Delay Distortion
GD
0
s
Group Delay
(Note 14)
GD
16
1/fs
ADC Digital Filter (HPF):
Frequency Response (Note 13) 3dB
FR
1.0
Hz
0.1dB
6.5
Hz
DAC Digital Filter (LPF):
Passband
(Note 13) 0.06dB
PB
0
21.8
kHz
6.0dB
24.0
kHz
Stopband
(Note 13)
SB
26.2
kHz
Passband Ripple
PR
0.06
dB
Stopband Attenuation
SA
54
dB
Group Delay Distortion
GD
0
s
Group Delay
(Note 14)
GD
22
1/fs
DAC Digital Filter + Analog Filter:
Frequency Response (Note 15) 20kHz
FR
-0.1
dB
FILTER CHARACTERISTICS (fs=96kHz)
(Ta= Tmin  Tmax; AVDD1=AVDD2=3.0 3.6V, DVDD=1.6 2.0V, TVDD1=TVDD2=1.6 3.6V; DEM=OFF)
Parameter
Symbol
min
typ
max
Unit
ADC Digital Filter (Decimation LPF):
Passband
(Note 13) 0.1dB
PB
0
37.8
kHz
0.2dB
40.0
kHz
3.0dB
46.0
kHz
Stopband
(Note 13)
SB
56
kHz
Passband Ripple
PR
0.1
dB
Stopband Attenuation
SA
68
dB
Group Delay Distortion
GD
0
s
Group Delay
(Note 14)
GD
16
1/fs
ADC Digital Filter (HPF):
Frequency Response (Note 13) 3dB
FR
2.0
Hz
0.1dB
13.0
Hz
DAC Digital Filter (LPF):
Passband
(Note 13) 0.06dB
PB
0
43.6
kHz
6.0dB
48.0
kHz
Stopband
(Note 13)
SB
52.4
kHz
Passband Ripple
PR
0.06
dB
Stopband Attenuation
SA
54
dB
Group Delay Distortion
GD
0
s
Group Delay
(Note 14)
GD
22
1/fs
DAC Digital Filter + Analog Filter:
Frequency Response (Note 15) 40kHz
FR
-0.3
dB
MS1050-E-05
2015/06
- 12 -
[AK4611]
FILTER CHARACTERISTICS (fs=192kHz)
(Ta= Tmin  Tmax; AVDD1=AVDD2=3.0 3.6V, DVDD=1.6 2.0V, TVDD1=TVDD2=1.6 3.6V; DEM=OFF)
Parameter
Symbol
min
typ
max
Unit
ADC Digital Filter (Decimation LPF):
Passband
(Note 13) 0.1dB
PB
0
56.6
kHz
0.2dB
57.0
kHz
3.0dB
90.3
kHz
Stopband
(Note 13)
SB
112
kHz
Passband Ripple
PR
0.1
dB
Stopband Attenuation
SA
70
dB
Group Delay Distortion
GD
0
s
Group Delay
(Note 14)
GD
16
1/fs
ADC Digital Filter (HPF):
Frequency Response (Note 13) 3dB
FR
4.0
Hz
0.1dB
26.0
Hz
DAC Digital Filter (LPF):
Passband
(Note 13) 0.06dB
PB
0
87.0
kHz
6.0dB
96.0
kHz
Stopband
(Note 13)
SB
104.9
kHz
Passband Ripple
PR
0.06
dB
Stopband Attenuation
SA
54
dB
Group Delay Distortion
GD
0
s
Group Delay
(Note 14)
GD
22
1/fs
DAC Digital Filter + Analog Filter:
Frequency Response (Note 15) 80kHz
FR
-1
dB
Note 13. The passband and stopband frequencies scale with fs (sampling frequency). For example, ADC: Passband
(0.1dB) = 0.39375 x fs (@ fs=48kHz), DAC: Passband (0.06dB) = 0.45412 x fs.
Note 14. The calculated delay time is resulting from digital filtering. For the ADC, this time is from the input of an analog
signal to the setting of 24bit data for both channels to the ADC output register. For the DAC, this time is from
setting the 24 bit data both channels at the input register to the output of an analog signal.
Note 15. The reference frequency is 1kHz.
MS1050-E-05
2015/06
- 13 -
[AK4611]
DC CHARACTERISTICS
(Ta= Tmin  Tmax; AVDD1=AVDD2=3.03.6; DVDD=1.62.0V; TVDD1=TVDD2=1.63.6V)
Parameter
Symbol
min
typ
max
TVDD1,TVDD2 ≤2.2V
High-Level Input Voltage
(TST2, M/S, PDN, MCKI, LRCK, BICK,
SDTI1, SDTI2, SDTI3, SDTI4,TST7, TST8,
DVMPD pins)
VIH
80%TVDD1
(TST1,TST3,TST4,TST5,CAD0,CAD1,I2C,
CSN,CCLK, CDTI pins)
VIH
80%TVDD2
Low-Level Input Voltage
(TST2, M/S, PDN, MCKI, LRCK, BICK,
SDTI1, SDTI2, SDTI3, SDTI4,TST7, TST8,
DVMPD pins)
VIL
20%TVDD1
(TST1,TST3,TST4,TST5,CAD0,CAD1,I2C,
CSN,CCLK, CDTI pins)
VIL
20%TVDD2
TVDD1,TVDD2 > 2.2V
High-Level Input Voltage
(TST2, M/S, PDN, MCKI, LRCK, BICK,
SDTI1, SDTI2, SDTI3, SDTI4,TST7, TST8,
VIH
70%TVDD1
DVMPD pins)
(TST1,TST3,TST4,TST5,CAD0,CAD1,I2C,
VIH
70%TVDD2
CSN,CCLK, CDTI pins)
Low-Level Input Voltage
(TST2, M/S, PDN, MCKI, LRCK, BICK,
SDTI1, SDTI2, SDTI3, SDTI4,TST7, TST8,
DVMPD pins)
VIL
30%TVDD1
(TST1,TST3,TST4,TST5,CAD0,CAD1,I2C,
CSN,CCLK, CDTI pins)
VIL
30%TVDD2
High-Level Output Voltage
(SDTO1,SDTO2,TST6, LRCK, BICK,
MCKO pins:
Iout=-100µA)
VOH
TVDD1-0.5
(CDTO pin:
Iout=-100µA)
VOH
TVDD2-0.5
(DZF1/OVF1, DZF2/OVF2 pins: Iout=-100µA)
AVDD2-0.5
Low-Level Output Voltage
(SDTO1,SDTO2,TST6, LRCK, BICK,
MCKO, CDTO, DZF1, DZF2/OVF pins:
Iout= 100µA)
VOL
0.5
(SDA pin, 2.0V≤TVDD2≤3.6V
Iout= 3mA)
VOL
0.4
VOL
20%TVDD2
(SDA pin, 1.6VTVDD2<2.0V
Iout= 3mA)
Input Leakage Current
Iin
10
MS1050-E-05
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
2015/06
- 14 -
[AK4611]
SWITCHING CHARACTERISTICS
(Ta= Tmin  Tmax; AVDD1=AVDD2=3.03.6; DVDD=1.62.0V; TVDD1=1.63.6V, TVDD2=1.63.6V; CL=20pF;
unless otherwise specified)
Parameter
Symbol
min
typ
max
Unit
Master Clock Timing
Crystal Resonator
Frequency
fXTAL
11.2896
24.576
MHz
MCKO Output
fMCK
5.6448
24.576
MHz
Frequency (TVDD1 ≥3.0V)
dMCK
40
50
60
%
Duty
External Clock
256fsn:
fCLK
8.192
12.288
MHz
Pulse Width Low
tCLKL
32
ns
Pulse Width High
tCLKH
32
ns
384fsn:
fCLK
12.288
18.432
MHz
Pulse Width Low
tCLKL
22
ns
Pulse Width High
tCLKH
22
ns
512fsn, 256fsd, 128fsq:
fCLK
16.384
24.576
MHz
Pulse Width Low
tCLKL
16
ns
Pulse Width High
tCLKH
16
ns
MCKO Output
fMCK
4.096
12.288
MHz
Frequency
fMCK
12.288
24.576
MHz
(TVDD1 ≥3.0V)
dMCK
40
50
60
%
Duty
(Note 16)
LRCK Timing (Slave mode)
Stereo mode
(TDM1 bit = “0”, TDM0 bit = “0”)
Normal Speed Mode
fsn
32
48
kHz
Double Speed Mode
fsd
64
96
kHz
Quad Speed Mode
fsq
128
192
kHz
Duty Cycle
Duty
45
55
%
TDM512 mode
(Note 17)
(TDM1 bit = “0”, TDM0 bit = “1”)
LRCK frequency
fsn
32
48
kHz
“H” time
tLRH
1/512fs
ns
“L” time
tLRL
1/512fs
ns
TDM256 mode
(Note 18)
(TDM1 bit = “1”, TDM0 bit = “0”)
LRCK frequency
fsd
64
96
kHz
“H” time
tLRH
1/256fs
ns
“L” time
tLRL
1/256fs
ns
TDM128 mode
(Note 19)
(TDM1 bit = “1”, TDM0 bit = “1”)
LRCK frequency
fsq
128
192
kHz
“H” time
tLRH
1/128fs
ns
“L” time
tLRL
1/128fs
ns
MS1050-E-05
2015/06
- 15 -
[AK4611]
Parameter
Symbol
min
typ
max
LRCK Timing (Master Mode)
Stereo mode
(TDM1 bit = “0”, TDM0 bit = “0”)
Normal Speed Mode
fsn
32
48
Double Speed Mode
fsd
64
96
Quad Speed Mode
fsq
128
192
Duty Cycle
Duty
50
TDM512 mode
(Note 17)
(TDM1 bit = “0”, TDM0 bit = “1”)
LRCK frequency
fsn
32
48
“H” time
(Note 20)
tLRH
1/16fs
TDM256 mode
(Note 18)
(TDM1 bit = “1”, TDM0 bit = “0”)
LRCK frequency
fsd
64
96
“H” time
(Note 20)
tLRH
1/8fs
TDM128 mode
(Note 19)
(TDM1 bit = “1”, TDM0 bit = “1”)
LRCK frequency
fsq
128
192
“H” time
(Note 20)
tLRH
1/4fs
Note 16. Except the case of DIV bit = “0”.
Note 17. Please use for Normal Speed mode. Master clock should be input the 512fs in Master mode.
Note 18. Please use for Double Speed mode.
Note 19. Please use for Quad Speed mode.
Note 20. If the format is I2S, it is “L” time.
Unit
MS1050-E-05
2015/06
- 16 -
kHz
kHz
kHz
%
kHz
ns
kHz
ns
kHz
ns
[AK4611]
Parameter
Audio Interface Timing (Slave mode)
Stereo mode (TDM1 bit = “0”, TDM0 bit = “0”)
(TVDD1= 1.6V3.6V)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “”
(Note 21)
BICK “” to LRCK Edge
(Note 21)
LRCK to SDTO(MSB) (Except I2S mode)
BICK “” to SDTO
SDTI Hold Time
SDTI Setup Time
(TVDD1= 3.0V3.6V)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “”
(Note 21)
BICK “” to LRCK Edge
(Note 21)
LRCK to SDTO(MSB) (Except I2S mode)
BICK “” to SDTO
SDTI Hold Time
SDTI Setup Time
TDM512 mode (TDM1 bit = “0”, TDM0 bit = “1”)
(TVDD1= 3.0V3.6V)
(Note 17)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “”
(Note 21)
BICK “” to LRCK Edge
(Note 21)
SDTO Setup time BICK “”
SDTO Hold time BICK “”
SDTI Hold Time
SDTI Setup Time
TDM256 mode (TDM1 bit = “1”, TDM0 bit = “0”)
(TVDD1= 3.0V3.6V)
(Note 18)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “”
(Note 21)
BICK “” to LRCK Edge
(Note 21)
SDTO Setup time BICK “”
SDTO Hold time BICK “”
SDTI Hold Time
SDTI Setup Time
TDM128 mode (TDM1 bit = “1”, TDM0 bit = “1”)
(TVDD1= 3.0V3.6V)
(Note 19)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “”
(Note 21)
BICK “” to LRCK Edge
(Note 21)
SDTO Setup time BICK “”
SDTO Hold time BICK “”
SDTI Hold Time
SDTI Setup Time
Symbol
MS1050-E-05
min
typ
max
Unit
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
324
130
130
20
20
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
81
33
33
23
23
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSS
tBSH
tSDH
tSDS
40
16
16
10
10
6
5
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSS
tBSH
tSDH
tSDS
40
16
16
10
10
6
5
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSS
tBSH
tSDH
tSDS
40
16
16
10
10
6
5
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
80
80
50
50
23
23
ns
ns
ns
ns
ns
ns
ns
ns
ns
2015/06
- 17 -
[AK4611]
Parameter
Symbol
Audio Interface Timing (Master mode)
Stereo mode (TDM1 bit = “0”, TDM0 bit = “0”)
(TVDD1= 1.6V3.6V)
BICK Frequency
fBCK
BICK Duty
dBCK
tMBLR
BICK “” to LRCK
tBSD
BICK “” to SDTO
tSDH
SDTI Hold Time
tSDS
SDTI Setup Time
(TVDD1= 3.0V3.6V)
BICK Frequency
fBCK
BICK Duty
dBCK
tMBLR
BICK “” to LRCK
tBSD
BICK “” to SDTO
tSDH
SDTI Hold Time
tSDS
SDTI Setup Time
TDM512 mode (TDM1 bit = “0”, TDM0 bit = “1”)
(TVDD1= 3.0V3.6V)
(Note 17)
BICK Frequency
fBCK
BICK Duty
dBCK
tMBLR
BICK “” to LRCK
tBSS
SDTO Setup time BICK “”
tBSH
SDTO Hold time BICK “”
tSDH
SDTI Hold Time
tSDS
SDTI Setup Time
TDM256 mode (TDM1 bit = “1”, TDM0 bit = “0”)
(TVDD1= 3.0V3.6V)
(Note 18)
BICK Frequency
fBCK
BICK Duty
dBCK
tMBLR
BICK “” to LRCK
tBSS
SDTO Setup time BICK “”
tBSH
SDTO Hold time BICK “”
tSDH
SDTI Hold Time
tSDS
SDTI Setup Time
TDM128 mode (TDM1 bit = “1”, TDM0 bit = “1”)
(TVDD1= 3.0V3.6V)
(Note 19)
BICK Frequency
fBCK
BICK Duty
dBCK
BICK “” to LRCK
tMBLR
tBSS
SDTO Setup time BICK “”
tBSH
SDTO Hold time BICK “”
tSDH
SDTI Hold Time
tSDS
SDTI Setup Time
Note 21. BICK rising edge must not occur at the same time as LRCK edge.
MS1050-E-05
min
typ
max
Unit
40
70
50
50
64fs
50
-
40
70
-
Hz
%
ns
ns
ns
ns
23
23
10
10
64fs
50
-
23
23
-
Hz
%
ns
ns
ns
ns
-10
6
5
10
10
512fs
50
-
10
-
Hz
%
ns
ns
ns
ns
ns
10
6
5
10
10
256fs
50
-
10
-
Hz
%
ns
ns
ns
ns
ns
10
6
5
10
10
128fs
50
-
10
-
Hz
%
ns
ns
ns
ns
ns
2015/06
- 18 -
[AK4611]
Parameter
Symbol
min
Control Interface Timing (4-wire Serial mode):
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
CSN “” to CCLK “”
tCSS
50
CCLK “” to CSN “”
tCSH
50
CDTO Delay
tDCD
CSN “” to CDTO Hi-Z
tCCZ
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling
(Note 22)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
Capacitive load on bus
Cb
Power-down & Reset Timing
PDN Pulse Width
(Note 23)
tPD
150
PDN “” to SDTO valid
(Note 24)
tPDV
Note 22. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 23. The AK4611 can be reset by setting the PDN pin to “L” upon power-up.
Note 24. These cycles are the numbers of LRCK rising from the PDN pin rising.
Note 25. I2C-bus is a trademark of NXP B.V.
MS1050-E-05
typ
518
max
Unit
50
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
400
1.0
0.3
50
400
kHz
s
s
s
s
s
s
s
s
s
s
ns
pF
ns
1/fs
2015/06
- 19 -
[AK4611]
■ Timing Diagram
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fsn, 1/fsd, 1/fsq
VIH
LRCK
VIL
tdLRKH
tdLRKL
Duty
= tdLRKH (or tdLRKL) x fs x 100
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 3. Clock Timing (TDM1/0 bit = “00” & Slave mode)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRH
tLRL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 4. Clock Timing (Except TDM1/0 bit = “00” & Slave mode)
MS1050-E-05
2015/06
- 20 -
[AK4611]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fMCK
MCKO
50%TVDD1
tdMCKH
tdMCKL
dMCK
= tdMCKH (or tdMCKL) x fMCK x 100
1/fs
LRCK
50%TVDD1
tdLRKH
tdLRKL
dLRK
= tdLRKH (or tdLRKL) x fs x 100
1/fBCK
50%TVDD1
BICK
tdBCKH
tdBCKL
dBCK
= tdBCKH (or tdBCKL) x fs x 100
Figure 5. Clock Timing (TDM1/0 bit = “00” & Master mode)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fMCK
MCKO
50%TVDD1
tdMCKH
tdMCKL
dMCK
= tdMCKH (or tdMCKL) x fMCK x 100
1/fs
LRCK
50%TVDD1
tLRH
1/fBCK
50%TVDD1
BICK
tdBCKH
tdBCKL
dBCK
= tdBCKH (or tdBCKL) x fs x 100
Figure 6. Clock Timing (Except TDM1/0 bit = “00” & Master mode)
MS1050-E-05
2015/06
- 21 -
[AK4611]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tLRS
tBSD
SDTO
50%TVDD1
tSDS
tSDH
VIH
SDTI
VIL
Figure 7. Audio Interface Timing (TDM1/0 bit = “00” & Slave mode)
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSH
tBSS
SDTO
50%TVDD1
tSDS
tSDH
VIH
SDTI
VIL
Figure 8. Audio Interface Timing (Except TDM1/0 bit = “00” & Slave mode)
MS1050-E-05
2015/06
- 22 -
[AK4611]
LRCK
50%TVDD1
tMBLR
50%TVDD1
BICK
tBSD
50%TVDD1
SDTO
tSDS
tSDH
VIH
SDTI
VIL
Figure 9. Audio Interface Timing (TDM1/0 bit = “00” & Master mode)
LRCK
50%TVDD1
tMBLR
50%TVDD1
BICK
tBSS
tBSH
50%TVDD1
SDTO
tSDS
tSDH
VIH
SDTI
VIL
Figure 10. Audio Interface Timing (Except TDM1/0 bit = “00” & Master mode)
MS1050-E-05
2015/06
- 23 -
[AK4611]
VIH
CSN
VIL
tCSH
tCSS
tCCKL
tCCKH
VIH
CCLK
VIL
tCDS
tCDH
VIH
CDTI
C1
C0
R/W
VIL
Hi-Z
CDTO
Figure 11. WRITE Command Input Timing (4-wire Serial mode)
tCSW
VIH
CSN
VIL
tCSH
tCSS
VIH
CCLK
VIL
VIH
CDTI
D2
D1
D0
VIL
CDTO
Hi-Z
Figure 12. WRITE Data Input Timing (4-wire Serial mode)
MS1050-E-05
2015/06
- 24 -
[AK4611]
VIH
CSN
VIL
VIH
CCLK
VIL
VIH
CDTI
A1
A0
VIL
tDCD
Hi-Z
CDTO
D7
D6
50%TVDD2
Figure 13. Read Data Output Timing1(4-wire Serial mode)
tCSW
VIH
CSN
VIL
tCSH
tCSS
VIH
CCLK
VIL
VIH
CDTI
VIL
tCCZ
CDTO
D2
D1
D0
Hi-Z
50%TVDD2
Figure 14. Read Data Output Timing2(4-wire Serial mode)
MS1050-E-05
2015/06
- 25 -
[AK4611]
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
Figure 15. I2C Bus mode Timing
tPD
VIH
PDN
VIL
tPDV
SDTO
50%TVDD1
Figure 16. Power-down & Reset Timing
MS1050-E-05
2015/06
- 26 -
[AK4611]
OPERATION OVERVIEW
■ System Clock
It is possible to select the clock source either extra clock input or X’tal input for the AK4611. (Figure 17, Figure 18) The
external clocks which are required to operate the AK4611 in slave mode are MCLK, LRCK and BICK. MCLK should be
synchronized with LRCK but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting
Mode (ACKS bit= “0”: Default), the sampling speed is set by DFS0, DFS1 (Table 1). The frequency of MCLK at each
sampling speed is set automatically. (Table 3, Table 4, Table 5). In Auto Setting Mode (ACKS bit= “1”), as MCLK
frequency is detected automatically (Table 6) and the internal master clock attains the appropriate frequency (Table 7), so
it is not necessary to set DFS.
In master mode, only MCLK is required. Master Clock Input Frequency should be set with the CKS1-0 bits, and the
sampling speed should be set by the DFS1-0 bits. The frequencies and the duties of the clocks (LRCK, BICK) are not
stabile immediately after setting CKS1-0 bits and DFS1-0 bits up.
After exiting reset at power-up in slave mode, the AK4611 is in power-down mode until MCLK and LRCK are input.
If the clock is stopped, click noise occurs when restarting the clock. Mute the digital output externally if the click noise
influences system applications.
DFS1
0
0
1
1
DFS0
0
1
0
1
Sampling Speed Mode (fs)
(default)
Normal Speed Mode
32kHz~48kHz
Double Speed Mode
64kHz~96kHz
Quad Speed Mode
128kHz~192kHz
N/A
(N/A: Not available)
Table 1. Sampling Speed (Manual Setting Mode)
CKS1
CKS0
0
0
1
1
0
1
0
1
Normal Speed
Mode
256fs
384fs
512fs
512fs
Double Speed
Mode
256fs
256fs
256fs
256fs
Quad Speed
Mode
128fs
128fs
128fs
128fs
(default)
Table 2. Master Clock Input Frequency Select (Master Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920
11.2896
12.2880
MCLK (MHz)
384fs
12.2880
16.9344
18.4320
512fs
16.3840
22.5792
24.5760
BICK (MHz)
64fs
2.0480
2.8224
3.0720
Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode)
MS1050-E-05
2015/06
- 27 -
[AK4611]
LRCK
fs
88.2kHz
96.0kHz
MCLK (MHz)
256fs
22.5792
24.5760
BICK (MHz)
64fs
5.6448
6.1440
Table 4. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK
fs
176.4kHz
192.0kHz
MCLK (MHz)
128fs
22.5792
24.5760
BICK (MHz)
64fs
11.2896
12.2880
Table 5. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MCLK
512fs
256fs
128fs
Sampling Speed Mode
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Table 6. Sampling Speed (Auto Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
22.5792
24.5760
MCLK (MHz)
256fs
22.5792
24.5760
-
512fs
16.3840
22.5792
24.5760
-
Sampling
Speed Mode
Normal Speed
Mode
Double Speed
Mode
Quad Speed
Mode
Table 7. System Clock Example (Auto Setting Mode)
MS1050-E-05
2015/06
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[AK4611]
■ Clock Source
The clock for the XTI pin can be generated by the two methods.
1) External clock
XTI
External Clock
AK4611
XTO
Figure 17. External clock mode
Note: Input clock must not exceed TVDD1.
2) X’tal
XTI
AK4611
XTO
Figure 18. X’tal mode
Note: External capacitance depends on the crystal oscillator (Typ. 10pF)
TVDD1 should be used in the range of 3.0 ~ 3.6V in X’tal mode.
MS1050-E-05
2015/06
- 29 -
[AK4611]
■ Differential / Single-End Input selection
The AK4611 supports the differential input (Figure 19) by setting DIE1-2 bits = “1”, supports the single-end input (Figure
20) by setting DIE1-2 bits = “0”. In differential input mode, two input pins must not be connected to a signal input in
combination with a VCOM voltage. When single-end input mode, L/RIN1-/2- pins should be open, because L/RIN1-/2pins output an invert signal of the input signal. The AK4611 includes an anti-aliasing filter (RC filter) for both differential
input and the single-end input.
AK4611
L/RIN+
AK4611
L/RIN
LPF
LPF
SCF
L/RIN-
SCF
LPF
L/RIN(Open)
Figure 19. Differential Input (DIE1-2 bit = “1”)
Figure 20. Single-end Input (DIE1-2 bit = “0”)
■ Differential / Single-End Output selection
The AK4611 supports the differential output (Figure 21) by setting DOE1-4 bits = “1”, and the single-end output (Figure
22) by setting DOE1-4 bits = “0”. When single-end output mode, L/ROUT1-4 pins should be open, because of
L/ROUT1-4 pins outputs VCOM voltage. The internal analog filters remove most of the noise beyond the audio passband
generated by the delta-sigma modulator of a DAC in single-end input mode. There is no internal analog filter for
differential output. Use external analog filters if needed to remove this noise.
AK4611
AK4611
L/ROUT+
LPF
SCF
SCF
L/ROUT-
Figure 21. Differential Output (DOE1-4 bit = “1”)
L/ROUT
Diff
to
Single
L/ROUT(Open)
Figure 22. Single-end Output (DOE1-4 bit = “0”)
MS1050-E-05
2015/06
- 30 -
[AK4611]
■ De-emphasis Filter
The AK4611 has a digital de-emphasis filter (tc=50/15µs) by an IIR filter. The de-emphasis filter supports only Normal
Speed Mode. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis of each DAC
can be set individually by registers, DAC1(SDTI1), DAC2(SDTI2), DAC3(SDTI3), DAC4(SDTI4).
Mode
Sampling Speed Mode
0
1
2
3
Normal Speed Mode
Normal Speed Mode
Normal Speed Mode
Normal Speed Mode
DEM11
(DEM61-21)
0
0
1
1
DEM10
(DEM60-20)
0
1
0
1
DEM
44.1kHz
OFF
48kHz
32kHz
(default)
Table 8. De-emphasis control
■ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz
and scales with the sampling rate (fs).
■ Master Clock Output
The AK4611 has a master clock output pin. If DIV bit = “1”, the MCKO pin output the frequency divided in half.
DIV
0
1
MCKO
XTI x1
XTI x1/2
(default)
Table 9. The select of Master clock output frequency
■ Master Mode and Slave Mode
Master Mode and Slave Mode are selected by setting the M/S pin. (Master Mode= “H”, Slave Mode= “L”)
LRCK and BICK pins are outputs in Master Mode (M/S pin= “H”)
LRCK and BICK pins are inputs in Slave Mode (M/S pin= “L”)
PDN
L
H
M/S pin
L
H
L
H
LRCK pin
Input
“L” Output
Input
Output
BICK pin
Input
“L” Output
Input
Output
Table 10. LRCK and BICK pins
MS1050-E-05
2015/06
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[AK4611]
■ Audio Serial Interface Format
(1) Stereo Mode
When TDM1-0 bits = “00”, ten modes can be selected by the DIF2-0 bits as shown in Table 11. In all modes the serial data
is MSB-first, 2’s compliment format. The data SDTO1-2 is clocked out on the falling edge of BICK and the SDTI1-4 is
latched on the rising edge of BICK.
Mode3/4/8/9/13/14/18/19/23/24/28/29/33/34/38/39 in SDTI input formats can be used for 16-20bit data by zeroing the
unused LSBs.
Mode
M/S
TDM1
TDM0
DIF2
DIF1
DIF0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
2
0
0
0
0
1
0
3
0
0
0
0
1
1
4
0
0
0
1
0
0
5
1
0
0
0
0
0
6
1
0
0
0
0
1
7
1
0
0
0
1
0
8
1
0
0
0
1
1
9
1
0
0
1
0
0
SDTO1-2
SDTI1-4
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
16bit, Right
justified
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I2S
16bit, Right
justified
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I2S
LRCK
I/O
BICK
I/O
H/L
I
 32fs
I
H/L
I
 48fs
I
H/L
I
 48fs
I
H/L
I
 48fs
I
L/H
I
 48fs
I
H/L
O
64fs
O
H/L
O
64fs
O
H/L
O
64fs
O
H/L
O
64fs
O
L/H
O
64fs
O
(default)
Table 11. Audio data formats (Stereo mode)
Note. TVDD1 which is the Power of I/O buffer should be kept in the range of 1.6V~3.6V at Normal Speed Mode in Stereo
Mode. TVDD1 should be kept in the range of 3.0V~3.6V at Double Speed Mode and Quad Speed Mode.
MS1050-E-05
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[AK4611]
(2) TDM Mode
The audio serial interface format is set in TDM mode by the TDM1-0 bits = “01”. Five modes can be selected by the
DIF2-0 bits as shown in Table 12. In all modes the serial data is MSB-first, 2’s compliment format. The SDTO1 is clocked
out on the rising edge of BICK and the SDTI1/2/3 are latched on the rising edge of BICK. In the TDM512 mode (fs =
48kHz), the serial data of all ADC (four channels) is output to the SDTO1 pin. SDTO2 pin = “L”. And the serial data of all
DAC (eight channels) is input to the SDTI1 pin. The input data to SDTI2-4 pins are ignored. BICK should be fixed to
512fs. “H” time and “L” time of LRCK should be 1/512fs at least.
TDM256 mode can be set by TDM1-0 bits as show in Table 13. In the TDM256 mode (fs = 96kHz), the serial data of all
ADC (four channels) is output to the SDTO1 pin. SDTO2 pin = “L”. And the serial data of DAC (eight channels; L1, R1,
L2, R2, L3, R3, L4, R4) is input to the SDTI1 pin. The input data to SDTI2-4 pins are ignored. BICK should be fixed to
256fs. “H” time and “L” time of LRCK should be 1/256fs at least. TDM128 mode can be set by TDM1-0 bits as show in
Table 14.
In TDM128 mode (fs=192kHz), the serial data of four ADC (four channels; L1, R1, L2, R2) is output to the SDTO1 pin.
The SDTO2 pin = “L”. And the serial data of DAC (four channels; L1, R1, L2, R2) is input to the SDTI1 pin and the serial
data of DAC (four channels; L3, R3, L4, R4) is input to the SDTI2 pin. The input data to SDTI3-4 pins are ignored. BICK
should be fixed to 128fs. “H” time and “L” time of LRCK should be 1/128fs at least.
Mode
M/S
TDM1
TDM0
DIF2
DIF1
DIF0
10
0
0
1
0
0
0
11
0
0
1
0
0
1
12
0
0
1
0
1
0
13
0
0
1
0
1
1
14
0
0
1
1
0
0
15
1
0
1
0
0
0
16
1
0
1
0
0
1
17
1
0
1
0
1
0
18
1
0
1
0
1
1
19
1
0
1
1
0
0
SDTO1-2
SDTI1-4
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
16bit, Right
justified
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I2S
16bit, Right
justified
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I2S
LRCK
I/O
BICK
I/O

I
512fs
I

I
512fs
I

I
512fs
I

I
512fs
I

I
512fs
I

O
512fs
O

O
512fs
O

O
512fs
O

O
512fs
O

O
512fs
O
Table 12. Audio data formats (TDM512 mode)
MS1050-E-05
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[AK4611]
Mode
M/S
TDM1
TDM0
DIF2
DIF1
DIF0
20
0
1
0
0
0
0
21
0
1
0
0
0
1
22
0
1
0
0
1
0
23
0
1
0
0
1
1
24
0
1
0
1
0
0
25
1
1
0
0
0
0
26
1
1
0
0
0
1
27
1
1
0
0
1
0
28
1
1
0
0
1
1
29
1
1
0
1
0
0
SDTO1-2
SDTI1-4
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
16bit, Right
justified
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I2S
16bit, Right
justified
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I2S
LRCK
I/O
BICK
I/O

I
256fs
I

I
256fs
I

I
256fs
I

I
256fs
I

I
256fs
I

O
256fs
O

O
256fs
O

O
256fs
O

O
256fs
O

O
256fs
O
Table 13. Audio data formats (TDM256 mode)
Mode
M/S
TDM1
TDM0
DIF2
DIF1
DIF0
30
0
1
1
0
0
0
31
0
1
1
0
0
1
32
0
1
1
0
1
0
33
0
1
1
0
1
1
34
0
1
1
1
0
0
35
1
1
1
0
0
0
36
1
1
1
0
0
1
37
1
1
1
0
1
0
38
1
1
1
0
1
1
39
1
1
1
1
0
0
SDTO1-2
SDTI1-4
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
16bit, Right
justified
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I2S
16bit, Right
justified
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I2S
LRCK
I/O
BICK
I/O

I
128fs
I

I
128fs
I

I
128fs
I

I
128fs
I

I
128fs
I

O
128fs
O

O
128fs
O

O
128fs
O

O
128fs
O

O
128fs
O
Table 14. Audio data formats (TDM128 mode)
Note. TVDD1 should be used in the range of 3.0V~3.6V in TDM mode.
MS1050-E-05
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[AK4611]
LRCK
0
1
2
16
17
18
24
25
31
0
1
2
16
17
18
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
8
7
Don’t Care
6
0
15 14
8
23 22
7
1
8
7
Don’t Care
0
6
0
15 14
SDTO-23:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
23
8
7
1
0
Rch Data
Figure 23. Mode 0/5 Timing (Stereo Mode)
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
12 11 10
0
19 18
8
Don’t Care
23 22
7
1
12
11 10
Don’t Care
0
0
19 18
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
23
8
7
1
0
Rch Data
Figure 24. Mode 1/6 Timing (Stereo Mode)
LRCK
0
1
2
8
9
10
24
25
31
0
1
2
8
9
10
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
16 15 14
Don’t Care
0
23 22
23:MSB, 0:LSB
23 22
8
7
1
16 15 14
Don’t Care
0
0
23 22
Lch Data
23
8
7
1
0
Rch Data
Figure 25. Mode 2/7 Timing (Stereo Mode)
LRCK
0
1
2
21
22
23
24
28
29
30
31
0
1
2
22
23
24
28
29
30
31
0
1
BICK(64fs)
SDTO(o)
23 22
2
1
0
SDTI(i)
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
23
Don’t Care
23
Rch Data
Figure 26. Mode 3/8 Timing (Stereo Mode)
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[AK4611]
LRCK
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
2
1
0
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
Don’t Care
Rch Data
Figure 27. Mode 4/9 Timing (Stereo Mode)
512BICK
LRCK(Mode15)
LRCK(Mode10)
BICK(512fs)
SDTO1(o)
23 22
0
23 22
L1
0
23 22
R1
0
23 22
L2
0
23 22
R2
32 BICK 32 BICK 32 BICK 32 BICK
SDTI1(i)
15 14
0
15 14
0
R1
L1
15 14
0
15 14
0
R2
L2
15 14
0
15 14
0
R3
L3
15 14
0
15 14
0
15
R4
L4
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 28. Mode 10/15 Timing (TDM512 Mode)
512BICK
LRCK(Mode16)
LRCK(Mode11)
BICK(512fs)
SDTO1(o)
23 22
0
23 22
L1
0
23 22
R1
0
23 22
L2
0
23 22
R2
32 BICK 32 BICK 32 BICK 32 BICK
SDTI1(i)
19 18
0
19 18
0
R1
L1
19 18
0
19 18
0
R2
L2
19 18
0
19 18
0
R3
L3
19 18
0
19 18
0
19
R4
L4
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 29. Mode 11/16 Timing (TDM512 Mode)
512BICK
LRCK(Mode17)
LRCK(Mode12)
BICK(512fs)
SDTO1(o)
23 22
0
23 22
L1
0
23 22
R1
0
23 22
L2
0
23 22
R2
32 BICK 32 BICK 32 BICK 32 BICK
SDTI1(i)
23 22
L1
0
23 22
R1
0
23 22
L2
0
23 22
R2
0
23 22
L3
0
23 22
R3
0
23 22
0
L4
23 22
0
23
R4
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 30. Mode 12/17 Timing (TDM512 Mode)
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[AK4611]
512BICK
LRCK(Mode18)
LRCK(Mode13)
BICK(512fs)
SDTO1(o)
23 22
0
23 22
L1
0
R1
23 22
0
23 22
L2
0
23 22
R2
32 BICK 32 BICK 32 BICK 32 BICK
SDTI1(i)
23 22
0
23 22
0
R1
L1
23 22
0
23 22
23 22
0
R2
L2
0
23 22
0
23 22
R3
L3
0
23 22
23 22
0
R4
L4
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 31. Mode 13/18 Timing (TDM512 Mode)
512BICK
LRCK(Mode19)
LRCK(Mode14)
BICK(512fs)
SDTO1(o)
23
0
L1
23
0
R1
23
0
23
L2
0
23
R2
32 BICK 32 BICK 32 BICK 32 BICK
SDTI1(i)
23
0
L1
23
0
R1
23
0
23
0
23
R2
L2
0
23
0
23
R3
L3
0
23
0
23
R4
L4
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 32. Mode 14/19 Timing (TDM512 Mode)
256 BICK
LRCK (Mode25)
LRCK (Mode20)
BICK(256fs)
SDTO1(o)
SDTI1(i)
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
15 14
0
4
15 14
0
15 14
0
23 22
0
15 14
0
15 14
0
15 14
0
15 14
0
15 14
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0
15
Figure 33. Mode 20/25 Timing (TDM256 Mode)
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[AK4611]
256 BICK
LRCK (Mode26)
LRCK (Mode21)
BICK(256fs)
SDTO1(o)
SDTI1(i)
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
19 18
0
19 18
0
19 18
0
23 22
0
19 18
0
19 18
0
19 18
0
19 18
0
19 18
0
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
19
Figure 34. Mode 21/26 Timing (TDM256 Mode)
256 BICK
LRCK (Mode27)
LRCK (Mode22)
BICK(256fs)
SDTO1(o)
SDTI1(i)
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
Figure 35. Mode 22/27 Timing (TDM256 Mode)
256 BICK
LRCK (Mode28)
LRCK (Mode23)
BICK(256fs)
SDTO1(o)
SDTI1(i)
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
0
23 22
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23 22
Figure 36. Mode 23/28 Timing (TDM256 Mode)
MS1050-E-05
2015/06
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[AK4611]
256 BICK
LRCK (Mode29)
LRCK (Mode24)
BICK(256fs)
SDTO1(o)
SDTI1(i)
23
0
23
0
23
0
23
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23
0
23
0
23
0
23
23
0
23
0
23
0
23
0
23
0
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
Figure 37. Mode 24/29 Timing (TDM256 Mode)
128 BICK
LRCK (Mode35)
LRCK (Mode30)
BICK(128fs)
SDTO1(o)
SDTI1(i)
SDTI2(i)
23 22
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
15 14
0
0
15 14
15 14
0
15 14
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
0
15 14
0
15 14
15 14
0
23 22
0
15 14
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
0
15
0
15
Figure 38. Mode 30/35 Timing (TDM128 Mode)
MS1050-E-05
2015/06
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[AK4611]
128 BICK
LRCK (Mode36)
LRCK (Mode31)
BICK(128fs)
SDTO1(o)
SDTI1(i)
SDTI2(i)
23 22
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
19 18
0
0
19 18
19 18
0
19 18
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
0
19 18
0
19 18
19 18
0
23 22
0
19 18
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
0
19
0
19
Figure 39. Mode 31/36 Timing (TDM128 Mode)
128 BICK
LRCK (Mode37)
LRCK (Mode32)
BICK(128fs)
SDTO1(o)
SDTI1(i)
SDTI2(i)
23 22
23 22
0
0
23 22
23 22
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
0
23 22
23 22
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
0
23 22
0
23 22
23 22
0
23 22
0
23 22
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
0
23
0
23
Figure 40. Mode 32/37 Timing (TDM128 Mode)
MS1050-E-05
2015/06
- 40 -
[AK4611]
128 BICK
LRCK (Mode38)
LRCK (Mode33)
BICK(128fs)
SDTO1(o)
SDTI1(i)
SDTI2(i)
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
0
23 22
23 22
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
0
23 22
0
23 22
23 22
0
23 22
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
0
23 22
0
23 22
0
23 22
0
23
0
23
0
23
Figure 41. Mode 33/38 Timing (TDM128 Mode)
128 BICK
LRCK (Mode39)
LRCK (Mode34)
BICK(128fs)
SDTO1(o)
SDTI1(i)
SDTI2(i)
22
0
23
0
23
0
23
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
0
23
0
23
0
23
23
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
0
23
0
23
0
23
23
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
Figure 42. Mode 34/39 Timing (TDM128 Mode)
MS1050-E-05
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- 41 -
[AK4611]
■ Overflow Detection
The AK4611 has an overflow detect function for the analog input. The overflow detect function is enabled when the
OVFE bit is set to “1”. Overflow detection is applied to the analog input of each channel, and the result is OR’d. OVF1/2
pins goes to “H” according to the group set by OVFM2-0 bits, if analog input of Lch or Rch overflows (more than
-0.3dBFS). When the analog input is overflowed, the output signal of OVF1/2 pins have the same group delay as ADC
(GD = 16/fs = 333s @fs=48kHz). OVF1/2 pins are “L” for 518/fs (=11.8ms @fs=48kHz) after PDN = “”, and then
overflow detection is enabled.
Mode
0
1
2
3
4
5
6
7
OVFM2
0
0
0
0
1
1
1
1
OVFM1
0
0
1
1
0
0
1
1
OVFM0
0
1
0
1
0
1
0
1
LIN1 or RIN1
OVF1
OVF1
OVF2
OVF2
LIN2 or RIN2
OVF1
OVF2
OVF1
OVF2
disable (OVF2=OVF1= “L”)
(default)
Table 15. Overflow detect control (OVFE bit = “1”)
■ Zero Detection
The AK4611 has two pins for zero detect flag outputs. Zero detect function is enabled when the OVFE bit is set to “0”.
Channel grouping can be selected by the DZFM3-0 bits. (Table 16) The DZF1 pin corresponds to the group 1 channels
and the DZF2 pin corresponds to the group 2 channels. DZF1 is AND operation of all eight channels and DZF2 is disabled
(“L”) at mode 0, “H” at mode 1-3. When the input data of all channels in the group 1(group 2) are continuously zeros for
8192 LRCK cycles, the DZF1 (DZF2) pin goes to “H”. The DZF1 (DZF2) pin immediately returns to “L” if input data of
any channels in the group 1(group 2) is not zero.
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DZFM
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
L1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
R1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
L2
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF2
AOUT
R2
L3
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
R3
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
L4
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
R4
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
disable (DZF1=DZF2= “L”)
(default)
Table 16. Zero detect control (OVFE bit = “0”)
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[AK4611]
■ Digital Attenuator
AK4611 has a channel-independent digital attenuator (256 levels, 0.5dB steps). Attenuation level of each channel can be
set by each the ATT7-0 bits (Table 17).
ATT7-0
00H
01H
02H
:
7DH
7EH
7FH
FEH
FFH
Attenuation Level
0dB
-0.5dB
-1.0dB
:
-62.5dB
-63.0dB
-63.5dB
:
-127.0dB
MUTE (-∞)
(default)
Table 17. Attenuation level of digital attenuator
Transition time between set values of ATT7-0 bits can be selected by the ATS1-0 bits (Table 18). Transition between set
values is the soft transition in Mode1/2/3 eliminating switching noise in the transition.
Mode
0
1
2
3
ATS1
0
0
1
1
ATS0
0
1
0
1
ATT speed
4096/fs
2048/fs
512/fs
256/fs
(default)
Table 18. Transition time between set values of ATT7-0 bits
The transition between set values is a soft transition of 4096 levels in mode 0. It takes 4096/fs ([email protected]=48kHz) from
00H(0dB) to FFH(MUTE). If the PDN pin goes to “L”, the ATTs are initialized to 00H. The ATTs also become 00H when
RSTN bit = “0”, and fade to their current value when RSTN bit returns to “1”.
* A power-down release command must be write again (dummy write) after 5 LRCK cycles or later form the first
command when releasing power-down mode by PMVR, PMDAC, RSTN, PMDA1, PMDA2, PMDA3 or PMDA4 bit
in I2C mode. If this dummy write is not executed, DATT output will keep the initial value (0dB) until the next write is
executed.
> 5LRCK (5/fs)
LRCK
I2C
ContIrol
Power-down Release
Command
Power-down Release
Command (Dummy)
A power-down release command must be write again
after 5 LRCK cycle or later from the first command.
Figure 43. Power-up Sequence Example
MS1050-E-05
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- 43 -
[AK4611]
■ Soft Mute Operation
Soft mute operation is performed in the digital domain. When the SMUTE bit becomes “1”, the output signal is attenuated
to - in the cycle set by ATS bits (Table 18) from the current ATT level. When the SMUTE bit is returned to “0”, the
mute is cancelled and the output attenuation gradually changes to the ATT level in the cycle set by ATS bits. If the soft
mute is cancelled before attenuating to - after starting the operation, attenuation is discontinued and it is returned to ATT
level by the same cycle. Soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTE bit
ATT Level
(1)
(2)
(4)
Attenuation
-
GD
(3)
GD
AOUT
DZF1,2
(5)
8192/fs
Notes:
(1) The time for input data attenuation to - (Table 18). For example, in Normal Speed Mode, this time is 4096LRCK
cycles (4096/fs) at ATT_DATA=00H. ATT transition of the soft-mute is from 00H to FFH
(2) The time for input data recovery to ATT level (Table 18). For example, in Normal Speed Mode, this time is
4096LRCK cycles (4096/fs) at ATT-DATA=FFH. ATT transition of soft-mute is from FFH to 00H.
(3) The analog output corresponding to the digital input has group delay, GD.
(4) If the soft mute is cancelled before attenuating to -, the attenuation is discontinued and returned to ATT level by
the same cycle.
(5) When the input data at all the channels of the group are continuously zeros for 8192 LRCK cycles, DZF1, 2 pins of
each channel goes to “H”. DZF1/2 pins immediately returns to “L” if the input data of either channel of the group
are not zero after going “H”.
Figure 44. Soft mute and zero detection
■ System Reset
The AK4611 should be reset once by bringing the PDN pin = “L” upon power-up. The AK4611 is powered up and the
internal timing starts clocking by LRCK “” after exiting the power down state of reference voltage (such as VCOM) by
MCLK. The AK4611 is in power-down mode until MCLK and LRCK are input.
MS1050-E-05
2015/06
- 44 -
[AK4611]
■ Power-Down
All ADCs and DACs of the AK4611 are placed in power-down mode by bringing the PDN pin “L” which resets both
digital filters at the same time. The PDN pin “L” also resets the control registers to their default values. In power-down
mode, when the DVMPD pin “L”, the analog outputs go to VCOM voltage, when the DVMPD pin =“H”, the analog
outputs go to Hi-Z. The SDTO1-2, DZF1-2 pins go to “L” in the power-dwon mode. This reset should always be executed
after power-up. For the ADC, an analog initialization cycle (518/fs) starts 3~4/fs after exiting power-down mode. The
output data, SDTO1-2, is available after 521~522 cycles of the LRCK clock. For the DAC, an analog initialization cycle
(516/fs) starts 3~4/fs after exiting power-down mode. The analog outputs are VCOM voltage when the DVMPD =pin
“L”, and the analog outputs go to Hi-Z when the DVMPD pin =“H” during the initialization. Figure 45 shows the
power-down and power-up sequences.
Power
3~4/fs
PDN
(10)
(12)
518/fs
ADC Internal
State
(1)
Init Cycle
Normal Operation
Power-down
Normal Operation
Power-down
516/fs (2)
DAC Internal
State
Init Cycle
GD (3)
GD
ADC In
(Analog)
ADC Out
(Digital)
“0”data
DAC In
(Digital)
“0”data
(6)
(4)
“0”data
“0”data
(3)
GD
DAC Out
(Analog)
(5)
GD
(7)
(7)
(7)
Clock In
Don’t care
Don’t care
MCLK,LRCK,SCLK
10~11/fs (11)
(7)
DZF1/DZF2
External
Mute
Don’t care
Mute ON
Mute ON
(9)
Notes:
(1) The analog part of ADC is initialized after exiting power-down state.
(2) The analog part of DAC is initialized after exiting power-down state.
(3) Digital output corresponds to analog input and analog output corresponds to digital input have group delay (GD).
(4) ADC output is “0” data at power-down state.
(5) The analog outputs are VCOM voltage when the DVMPD pin “L”, and the analog outputs go to Hi-Z when the
DVMPD pin “H” in power-down mode.
(6) Click noise occurs at the end of initialization of the analog part. Mute the digital output externally if the click noise
influences system applications.
(7) Click noise occurs at the falling edge of PDN and at 519~520/fs after the rising edge of the PDN pin.
(8) DZF1-2 pins are “L” in power-down mode (PDN pin = “L”).
(9) Please mute the analog output externally if the click noise (7) influences system applications.
(10) There is a delay, 3~4/fs from PDN pin “H” to the start of initial cycle.
(11) DZF pin= “L” for 1011/fs after PDN pin = “”.
(12) The PDN pin must be “L” when power up the AK4611 and set to “H” after all poweres are supplied.
Figure 45. Pin power-down/Pin power-up sequence example
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[AK4611]
All ADCs and all DACs can be powered-down individually through the PMADC bits and PMDAC bits, when the PMVR
bit “1”. ADC1-2 can be power-down individually through the PMAD2-1 bits. DAC1-4 can be power-down individually
by PMDA4-1 bits. In this case, the internal register values are not initialized. When PMADC bit = “0”, SDTO1-2 goes to
“L”. When PMDAC bit = “0”, the analog outputs go to VCOM voltage when the DVMPD pin is “L”, and the analog
outputs go to Hi-Z when the DVMPD pin “H”. When PMDAC bit = “0”, DZF1-2 pins go to “H”. As some click noise
occurs, the analog output should be muted externally if the click noise influences system applications. Figure 46 shows
the power-down and power-up sequences.
PMVR bit
4~5/fs (10)
3~4/fs (11)
PMADC/PMDAC bit
518/fs
ADC Internal
State
Normal Operation
Power-down
(1)
Init Cycle
Normal Operation
516/fs (2)
DAC Internal
State
Normal Operation
Power-down
Init Cycle
Normal Operation
GD (3)
GD
ADC In
(Analog)
ADC Out
(Digital)
“0”data
DAC In
(Digital)
(4)
(6)
“0”data
GD
(3)
GD
(7)
DAC Out
(Analog)
Clock In
(5)
(7)
Don’t care
MCLK,LRCK,SCLK
(8)
89/fs (12)
DZF1/DZF2
External
Mute
(9)
Mute ON
Notes:
(1) The analog section of ADC is initialized after exiting power-down state.
(2) The analog section of DAC is initialized after exiting power-down state.
(3) Digital output corresponding to the analog inputs and analog outputs corresponding to the digital inputs have group
delay (GD).
(4) ADC output is “0” data at power-down state.
(5) The analog outputs are VCOM voltage when the DVMPD pin “L”, and the analog outputs go to Hi-Z when the
DVMPD pin “H” in power-down mode.
(6) Click noise occurs at the end of initialization of the analog part. Mute the digital output externally if the click noise
influences system application.
(7) Click noise occurs at 45/fs after PMDAC bit becomes “0”, and occurs at 519520/fs after PMDAC bit becomes
“1”.
(8) DZF1-2 pins are “H” in power-down mode (PMDAC bit = “0”).
(9) Mute the analog output externally if the click noise (7) influences system application.
(10) There is a delay, 4~5/fs from PMDAC bit becomes “0” to the applicable ADC power-down.
There is a delay, 4~5/fs from PMDAC bit becomes “0” to the applicable DAC power-down.
(11) There is a delay, 3~4/fs from PMADC and PMDAC bits become “1” to the start of initial cycle.
(12) DZF pin= “L” for 89/fs after PMDAC bit becomes “1”.
Figure 46. Bit power-down/Bit power-up sequence example
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[AK4611]
■ Reset Function
When RSTN bit= “0”, the analog and digital part of ADC and the digital part of DACs are powered-down, but the internal
register are not initialized. The analog outputs go to VCOM voltage regardless of the DVMPD pin setting, then DZF1-2
pins go to “H” and SDTO1-2 pins go to “L”. As some click noise occurs, the analog output should be muted externally if
the click noise influences system application. Figure 47 shows the power-up sequence.
RSTN bit
4~5/fs (8)
3~4/fs (9)
Internal
RSTN bit
518/fs (1)
ADC Internal
State
Normal Operation
Power-down
DAC Internal
State
Normal Operation
Digital Block Power-down
Normal Operation
Init Cycle
Normal Operation
GD (2)
GD
ADC In
(Analog)
ADC Out
(Digital)
(3)
“0”data
DAC In
(Digital)
(4)
“0”data
(2)
GD
DAC Out
(Analog)
Clock In
MCLK,LRCK,SCLK
GD
(6)
(5)
(6)
Don’t care
89/fs (7)
DZF1/DZF2
Notes:
(1) The analog section of the ADC is initialized after exiting reset state.
(2) Digital output corresponding to the analog inputs, and analog outputs corresponding to the digital inputs have group
delay (GD).
(3) ADC output is “0” data at power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Mute the digital output externally if the click noise
influences system application.
(5) The analog outputs go to VCOM voltage regardless of the DVMPD pin setting when RSTN bit becomes “0”.
(6) Click noise occurs at 45/fs after RSTN bit becomes “0”, and occurs at 34/fs after RSTN bit becomes “1”.
(7) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 8~9/fs after RSTN bit becomes “1”.
(8) There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”.
(9) There is a delay, 3~4/fs from RSTN bit “1” to the start of initial cycle.
Figure 47. Reset sequence example
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[AK4611]
■ ADC partial Power-Down Function
All of the ADCs can be powered-down individually by PMAD2-1 bits. The analog section and the digital section of the
ADC are in power-down mode when the PMAD2-1 bits = “0”. The analog section of ADCs are initialized after exiting the
power-down state. Digital output corresponding to analog input have group delay (GD). ADC output is “0” data at the
power-down state. Click noise occurs when the internal RSTN bit becomes “1”. Mute the digital output externally if the
click noise influences system applications. Figure 48 shows the power-down and power-up sequences by PMAD2-1 bits.
PMAD2-1 bit
4~5/fs (1)
Power Down Channel
ADCDigital
Internal State
Normal Operation
2~3/fs (2)
Power-down
2~3/fs (2)
4~5/fs (1)
Normal Operation
Power-down
518/fs (3)
ADC Analog
Internal State
Normal Operation
Power-down
Init Cycle
Normal Operation
518/fs (3)
Normal Operation Power-down
Init Cycle
Normal Operation
(4)
GD
GD (4)
ADC In
(Analog)
(5)
“0”data
ADC Out
(Digital)
Normal Operation Channel
(6)
GD (4)
(6)
GD (4)
ADC In
(Analog)
ADC Out
(Digital)
(5)
“0”data
Clock In
MCLK,LRCK,SCLK
Notes.
(1) There is a delay, 4~5/fs from PMAD2-1 bits become “0” to the applicable ADC power-down.
(2) There is a delay, 2~3/fs from PMAD2-1 bits “1” to the start of initial cycle.
(3) The analog section of the ADC is initialized after exiting reset state.
(4) Analog output corresponding to the digital inputs have group delay (GD).
(5) ADC output is “0” data at power-down state.
(6) Click noise occurs when the internal RSTN bit becomes “1”. Mute the digital output externally if the click noise
influences system application.
Figure 48. ADC partial power-down example
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[AK4611]
■ DAC partial Power-Down Function
All of the DACs can be powered-down individually by PMDA4-1 bits. The analog section and the digital section of the
DAC are placed in power-down mode when the PMDA4-1 bits = “0”. The analog output of the powered-down channels,
which is by PMDA4-1 bits, go to the voltage of VCOM when the DVMPD pin is “L”, and go to Hi-Z when the DVMPD
pin “H”. Although DZF detection is in operation, the AK4611 stops reflecting the result of DZF detection to DZF1-2 pins.
Some click noise occurs in both set-up and release of power-down. Mute the analog output externally or set PMDA4-1
bits when PMDAC bit = “0” or RSTN bit = “0”, if click noise aversely affects system performance. Figure 49 shows the
sequence of the power-down and the power-up by PMDA4-1 bits.
PMDA4-1 bit
4~5/fs (4)
Power Down Channel
2~3/fs (5)
DAC Digital
Internal State
Normal Operation
Power-down
DAC Analog
Internal State
Normal Operation
Power-down
2~3/fs (5)
4~5/fs (4)
Normal Operation
Power-down
516/fs (6)
DAC In
(Digital)
Init Cycle
Normal Operation
516/fs (6)
Normal Operation Power-down
Init Cycle
Normal Operation
“0”data
(1)
GD
GD
(3)
DAC Out
(Analog)
(2)
(3)
(3)
(2)
(3)
8192/fs
DZF Detect
Internal State
(7)
(7)
Normal Operation Channel
DAC In
(Digital)
“0”data
GD
GD
DAC Out
(Analog)
8192/fs
DZF Detect
Internal State
Clock In
MCLK,LRCK,SCLK
(8)
(9)
DZF1/DZF2
Notes:
(1) Digital output corresponding to the analog inputs, and analog outputs corresponding to the digital inputs have group
delay (GD).
(2) Analog output of the DAC powered down by PMDA4-1 = “0” and goes to VCOM voltage when the DVMPD pin
=“L”, and the analog outputs go to Hi-Z when the DVMPD pin =“H”.
(3) Click noise occurs at 45/fs after RSTN bit becomes “0”, and occurs at 34/fs after RSTN bit becomes “1”. after
PMDA4-1 bits are changed, some click noise occurs immediately at output of the channel changed by the own PD
bits.
(4) The DACs will be powered-down 4~5fs after PMDA4-1 bits = “0”
(5) The initiation stars 2~3fs after PMDA4-1 bits are set to “1”.
(6) The analog parts of DACs are initilised after exiting power down mode.
(7) Although DZF detection is active at a certain channel set up though PMDA4-1 = “0”, the AK4611 stops reflecting
the result of DZF detection to DZF1-2 pins.
(8) DZF detection of the DAC which is set up by the power-down setting is ignored, and DZF1-2 pins go to “H”.
(9) When signal is input to a DAC, even if the partical power down is applied, DZF1-2 pins will not become “H”.
Figure 49. DAC partial power-down example
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[AK4611]
■ Serial Control Interface
The AK4611’s functions are controlled through registers. The registers may be written by two types of control modes.
The chip address is determined by the state of the CAD0 and CAD1 inputs. The PDN pin = “L” initializes the registers to
their default values. Writing “0” to the RSTN bit can initialize the internal timing circuit, but the register data will not be
initialized.
(1) 4-wire Serial Control Mode (I2C pin = “L”)
The internal registers may be written through the 4-wire µP interface pins (CSN, CCLK, CDTI and CDTO). The data on
this interface consists of a 2-bit Chip address, Read/Write, Register address (MSB first, 5bits) and Control data (MSB
first, 8bits). The chip address high bit is fixed to “1” and the lower bit is set by the CAD0 pin. Address and data are
clocked in on the rising edge of CCLK and data is clocked out on the falling edge. After a low-to-high transition of CSN,
data is latched for write operations and CDTO bit outputs Hi-Z. The clock speed of CCLK is 5MHz (max). The value of
internal registers is initialized when the PDN pin = “L”.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
“H” or “L”
“H” or “L”
CDTI
“H” or “L”
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 “H” or “L”
WRITE
Hi-Z
CDTO
CDTI
READ
CDTO
“H” or “L”
“H” or “L”
C1 C0 R/W A4 A3 A2 A1 A0
Hi-Z
D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
C1 – C0: Chip Address (C1=CAD1, C0=CA0)
R/W: READ / WRITE (“1”: WRITE, “0”: READ)
A4 - A0: Register Address
D7 – D0: Control Data
Figure 50. Serial Control I/F Timing
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[AK4611]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4611 supports the fast-mode I2C-bus (max: 400kHz).
(2)-1. WRITE Operations
Figure 51 shows the data transfer sequence of the I2C-bus mode. All commands are preceded by START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition (Figure 57). After the START
condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W).
The most significant five bits of the slave address are fixed as “00100”. The next bits are CAD1 and CAD0 (device
address bit). This bit identifies the specific device on the bus. The hard-wired input pins (CAD1/0 pins) set these device
address bits (Figure 52). If the slave address matches that of the AK4611, the AK4611 generates an acknowledge and the
operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH)
during the acknowledge clock pulse (Figure 58). R/W bit = “1” indicates that the read operation is to be executed. “0”
indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4611. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 53). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 54). The AK4611 generates an acknowledge after each byte is received. Data transfer is always
terminated by STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH
defines STOP condition (Figure 57).
The AK4611 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4611
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 59) except for the START and STOP
conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 51. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
CAD1
CAD0
R/W
(Those CAD1/0 should match with CAD1/0 pins)
Figure 52. The First Byte
0
0
0
A4
A3
A2
A1
A0
D2
D1
D0
Figure 53. The Second Byte
D7
D6
D5
D4
D3
Figure 54. Byte Structure after the second byte
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[AK4611]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4611. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is
automatically taken into the next address.
The AK4611 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4611 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would
access data from the address “n+1”. After receipt of the slave address with R/W bit “1”, the AK4611 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK4611
ceases transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
Data(n+1)
Data(n+2)
MA
AC
SK
T
E
R
A
C
K
MA
AC
SK
T
E
R
Data(n+x)
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
P
MN
AA
SC
T
EK
R
Figure 55. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing a slave address
with the R/W bit =“1”, the master must execute a “dummy” write operation first. The master issues a start request, a slave
address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit =“1”. The AK4611 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge but generates a stop condition instead, the AK4611 ceases transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Sub
Address(n)
A
C
K
Slave
S Address
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
MA
AC
S K
T
E
R
Data(n+x)
MA
AC
S
T K
E
R
MA
AC
S
T K
E
R
P
MN
A A
S
T C
E K
R
Figure 56. RANDOM ADDRESS READ
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[AK4611]
SDA
SCL
S
P
start condition
stop condition
Figure 57. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 58. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 59. Bit Transfer on the I2C-Bus
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[AK4611]
■ Register Map
Addr
Register Name
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
Power Management 1
Power Management 2
Power Management 3
Control 1
Control 2
De-emphasis1
Reserved
Overflow Detect
Zero Detect
Input Control
Output Control
LOUT1 Volume Control
ROUT1 Volume Control
LOUT2 Volume Control
ROUT2 Volume Control
LOUT3 Volume Control
ROUT3 Volume Control
LOUT4 Volume Control
ROUT4 Volume Control
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
TDM1
0
DEM41
0
0
LOOP1
0
0
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
0
0
0
TDM0
MCKO
DEM40
0
0
LOOP0
0
0
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
0
0
1
DIF2
CKS1
DEM31
0
0
0
0
1
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
0
0
1
DIF1
CKS0
DEM30
0
0
0
0
1
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
PMVR
0
PMDA4
DIF0
DFS1
DEM21
0
OVFE
DZFM3
0
DOE4
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
PMADC
1
PMDA3
ATS1
DFS0
DEM20
1
OVFM2
DZFM2
1
DOE3
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
PMDAC
PMAD2
PMDA2
ATS0
ACKS
DEM11
0
OVFM1
DZFM1
DIE2
DOE2
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
RSTN
PMAD1
PMDA1
SMUTE
DIV
DEM10
1
OVFM0
DZFM0
DIE1
DOE1
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
Note: For addresses from 13H to 1FH, data is not written.
When the PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the internal timing is reset and the DZF1-2 pins go to “H”, but registers are not
initialized to their default values.
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[AK4611]
■ Register Definitions
Addr
00H
Register Name
Power Management 1
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
RD
0
0
RD
0
0
RD
0
0
RD
0
PMVR
PMADC
PMDAC
RSTN
R/W
R/W
R/W
R/W
1
1
1
1
RSTN: Internal timing reset
0: Reset. DZF1-2 pins go to “H”, but registers are not initialized.
1: Normal operation
PMDAC: Power management of DAC1-4
0: Power-down
1: Normal operation
PMADC: Power management of ADC1-2
0: Power-down
1: Normal operation
PWVR: Power management of reference voltage
0: Power-down
1: Normal operation
When any blocks are powered-up, the PMVR bit must be set to “1”. PMVR bit can be set to “0” only when
PMADAL=PMADAR= bits = “0”.
Addr
01H
Register Name
Power Management 2
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
1
D1
PMAD2
D0
PMAD1
RD
1
R/W
1
R/W
1
PMAD2-1: Power management of ADC1-2 (0: Power-down, 1: Normal operation)
PMAD1: Power management control of ADC1
PMAD2: Power management control of ADC2
Addr
02H
Register Name
Power Management 3
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
RD
0
RD
1
1
PMDA4
PMDA3
PMDA2
PMDA1
RD
RD
R/W
R/W
R/W
R/W
0
0
1
1
1
1
1
1
PMDA4-1: Power management of DAC1-4 (0: Power-down, 1: Normal operation)
PMDA1: Power management control of DAC1
PMDA2: Power management control of DAC2
PMDA3: Power management control of DAC3
PMDA4: Power management control of DAC4
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[AK4611]
Addr
03H
Register Name
Control 1
R/W
Default
D7
TDM1
R/W
0
D6
TDM0
R/W
0
D5
DIF2
R/W
1
D4
DIF1
R/W
0
D3
DIF0
R/W
0
D2
ATS1
R/W
0
D1
ATS0
R/W
0
D0
SMUTE
R/W
0
SMUTE: Soft Mute Enable
0: Normal operation
1: All DAC outputs soft-muted
ATS1-0: Digital attenuator transition time setting (Table 18)
Initial: “00”, mode 0
DIF2-0: Audio Data Interface Modes (Table 11, Table 12, Table 13, Table 14)
Initial: “100”, mode 4
TDM1-0: TDM Format Select (Table 11, Table 12, Table 13, Table 14)
Mode
0
1
2
3
Addr
04H
TDM1 TDM0
0
0
0
1
1
0
1
1
SDTI
1-6
1
1-2
1-3
Sampling Speed
Stereo mode (Normal, Double, Quad Speed Mode)
TDM512 mode (Normal Speed Mode)
TDM256 mode (Double Speed Mode)
TDM128 mode (Quad Speed Mode)
Register Name
Control 2
D7
0
D6
MCKO
D5
CKS1
D4
CKS0
D3
DFS1
D2
DFS0
D1
ACKS
D0
DIV
R/W
RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
1
0
0
0
0
0
DIV: Output of Master clock frequency
0: x 1
1: x 1/2
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS are
ignored. When this bit is “0”, DFS0, 1 set the sampling speed mode.
DFS1-0: Sampling speed mode (Table 1)
The setting of DFS is ignored at ACKS bit =“1”.
CKS1-0: Master Clock Input Frequency Select (Table 2)
MCKO: Master clock output enable
0: Output “L”
1: Output “MCKO”
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Addr
05H
Register Name
De-emphasis1
R/W
Default
D7
DEM41
R/W
0
D6
DEM40
R/W
1
D5
DEM31
R/W
0
D4
DEM30
R/W
1
D3
DEM21
R/W
0
D2
DEM20
R/W
1
D1
DEM11
R/W
0
D0
DEM10
R/W
1
DEMA11-10: De-emphasis response control for DAC1 data on SDTI1 (Table 8)
Initial: “01”, OFF
DEMA21-20: De-emphasis response control for DAC2 data on SDTI1 (Table 8)
Initial: “01”, OFF
DEMA31-30: De-emphasis response control for DAC3 data on SDTI1 (Table 8)
Initial: “01”, OFF
DEMA41-40: De-emphasis response control for DAC4 data on SDTI1 (Table 8)
Initial: “01”, OFF
Addr
07H
Register Name
Overflow Detect
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
OVFE
R/W
0
D2
OVFM2
R/W
1
D1
OVFM1
R/W
1
D0
OVFM0
R/W
1
OVFM2-0: Overflow detect mode select (Table 15)
Initial: “111”, disable
OVFE: Overflow detection enable (Table 15)
0: Disable, pin#33 becomes DZF2 pin.
1: Enable, pin#33 becomes OVF pin.
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[AK4611]
Addr
08H
Register Name
Zero Detect
D7
LOOP1
D6
LOOP0
R/W
R/W
R/W
Default
0
0
D5
0
RD
0
D4
0
RD
0
D3
DZFM3
D2
DZFM2
D1
DZFM1
D0
DZFM0
R/W
R/W
R/W
R/W
1
1
1
1
DZFM3-0: Zero detect mode select (Table 16)
Initial: “1111”, disable
LOOP1-0: Loopback mode enable
00: Normal (No loop back)
01: LIN1  LOUT1, LOUT2
RIN1  ROUT1, ROUT2
LIN2  LOUT3, LOUT4
RIN2  ROUT3, ROUT4
The digital ADC output is connected to the digital DAC input. In this mode, the input DAC data to
SDTI1-4 are ignored. The audio format of SDTO at loopback mode becomes mode 3 at mode 0 or 1,
and mode 5 at mode 2, respectively.
10: SDTI1(L)  SDTI2(L), SDTI3(L), SDTI4(L)
SDTI1(R)  SDTI2(R), SDTI3(R), SDTI4(R)
In this mode, the input DAC data to SDTI2-4 are ignored.
11: Not Available
LOOP1-0 should be set to “00” at TDM mode.
Addr
09H
Register Name
Output Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
1
RD
1
D1
DIE2
R/W
1
D0
DIE1
R/W
1
D1
DOE2
R/W
1
D0
DOE1
R/W
1
DIE2-1: ADC1-2 Differential Input Enable (0: Single-End Input, 1: Differential Input)
DIE1: ADC1 Differential Input Enable
DIE2: ADC2 Differential Input Enable
Addr
0AH
Register Name
Output Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
1
RD
1
D4
1
RD
1
D3
DOE4
R/W
1
D2
DOE3
R/W
1
DOE4-1: DAC1-4 Differential Output Enable (0: Single-End Input, 1: Differential Input)
DOE1: DAC1 Differential Output Enable
DOE2: DAC2 Differential Output Enable
DOE3: DAC3 Differential Output Enable
DOE4: DAC4 Differential Output Enable
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[AK4611]
Addr
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
Register Name
LOUT1 Volume Control
ROUT1 Volume Control
LOUT2 Volume Control
ROUT2 Volume Control
LOUT3 Volume Control
ROUT3 Volume Control
LOUT4 Volume Control
ROUT4 Volume Control
R/W
Default
D7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
R/W
D6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
R/W
D5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
R/W
D4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
R/W
D3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
R/W
D2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
R/W
D1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
R/W
D0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
R/W
0
0
0
0
0
0
0
0
ATT7-0: Attenuation Level (Table 17)
* A power-down release command must be write again (dummy write) after 5 LRCK cycles or later form the first
command when releasing power-down mode by PMVR, PMDAC, RSTN, PMDA1, PMDA2, PMDA3 or PMDA4 bit
in I2C mode. If this dummy write is not executed, DATT output will keep the initial value (0dB) until the next write
is executed. (Figure 43)
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[AK4611]
SYSTEM DESIGN
Condition: Differential Input (DIE2-1 bit = “11”), Differential Output (DOE4-1 bit = “1111”)
4-wire Serial Control Interface (I2C pin = “L”)
Master mode (M/S pin = “H”)
MUTE
LPF
MUTE
MUTE
LPF
MUTE
MUTE
Analog 3.3V
The AK4611 has the analog Anti-Alias Filter for Differential Input.
The AK4611 does not have the analog Smoothing Filter for Differential Output.
LPF
LPF
LPF
LOUT2+
40
ROUT1-
39
63 OVF1 / DZF1
ROUT1+-
38
64 OVF2 / DZF2
LOUT1-
37
65 LIN1+
LOUT1+
36
66 LIN1-
62 TST16
DVMPD
35
67 RIN1+
TST8
34
68 RIN1-
TST7
33
69 LIN2+
SDTI4
32
70 LIN2-
SDTI3
31
SDTI2
30
72 RIN2-
SDTI1
29
73 TST17
BICK
28
74 TST18
LRCK
27
AK4611
71 RIN2+
26
25
SDTO1
24
78 VCOM
VSS4
23
79 TST19
TVDD1
22
XTI / MCLK
21
TST2
M/S
MCKO
PDN
XTO
16
17
18
19
20
MUTE
LPF
MUTE
LPF
MUTE
DSP
0.1u 10u
+
1.6V to 3.6V
Digital
+
10u
0.1u
14
LPF
C1
C1
1.8V
Digital Core
µP
NC
VSS3
13
DVDD
TVDD2
0.1u
10u
Digital Ground
+
1.6V to 3.6V
Digital
Analog Ground
15
CDTO
8
12
CCLK / SCL
7
11
I2C
6
CDTI / SDA
CAD1
5
CSN
CAD0
4
9
TST5
3
80 TST20
10
TST4
2
77 VREFH1
TST3
+
TST6
SDTO2
TST1
2.2u 0.1u
10u 0.1u
75 VSS1
+
76 AVDD1
1
Analog 3.3V
1
VSS2 48
1
ROUT3- 47
1
ROUT3+ 46
1
LOUT3- 45
1
LOUT3+ 44
1
ROUT2- 43
1
ROUT2+ 42
LOUT2- 41
1
VREFH2 50
0.1u 10u
AVDD2 49
1
61 TST15
1
1
TST11 57
1
TST10 56
1
TST9 55
1
ROUT4- 54
1
ROUT4+ 53
1
LOUT4-1 52
+
LOUT4+ 51
TST14 60
TST13 59
1
TST12 58
+
Figure 60. Typical Connection Diagram1
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[AK4611]
MUTE
1
1
LOUT2- 41
ROUT2 42
1
ROUT2- 43
LOUT3 44
1
ROUT3 46
LOUT3- 45
1
1
VSS2 48
ROUT3- 47
1
1
AVDD2 49
1
LOUT4 51
VREFH2 50
1
ROUT4 53
LOUT4- 52
1
1
TST9 55
ROUT4- 54
0.1u 10u
+
LOUT2
40
ROUT1-
39
63 OVF1 / DZF1
ROUT1
38
64 OVF2 / DZF2
LOUT1-
37
65 LIN1
LOUT1
36
66 LIN1-
DVMPD
35
67 RIN1
TST8
34
68 RIN1-
TST7
33
69 LIN2
SDTI4
32
70 LIN2-
SDTI3
31
SDTI2
30
72 RIN2-
SDTI1
29
73 TST17
BICK
28
LRCK
27
TST6
26
SDTO2
25
SDTO1
24
VSS4
23
TVDD1
22
XTI / MCLK
21
61 TST15
1
TST13 59
1
TST12 58
1
TST11 57
1
TST10 56
1
TST14 60
MUTE
MUTE
MUTE
MUTE
Analog 3.3V
Condition: Single-end Input (DIE2-1 bit = “00”), Single-end Output (DOE4-1 bit = “0000”)
I2C Bus Control Interface (I2C pin = “H”)
Slave mode (M/S pin = “L”)
The AK4611 has the analog Anti-Alias Filter for Single-Ended Input.
The AK4611 has the analog Smoothing Filter for Single-Ended Output.
62 TST16
AK4611
71 RIN2
Analog 3.3V
2.2u 0.1u
+
74 TST18
10u 0.1u
75 VSS1
+
76 AVDD1
77 VREFH1
78 VCOM
PDN
XTO
20
VSS3
13
19
TVDD2
12
MCKO
CDTO
11
M/S
CDTI / SDA
10
18
CSN
9
17
CCLK / SCL
8
TST2
I2C
7
NC
CAD1
6
16
CAD0
5
15
TST5
4
DSP
0.1u 10u
+
1.6V to 3.6V
Digital
+
1.8V
Digital Core
µP
MUTE
10u
0.1u
10u
Digital Ground
+
1.6V to 3.6V
Digital
Analog Ground
MUTE
0.1u
TST4
3
DVDD
TST3
2
80 TST20
14
TST1
1
79 TST19
MUTE
Figure 61. Typical Connection Diagram2
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[AK4611]
1. Grounding and Power Supply Decoupling
The AK4611 requires careful attention to power supply and grounding arrangements. AVDD1, AVDD2, TVDD1 and
TVDD2 are usually supplied from analog supply in system. Alternatively if AVDD1, AVDD2, TVDD1 and TVDD2 are
supplied separately, the power up sequence is not critical. VSS1, VSS2, VSS3 and VSS4 of the AK4611 must be
connected to analog ground plane. System analog ground and digital ground should be connected together near to
where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4611 as
possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference Inputs
The voltage of VREFH1, VREFH2 set the analog input/output range. The VREFH1 pin is normally connected to AVDD1
with a 0.1µF ceramic capacitor. The VREFH2 pin is normally connected to AVDD2 with a 0.1µF ceramic capacitor.
VCOM is a signal ground of this chip and output the voltage AVDD1x1/2. An electrolytic capacitor 2.2µF parallel with a
0.1µF ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. Ceramic capacitors
should be as near to the pin as possible. No load current may be drawn from the VCOM pin. All signals, especially clocks,
should be kept away from the VREFH1, VREFH2 and VCOM pins in order to avoid unwanted coupling into the AK4611.
3. Analog Inputs
The ADC inputs correspond to single-ended and differential are able to select by DIE2-1 bits. When the inputs are
single-ended, internally biased to the common voltage (AVDD1x1/2) with 9k(typ) resistance. The input signal range
scales with the supply voltage and nominally 0.65xVREFH1 Vpp (typ) @fs=48kHz. When the inputs are differential,
internally biased to the common voltage (AVDD2x1/2) with 13k(typ) resistance. The input signal range between
LIN(RIN)+ and LIN(RIN) scales with the supply voltage and nominally ±0.65xVREFH1 Vpp (typ) @fs=48kHz The
ADC output data format is 2’s complement. The internal HPF removes the DC offset.
The AK4611 samples the analog inputs at 128fs (@ fs=48kHz). The digital filter rejects noise above the stop band except
for multiples of the sampling frequency of analog inputs. The AK4611 includes an anti-aliasing filter (RC filter) to
attenuate a noise around the sampling frequency of analog inputs.
4. Analog Outputs
The DAC outputs correspond to single-ended and differential are able to select by DOE4-1 bits. When the outputs are
single-ended, the output signal range is centered around the VCOM voltage and nominally 0.63 x VREFH2 Vpp. When
the outputs are differential, the output signal ranges are ±0.63 x VREFH2 Vpp (typ) centered around the VCOM voltage.
The differential outputs are summed externally, V AOUT = [L(R)OUT+]-[L(R)OUT-] between L(R)OUT+ and L(R)OUT-.
If the summing gain is 1, the output range is 4.16Vpp ([email protected]=3.3V). The bias voltage of the external summing
circuit is supplied externally. The DAC input data format is 2’s complement. The output voltage is a positive full scale for
7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is VCOM voltage for
000000H(@24bit). The internal analog filters remove most of the noise generated by the delta-sigma modulator of DAC
beyond the audio passband, when the single-end input mode. The differential output mode does not have the internal
analog filters, therefore this noise should be remove by the external analog filters.
DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV.
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[AK4611]
5. External Analog Inputs Circuit
Figure 62 shows the input buffer circuit example 1. The input level of this circuit is 4.3Vpp (AK4611: typ. 2.15Vpp).
5.1k
4.7k
Analog In
4.3Vpp
VP+
4.7k
22
10k
2.15Vpp
AIN+
VA
10k
Bias
VPNJM5532
AK4611
NJM5532
Bias
0.1 10
Bias
10k
AIN-
VA = +3.3V
VP+ = +12V
VP- = -12V
Figure 62. Input buffer circuit example 1 (DC coupled single-end input)
Figure 63 shows the input buffer circuit example 2. The input level of this circuit is 4.3Vpp (AK4611: typ. 2.15Vpp).
5.1k
4.7k
Analog In
4.3Vpp
VP+
4.7k
22
10k
VP+ = +12V
VP- = -12V
2.15Vpp
AIN+
VPNJM5532
10
AK4611
NJM5532
AIN2.15Vpp
10
Figure 63. Input buffer circuit example 2 (AC coupled single-end input)
Figure 64 shows the input buffer circuit example 3. The input level of this circuit is 2.15Vpp (AK4611: typ. 2.15Vpp).
Analog In
2.15Vpp
AIN+
10
AK4611
Analog In
2.15Vpp
AIN10
Figure 64. Input buffer circuit example 3 (AC coupled differential input)
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Figure 65 shows the input buffer circuit example 4. The input level of this circuit is 2.15Vpp (AK4611: typ. 2.15Vpp).
Analog In
2.15Vpp
AIN+
10
AK4611
AIN-
Open
Figure 65. Input buffer circuit example 4 (AC coupled single-end input)
6. External Analog Outputs Circuit
Figure 66 shows the output buffer circuit example 1. The output level of this circuit is 4.16Vpp (AK4611: typ. 2.08Vpp).
2.08Vpp
20
A
4.7k
4.7k
AOUT470p
R1
2200p
AK4611
VP+
3900p
20
4.7k
R1
Analog Out
4.16Vpp
AOUT+
B
2.08Vpp
VPVP+ = +12V
NJM5532
VP- = -12V
When R1=200
fc=93.2kHz, Q=0.712, g=-0.1B at 40kHz
When R1=180
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
470p
4.7k
Figure 66. Output buffer circuit example 1 (DC coupled differential output)
Figure 67 shows the output buffer circuit example 2. The output level of this circuit is 4.16Vpp (AK4611: typ. 2.08Vpp).
2.08Vpp
20
4.7k
A
4.7k
AOUT22
R1
470p
2200p
AK4611
3900p
4.7k
20
VP+
R1
AOUT+
2.08Vpp
B 22
4.7k
470p
Analog Out
4.16Vpp
VP- VP+ = +12V
NJM5532
VP- = -12V
When R1=180
fc=90.1kHz, Q=0.735, g=-0.04B at 40kHz
When R1=150
fc=99.0kHz, Q=0.680, g=-0.23dB at 40kHz
Figure 67. Output buffer circuit example 2 (AC coupled differential output)
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[AK4611]
Figure 68 shows the output buffer circuit example 3. The output level of this circuit is 4.16Vpp (AK4611: typ. 2.08Vpp).
470p
AOUT-
OPEN
4.7k
4.7k
AK4611
VP+
2.08Vpp
4.7k
4.7k
Analog Out
AOUT+
22
10k
470p
VPNJM5532
4.16Vpp
VP+ = +12V
VP- = -12V
Figure 68. Output buffer circuit example 3 (AC coupled single-end output)
Figure 69 shows the output buffer circuit example 4. The output level of this circuit is 2.08Vpp (AK4611: typ. 2.08Vpp).
AOUT-
OPEN
AK4611
2.08Vpp
AOUT+
Analog Out
22
10k
2.08Vpp
Figure 69. Output buffer circuit example 4 (AC coupled single-end output)
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[AK4611]
PACKAGE

80-pin LQFP
( Unit: mm )
14.0±0.2
12.0±0.2
41
61
40
80
21
12.0±0.2
1
20
0.08
0.125+0.10
-0.05
0.50±0.2
0.10
M
+0.15
0.10 -0.10
0.50
1.25TYP
1.85MAX
0° ~ 10°
0.20±0.1
1.40±0.2
14.0±0.2
60
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy resin, Halogen (bromine and chlorine) free
Cu
Solder (Pb free) plate
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[AK4611]
MARKING (AK4611EQ)
AK4611EQ
XXXXXXX
1) Pin #1 indication
2) Date Code: XXXXXXX(7 digits)
3) Marking Code: AK4611EQ
4) Asahi Kasei Logo
MARKING (AK4611VQ)
AK4611VQ
XXXXXXX
1) Pin #1 indication
2) Date Code: XXXXXXX(7 digits)
3) Marking Code: AK4611VQ
4) Asahi Kasei Logo
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[AK4611]
REVISION HISTORY
Date (Y/M/D)
09/02/06
09/06/05
Revision
00
01
Reason
First Edition
Specificatio
n Change
10/06/14
02
13/07/03
03
Description
Addition
Description
Addition
Page
Contents
10
ANALOG CHARACTERISTICS
ADC Analog Input Characteristics (differential)
S/(N+D) fs=48kHz, -1dBFS: 89 → 88 (min)
AK4611EQ was added.
43
■ Digital Attenuator
A description was added.
Figure 43 was added.
■ Register Definitions
A description was added.
■ Differential / Single-End Input selection
59
14/09/29
04
15/06/11
05
Error
Correction
Error
Correction
30
“L/RIN1-2 pins” → “L/RIN1-/2- pins”
15-18
33
SWITCHING CHARACTERISTICS
TDM512 mode: TDM0 bit = “0”, TDM1 bit = “1”
→TDM1 bit = “0”, TDM0 bit = “1”
TDM256 mode: TDM0 bit = “1”, TDM1 bit = “0”
→TDM1 bit = “1”, TDM0 bit = “0”
■ Audio Serial Interface Format
(2) TDM Mode
TDM256 mode (fs = 48kHz) → (fs= 96kHz)
56
■ Register Definitions
Table for TDM1-0 bits is corrected.
Mode 2: TDM1 “1”, TDM0 “1”
→ TDM1 “1”, TDM0 “0”
Mode 3: TDM1 “1”, TDM0 “0”
→ TDM1 “1”, TDM0 “1”
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[AK4611]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application of
AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM
or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of AKM or any third party with respect to the
information in this document. You are fully responsible for use of such information contained in this
document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY
LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH
INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact, including
but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry,
medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic
signaling equipment, equipment used to control combustions or explosions, safety devices, elevators
and escalators, devices related to electric power, and equipment used in finance-related fields. Do not
use Product for the above use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible
for complying with safety standards and for providing adequate designs and safeguards for your
hardware, software and systems which minimize risk and avoid situations in which a malfunction or
failure of the Product could cause loss of human life, bodily injury or damage to property, including
data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or related
technology or any information contained in this document, you should comply with the applicable
export control laws and regulations and follow the procedures required by such laws and regulations.
The Products and related technology may not be used for or incorporated into any products or systems
whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation,
the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth
in this document shall immediately void any warranty granted by AKM for the Product and shall not
create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
MS1050-E-05
2015/06
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