PRELIMINARY PRODUCT INFORMATION MOS INTEGRATED CIRCUIT µPD78F0701Y 8-BIT SINGLE-CHIP MICROCONTROLLER The µPD78F0701Y is a µPD780701Y sub-series product of the 78K/0 series. The µPD78F0701Y features a TM DCAN controller and an IEBus controller. It also features flash memory as internal ROM. Programs can be written into the flash memory without having to remove it from the board. The functions of the µPD78F0701Y are described in the following user's manuals. Be sure to read these manuals when designing a system based on the µPD78F0701Y. µPD780701Y Sub-Series User's Manual : 78K/0 Series User's Manual, Instruction : U13781E U12326E FEATURES TM • Built-in IEBus (Inter Equipment Bus ) controller • Built-in DCAN (Direct Storage Controller Area Network) controller • Pin-compatible with masked ROM versions (other than the VPP pin) • Flash memory : 60K bytes (supported for self-programming) • Internal high-speed RAM : 1,024 bytes • Internal expansion RAM : 2,048 bytes • Buffer RAM for DCAN : 288 bytes • Can be operated within the same power supply voltage ranges as masked ROM versions (VDD = 3.5 to 5.5 V) Remark For differences between flash memory versions and masked ROM versions, see Chapter 1. APPLICATIONS Car audio systems, etc. ORDERING INFORMATION Part number Package µPD78F0701YGC-8BT 80-pin plastic QFP (14 × 14 mm) Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Document No. U13563EJ2V0PM00 (2nd edition) Date Published March 1999 J CP(K) Printed in Japan The mark shows major revised points. © 1998 µPD78F0701Y 78K/0 SERIES DEVELOPMENT The 78K/0 series products are shown below. The sub-series names are indicated in frames. Products being mass-produced Products under development Y sub-series products are compatible with the I2C bus. For control 100-pin µPD78075B 100-pin µ PD78078 µ PD78078Y 100-pin µ PD78070A µ PD78070AY EMI noise-reduced version of the µPD78078 µPD780018AY 100-pin µ PD780058 µPD78058F µ PD780058Y µPD78058FY 80-pin µPD78054 µPD78054Y 80-pin µPD780065 80-pin 80-pin A timer has been added to the µPD78054 to enhance external interface functions. ROM-less versions of the µPD78078 The serial I/O of the µPD78078Y has been enhanced, and only selected functions are provided. The serial I/O of the µPD78054 has been enhanced. EMI noise-reduced versions EMI noise-reduced versions of the µPD78054 A UART and D/A converter have been added to the µPD78018F and I/O has been enhanced. RAM capacity of the µPD780024A has been expanded. 64-pin µPD780034A µPD780034AY An A/D converter of the µ PD780024A has been enhanced. 64-pin 64-pin µPD780024A µPD780024AY Serial I/O of the µPD78018F has been enhanced. EMI noise-reduced version of the µPD78018F 64-pin µ PD78018F µ PD78083 µ PD78018FY Basic sub-series for control This product includes a UART and can operate at a low voltage (1.8 V). 42-/44-pin µPD78014H For inverter control 64-pin µPD780988 This product includes an inverter control circuit and UART. EMI noise-reduced version For FIPTM driving 78K/0 series 100-pin µPD780208 100-pin µPD780228 µ PD780232 80-pin 80-pin µPD78044H 80-pin µ PD78044F For LCD driving 100-pin µ PD780308 100-pin µPD78064B 100-pin µPD78064 The I/O and FIP C/D of the µPD78044F have been enhanced. Total indication output pins: 53 The I/O and FIP C/D of the µPD78044H have been enhanced. Total indication output pins: 48 This product is for panel control and includes the FIP C/D. Total indication output pins: 53 N-ch open-drain I/O ports have been added to the µPD78044F. Total indication output pins: 34 Basic sub-series for FIP driving. Total indication output pins: 34 µ PD780308Y The SIO of the µPD78064 has been enhanced and ROM and RAM have been expanded. EMI noise-reduced version of the µPD78064 µ PD78064Y Basic sub-series for LCD driving. These products include a UART. Compatible with bus interface 100-pin 80-pin µ PD780948 This product includes a DCAN controller. An IEBus controller has been added to the µPD78054. EMI noise-reduced version µPD78098B 80-pin µPD780701Y This product includes a DCAN and an IEBus controller. 80-pin µPD780833Y This product includes a controller complying with J1850 (CLASS 2). For meter control 2 100-pin µ PD780958 80-pin 80-pin µPD780973 µPD780955 For industrial meter control This product includes a controller/driver for driving an automobile meter. Ultra-low power consumption. This product includes a UART. Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y FUNCTIONS Item Internal memory Function Flash memory 60K bytes High-speed RAM 1,024 bytes Extended RAM 2,048 bytes Buffer RAM for DCAN 288 bytes Minimum instruction execution time On-chip minimum instruction execution time modification function • 0.32 µs/0.64 µs/1.27 µs/2.54 µs/5.09 µs (operation with system clock running at 6.29 MHz) General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Instruction set • 16-bit operations • Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits) • Bit manipulations (such as set, reset, test, and Boolean operation) I/O ports Total • CMOS I/O • TTL input/CMOS output • N-ch open-drain I/O A/D converters • 16 channels with 8-bit resolution • Power failure detection function Serial interface • Three-wire serial I/O mode : 2 channels : 1 channel • UART mode 2 : 1 channel • I C bus mode Timers • • • • Timer output 5 lines (8-bit PWM output: 3 lines) DCAN controller 1 channel IEBus controller Effective transmission rate: 18 kbps Clock output 49.2 kHz, 98.3 kHz, 197 kHz, 393 kHz, 786 kHz, 1.57 MHz, 3.15 MHz, 6.29 MHz (operation with system clock running at 6.29 MHz) Buzzer output 0.768 kHz, 1.54 kHz, 3.07 kHz, 6.14 kHz (operation with system clock running at 6.29 MHz) Vectored interrupt sources : : : : 67 56 8 3 16-bit timer/event counters : 8-bit timer/event counters : Watch timer : Watchdog timer : Maskable Internal: 20, External: 8 Nonmaskable Internal: 1 Software 1 2 channels 3 channels 1 channel 1 channel Power supply voltage VDD = 3.5 to 5.5 V Operating ambient temperature TA = -40°C to +85°C Package 80-pin plastic QFP (14 × 14 mm) Preliminary Product Information U13563EJ2V0PM00 3 µPD78F0701Y PIN CONFIGURATION (TOP VIEW) • 80-pin plastic QFP (14 × 14 mm) AVSS P87/ANI7 P86/ANI6 P85/ANI5 P84/ANI4 P83/ANI3 P82/ANI2 P81/ANI1 P80/ANI0 AVREF VSS1 VDD1 CPUREG X1 X2 VPP RESET CTXD/ITX0 CRXD/IRX0 P67 µPD78F0701YGC-8BT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P90/ANI8 P91/ANI9 P92/ANI10 P93/ANI11 P94/ANI12 P95/ANI13 P96/ANI14 P97/ANI15 P70/TI52/TO52 P71/SDA0 P72/SCL0 P73/TO01 P74/TI001 P75/TI011 P76/TI50/TO50 P77/TI51/TO51 P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P66 P65 P64 P27/PCL P26/ASCK0 P25/TxD0 P24/RxD0 P23/BUZ P07/INTP7 P06/INTP6 P05/INTP5 P04/INTP4 P22/SCK31 P21/SO31 P20/SI31 P57 P56 P55 P54 P53 P40 P41 P42 P43 P44 P45 P46 P47 P30/SI30 P31/SO30 P32/SCK30 VDD0 VSS0 P33 P34/TO00 P35/TI000 P36/TI010 P50 P51 P52 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Cautions 1. In normal operation mode, connect the VPP pin directly to the VSS0 or VSS1 pin. 2. Connect the AVSS pin to the VSS0 pin. 3. Connect the AVREF pin to the VDD0 pin. 4 Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y ANI0-ANI15 : Analog Input P90-P97 : Port 9 ASCK0 : Asynchronous Serial Clock PCL : Programmable Clock AVREF : Analog Reference Voltage RESET : Reset AVSS : Analog Ground RxD0 : Receive Data (for UART0) BUZ : Buzzer Output SCK30, SCK31 : Serial Clock (for SIO30, SIO31) CPUREG : Regulator for CPU Power Supply SCL0 : Serial Clock (for IIC0) CRXD : CAN Receive Data SDA0 : Serial Data CTXD : CAN Transmit Data SI30, SI31 : Serial Input INTP0-INTP7 : Interrupt from Peripherals SO30, SO31 : Serial Output IRX0 : IEBus Receive Data TI000, TI010, TI001, ITX0 : IEBus Transmit Data TI011, TI50, TI51, P00-P07 : Port 0 TI52 P20-P27 : Port 2 TO00, TO01, TO50, P30-P36 : Port 3 TO51, TO52 : Timer Output P40-P47 : Port 4 TxD0 : Transmit Data (for UART0) : Timer Input P50-P57 : Port 5 VDD0, VDD1 : Power Supply P64-P67 : Port 6 VPP : Programming Power Supply P70-P77 : Port 7 VSS0, VSS1 : Ground P80-P87 : Port 8 X1, X2 : Crystal Preliminary Product Information U13563EJ2V0PM00 5 µPD78F0701Y BLOCK DIAGRAM TO00/P34 16-bit TIMER/ EVENT COUNTER 00 (TM00) TI000/P35 TI010/P36 TO01/P73 16-bit TIMER/ EVENT COUNTER 01 (TM01) TI001/P74 TI011/P75 8-bit TIMER/ EVENT COUNTER 50 (TM50) TI50/TO50/P76 TI51/TO51/P77 8-bit TIMER/ EVENT COUNTER 51 (TM51) TI52/TO52/P70 8-bit TIMER/ EVENT COUNTER 52 (TM52) WATCH TIMER (WTN0) WATCHDOG TIMER (WDT) SI30/P30 78K/0 CPU CORE FLASH MEMORY 60K Bytes INTERNAL INTERNAL HIGH-SPEED EXPANSION RAM RAM 1,024 Bytes 2,048 Bytes SERIAL INTERFACE 30 (SIO30) SO30/P31 SCK30/P32 SI31/P20 SCK31/P22 P00-P07 PORT 2 8 P20-P27 PORT 3 7 P30-P36 PORT 4 8 P40-P47 PORT 5 8 P50-P57 PORT 6 4 P64-P67 PORT 7 8 P70-P77 PORT 8 8 P80-P87 PORT 9 8 P90-P97 16 ANI0/P80ANI7/P87, ANI8/P90ANI15/P97 A/D CONVERTER3 (AD3) (ADCTL3) IEBus CONTROLLER (IEBUS0) DCAN CONTROLLER I2C BUS (IIC0) SDA0/P71 SCL0/P72 8 AVSS AVREF SERIAL INTERFACE 31 (SIO31) SO31/P21 PORT 0 (DCAN) IRX0/CRXD ITX0/CTXD CRXD/IRX0 CTXD/ITX0 RxD0/P24 UART (UART0) TxD0/P25 ASCK0/P26 INTP0/P00INTP7/P07 8 DCAN RAM 288 Bytes INTERRUPT CONTROL (INT29) SYSTEM CONTROL PCL/P27 CLOCK OUTPUT CONTROL BUZ/P23 BUZZER OUTPUT VOLTAGE REGULATOR VDD0 6 VSS0 VPP Preliminary Product Information U13563EJ2V0PM00 RESET X1 X2 VDD1 CPUREG VSS1 µPD78F0701Y CONTENTS 1. DIFFERENCES BETWEEN THE µPD78F0701Y AND MASKED ROM VERSIONS.............................8 2. PIN FUNCTIONS.....................................................................................................................................9 2.1 Port Pins .......................................................................................................................................................9 2.2 Non-Port Pins .............................................................................................................................................10 2.3 Pin Input/Output Circuits and Handling of Unused Pins........................................................................12 3. SELECTING INTERNAL BUS CONTROLLERS (DCAN and IEBus) .................................................14 4. MEMORY SIZE SELECT REGISTER (IMS) .........................................................................................15 5. INTERNAL EXPANSION RAM SIZE SELECT REGISTER (IXS) ........................................................15 6. FLASH MEMORY PROGRAMMING ....................................................................................................16 6.1 Selecting the Transmission Method.........................................................................................................16 6.2 Flash Memory Programming Functions ..................................................................................................17 6.3 Connecting the Flashpro III.......................................................................................................................18 6.4 Flash Memory Programming by Self-Writing ..........................................................................................19 7. ELECTRICAL CHARACTERISTICS ....................................................................................................27 8. PACKAGE DRAWINGS........................................................................................................................40 APPENDIX A DEVELOPMENT TOOLS.....................................................................................................41 APPENDIX B RELATED DOCUMENTS ....................................................................................................45 Preliminary Product Information U13563EJ2V0PM00 7 µPD78F0701Y 1. DIFFERENCES BETWEEN THE µPD78F0701Y AND MASKED ROM VERSIONS The µPD78F0701Y is a product provided with flash memory that enables writing, erasing, and rewriting of programs without being removed from the board. Table 1-1 shows the differences between the flash memory version (µPD78F0701Y) and masked ROM versions (µPD780701Y and µPD780702Y). Table 1-1. Differences between the µPD78F0701Y and Masked ROM Versions µPD78F0701Y Item µPD780701Y µPD780702Y Internal ROM type Flash memory Masked ROM IC pin Not provided Provided VPP pin Provided Not provided Built-in bus controller DCAN controller and IEBus controller DCAN controller IEBus controller TX pin DCAN or IEBus output (switched by software) DCAN output IEBus output RX pin DCAN or IEBus input (switched by software) DCAN input IEBus input Electrical characteristics Refer to the data sheet of individual products. Caution The flash memory versions and masked ROM versions have different noise immunity and noise radiation characteristics. Do not use ES products for evaluation when considering switching from flash memory versions to those using masked ROM upon the transition from preproduction to mass-production. CS products (masked ROM versions) should be used in this case. 8 Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y 2. PIN FUNCTIONS 2.1 Port Pins (1/2) Pin name I/O Function When reset Also used as P00-P07 I/O Port 0 8-bit input/output port Can be set to either input or output in 1-bit units. Whether an on-chip pull-up resistor is to be used can be specified by software. Input INTP0-INTP7 P20 I/O Port 2 8-bit input/output port Can be set to either input or output in 1-bit units. Whether an on-chip pull-up resistor is to be used can be specified by software. Input SI31 P21 P22 P23 SO31 SCK31 BUZ P24 RxD0 P25 TxD0 P26 ASCK0 P27 PCL P30 I/O P31 P32 Port 3 7-bit input/output port Can be set to either input or output in 1-bit units. Whether an on-chip pull-up resistor is to be used can be specified by software. SI30 SO30 SCK30 P33 N-ch open-drain input/output port (15-V withstand voltage) Can directly drive LEDs. P34 Whether an on-chip pull-up resistor is to be used can be specified by software. P35 Input - TO00 TI000 P36 TI010 P40-P47 I/O Port 4 8-bit input/output port Can be set to either input or output in 1-bit units. Whether an on-chip pull-up resistor is to be used can be specified by software. When a falling edge is detected, the interrupt request flag (KRIF) is set to 1. Input - P50-P57 I/O Port 5 8-bit input/output port TTL-level input and CMOS output Can be set to either input or output in 1-bit units. Whether an on-chip pull-up resistor is to be used can be specified by software. Input - P64-P67 I/O Port 6 4-bit input/output port Can be set to either input or output in 1-bit units. Whether an on-chip pull-up resistor is to be used can be specified by software. Input - Preliminary Product Information U13563EJ2V0PM00 9 µPD78F0701Y 2.1 Port Pins (2/2) Pin name P70 I/O I/O P71 P72 P73 Function Port 7 8-bit input/output port Can be set to either input or output in 1-bit units. Whether an on-chip pull-up resistor is to be used can be specified by software. When reset Input N-ch open-drain input/output port (5-V withstand voltage) TI52/TO52 SDA0 SCL0 TO01 Whether an on-chip pull-up resistor is to be used can be specified by software. P74 Also used as TI001 P75 TI011 P76 TI50/TO50 P77 TI51/TO51 P80-P87 I/O Port 8 8-bit input/output port Can be set to either input or output in 1-bit units. Input ANI0-ANI7 P90-P97 I/O Port 9 8-bit input/output port Can be set to either input or output in 1-bit units. Input ANI8-ANI15 2.2 Non-Port Pins (1/2) Pin name I/O Function When reset INTP0-INTP7 Input External interrupt input for which effective edges (rising and/or falling edges) can be specified. Input P00-P07 SI30 Input Serial data input to serial interface Input P30 SI31 SO30 Also used as P20 Output Serial data output to serial interface Input SO31 P31 P21 SDA0 I/O Serial data input/output to serial interface Input P71 SCK30 I/O Serial clock input/output to serial interface Input P32 SCK31 P22 SCL0 P72 RxD0 Input Serial data input to asynchronous serial interface Input P24 TxD0 Output Serial data output to asynchronous serial interface Input P25 ASCK0 Input Serial clock input to asynchronous serial interface Input P26 CRXD Input DCAN controller (DCAN) data input Input IRX0 CTXD Output DCAN controller (DCAN) data output Output ITX0 IRX0 Input IEBus controller (IEBUS0) data input Input CRXD ITX0 Output Output CTXD 10 IEBus controller (IEBUS0) data output Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y 2.2 Non-Port Pins (2/2) Pin name TI000 I/O Input Function External count clock input to 16-bit timer (TM00) When reset Input Also used as P35 TI010 External count clock input to 16-bit timer (TM00) P36 TI001 External count clock input to 16-bit timer (TM01) P74 TI011 External count clock input to 16-bit timer (TM01) P75 TI50 External count clock input to 8-bit timer (TM50) P76/TO50 TI51 External count clock input to 8-bit timer (TM51) P77/TO51 TI52 External count clock input to 8-bit timer (TM52) P70/TO52 TO00 Output 16-bit timer (TM00) output Input P34 TO01 16-bit timer (TM01) output P73 TO50 8-bit timer (TM50) output P76/TI50 TO51 8-bit timer (TM51) output P77/TI51 TO52 8-bit timer (TM52) output P70/TI52 PCL Output Clock output Input P27 BUZ Output Buzzer output Input P23 A/D converter (AD3) analog input Input P80-P87 ANI0-ANI7 Input ANI8-ANI15 P90-P97 AVREF Input AVSS - X1 Input X2 - RESET Input A/D converter (AD3) reference voltage and analog power supply - - A/D converter (AD3) ground potential - - Connected to crystal for system clock oscillation - - - - Input - System reset input CPUREG - CPU supply voltage regulator. Connect this pin to the VSS0 or VSS1 pin through a 0.1-µF capacitor. - - VDD0 - Positive supply voltage for ports - - VDD1 - Positive supply voltage (except ports and analog section) - - VSS0 - Ground potential for ports - - VSS1 - Ground potential (except ports and analog section) - - VPP - This pin applies a high voltage when a program is written or verified. In normal operation mode, connect this pin directly to the VSS0 or VSS1 pin. - - Preliminary Product Information U13563EJ2V0PM00 11 µPD78F0701Y 2.3 Pin Input/Output Circuits and Handling of Unused Pins Table 2-1 lists the types of input/output circuits for each pin and explains how unused pins are handled. Figure 2-1 shows the configuration of each type of input/output circuit. Table 2-1. Types of Input/Output Circuit for Each Pin and Handling of Unused Pins Pin name P00/INTP0-P07/INTP7 I/O circuit type I/O 8-C I/O Recommended connection of unused pins Connect these pins to the VSS0 pin via respective resistors. Connect these pins to the VDD0 or VSS0 pin via respective resistors. P20/SI31 P21/SO31 5-H P22/SCK31 8-C P23/BUZ 5-H P24/RxD0 8-C P25/TxD0 5-H P26/ASCK0 8-C P27/PCL 5-H P30/SI30 8-C P31/SO30 5-H P32/SCK30 8-C P33 13-P Connect this pin to the VDD0 pin via resistors. P34/TO00 5-H P35/TI000 8-C Connect these pins to the VDD0 or VSS0 pin via respective resistors. P40-P47 5-H Connect these pins to the VDD0 pin via respective resistors. P50-P57 5-T P64-P67 5-H Connect these pins to the VDD0 or VSS0 pin via respective resistors. 13-R Connect these pins to the VDD0 pin via respective resistors. P73/TO01 5-H P74/TI001 8-C Connect these pins to the VDD0 or VSS0 pin via respective resistors. P36/TI010 P70/TI52/TO52 P71/SDA0 P72/SCL0 P75/TI011 P76/TI50/TO50 P77/TI51/TO51 P80/ANI0-P87/ANI7 11-E P90/ANI8-P97/ANI15 CRXD/IRX0 2 Input CTXD/ITX0 3-B Output RESET 2 Input AVREF - AVSS VPP 12 Connect this pin to the VDD0 or VSS0 pin via resistors. Leave this pin open. Connect this pin to the VDD0 pin. - Connect this pin to the VSS0 pin. Connect this pin directly to the VSS0 or VSS1 pin. Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y Figure 2-1. Pin Input/Output Circuits Type 2 VDD0 Type 8-C Pull-up enable P-ch VDD0 IN Data P-ch IN/OUT Schmitt trigger input with hysteresis characteristics Type 3-B Output disable N-ch VSS0 VDD0 Type 11-E Data P-ch IN/OUT VDD0 Output disable P-ch Data N-ch VSS0 OUT Comparator N-ch + - VSS0 P-ch N-ch AVSS VREF (Threshold voltage) Input enable VDD0 Type 5-H Pull-up enable Type 13-P P-ch IN/OUT Output data Output disable VDD0 Data P-ch VSS0 IN/OUT Output disable N-ch N-ch Input enable VSS0 Input enable Type 5-T Type 13-R VDD0 Pull-up enable P-ch IN/OUT VDD0 Data Output data Output disable N-ch VSS0 P-ch IN/OUT Output disable N-ch TTL input VSS0 Input enable Preliminary Product Information U13563EJ2V0PM00 13 µPD78F0701Y 3. SELECTING INTERNAL BUS CONTROLLERS (DCAN and IEBus) The µPD78F0701Y has two internal bus controllers: a DCAN controller and IEBus controller. These bus controllers cannot be used simultaneously. By default, the DCAN controller is selected. The IEBus controller is selected by making the IEBus unit active (by setting bit 7 (ENIEBUS) of the IEBus control register 0 (BRC0) to 1). The default statuses of the interrupt request signals and pins differ depending on which of the internal bus controllers is used. Table 3-1 shows the default statuses of the interrupt request signals and pins. Table 3-1. Default Statuses of Interrupt Request Signals and Pins Item Using DCAN controller Default status of CTXD/ITX0 pin Interrupt request signals Note Using IEBus controller High level Low level INTCR INTIE1 INTCT INTIE2 INTCE None Note The statuses of the flags corresponding to the interrupt signals also differ. 14 Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y 4. MEMORY SIZE SELECT REGISTER (IMS) The memory size select register (IMS) selects the internal memory size. This register is set by an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Caution Use IMS with its default value (CFH). Do not set any other values for the IMS. Figure 4-1. Format of Memory Size Select Register (IMS) 7 Symbol 6 5 4 IMS RAM2 RAM1 RAM0 0 3 2 1 0 ROM3 ROM2 ROM1 ROM0 Address When reset R/W FFF0H CFH R/W ROM3 ROM2 ROM1 ROM0 Internal ROM capacity selection 1 1 1 60K bytes 1 Other settings Not to be set RAM2 RAM1 RAM0 1 1 Internal high-speed RAM capacity selection 1,024 bytes 0 Other settings Not to be set 5. INTERNAL EXPANSION RAM SIZE SELECT REGISTER (IXS) The internal expansion RAM size select register (IXS) selects the internal expansion RAM capacity. This register is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets IXS to 0CH. Caution Set IXS to 08H as the default status of the program. Because IXS is set to 0CH at a reset, set it to 08H after a reset. Figure 5-1. Format of Internal Expansion RAM Size Select Register (IXS) Symbol IXS 7 0 6 0 5 0 4 3 2 1 0 Address FFF4H IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 0 1 0 Other settings Preliminary Product Information U13563EJ2V0PM00 0 0 When reset 0CH R/W R/W Internal expansion RAM capacity selection 2,048 bytes Not to be set 15 µPD78F0701Y 6. FLASH MEMORY PROGRAMMING The flash memory can be written even while the device is mounted on the target system (on-board write). To write a program into the flash memory, connect the dedicated flash writer (Flashpro III (model number: FL-PR3 and PGFP3)) to both the host machine and target system. A program can also be written by using an adapter, for flash memory writing, connected to the Flashpro III. Remark The FL-PR3 is manufactured by Naito Densei Machida Mfg. Co., Ltd. 6.1 Selecting the Transmission Method The Flashpro III writes into flash memory by means of serial transmission. The transmission method to be used for writing is selected from those listed in Table 6-1. To select a transmission method, use the format shown in Figure 6-1, according to the number of VPP pulses listed in Table 6-1. Table 6-1. Transmission Methods Transmission method Number of channels Three-wire serial I/O Pins 2 2 Number of VPP pulses SI30/P30 SO30/P31 SCK30/P32 0 SI31/P20 SO31/P21 SCK31/P22 1 I C bus 1 SDA0/P71 SCL0/P72 4 UART 1 RxD0/P24 TxD0/P25 8 Caution To select a transmission method, always use the corresponding number of V PP pulses listed in Table 6-1. Figure 6-1. Format of Transmission Method Selection VPP pulses 10 V VPP VDD 1 2 n VSS VDD RESET VSS Flash memory write mode 16 Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y 6.2 Flash Memory Programming Functions Flash memory writing and other operations can be performed by transmitting/receiving commands and data according to the selected transmission method. Table 6-2 lists the main flash memory programming functions. Table 6-2. Main Flash Memory Programming Functions Function Description Reset Stops writing or detects communication synchronization. Batch verify Compares the entire contents of memory with the input data. Batch internal verify Compares the entire contents of memory in different modes. Batch erase Erases the entire contents of memory. Batch blank check Checks that the entire contents of memory have been erased. High-speed write Writes to the flash memory according to the specified write start address and number of data bytes to be written. Continuous write Continues writing based on the information input by using the high-speed write function. Batch prewrite Writes 00H into the entire contents of memory. Status Checks the current operation mode and whether the operation has terminated. Oscillation frequency setting Inputs the frequency information of the resonator. Erase time setting Inputs the memory erase time. Baud rate setting Sets the communication rate in UART mode. 2 2 I C communication mode setting Sets standard or high-speed mode upon communication via I C. Silicon signature read Outputs the device name, memory capacity, and device block information. Preliminary Product Information U13563EJ2V0PM00 17 µPD78F0701Y 6.3 Connecting the Flashpro III The connection between the Flashpro III and µPD78F0701Y varies with the transmission method. Figures 6-2 to 6-4 show the connection for each transmission method. Figure 6-2. Flashpro III Connection in Three-Wire Serial I/O Mode µPD78F0701Y Flashpro III VPP VPP VDD VDD0 RESET RESET SCK SCK3n SO SI3n SI SO3n GND VSS0 n = 0 or 1 2 Figure 6-3. Flashpro III Connection in I C Bus Mode µ PD78F0701Y Flashpro III VPP VPP VDD VDD0 RESET RESET SCK SCL0 SI SDA0 GND VSS0 Figure 6-4. Flashpro III Connection in UART Mode µ PD78F0701Y Flashpro III VPP VPP VDD VDD0 RESET SO RxD0 SI TxD0 GND 18 RESET VSS0 Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y 6.4 Flash Memory Programming by Self-Writing The flash memory of the µPD78F0701Y can be rewritten by a program. (1) Configuration of flash memory Figure 6-5 shows the configuration of the flash memory. Figure 6-5. Configuration of Flash Memory Self-writing mode Normal operation mode F7FFH F000H EFFFH F7FFH Internal extension RAM are (2K bytes) Internal extension F000H RAM are (2K bytes) EFFFH FLPMC Flash memory area (60K bytes) 0000H 9BFFH 09H Flash memory area (60K bytes) FLPMC Erase/write routine call 08H Firmware area (erase/write routine included) Erase/write * Cannot be accessed by an ordinary instruction. 8000H 0000H Preliminary Product Information U13563EJ2V0PM00 19 µPD78F0701Y (2) Flash programming mode control register (FLPMC) The flash programming mode control register (FLPMC) is used to select an operation mode and check the status of the VPP pin. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets FLPMC to 08H. Figure 6-6. Format of Flash Programming Mode Control Register (FLPMC) Symbol 7 6 5 4 3 2 1 0 FLPMC 0 0 0 0 1 VPP 0 FLSPM0 Address When reset FFCDH 08HNote 1 R/W R/WNote 2 Applied voltage of VPP pin VPP 0 The voltage necessary for erasing/writing flash memory is not applied to the VPP pin. 1 A voltage higher than that on the VDD pin is applied to the VPP pin. FLSPM0 Operation mode selection 0 Normal operation mode 1 Self-writing mode Notes 1. Bit 2 changes depending on the level of the VPP pin. 2. Bit 2 is a read-only bit. Cautions 1. Clear bits 1 and 4 to 7 to 0, and set bit 3 to 1. 2. The VPP bit indicates the status of the voltage applied to the VPP pin. When the VPP bit is "0", the voltage necessary for erasing/writing the flash memory is not applied to the VPP pin. However, the voltage necessary for erasing/writing is not always applied even when the VPP bit is "1". Configure the hardware so that the necessary voltage is accurately applied to the VPP pin. To check whether the necessary voltage is also applied to the VPP pin by software, not only by hardware, use an external hardware detection circuit and its output signals. 20 Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y (3) Self writing procedure The procedure for self writing the flash memory is as follows (see Figure 6-7): (1) Disable the interrupts. (2) Set self-writing mode (FLPMC = 09H). (3) Select register bank 3. (4) Specify the first address of the entry RAM to the HL register. (5) VPP: ON (ON signal for power IC). (6) Check the VPP level. (7) Initialize the flash subroutine. (8) Set the parameters. (9) Control the flash memory (erasing, writing, etc.). (10) VPP: OFF (OFF signal for power IC). (11) Normal operation mode (FLPMC = 08H) Preliminary Product Information U13563EJ2V0PM00 21 µPD78F0701Y Figure 6-7. Self-Programming Flowchart (1) Disable interrupts. (2) Self-writing mode (FLPMC = 09H) (3) Select register bank 3. (4) Specify entry RAM address. (5) VPP: ON (6) VPP = 1? No Yes (7) Initialize flash subroutine. (8) Set parameter. Pre-write Erase Yes Error? No (9) Less than nNote Number of errors? Write data. nthNote Yes Error? No Verify. Yes Error? No Note 22 (10) VPP: OFF (11) Normal operation mode (FLPMC = 08H) Flash memory is abnormal. This differs depending on the user program. Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y Figure 6-8. Self-Writing Timing 5V 4.5 V 4.5 V VDD 0V 10 V VPP 9.7 V 0.2 VDD 0V 5V RESET 0.2 VDD 0.2 VDD 0V CPU operation and program processing Reset mode Normal operation mode Normal Mode program setting processing FLPMC Self-writing mode Erase Write Verify Normal operation mode Normal Mode program setting processing Reset mode 09H VPP ON Flash memory being written VPP = 10 V ±0.3 V VPP OFF FLPMC 08H Preliminary Product Information U13563EJ2V0PM00 23 µPD78F0701Y (4) CPU resources The CPU resources used for self-writing the flash memory are as follows: • Register bank: BANK3 (8 bytes) B register: Status flag C register: Function number HL register: Entry RAM area first address • Stack area: 16 bytes MAX. • Write data storage area: 1 to 256 bytes • Entry RAM area: 32 bytes RAM area used by self-writing subroutine. Can be specified by user by using HL register. • Status flag 7 Parameter setting error 6 - 5 - 4 Verify error 3 Write error 2 1 0 - Blank check error - (5) Entry RAM area Table 6-3 shows the contents of the entry RAM area. Table 6-3. Entry RAM Area Offset value Contents +0 Reserved area (1 byte) +1 Reserved area (1 byte) +2 Flash memory start address (2 bytes) +4 Flash memory end address (2 bytes) +6 Number of bytes written to flash memory (1 byte) +7 Write time data (1 byte) +8 Erase time data (3 bytes) +11 Reserved area (3 bytes) +14 Write data storage buffer first address (2 bytes) +16 Total number of blocks (1 byte) +17 Total number of areas (1 byte) +18 : Reserved area (14 bytes) Example: When the value of the HL register in register bank 3 is 0FD00H 0FD00H: Status 0FD02H: Flash memory start address 0FD06H: Number of bytes written to flash memory : 24 Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y The following explains the entry RAM area in detail. (a) Flash memory start address Flash memory address value used for _FlashByteWrite subroutine (b) Flash memory end address Flash memory address value used for _FlashGetInfo subroutine (c) Number of bytes written to flash memory Area number and number of bytes written to flash memory (d) Write time Set one of the following values according to the operating frequency. fX (MHz) Set value 1.00 to 1.28 20H 1.29 to 2.56 40H 2.57 to 5.12 60H 5.13 to 8.38 80H (e) Erase time data Set value = Erase time (s) × Operating frequency/29 + 1 (Erase time range: 0.5 to 20 s) Example: When the erase time is two seconds and the operating frequency is 6.29 MHz Set value = 2 × 6,291,456/512 + 1 = 24,577 (decimal) = 6001H (hexadecimal) (f) Write data storage buffer first address This area stores the first address of the write data storage buffer area. The data (write data) in the RAM addressed by using the data in this area is written into flash memory (_FlashByteWrite subroutine). Up to 256 bytes of write data can be specified with the data in this area as the first address. (g) Total number of blocks Total number of flash memory blocks stored by _FlashGetInfo subroutine (h) Total number of areas Total number of flash memory areas stored by _FlashGetInfo subroutine Preliminary Product Information U13563EJ2V0PM00 25 µPD78F0701Y (6) Self-writing subroutine Table 6-4 lists the subroutines to be used for self-writing and their functions. Table 6-4. Self-Writing Subroutines Function No. Subroutine name Function Decimal Hexadecimal 0 00H _FlashEnv Initializes flash subroutine. 1 01H _FlashSetEnv Sets parameter. 2 02H _FlashGetInfo Reads flash memory information. 16 10H _FlashAreaBlankCheck Blank check of specified area 32 20H _FlashAreaPreWrit Pre-write of specified area 48 30H _FlashAreaErase Erases specified area 80 50H _FlashByteWrite Successive write in byte units 96 60H _FlashAreaIVerify Internal verification of specified area (7) Configuration of self-writing circuit Figure 6-9 shows the configuration of the self-writing circuit. Figure 6-9. Configuration of Self-Writing Circuit µ PD78F0701Y Power IC µ PC29S10, etc. VDD VPP VOUT = 9.7 to 10.2 V OUTPUT INPUT ON/OFF VSS 10 k Ω Output port VSS 26 ≥ 10 kΩ Preliminary Product Information U13563EJ2V0PM00 VIN = 11 to 13.5 V µPD78F0701Y 7. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (TA = 25°°C) Parameter Supply voltage Symbol Rated value Unit -0.3 to +6.5 V VPP -0.3 to +10.5 V AVSS -0.3 to +0.3 V -0.3 to VDD + 0.3 V -0.3 to +16 V -0.3 to VDD + 0.3 V AVSS - 0.3 to AVREF + 0.3 and -0.3 to VDD + 0.3 V VDD Conditions VDD = AVREF AVREF Input voltage VI1 P00-P07, P20-P27, P30-P32, P34-P36, P40-P47, P50-P57, P64-P67, P70-P77, P80-P87, P90-P97, CRXD/IRX0, X1, X2, RESET VI2 P33 Output voltage VO P00-P07, P20-P27, P30-P36, P40-P47, P50-P57, P64-P67, P70-P77, P80-P87, P90-P97, CTXD/ITX0 Analog input voltage VAN P80-P87, P90-P97 High-level output current IOH P00-P07, P20-P27, P30-P32, P34-P36, P40-P47, P50-P57, P64-P67, P70, P73-P77, P80-P87, P90P97, CTXD/ITX0 per pin -10 mA Total for all pins -30 mA Low-level output current Note IOL Analog input pin P00-P07, P20-P27, P30-P32, P34P36, P40-P47, P50-P57, P64-P67, P70-P77, P80-P87, P90-P97, CTXD/ITX0 per pin Peak value 20 mA rms value 10 mA P33 Peak value 30 mA rms value 15 mA Peak value 100 mA rms value 60 mA -40 to +85 °C -10 to +55 °C Before 2,000 hours elapses after flash memory programming was performed -65 to +150 °C After flash memory programming was performed and 2,000 hours or more has elapsed -65 to +125 °C Total for all pins Operating ambient temperature N-ch open drain TA Programming ambient temperature Storage temperature Tstg Note To obtain the rms value, calculate [rms value] = [peak value] × √duty. Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. Always use the product within its rated values. Remark Unless otherwise specified, the characteristics of a dual-function pin are the same as those of the corresponding port pin. Preliminary Product Information U13563EJ2V0PM00 27 µPD78F0701Y CHARACTERISTICS OF THE SYSTEM CLOCK OSCILLATION CIRCUIT (TA = -40°°C to +85°°C, VDD = 3.5 to 5.5 V) Resonator Crystal Recommended circuit VPP X2 X1 Conditions MIN. Oscillation frequency TYP. MAX. Unit Note 2 6.29 MHz Note 1 (fX) R1 C2 Parameter Oscillation settling C1 Note 3 30 ms time Notes 1. Only the characteristics of the oscillation circuit are indicated. 2. 6.29 = 6.291456 (MHz) 3. Time required for oscillation to settle once a reset sequence ends or STOP mode is deselected. Caution When using the system clock oscillation circuit, observe the following conditions for the wiring of that section enclosed in dotted lines in the above diagrams, so as to avoid the influence of the wiring capacitance. • Keep the wiring as short as possible. • Do not allow signal wires to cross one another. • Keep the wiring away from wires that carry a high, non-stable current. • Keep the grounding point of the capacitors at the same level as VSS1. • Do not connect the grounding point to a grounding wire that carries a high current. • Do not extract a signal from the oscillation circuit. 28 Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y DC CHARACTERISTICS (TA = -40°°C to +85°°C, VDD = 3.5 to 5.5 V) Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level input leakage current Symbol Conditions TYP. MAX. Unit VIH1 P21, P23, P25, P27, P31, P34, P40-P47, P64-P67, P73, P80-P87, P90-P97 0.7VDD VDD V VIH2 P00-P07, P20, P22, P24, P26, P30, P32, P35, P36, P70-P72, P74-P77, CRXD/IRX0, RESET 0.8VDD VDD V VIH3 P50-P57 2.3 VDD V VIH4 P33 0.7VDD 15 V VIH5 X1, X2 VDD - 0.5 VDD V VIL1 P21, P23, P25, P27, P31, P34, P40-P47, P64-P67, P73, P80-P87, P90-P97 0 0.3VDD V VIL2 P00-P07, P20, P22, P24, P26, P30, P32, P35, P36, P70-P72, P74-P77, CRXD/IRX0, RESET 0 0.2VDD V VIL3 P50-P57 0 0.75 V VIL4 P33 0 0.3VDD V VIL5 X1, X2 0 0.4 V VOH1 IOH = -1 mA VDD - 1.0 VDD V VOH2 IOH = -100 µA VDD - 0.5 VDD V VOL1 IOL = 15 mA P33 2.0 V VOL2 IOL = 1.6 mA P71, P72 0.4 V VOL3 IOL = 1 mA 1.0 V VOL4 IOL = 100 µA 0.5 V ILIH1 VIN = VDD P00-P07, P20-P27, P30-P32, P34-P36, P40-P47, P50-P57, P64-P67, P70-P77, P80-P87, P90-P97, CRXD/IRX0, RESET 3 µA X1, X2 20 µA ILIH2 Low-level input leakage current MIN. N-ch open drain N-ch open drain P00-P07, P20-P27, P30-P32, P34-P36, P40-P47, P50-P57, P64-P67, P70, P73-P77, P80-P87, P90-P97, CTXD/ITX0 0.4 P00-P07, P20-P27, P30-P32, P34-P36, P40-P47, P50-P57, P64-P67, P70, P73-P77, P80-P87, P90-P97, CTXD/ITX0 ILIH3 VIN = 15 V P33 80 µA ILIL1 VIN = 0 V P00-P07, P20-P27, P30-P32, P34-P36, P40-P47, P50-P57, P64-P67, P70-P77, P80-P87, P90-P97, CRXD/IRX0, RESET -3 µA ILIL2 X1, X2 -20 µA ILIL3 P33 (during other than input -3 µA Note instruction execution ) Note During input instruction execution, a leakage current of -200 µA (MAX.) is input to P33 for one clock (during no wait). Remark Unless otherwise specified, the characteristics of a dual-function pin are the same as those of the corresponding port pin. Preliminary Product Information U13563EJ2V0PM00 29 µPD78F0701Y DC CHARACTERISTICS (TA = -40°°C to +85°°C, VDD = 3.5 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit High-level output leakage current ILOH VOUT = VDD P00-P07, P20-P27, P30-P36, P40-P47, P50-P57, P64-P67, P70-P77, P80-P87, P90-P97, CTXD/ITX0 3 µA Low-level output leakage current ILOL VOUT = 0 V P00-P07, P20-P27, P30-P36, P40-P47, P50-P57, P64-P67, P70-P77, P80-P87, P90-P97, CTXD/ITX0 -3 µA Software pull-up resistor R1 VIN = 0 V P00-P07, P20-P27, P30-P32, P34-P36, P40-P47, P50-P57, P64-P67, P70, P73-P77 30 90 kΩ IDD1 6.29-MHz crystal oscillation operating mode 4.0 20 mA Note 1 Power supply current Note 2 15 IDD2 6.29-MHz crystal oscillation HALT mode 500 1,000 µA IDD3 STOP mode 0.1 30 µA Notes 1. The current flowing through the VDD1 pin. The power supply current does not include the current flowing through the A/D converter and on-chip pull-up resistors. 2. During low-speed mode operation (when 04H is loaded into the processor clock control register (PCC)). The power supply current does not include the current for peripheral circuit operation. Remark Unless otherwise specified, the characteristics of a dual-function pin are the same as those of the corresponding port pin. 30 Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y AC CHARACTERISTICS (1) Basic operations (TA = -40°°C to +85°°C, VDD = 3.5 to 5.5 V) Parameter Symbol Conditions MIN. Cycle time (minimum instruction execution time) TCY System clock operation (at fX = 6.291456 MHz) 0.318 TI000, TI010, TI001, and TI011 input high/low level width tTIH0 tTIL0 TI50, TI51, and TI52 input frequency fTI5 TI50, TI51, and TI52 input high/low level width tTIH5 tTIL5 Interrupt request input high/low level width tINTH tINTL RESET low level width tRSL TYP. MAX. Unit 5.09 µs µs 4/fsam + Note 0.25 2 INTP0 to INTP7, P40 to P47 MHz 200 ns 10 µs 10 µs Note fX/2, fX/4, or fX/64 can be selected as fsam by using bits 0 and 1 (PRM0n0 and PRM0n1) of the prescaler mode register 0n (PRM0n). If the valid edge of TI00n is selected as the count clock, however, fsam = fX/8 (n = 0 or 1). TCY vs VDD (with system clock running) 10.0 5.09 Cycle time TCY [ µ s] 5.0 2.0 Guaranteed operating range 1.0 0.5 0.318 0.1 0 1.0 2.0 3.0 3.5 4.0 5.0 5.5 6.0 Supply voltage VDD [V] Preliminary Product Information U13563EJ2V0PM00 31 µPD78F0701Y (2) Serial interface (TA = -40°°C to +85°°C, VDD = 3.5 to 5.5 V) (a) Three-wire serial I/O mode (SCK30...Internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK30 cycle time tKCY1 1.9 µs SCK30 high/low level width tKH1 tKL1 tKCY1/2 - 50 ns SI30 setup time (for SCK30 ↑) tSIK1 100 ns SI30 hold time (for SCK30 ↑) tKSI1 400 ns Delay from SCK30 ↓ to SO30 output tKSO1 C = 100 pF Note 300 ns MAX. Unit Note C is the capacitance of the SCK30 and SO30 output line. (b) Three-wire serial I/O mode (SCK30...External clock input) Parameter Symbol Conditions MIN. TYP. SCK30 cycle time tKCY2 800 ns SCK30 high/low level width tKH2 tKL2 400 ns SI30 setup time (for SCK30 ↑) tSIK2 100 ns SI30 hold time (for SCK30 ↑) tKSI2 400 ns Delay from SCK30 ↓ to SO30 output tKSO2 C = 100 pF Note Note C is the capacitance of the SO30 output line. 32 Preliminary Product Information U13563EJ2V0PM00 300 ns µPD78F0701Y (c) Three-wire serial I/O mode (SCK31...Internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK31 cycle time tKCY3 1.9 µs SCK31 high/low level width tKH3 tKL3 tKCY1/2 - 50 ns SI31 setup time (for SCK31 ↑) tSIK3 100 ns SI31 hold time (for SCK31 ↑) tKSI3 400 ns Delay from SCK31 ↓ to SO31 output tKSO3 C = 100 pF Note 300 ns MAX. Unit Note C is the capacitance of the SCK31 and SO31 output line. (d) Three-wire serial I/O mode (SCK31...External clock input) Parameter Symbol Conditions MIN. TYP. SCK31 cycle time tKCY4 800 ns SCK31 high/low level width tKH4 tKL4 400 ns SI31 setup time (for SCK31 ↑) tSIK4 100 ns SI31 hold time (for SCK31 ↑) TKSI4 400 ns Delay from SCK31 ↓ to SO31 output tKSO4 C = 100 pF Note 300 ns Note C is the capacitance of the SO31 output line. Preliminary Product Information U13563EJ2V0PM00 33 µPD78F0701Y (e) UART mode (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate (f) MAX. Unit 38,836 bps MAX. Unit UART mode (external clock input) Parameter Symbol ASCK0 cycle time tKCY3 800 ns tKH3, tKL3 400 ns ASCK0 high/low level width Conditions MIN. TYP. Transfer rate 39,063 bps 2 (g) I C bus mode Parameter Symbol Standard mode High-speed mode MIN. MAX. MIN. MAX. Unit SCL0 clock frequency fSCL 0 100 0 400 kHz Bus free time (between stop-start conditions) tBUF 4.7 - 1.3 - µs tHD:STA 4.0 - 0.6 - µs SCL0 clock low level width tLOW 4.7 - 1.3 - µs SCL0 clock high level width tHIGH 4.0 - 0.6 - µs Start/restart condition setup time tSU:STA 4.7 - 0.6 - µs Data hold time tHD:DAT 5.0 - Note 1 Hold time CBUS-compatible master Note 2 2 I C bus Data setup time 0 - - µs Note 3 µs - ns Note 2 0 Note 4 0.9 tSU:DAT 250 - SDA0 and SCL0 signal rising time tR - 1,000 - 300 ns SDA0 and SCL0 signal falling time tF - 300 - 300 ns tSU:STO 4.0 - 0.6 - µs Pulse width of spikes controlled by the input filter tSP - - 0 50 ns Capacitive load of each bus line Cb - 400 - 400 pF Stop condition setup time 100 Notes 1. In the start condition, the first clock pulse is generated after this period of time. 2. To fill the undefined area of the SCL0 falling edge (at VIHmin. of the SCL0 signal), the device needs to internally provide a hold time of at least 300 ns for the SDA0 signal. 3. If the device does not extend the low hold time (tLOW) of the SCL0 signal, the maximum data hold time (tHD:DAT) only needs to be satisfied. 2 2 4. High-speed mode I C bus can be used in standard mode I C bus system. In this case, the following conditions must be satisfied: • When the device does not extend the low hold time of the SCL0 signal tSU:DAT ≥ 250 ns • When the device extends the low hold time of the SCL0 signal Before SCL0 is released (tRmax. + tSU:DAT = 1,000 + 250 = 1,250 ns: for standard mode I2C bus system), the next data bit must be sent onto the SDA0 line. 34 Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y AC TIMING MEASUREMENT POINTS (except the X1 inputs) 0.8VDD 0.2VDD 0.8VDD Measurement points 0.2VDD CLOCK TIMING 1/fX tXL tXH VIH5 (MIN.) X1 input VIL5 (MAX.) TI TIMING tTIL0 tTIH0 TI000, TI010, TI001, TI011 1/fTI5 tTIL5 tTIH5 TI50, TI51, TI52 Preliminary Product Information U13563EJ2V0PM00 35 µPD78F0701Y SERIAL TRANSFER TIMING Three-Wire Serial I/O Mode: tKCYn tKHn tKLn SCK30, SCK31 tSIKn tKSIn Input data SI30, SI31 tKSOn Output data SO30, SO31 n = 1-4 UART Mode (External Clock Input): tKCY5 tKL5 tKH5 ASCK0 2 I C Bus Mode: tLOW tR SCL0 tHD:DAT tHD:STA tHIGH tSU:DAT tF tSU:STA tHD:STA tSP tSU:STO SDA0 tBUF Stop Start condition condition 36 Restart condition Preliminary Product Information U13563EJ2V0PM00 Stop condition µPD78F0701Y IEBus 0 CONTROLLER CHARACTERISTICS (TA = -40°°C to +85°°C, VDD = 3.5 to 5.5 V) Parameter IEBus system clock frequency Symbol fS Driver delay (from ITX0 output to bus line) tDTX Receiver delay (from bus line to IRX0 input) tDRX Transmission delay on bus tDBUS Conditions MIN. Fixed to mode 1 TYP. MAX. 6.29 Note Unit MHz 1.5 µs The µPC2590 is used as a driver/receiver. 0.7 µs The µPC2590 is used as a driver/receiver. 0.85 µs C = 50 pF The µPC2590 is used as a driver/receiver. Note C is the load capacitance of the ITX0 output line. Remarks 1. Although the IEBus standard recommends the 6.0-MHz system clock frequency, the µPD78F0701Y guarantees normal operation of the IEBus controller at 6.29 MHz. 2. fS: System clock frequency of the IEBus controller A/D CONVERTER CHARACTERISTICS (TA = -40°°C to +85°°C, VDD = AVREF = 3.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions Resolution MIN. TYP. MAX. Unit 8 8 8 bit ±0.6 % Note Total error Conversion time tCONV 14 100 µs Analog input voltage VIAN AVSS AVREF V RAIREF T.B.D T.B.D kΩ AVREF resistance 28 Note No quantization error (±0.2%) is included. This parameter is indicated as the ratio to the full-scale value. Preliminary Product Information U13563EJ2V0PM00 37 µPD78F0701Y DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = -40°°C to +85°°C) Parameter Symbol Data retention supply voltage VDDDR Data retention supply current IDDDR Release signal set time tSREL Oscillation settling time tWAIT Conditions MIN. TYP. 2.0 VDDDR = 2.0 V 0.1 MAX. Unit 5.5 V 10 µA µs 0 17 Released by RESET 2 /fX ms Released by interrupt Note ms 12 14 19 21 Note Selection of 2 /fX, 2 /fX, 2 /fX, or 2 /fX is available by bits 0 to 2 (OSTS0 to OSTS2) of the oscillation settling time selection register (OSTS). DATA RETENTION TIMING (STOP mode release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT DATA RETENTION TIMING (standby release signal: STOP mode release by interrupt signal) HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 38 Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y INTERRUPT REQUEST INPUT TIMING tINTL tINTH INTP0-INTP7 RESET INPUT TIMING tRSL RESET Preliminary Product Information U13563EJ2V0PM00 39 µPD78F0701Y 8. PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14×14) A B 60 61 41 40 detail of lead end C S D R Q 80 1 21 20 F G H I M J P K M N L NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 17.20±0.20 0.677±0.008 B 14.00±0.20 0.551 +0.009 –0.008 C 14.00±0.20 0.551 +0.009 –0.008 D 17.20±0.20 0.677±0.008 F 0.825 0.032 G 0.825 0.032 H 0.32±0.06 0.013 +0.002 –0.003 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.60±0.20 0.063±0.008 L 0.80±0.20 0.031 +0.009 –0.008 M 0.17 +0.03 –0.07 0.007 +0.001 –0.003 N 0.10 0.004 P 1.40±0.10 0.055±0.004 Q 0.125±0.075 0.005±0.003 R 3° +7° –3° 3° +7° –3° S 1.70 MAX. 0.067 MAX. P80GC-65-8BT 40 Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y APPENDIX A DEVELOPMENT TOOLS The following development tools are available for developing systems using the µPD78F0701Y. Be sure to see notes described in (5). (1) Language processing software RA78K/0 Assembler package used in common with the 78K/0 series CC78K/0 DF780701 C compiler package used in common with the 78K/0 series Note Device file for the µPD780701Y sub-series CC78K/0-L C compiler library source file used in common with the 78K/0 series Note Under development (2) Flash memory write tools Flashpro III (model No. FL-PR3, PG-FP3) Flash writer used only for microcontrollers with internal flash memory FA-80GC Flash memory write adapter. Connect this adapter to the Flashpro III. This adapter is dedicated to the 80-pin plastic QFP (GC-8BT type). Floashpro III controller Program controlled by a personal computer and which is supported by Flashpro III. Runs under Windows TM 95, etc. (3) Debugging tools • When in-circuit emulator IE-78K0-NS is used IE-78K0-NS In-circuit emulator used in common with the 78K/0 series IE-70000-MC-PS-B Power supply unit for the IE-78K0-NS IE-70000-98-IF-C Interface adapter required when a PC-9800 series computer (other than a notebook type) is used as the host machine (C bus supported) IE-70000-CD-IF-A PC card and interface cable required when a notebook-type computer is used as the host machine (PCMCIA socket supported) IE-70000-PC-IF-C Interface adapter required when an IBM PC/AT TM or compatible is used as the host machine (ISA bus supported) IE-70000-PCI-IF IE-780701-NS-EM1 Interface adapter when using PC that incorporates PCI bus as host machine Note Emulation board used to emulate the µPD780701Y sub-series products NP-80GC Emulation probe dedicated to the 80-pin plastic QFP (GC-8BT type) EV-9200GC-80 Conversion socket for connecting the target system board created for the 80-pin plastic QFP (GC-8BT type) with the NP-80GC ID78K0-NS Integrated debugger for IE-78K0-NS SM78K0 System simulator used in common with the 78K/0 series DF780701 Note Device file for the µPD780701Y sub-series Note Under development Preliminary Product Information U13563EJ2V0PM00 41 µPD78F0701Y • When in-circuit emulator IE-78001-R-A is used IE-78001-R-A In-circuit emulator used in common with the 78K/0 series IE-70000-98-IF-C Interface adapter required when a PC-9800 series computer (other than a notebook type) is used as the host machine (C bus supported) IE-70000-PC-IF-C Interface adapter required when an IBM PC/AT or compatible is used as the host machine (ISA bus supported) IE-70000-PCI-IF Interface adapter when using PC that incorporates PCI bus as host machine IE-78000-R-SV3 IE-780701-NS-EM1 Interface adapter and cable required when an EWS is used as the host machine Note Emulation board used to emulate the µPD780701Y sub-series IE-78K0-R-EX1 Emulation probe conversion board required when the IE-780701-NS-EM1 is used with the IE-78001-R-A EP-78230GC-R Emulation probe dedicated to the 80-pin plastic QFP (GC-8BT type) EV-9200GC-80 Conversion socket for connecting the target system board created for the 80-pin plastic QFP (GC-8BT type) with the EP-78230GC-R ID78K0 Integrated debugger for IE-78001-R-A SM78K0 System simulator used in common with the 78K/0 series DF780701 Note Device file for the µPD780701Y sub-series Note Under development (4) Real-time OS RX78K/0 Real-time OS for the 78K/0 series MX78K0 OS for the 78K/0 series (5) Notes on using development tools • ID78K0-NS, ID78K0, and SM78K0 are to be used in combination with DF780701. • CC78K/0 and RX78K/0 are to be used in combination with RA78K/0 and DF780701. • FL-PR3, FA-80GC, and NP-80GC are manufactured by Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Contact NEC sales representatives for purchase. • For third party development tools, refer to the 78K/0 Series Selection Guide (U11126E). • The host machines and OSs supporting each software product are as follows: Host machine [OS] Software PC PC-9800 series [Windows] IBM PC/AT and compatibles [Japanese/English Windows] TM HP9000 series 700 TM SPARCstation NEWS TM Ο Ο ID78K0-NS Ο - ID78K0 Ο Ο SM78K0 Ο - Note Ο Note Ο CC78K/0 Ο RX78K/0 Ο MX78K0 Ο Note DOS-based software Preliminary Product Information U13563EJ2V0PM00 TM TM ] , Solaris (RISC) [NEWS-OS Note Ο [HP-UX [SunOS Note RA78K/0 42 EWS TM ] TM ] µPD78F0701Y PACKAGE DRAWINGS OF THE CONVERSION SOCKET (EV-9200GC-80) AND RECOMMENDED PATTERN ON BOARDS Figure A-1. Package Drawings of the EV-9200GC-80 (Reference) Based on EV-9200GC-80 (1) Package drawing (in mm) A E M B N O L K S J C D R F EV-9200GC-80 Q 1 No.1 pin index P G H I EV-9200GC-80-G0E ITEM MILLIMETERS INCHES A 18.0 0.709 B 14.4 0.567 C 14.4 0.567 D 18.0 0.709 E 4-C 2.0 4-C 0.079 F 0.8 0.031 G 6.0 0.236 H 16.0 0.63 I 18.7 0.736 J 6.0 0.236 K 16.0 0.63 L 18.7 0.736 M 8.2 0.323 O 8.0 0.315 N 2.5 0.098 P 2.0 0.079 Q 0.35 0.014 R φ 2.3 φ 0.091 S 1.5 0.059 Preliminary Product Information U13563EJ2V0PM00 43 µPD78F0701Y Figure A-2. Recommended Pattern for Mounting the EV-9200GC-80 on Boards (Reference) Based on EV-9200GC-80 (2) Pad drawing (in mm) G J H D E F K I L C B A EV-9200GC-80-P1E ITEM MILLIMETERS A 19.7 B 15.0 0.776 0.591 C 0.65±0.02 × 19=12.35±0.05 D +0.003 0.65±0.02 × 19=12.35±0.05 0.026 +0.001 –0.002 0.748=0.486 –0.002 0.026+0.001 –0.002 × 0.748=0.486 +0.003 –0.002 E 15.0 0.591 F 19.7 0.776 G 6.0 ± 0.05 0.236 +0.003 –0.002 H 6.0 ± 0.05 0.236 +0.003 –0.002 I 0.35 ± 0.02 0.014 +0.001 –0.001 J φ 2.36 ± 0.03 φ 0.093+0.001 –0.002 K φ 2.3 φ 0.091 L φ 1.57 ± 0.03 φ 0.062+0.001 –0.002 Caution 44 INCHES Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y APPENDIX B RELATED DOCUMENTS • Documents related to devices Document name Document No. Japanese English µPD780701Y Sub-Series User's Manual U13781J U13781E µPD780701Y, 780702Y Preliminary Product Information U13920J U13920E µPD78F0701Y Preliminary Product Information U13563J This manual 78K/0 Series User's Manual, Instruction U12326J U12326E • Documents related to development tools (user's manual) Document name Document No. Japanese RA78K0 Assembler Package English Operation U11802J U11802E Language U11801J U11801E Structured Assembly Language U11789J U11789E U12323J EEU-1402 Operation U11517J U11517E Language U11518J U11518E Programming Know-How U13034J U13034E IE-78K0-NS To be created To be created IE-78001-R-A To be created To be created IE-78K0-R-EX1 To be created To be created IE-780701-NS-EM1 To be created To be created EP-78230 EEU-985 EEU-1515 RA78K Series Structured Assembler Preprocessor CC78K0 C Compiler CC78K/0 C Compiler Application Note SM78K0 System Simulator Windows Base Reference U10181J U10181E SM78K Series System Simulator External Parts User Open Interface Specifications U10092J U10092E ID78K0-NS Integrated Debugger Windows Base Reference U12900J U12900E ID78K0 Integrated Debugger EWS Base Reference U11151J ID78K0 Integrated Debugger Windows Base Guide U11649J U11649E ID78K0 Integrated Debugger PC Base Reference U11539J U11539E Preliminary Product Information U13563EJ2V0PM00 - 45 µPD78F0701Y • Documents related to software to be incorporated into the product (user's manual) Document name Document No. Japanese 78K/0 Series Real-Time OS OS for 78K/0 Series MX78K0 English Basic U11537J U11537E Installation U11536J U11536E Basic U12257J U12257E • Other documents Document name Document No. Japanese NEC IC Package Manual (CD-ROM) - English C13388E Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Device C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J C11892E Semiconductor Device Quality Control/Reliability Handbook C12769J - Guide for Products Related to Micro-Computer: Other Companies U11416J - Caution The above documents may be revised without notice. Use the latest versions when you design an application system. 46 Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Preliminary Product Information U13563EJ2V0PM00 47 µPD78F0701Y Caution This product contains an I2C bus interface circuit. When using the I2C bus interface, notify its use to NEC when ordering custom code. NEC can guarantee the following only when the customer informs NEC of the use of the interface: Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. FIP is a trademark of NEC Corporation. IEBus and Inter Equipment Bus are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of SONY Corporation. 48 Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Preliminary Product Information U13563EJ2V0PM00 49 µPD78F0701Y [MEMO] 50 Preliminary Product Information U13563EJ2V0PM00 µPD78F0701Y [MEMO] Preliminary Product Information U13563EJ2V0PM00 51 µPD78F0701Y Some related documents may be preliminary versions. Note that, however, what documents are preliminary is not indicated in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC’s Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5