AD ADC1121

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.
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LowPower
Analogto DigitalConverter
~ ANALOG
W DEVICES
ADC1121
FEATURES
12 Bit Resolution and Accuracy
CMOS Compatible
Very Low Power Consumption
Exceptional Power Supply Rejection
Can Operate From Single Battery
No Missing Codes, 0 to +70°C
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The special combination of high performance and low power
exhibited by this 2" x 4" x 0.4" (SIx 102 x IOmm) module
makes it ideal for use in applications such as remote and portable instrumentation, and large data handling networksTIMING
When the convert command is set to logic" 1", the internal
clock starts to run. The first '1' to '0' clock transition sets the
STATUS output to logic '1' and sets the MSB through LSB and
SERIAL output lines to logic '0'. The CONYERT COMMAND
input may be returned to logic '0' lOOns after this clock transition but may also remain at logic '1' until SOOnsbefore the
sixth clock transition. The MSB decision process starts on the
second negative~oing clock edge and concludes one clock
period later. The bit decisions continue at the rate of one per
clock cycle until the LSB decision has finally been made. After
Information
furnished by Analog Devices is believed to be
and reliable. However, no responsibility
is assumed by Analog
for itS use; nor for any infringementS of patents or other rights
parties which may result from its use. No license is granted by
tion or otherwise under any patent or patent rights of Analog
accurate
Devices
of third
implicaDevices.
,
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GENERAL DESCRIPTION
The CMOS compatible ADC112I requires less than 6 microjoules of energy to perform a complete, 12 bit analog-to-digital
conversion. In addition, it has :to.OI% relative accuracy, a 70fJ.s
maximum conversion time, a maximum power consumption of
IOOmWfor continuous conversions, and no missing codes from
0 to +70°C. Power may be supplied by a single +I2Y to +ISY
source, but the logic portions of the converter may also be
powered by a separate +SY to +ISY supply to permit logic
level matching. If batteries are used as a power source, the
resulting voltage droop will have little effect on the ADC112I
accuracy due to its excellent power supply rejection.
The ADC112I accepts analog inputs in the range of 0 to +SY,
0 to +IOY, :tSY, or :tIOY and produces both parallel and serial
digital outputs. Parallel outputs are binary, offset binary, or
two's complement coded; serial outputs are binary or offset
binary coded.
8
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OBS
8
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the LSB decision, the clock returns to logic' l' and the STATUS
output returns to logic '0'.
TE
The serial data output is of the non-return-to-zero (NRZ) type.
The data is available, MSB first, at the third and subsequent
positive~oing dock transitions,
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GATED
---,nnnnnr
mU U U U U U
CONVERT
COMMAND.-I
CLOCK
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--_J:LIL-
STATUS
....
MSB
BIT2=~""
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BIT
:
LSB
SERIAL
OUTPUT
....
1:
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n
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Ms! t
10)
BIT 2
11)
L
3
10)
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LSB
101
Figure 1. Timing Diagram
Route 1 Industrial Park; P.O. Box 280; Norwood, Mass. 02062
Tel: 617/3294700
TWX: 710/394-6577
West Coast
Mid,West
Texas
213/595-1783
312/894-3300
214/231,5094
..... "'~.a£
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SPECIFICA
TIONS (typical @+25°C unlessotherwise noted)
12 Bits
ACCURACY
Error Relative to Full Scale
Differential Nonlinearity Error
Missing Codes
i'hLSB max
i\-2LSB max
TEMPERATURE
Unipolar
,
J-
COEFFICIENT
i20ppm/oC
of Reading, max 1
i8ppm/C
of Range, max2
i20ppm/C
of Range, max2
:!:5ppm/C
of Range, max2
Zero
Bipolar' Offset
Differential
Dimensions
No Missing Codes from
0 to +70oC
Gain
Nonlinearity
CONVERSION
---
OUTLINE DIMENSIONS AND
PIN DESIGNATIONS
RESOLUTION
I
shown in inches and (mm).
j
2.01 MAX(51.1)
0.41 MAX (10.4)
u IrINI5,1)
u
-.
TIME3
631ls (701ls max)
HILs (611ls maxI
HILs (591ls max)
+5V Logic Supply
+ IOV Logic Supply
+15V Logic Supply
INPUT VOLTAGE
RANGES
36
37
19
t-t
18
54
+-+
55
0 to +5V, 0 to +IOV,
:!:5V, :!:10V
OBS
INPUT IMPEDANCE
400kn
144kn
144kn
120kn
0 to +5V Range
0 to +IOV Range
:!:5V Range
:!:10V Range
DIGITAL OUTPUTS
Logic Levels
Parallel Output Codes
Unipolar
Bipolar
min
min
min
min
OLE
4.02 MAX
1102.1)
CMOS Compatible (see pg. 4)
Positive True Binary
Positive True Offset Binary,
or Two's Complement
Serial Output Codes
Unipolar
Positive True Binary,
NRZ Format, MSB First
Positive True Offset Binary,
NRZ Format, MSB First
Logic 'I' During Conversion
Bipolar
Status Output
CONVERT COMMANDINPUT
Logic Levels
Pulse Width
Rise and Fall Times
+12V to +15V
+5V to +15V
See Graphs on pg. 3
POWER SUPPLY SENSITIVITYs
Gain
0 to +70oC
-55 to +125°C
Operating
Storage
COMeAR.TOR
ADJUSTMENT RANGES
Gain
Offset
for bipolar
operation
is defined
as;
ActUal
Reading
- (-Full Scale)
-0
, Range for unipolar operation is defined as; + Full Scale
Range for bipolar operation is defined as, 2 (+ Full Scale)
'Conversion time is measured from the rising edge of the convert
command pulse to the falling edge of the STATUS nutput. A
graph showing conversion time as a function of logic supply voltage is shown on page 3.
4 Power supply current for both the analog and logic supplies is very
transient in natUre; peak current for both is less than lOOrnA.
s Maximum change as analog supply voltage varies from +12Y to +15Y.
Specifications
68
67
66
65
64
2
to.2% of Range 2
iO.2% of Range
$229
PRICE (1-9)
I Reading
8 t
BLOCK DIAGRAM
t\4LSB
t\4LSB
:!:\4LSB
Unipolar Zero
Bipolar Offset
TEMPERATURE RANGE
--1 I--GRIDO.I" 12.5)
NOTE:
Terminal pins installed only in shaded hole
locations.
All pins are gold plated half-hard brass
(MIL-G-45204), 0.019" iO.001" (0.48
iO.03mm) dia.
For plug-in mounting card order Board
No. AC1521, $33.00 (1-9)
CMOS Compatible (see pg. 4)
61ls min, 151ls max;
Ills max
.POWER SUPPLY REQUIREMENTS4
Analog Supply (V s)
Logic Supply (VDD)
POWER CONSUMPTION
TE
BOTTOM VIEW
72
ANALOG
SUPPLY
COMMON
GAIN
GOG"AL TO
ANALOG
CONVERTER
18
ADJUST { 19
ANALOG
SUPPL Y
26 I 0--
success,v,
CLOCK
-2-
mROXOMAnON
LGG"
}
160 LOGICSUPPLY
*"
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
1
subject to change without norice.
ANALOG INPUT
B
RANGE
A
PROGRAMMING
ANALOG LOW
REF OUT
LOGIC GND
BIT 10
BIT 9
BIT 11
LSB
BIT 6
BIT 7
81T 8
BIT 5
MS8
BIT 2
BIT 3
BIT4
STATUS
STATUS
GATEDCLKOUT
SERIAL OUT
CONY. COMM,
~
18 t
~
Applyingthe ADC1121
74
10"
72
10"
70
""'
is
60
"0
56
~
z
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.....
62
~
..........
...........
"""'-
58
......
54
52
50
5
e
--
......
~ 68
... 66
:IE
;:: 64
~I
10"
Z
~
MAX
..
:IE
~
"
0
TYP
to--
TI
pl
M
be
di;
10'"
10"
ffi10"
~
6
8
9
10
11
LOGIC SUPPLY VOLTAGE
12
-
13
14
I I
I
5? 10., 'ANALOG [email protected]+15V
[email protected]+12V
15
VDD
10"
10"
10'"
10"
10"
Conversion Time Vs. Logic Supply Voltage
10"
10.
THROUGHPUT
10'
10'
10'
-
RATE
10<
10'
Hz
OBS
Power Consumption Vs. Throughput Rate
and Supply Voltages
70
60
50
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0
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4D
30
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g.,
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90
3.0
80
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iSe
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0=
100
20
15
10
9
8
7
6
2.0
1.5
IZ
~
~
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60
5t
"':IE
50
C:;!i!!
40
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30
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....
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0.6
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0.5
5
70
0::::>
1.0
0.9 ...
0.8
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9i
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0.4 :it...
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20
11.5
0.3 §:it
0::
...
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0.2 5?
12.0
12.6
Logic
8
9
10
11
LOGIC
SUPPLYVOLTAGE-
12
14
13
13.5
TE
14.0
ANALOG SUPPLY VOLTAGE
14.5
-
15.0
15.5
Volts
Analog Circuits Power Consumption
0.15
6
13.0
0.1
15
VDD
Circuits Power Consumption
ANALOG INPUT CHARACTERISTICS
The input circuit of the ADCl121 is shown below in block
diagram form.
68
ANALOG INPUT
67
B
66
A
sary to provide the comparator with a 0 to +5V input which is
then compared to the 0 to +5V D/ A converter output. Table I,
below, shows the range programming connections required for
the various input ranges and also shows the resulting input
impedances.
l00kil
l00kil
RANGE
PROGRAM
~
r
INPUT
RANGE
}
65
ANALOG GROUND
64
REFERENCE OUTPUT
0 to +5V
0 to +10V
:t5V
:tlOV
FROM
CONNECTIONS
PIN 66 TO:
PIN 67 TO:
68
65
64
64
68
68
68
65
INPUT
IMPEDANCE
500kil
180kil
180kll
150kll
min
min
min
min
-3...
Cl
n
ro;
th
pu
In!
IS
51
PARALLEL DATA OUTPUTS
TheADC1l21 produces natural binary coded outputs when
configured as a unipolar device; as a bipolar device it can produce either offset binary or two's complement output codes.
Analog signals in the range of 0 to +5V, 0 to +10V, :t5V, or
:t10V are applied between pins 68 and 65. The range programming circuitry serves to offset and divide these signals as neces-
SEI
STt
Table I. Range Programming
2. Analog Input Configuration
Fi!
se!
IS'
tr~
ti<
pu
sel
--
REFERENCE
SOURCE
Figure
SE
Th
to.
bi!
po
/-
...0-
WGIC LEVELS
The logic levels of the ADC1l21's CMOS digital outputs are as
shown below:
The most significant bit is represented by pin 46 (the MSB output) for binary and offset binary codes and by pin 37 (the
MSB output) for the two's complement code. Tables II and III,
below, illustrate the relationship between the analog input and
digital output for all three codes.
DIGITAL OUTPUT
ANALOG INPUT
0 TO +5Y
RANGE
0 TO +10Y
RANGE
+4.9988Y
+2.5000Y
+0.6250V
+0.0012Y
+9.9976Y
+5.0000Y
+1.2500Y
+0.0024Y
+O.OOOOY
+O.OOOOY
The logic power supply voltage (which is independent of the
analog supply voltage) can be varied from +5V to +15V. This
allows the user to match the converter's logic levels to the logic
levels of other CMOS devices in his system.
BINARY CODE
111111111111
100000000000
001000000000
000000000001
000000000000
Table II. Nominal Unipolar Input-Output
INPUT
Although TTL logic levels can be achieved by setting the logic
supply voltage to +5V, the MSB through LSB output gates do
not have sufficient current sink capability to drive standard
TTL logic. They can, however, readily drive low power TTL
such as the series 74L devices. The remaining digital outputs
(STATUS, STATUS, SERIAL OUT, CLOCK OUT, and MSB)
have a 4mA current sink capability and, thus, can be used
directly with standard TTL logic.
Relationships
OBS
ANALOG
VDD;;' Logic "1";;' VDD - O.IV; where VDDis the logic
supply voltage.
O.IV;;' Logic "0";;' O.OV
DIGIT AL OUTPUT
.
:t5Y
RANGE
:tlOY
RANGE
OFFSET BINARY
+4.9976Y
+2.5000Y
+0.0024V
+o.OOOOY
-5.0000Y
+9.9951Y
+5.0000Y
+0.0049Y
+O.OOOOY
-lO.OOOOY
111111111111
110000000000
100000000001
100000000000
000000000000
CODE
Table III. Nominal Bipolar Input-Output
I
TWO'S
CONVERT COMMAND, the only digital input, will respond to
logic levels of:
COMPLEMENT
CODE
OLE
VDD;;;' Logic "1";;' 0.7 VDD
0.3 VDD ;;. Logic "0";;' O.OV
011111111111
010000000000
000000000001
000000000000
100000000000
However, for minimum logic power supply consumption,
Logic '1' should be kept as close to VDD as possible and Logic
'0' as close to O.OVas possible.
TE
Relationships
GAIN AND OFFSET ADJUSTMENTS
The potentiometers used for making gain and offset adjustments
are connected as shown in Figure 4. These potentiometers
should be small 10 or 20 turn cermet type devices mounted as
close to the module pins as possible.
SERIAL DATA OUTPUTS
The serial data output, available at pin 39, is of the non-returnto-zero format. The data, which is transmitted MSB first, is
binary coded for unipolar units and offset binary coded for bipolar units.
Figure 3, below, indicates one method for transmitting data
serially using only three wires (plus a digital ground). The data
is clocked into a receiving shift register by the positive-going
transitions of the gated clock output. Since these clock transitions occur typically 250 to 5SOns after each bit of serial output data becomes valid, ample time is allowed for shift register
set-up.
LSB
SERIAL OUTPUT
39
CLOCK OUTPUT
40
STATUS OUTPUT
6
OFFSET ADJUST
Ik!J
GAIN ADJUST
2k!J
MSB STATUS
Figure 4. Adjustment Potentiometer
Connections
Proper gain and offset calibration requires great care and the
use of sensitive and accurate reference instruments. The voltage
standard used as a signal source must be very stable. It should
be capable of being set to within ::!:1/lOLSBof the desired value
at both ends of its range.
42
The gain and offset calibrations will be independent of each
other if the offset adjustment is made first. These adjustments
are not made with zero and full scale input signals and it may
be helpful to understand why. An AID converter will produce
a given digital word output for a small range of input signals,
the nominal width of the range being lLSB. If the input test
signal is set to a value which should cause the converter to be
on the verge of switching between two adjacent digital outputs,
the unit can be calibrated so that it does, in fact, switch at just
that point. With a high speed convert command rate and a visu-
Figure 3. Serial Data Transmission
The STATUS output goes from logic '1' to logic '0' approximately 100 to 450ns after the last '0' to '1' clock transition. If
the shift register's propagation delay exceeds this CLOCK output to STATUS output delay, the parallel output data appearing at its terminals will not be stable when end-of-conversion
is signalled. The introduction of a suitable delay into the
STATUS output line will readily circumvent this problem.
-4--
al display, these adjustments can be performed in a very accurate
and sensitive way. Analog Devices' Conversion Handbook gives
more detailed information on testing and calibrating A/D converters.
60
OFFSET CALIBRATION
For 0 to +5V units set the input voltage precisely to +0.0006V;
for 0 to +10V units set it to +0.0012V. Adjust the offset
potentiometer until the converter is just on the verge of switching from 000000000000 to 000000000001.
16
55
+
26
For :t5V units set the input voltage precisely to +0.0012V; for
:tlOV units set it to +0.0024V. Adjust the offset potentiometer
until offset binary coded units are just on the verge of switching
from 100000000000 to 100000000001 and.two's complement
coded units are just on the verge of switching from
000000000000 to 000000000001.
Figure 6. Single Source Connection
Since battery-powered equipment is one of the prime areas of
application for the ADC 1121, excellent power supply rejection
has been provided. The ADC1121 will have less than a :t\4LSB
gain shift and less than a :t\4LSB offset shift as the analog
supply voltage changes from +15V to +12V during the course
of a battery discharge cycle.
OBS
GAIN CALIBRATION
Set the input voltage precisely to +4.9982V for 0 to +5V units,
to +9.9963V for 0 to +10V units, to +4.9963V for :t5V units,
or to +9.9927V for :tlOV units. Note that these values are
1'hLSB's less than nominal full scale. Adjust the gain potentiometer until binary and offset binary coded units are just on the
verge of switching from 111111111110 to 111111111111 and
two's complement coded units are just on the verge of switch;ng from 011111111110 to 011111111111.
OLE
REPETITIVE CONVERSIONS
When making repetitive conversions, a new convert command
pulse may be initiated any time after the' 1' to '0' transition
of the STATUS output. If the STATUS output is connected to
the CONVERT COMMAND input, a new conversion will automatically begin as soon as the conversion in progress has been
completed. The STATUS line will remain in the logic' l' state
for approximately 4,us betWeen conversions in this mode of
operation.
TE
POWER SUPPLY AND GROUNDING CONNECTIONS
The ADC1121 has independent analog and logic supply inputs
which may be powered from a single source or from separate
sources. Figures 5 and 6, below, show the proper connections
for both cases. The analog supply ground, pin 16, and the digital supply ground, pin 55, are not connected internally but
should be jumpered together close to the module pins. Although
the analog supply ground and analog signal ground, pin 65, are
joined inside the module, pin 65 should never be used as a
power supply return. Due to the transient nature of the supply
currents encountered in a device of this type, it is recommended
[hat 15,uF, 35V tantalum bypass capacitors be added across
the analog and digital supplies at a location close to the module
JInS.
HANDLING CONSIDERATIONS
Care must be taken in the handling of the ADC1121 to prevent
electrostatic damage to its CMOS logic. The unit should be
transported on conductive foam or other suitable material and
should be handled only by properly grounded personnel.
Ground connections must be made before power is applied.
Electrostatic damage, should it occur, would be manifested by
excessive logic current drain and/or complete failure of one or
more logic IC's.
THE AC1521 MOUNTING CARD
The AC1521 mounting card is available to assist in the application of the ADC1121. This 4.5" x 4.4" (114 x I11mm) printed
circuit card, shown in Figure 7, has sockets which allow an
ADC1121 to be plugged directly onto it. It includes the necessary gain and offset adjustment potentiometers and bypass
capacitors; it mates with a Cinch 251-22-30-160 (or equivalent)
dual 22 pin edge connector which is supplied with every card.
60
16
55
26
Figure 5. Two Source Connection
-5.
----
~--
--
----
4.500
0
r
L
l
J
The input voltage range is programmed by means of jumpers
which the user installs as shown in Figure 8. The pin connections are as shown in Table IV.
/114.301
=::=1"
OFFSET
GAIN
0
0
..0
e,
ADC1121
4.375
(111.13)
I
@D
.c=J-
@E
@F
INPUT
VOLTAGE
RANGE
JUMPER
CONNECTIONS
0 to +5V
0 to +10V
:SV
:10V
E.D. B.A
E.F. B.A
E.G. B.A
E.G.B.C
<0
t::.
cy
co
I
fco
(')
()
@c
@G
OBS
Figure 8. AC1521 Range Programming
DIMENSIONS SHOWN IN INCHES AND Imml
Figure 7. AC1521 Outline Drawing
OLE
PIN
FUNCTION
PIN
A
B
C
D
E
F
H
MSB
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
LSB
Logic Ground
N.C.
+ Analog Supply
1
2
3
4
5
6
MSB
Convert Command
Serial Output
Gated Clock Out
Status
Status
:
N.C.
J
K
L
M
N
P
R
S
T
U
V
W
X
Y
Z
10
11
12
13
14
FUNCTION
}
15 -
Logic Supply
N.C.
Analog Supp. Comm.
TE
8 t
16
17
18
19
20
21
22
N.C.
Analog Low
N.C.
Analog Input
Table IV. AC1521 Pin Designations
~
~
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z
0
w
fZ
a:
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--
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4