Application Note - AN844

VISHAY SILICONIX
www.vishay.com
Power MOSFETs
Application Note - AN844
How to Select the Right MOSFET
for Power Factor Correction Applications
Power factor is the ratio of the real power (P = Watts) to the apparent power (VA = Volt Ampere); the goal is to achieve a power
factor as close to 1 as possible. A load with a lower power factor draws more reactive current than a load with a higher power
factor for the exact same output power. The higher current increases the energy lost within the system, and for utility companies,
results in excessive wasted power in transmission. For this reason, a power factor correction (PFC) circuit block, shown in
figure 1, is an important, and often mandatory, sub-system of any power supply with an output power of 75 W or more (per
EN61000-3-2). A PFC circuit block is used to align the input line current with the AC voltage waveforms, and in most cases
boosts the output voltage to a common 400 VDC. Figures 2 and 3 shows the impact of a PFC circuit on the line current and its
harmonics.
Fig. 1 - PFC Schematic
Fig. 3 - Waveforms with PFC
In figure 2, current is drawn from the AC supply only for a
short duration of the cycle. This results in a poor power
factor and excessive harmonics of 115 %. While the system
draws only 158 W of usable power, 272 Volt-Amperes are
circulated in the transmission system to deliver it.
Figure 3 shows the benefits of implementing PFC using the
same input power profile. With a power factor of 99.9 %,
harmonics are down to 3 %. Current is drawn from the AC
line throughout the cycle and no excessive Volt-Amperes
are wasted.
Revision: 03-Jun-13
Document Number: 65677
1
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APPLICATION NOTE
Fig. 2 - Line Voltage and Current without PFC
Application Note - AN844
www.vishay.com
Vishay Siliconix
How to Select the Right MOSFET
for Power Factor Correction Applications
It should be noted that PFC and harmonic current reduction
are not synonymous. For example, in a highly inductive load,
the current may be a perfect sinusoid lagging the voltage. It
will then have a poor power factor and high reactive power
without any harmonics at all. Whereas a distorted waveform,
rich in harmonic currents, usually has all the undesirable
features. The PFC circuit corrects more than just the power
factor; it reduces the harmonics. Today, there are different
standards specifying the quality of power drawn by
electronic equipment. EN61000-3-2 requires harmonic
current reduction on all systems with input power of > 75 W.
80 Plus power supply certification requires a power factor of
0.9 or more.
In a PFC circuit, the MOSFET is responsible for
approximately 20 % of all losses. By choosing the correct
device, PFC efficiency can be greatly increased. One way to
select the right MOSFET for a PFC circuit is by using an
application-specific Figure of Merit (FOM) that is focused on
minimizing total losses in the device. While it includes
on-resistance (RDS(on)) for conduction losses and gate
charge (Qg) for switching losses, the FOM is not a simple
product of the two. In order to account for switching losses,
a portion of the device's Qgs and Qgd, along with its output
capacitance (Coss), are used.
The four stages of a standard AC/DC power supply are:
• Input
• PFC Front End
• Converter
• Secondary
To meet 80 Plus Gold efficiency standards, the combined
loss for all stages is ~ 12 % of the rated output power. The
PFC MOSFET alone should be limited to around 2 % of the
total output power or the package power limit, whichever is
lower. The maximum power loss limits of “TO” packages
are:
In universal input power supplies, the PFC MOSFET is
always subjected to the bulk DC bus voltage of 380 VDC to
400 VDC. As a result, the output switching loss can be a
significant portion of the total losses. The Coss of a
high-voltage MOSFET (HVM) varies considerably with the
applied VDS. This variation is much wider for high-voltage
Super Junction power MOSFETs than for planar types. To
account for the non-linearity of the output capacitor,
Poss = ½ Coer x V2 x Fsw may be used as the loss equation.
Coer is the effective capacitance that has the same stored
energy and same losses as the integrated Coss of the
MOSFET, and is provided in the datasheets. So, the new
FOM will now look like RDS(on) (typ.) * (Qswitch (typ.) + Qoss),
where Qswitch is a combination of Qgd and Qgs.
As an example, we will use a TO-220 device with a
maximum package power loss of 10 W, and contribute 5 W
to conduction losses and 5 W to switching losses. The
Coss/Qoss losses would contribute to approximately 20 % of
the overall package loss, or 40 % of the total switching
losses, which is a large loss that is not taken into account
with the standard FOM equation. With this in mind we have
developed a list of components that we feel will achieve the
highest efficiency for a PFC design based on the following
operating conditions (see table 1) to help our customers
develop the most efficient design possible.
TABLE 1 - POWER FACTOR CORRECTION
DESIGN CONDITIONS
Input Voltage
100 V
• TO-220 / TO-220F: 10 W/8 W
Output DC Voltage
400 V
• TO-247: 20 W
PFC Switching Frequency
65 kHz
• Super TO-247 / Tmax.: 25 W
APPLICATION NOTE
switching loss is incurred both ways, as Coss is charged
when the device turns off and discharged when it is turned
on, and has to be taken into account in the design. The
larger the Coss/Qoss, the larger the switching losses. In
addition, the Qoss loss is fixed and independent of load, as
can be seen by the standard equation Poss = ½ CV2 x Fsw,
where Fsw is the switching frequency.
So, the maximum package power limits that consist of both
conduction and switching losses should not exceed the
above levels. Conduction loss is a simple I2 *R calculation
that takes into account the RDS(on) of the device as well as its
temperature coefficient. The switching losses need to take
into account not only Qg, Qgd, and Qgs, but also Qoss, which
is an integral function of Coss.
The traditional FOM, RDS(on) (typ.) * Qg (typ.), does not take
into account the Coss/Qoss of the device, which is a very
important loss, especially at light loads where switching
losses trump conduction losses. This component of the
Revision: 03-Jun-13
MOSFET Drive Voltage
On/Off Gate Current Range
12 V
0.5 A (25 W) to 1.2 A (475 W)
The list of recommended devices includes an “x” in
the “package” location. For the same set of electrical
characteristics, a number of package options may be
available per device. The packages used will depend on the
power level as well as what MOSFET real estate is allowed.
Figures 2 and 3 define the packages, current rating, voltage,
and device technology of the different part numbers.
Document Number: 65677
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note - AN844
www.vishay.com
Vishay Siliconix
How to Select the Right MOSFET
for Power Factor Correction Applications
Definition: Vishay High-Voltage MOSFET Part Number: SiHxDDNFFG
P – TO-220
F – TO-220F
B – D2PAK
D – DPAK
U – IPAK
N Channel
G – TO-247AC
W – TO-247AD
S – Super TO-247
SiH
Vishay Siliconix
High-Voltage MOSFETs
SiHxDDNFFG
C and D = Conventional Planar
E = Superjunction
Continuous
current rating
at 25°C
Voltage Rating
Divided by 10
40 = 400V
50 = 500V
60 = 600V
Fig. 4 - Part Numbers Definition
With many package options available, table 2 lists the
recommended maximum power rating for the different
package offerings.
With the design conditions, device part number
understanding, and maximum recommended per package
type, table 3 shows the respective devices for the different
power levels.
TABLE 2 - RECOMMENDED POWER LEVELS
BASED ON PACKAGE TYPE
This list shows many different devices. Depending on
whether voltage, efficiency, or price is the higher concern
you can pick and choose the device that best fits your
application.
PACKAGES
APPLICATION NOTE
DPAK (TO-252)
RECOMMENDED MAXIMUM
RATINGS(1)
up to 25 W
IPAK (TO-251)
up to 75 W
D2PAK (TO-263)
up to 200 W
TO-220
up to 350 W(2)
TO-220F
up to 350 W(2)
TO-247AC
up to 1000 W
TO-247AD
up to 1000 W
Super TO-247
up to 1500 W
Note
(1) If multi layer PCBs are used where heat sinking is enhanced then
the package(s) can be used at higher power levels
(2) If an interleaved PFC design is used then the output
power can be up to 750 W (using two TO-220s). Paralleling
two TO-220s or TO-220Fs will allow up to 750 W with a
non-interleaved design.
Revision: 03-Jun-13
Document Number: 65677
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For technical questions, contact: powermosfettechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Revision: 03-Jun-13
10 W
500 V
5W
500 V
500 V
20 W
Pout
500 V
75 W
to 100 W
25 W
to 50 W
500 V
Pout
Pout
500 V
125 W
Pout
500 V
150 W
Pout
500 V
200 W
to 250 W
Pout
500 V
300 W
to 500 W
Pout
SiHx7N60E
-
650 V
SiHx7N60E
-
650 V
650 V
-
SiHx7N60E
600 V
SiHx8N50D
600 V
-
600 V
-
-
-
750 W
to 1 kW
Pout
650 V
-
650 V
-
650 V
-
650 V
-
650 V
-
650 V
-
-
-
-
-
SiHx28N65E
-
SiHG47N65E
650 V
SiHG47N65E
SiHG64N65E
650 V
SiHx33N60E SiHG47N60E SiHG47N60E
Note: Devices with “x” can use multiple packages; ones with “G” and “S” must use the TO-247 and Super TO-247 type packages respectively.
-
600 V
-
SiHS36N60D
500 V
600 W
Pout
SiHx7N60E SiHx12N60E SiHx12N60E SiHx22N60E SiHx22N60E SiHx30N60E SiHG33N60E SiHG73N60E
600 V
600 V
600 V
600 V
600 V
-
SiHx8N50D SiHx12N50C SiHx14N50D SiHx14N50D SiHx16N50C
SiHx6N65E SiHx6N65E SiHx6N65E SiHx6N65E SiHx15N65E SiHx15N65E SiHx22N65E SiHx22N65E SiHx24N65E
600 V
600 V
SiHx5N50D SiHx8N50D
SiHx3N50D SiHx5N50D SiHx12N50C SiHx12N50C SiHx16N50C SiHx16N50C SiHx16N50C SiHx18N50D SiHS36N50D
Pout
Pout
TABLE 3 - POWER FACTOR CORRECTION MOSFET SELECTOR GUIDE
APPLICATION NOTE
Products
under
development
> 1 kW
Pout
Application Note - AN844
www.vishay.com
Vishay Siliconix
How to Select the Right MOSFET
for Power Factor Correction Applications
Document Number: 65677
4
For technical questions, contact: powermosfettechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000