Reference Layouts and Circuit Diagrams Vishay Semiconductors Reference Layouts and Circuit Diagrams For testing and comparing test results a common base is necessary. The layout of a test board can have a quite big influence on parameters, especially on rise and fall time and also on jitter. testing all transceivers with the common Vishay pin order and with a 1 mm lead pitch.1 The test boards and the Gerber plots of the test boards are available on request. In most cases the used power supplies are far away from the device under test and the wiring is done with long inductive cables. In such a case the power supply is not able to supply high peak currents. The only way to overcome this condition is to implement many capacitors close to the device under test. For comparison test data, especially as mentioned before for rise and fall times, the circuit ambient must be well defined. The circuit and the layout may have a quite big influence on the resulting data. Therefore a comparison should only be done under equal or very similar conditions. The boards for testing can be used for different types. Therefore redundant pads for circuit components may be in some cases not used or may have different purposes for different transceivers. For connecting to the test equipment, controllers, and power supplies twisted pair cables are used, which provide low capacitive load and defined impedance. The different usage of pin 7 of the transceiver in figure 2 leads to a layout where only for the case of Vlog at pin 7 the components C5, C6, and R4 may be used. In other cases a jumper replaces R4, and C5 and C6 are omitted. It is very important to note, that the circuit for testing is different from the application circuit, where e.g. in a telephone application the battery is very close to the transceiver and the wiring is also low impedance. In general we recommend using in application circuits the combination R1/C4 (shown in figure 1 and figure 2) and not more than that. In this chapter a common reference layout and the circuit diagram is described which is used for JP1 1 IRED Anode R2 Vlogic Vlogic V cc1 GND V cc R1 C1 SD TXD RXD C4 Ground SD TXD RXD I R T ra ns c e ive r V cc2 2 4 + C1 R1 7 6 8 10 9 5 R2 C2 GND GND 3 19706 R3 VCC GND 2 RXD 4 GND 6 C3 GND + C4 GND C5 Vlog. Mode or NC SD + 8 IRED Cathode IRED Anode RXD TXD Transceiver VCC1 GND SD Vlog. Mode or NC 1 3 5 7 C6 R4 opt. TXD 19707 Figure 1. Generally recommended application circuit for all Vishay IR transceivers. R1/C4 are recommended, R2 necessary only for not internally current controlled transceivers, C1 is optional, when inductive wiring is used. Figure 2. Test circuit for IR transceivers. The component positions are provided on the reference test board and can be populated depending on the demand and the test conditions Circuit description The test board is using only one power supply voltage VCC (at pin 1 of connector JP1, figure 2) for the transmitter and receiver. Another supply voltage is available for different logic voltages Vlog at JP1, pin 3 connected to pin 7 of the transceiver. The analog supply voltage VCC1 at pin 6 of the transceiver is connected to VCC via a low pass filter given by R1 and C3/C4. Also C1/C2 contribute to smoothing and stabilizing the voltage at pin 6, VCC1. The IRED anode is connected to the power supply via R2/R3 (two parallel resistors for increased power dissipation). These re1 sistors define the IRED current for the case a switch is built into the transceiver. In case of a built-in current controller, these two resistors can be replaced by a jumper. For supply voltages above 4 V it might by advisable to use these for lowering the power dissipation inside the transceiver, especially in case the maximum operating temperature will be used. In that case care should be taken, that the voltage at the IRED pin doesn’t drop below the minimum specified supply voltage. Note: This is an example for the 8 pin devices with 1-mm pitch. For other devices with different pitch and less pins equivalent boards are also available. Document Number: 82610 Rev. 2.0, 20-Sep-06 www.vishay.com 87 Reference Layouts and Circuit Diagrams Vishay Semiconductors In figure 3 the test board layout is shown with top and 9-pin Sub-D connector or a twisted pair cable (see bottom layer, the component placement and the dif- table 3). ferent option for external connection, either via a Table 1. Component list for testing SIR - devices at VCC = 3.3 V TFDU4300 max. distance Component TFDU4300 Low Power mode TFDU4100 Test board C8P_5102 acc. figure 2 Application acc. figure 1 C8P_5102 acc. figure 2 Application acc. figure 1 U8-P_5002 acc. figure 2 Application acc. figure 1 R1 47 : 47 : 47 : 47 : 47 : 47 : 56 : 10 : 4.7 : R2 0: 56 : R3 open open R2/R3 0: 56 : R4 0: 0: 5: C1 10 μF 10 μF 10 μF C2 470 nF 470 nF 470 nF C3 6.8 μF 6.8 μF C4 470 nF C5 - - - C6 - - - 100 nF 10 : 470 nF 100 nF 6.8 μF 4.7 μF 470 nF 100 nF - Remark: For component values in application circuits for volume production and other SIR transeivers see the relevant data sheets. Table 2. Component list for testing FIR/VFIR - devices at VCC = 3.3 V Component TFBS6614 TFDU6102 TFDU8108 Test board C8P_5102 acc. figure 2 Application acc. figure 1 C8P_5102 acc. figure 2 Application acc. figure 1 U8-P_5002 acc. figure 2 Application acc. figure 1 R1 10 : to 47 : 10 : 10 : to 47 : 10 : 4.7 : 4.7 : R2 0: 0: 0: 0: 0: 0: R3 - - - - - R2/R3 0: 0: 0: R4 0: 0: 0: C1 10 μF 10 μF 10 μF C2 470 nF 470 nF 470 nF C3 6.8 μF 6.8 μF 6.8 μF C4 470 nF 100 nF 470 nF 100 nF 220 nF 220 nF C5 C6 470 nF 470 nF 470 nF Table 3. Signal and pin assignment for test board Connector D_Sub 9 pos. male Function Cable pinning and color (when using twisted pair cables) Pin Signal Pin / Color 1 SD 9 / Blue 2 RX 7 / Green www.vishay.com 88 3 TX 5 / Yellow 4 Vlogic, SC, Mode or NC 3 / Orange 5 VCC 1 / Red 6 GND 2, 4, 6, 8, 10 / White 7 VCC (opt.) 8 VCC (opt.) 9 GND Document Number: 82610 Rev. 2.0, 20-Sep-06 Reference Layouts and Circuit Diagrams Vishay Semiconductors 19711 19708 Figure 6. Board layout BOTTOM-Side. See from Top-Side. Figure 3. Board dimensions. 19709 19712 Figure 7. Upper layer with Connector pinning. Figure 4. Component placement. 19710 19713 Figure 5. Board layout TOP-Side. Figure 8. Upper layer with cable pinning. Figure 3 to figure 8. Test board layout for 8 pin transceiver – modules with 1-mm pitch. “U8P_5002” is the internal ID number, another test board with 0.95 mm pitch is available with the ID “C8P_5102”. For 6-pin and 7-pin transceivers equivalent test boards are available on request. Document Number: 82610 Rev. 2.0, 20-Sep-06 www.vishay.com 89 Reference Layouts and Circuit Diagrams Vishay Semiconductors Remarks to the Test Board Layout and Pin - Function The circuit layouts are designed to operate with transceivers with the general Vishay pin order as SIR (9600 bit/s to 115.2 kbit/s) to VFIR(16 Mbit/s) shown in the following table. data rates. Our test boards can be used with pin #1 pin #2 pin #3 pin #4 pin #5 pin #6 pin #7 pin #8 IR Emitter Annode IR Emitter Cathode Transmitter Input Receiver Output Shutdown Analog Supply Voltage Digital Supply Voltage Ground IREDA IREDC TXD RXD SD VCC Vlogic GND IR Emitter Annode IR Emitter Cathode Transmitter Input Receiver Output Shutdown Analog Supply Voltage Mode Input Ground IREDA IREDC TXD RXD SD VCC Mode GND IR Emitter Annode IR Emitter Cathode Transmitter Input Receiver Output Serial Clock Analog Supply Voltage Mode Input Ground IREDA IREDC TXD RXD SD VCC Mode GND Function 7-pin device TFBS4650 IR Emitter Anode IR Emitter Cathode Transmitter Input Receiver Output Shutdown Analog Supply Voltage Ground Symbol IREDA IREDC TXD RXD SD VCC GND Function 7-pin device TFBS4652 IR Emitter Anode Receiver Output Transmitter Input Shutdown Digital Supply Voltage Analog Supply Voltage Ground Symbol IREDA RXD TXD SD Vlogic VCC GND Function 6-pin device as e.g. TFBS4711 TFBS6711 TFBS6712 IR Emitter Anode Transmitter Input Receiver Output Shutdown Analog Supply Voltage Ground Symbol IREDA TXD RXD SD VCC GND Function 8-pin device as e.g. TFBS6614 Symbol Function 8-pin device as e.g. TFBS6102 Symbol Function 8-pin device as e.g. TFBS8108 Symbol The recommended board layouts are Vishay references for testing the transceivers. Identical boards are used for all speeds from SIR to VFIR. The layout has an influence on the rise/fall times of the signals, especially of the optical output pulse due to the quite high drive current through the LED. The circuit is also identical for all transceivers apart from the different use of pin 5 (SD or not connected as e.g. in case of TFDU4100, which has no SD function), pin 7 (Mode, Vlogic, or NC), and the device dependent current limiting resistors R2 for controlling the current through the IR emitter. As already described, the given layout is nearly identical for all Vishay transceivers because the pin order is identical for all devices. For different lead pitch different boards are available. www.vishay.com 90 Transceiver I/Os (8-pin as example) Optical Domain, Input and Output The IrDA® physical layer standard specifies only the optical interlink, not the electrical input or output signals. The optical domain is strictly specified and tested with the IrDA-given conditions. However, the constriction to the IrDA standard limits the application of the transceivers outside the IrDA protocol. Due to the pulse duration limits of minimum and maximum optical pulse width IrDA receivers are designed to suppress low frequency and DC radiation as sunlight, incandescent or fluorescent lamps. Therefore these receivers cannot be used as DC-radiation sensors. The emitter pulse duration is limited to overcome the overload risk during start-up conditions of computers and for eye safety issues, too. Document Number: 82610 Rev. 2.0, 20-Sep-06 Reference Layouts and Circuit Diagrams Vishay Semiconductors Pin #1 - IR Emitter Anode There are in general different LED (or IRED) drive options in the different devices. Most of the new designs have a built-in current control for the LED drive current to set the intensity correctly for the application adapted to the IrDA standards (e.g. TFDU6102, TFBS6614, TFDU4300, TFBS4650). In that case the IREDA-pin is directly connected to the supply voltage. Only in special cases a series resistor is applicable: Adding an external resistor in series to the LED can have two reasons. The first is to reduce the dissipated power inside the receiver when supply voltages above 4 V are used (and specified) and the full temperature range should be covered keeping the internal current control active. The second is to reduce the internally set current e.g. for low power application or just saving power when the full range is not needed. In that case the controller function is changed just to a switch. Other transceivers are using only an internal switch. In that case the external resistor R2 from pin #1 to the power supply is responsible for the current limitation. With the internally defined current through the LED the intensity is to a great extent independent of the applied voltage while in case of using the switch the intensity is strongly voltage dependent and the resistor R2 is to be selected depending on the applied voltage. Also when the internal regulation is overruled by an external resistor this will behave like a switched but not controlled IRED. In figure 9 the typical resulting currents dependent on the applied voltages are shown when the current limitation is done by a series resistor Rs. In figure 10 the influence of the series resistance on the resulting current is shown. 400 350 IRED current (mA) 300 250 200 150 100 Rs = 3.3 Ohm 50 0 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 19714 Voltage VIRED = VCC (V) Figure 9. Resulting current depending on the operating voltage LED drive current, limiting series resistor Rs = 3.3 : Document Number: 82610 Rev. 2.0, 20-Sep-06 www.vishay.com 91 Reference Layouts and Circuit Diagrams Vishay Semiconductors 450 Resulting IRED current (mA) 400 350 300 250 200 150 100 VCC1 = VCC2 = 3.3 V 50 0 1 10 100 Series Resistor Rs (Ω) 19722 Figure 10. Resulting current depending on the series resistor for limiting the LED drive current, VCC1 = VCC2 = 3.3 V The on-resistances RDSon of the driver transistors do not vary very much. Therefore this example is quite representative for all transceiver types with built-in switches. One should keep in mind that the parameters may slightly change over the temperature range. In figure 11 and figure 12 the behavior of transmitters with built-in current control is shown. There only a little voltage dependency can be observed for the drive current and the intensity, respectively. To increase the intensity a serial LED can be used when the quite high operating voltage is available. The abs. max ratings must be taken into account. 350 100 Intensity le (mW/sr) Peak current lf (mA) 300 250 200 150 100 50 60 40 20 0 0 2 3 4 2 5 IRED Anode Voltage (V) 19723 Figure 11. TFBS4711, peak emitter current as a function of the applied voltage Pin #2 – IR Emitter Cathode In most cases the IR Emitter Cathode pin is not to be connected. The IR Emitter cathode is internally connected to the LED driver. When the IR Emitter should be driven from an additional source as a Remote Control controller (Figure 13) an n-channel FET can be added to operate the Emitter like via an “or”-gate. An additional external diode can be operated in parallel when the intensity should be improved. That is efwww.vishay.com 92 80 3 4 5 IRED Anode Voltage (V) 19725 Figure 12. TFBS4711, intensity as a function of supply voltage ficient, when the transceiver is internally operated by a switch (Figure 14). In all cases the abs. max ratings must be taken into account. Connecting this pin to a large copper PCB-area would improve the heat dissipation especially in lead frame based designs (TFDUxxxx-types). Document Number: 82610 Rev. 2.0, 20-Sep-06 Reference Layouts and Circuit Diagrams Vishay Semiconductors V cc1 R1 C1 GND IRED Anode V cc2 Vlogic Vlogic V cc C4 Ground SD SD TXD TXD RXD RXD R2 IRED Anode Vlogic V cc R1 V cc1 C1 GND C4 Ground SD SD TXD TXD RXD RXD IR Transceiver R2 Vlogic I R T ra ns c e ive r V cc2 Si1012R/X TXD_RC IRED Cathode IRED Cathode R2’ 19727 19726 Figure 13. Figure 14. Pin #3 – TXD Transmitter Input Inputs in general All inputs (as all other pins) are ESD protected. For the protection level see the data sheets or the Qualpacks for the special transceivers. Nevertheless, care should be taken that the voltage at the inputs does not exceed the specified values. Voltages above the threshold will trigger the input. This is valid also for applied RF – signals. Some EMI is just generated by too high applied RF voltages to the inputs (e.g. of more than 1.5 V with 3 V logic levels). When the transceivers are operated close to RF-antenna it should be avoided to couple RF to the input or output lines. As a counter measure terminating inputs (and also output lines) is recommended. Most devices have a built-in dynamic load circuit at the inputs (TXD, SD, Mode, SC), which keeps the input in the Low state. Changing the state will cause a current of some μA. The typical behavior and current flow is shown in figure 15. In figure 15 a simulation is shown with rising TXI input voltage over time. IVIC is the resulting input current and IDDadd is the additional operating current. Other inputs (e.g. SD) show the same behavior. V(TXI)_1:1 V 7 6 5 4 3 2 1 0 -1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0e-3 s 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0e-3 s 1.0 1.2 1.4 1.6 1.8 IVIC 1.5e-5 1.0 0.5 0.0 -0.5 -1.0 -1.5 0.0 IDDadd 4.0e-4 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 0.0 VDD = 3.0 V 0.2 0.4 0.6 0.8 19731 2.0e-3 s Figure 15. Input current characteristic Document Number: 82610 Rev. 2.0, 20-Sep-06 www.vishay.com 93 Reference Layouts and Circuit Diagrams Vishay Semiconductors To demonstrate the current vs. input voltage characteristics a triangular voltage function V(TXI) is applied to the TXD input pin. With increasing voltage the input current IVIC is increasing until the voltage crosses the switching point of the input. Above that the input load is switched off. However, there is still an additional operating current in the vicinity of the logic threshold level. That current vanishes, when the input voltage comes closer to the operating voltage (3 V in this case). Pin #3 – TXD Input Setting the transceiver input active will cause to output an electrical drive current through the LED and emitting a specified optical intensity. The pulse duration of IrDA-standard related transmission is limited to a maximum of about 20 μs2. To protect the emitter against wrong timing and also to comply with eye safety regulations the pulse duration in VISHAY emitters is limited to a value between 20 μs to 100 μs. This indicates that an NRZ-code (NRZ: no return to zero) cannot be transmitted with these devices spe- cialized for the IrDA standard. For communicating with RS232 via IrDA transceivers a code converter (ENDEC as the device TOIM4232) from NRZ to RZI (return to zero inverted) is necessary. Remote Control codes are supported. The IrDA standardized wavelength is shorter than the remote control wavelength. However, the RC receivers are able to receive IrDA signals, at least when the emitted wavelength is in the IrDA band above 870 nm as used by VISHAY. Pin #4 – RXD Receiver Output Outputs Vishay transceivers use tri-state outputs. When the device is set to the shut down mode, the output is floating with a very little load (in the order of 500 k: to 1 M:) to the digital supply voltage Vlogic, if available, or Vcc. The only device, which is using an open collector output, is TFDU4100 with an internal pull-up of 20 k: to Vcc. protected. With that feature programming errors will not kill outputs. All Vishay FIR transmitter outputs are short circuit As already noted for the TXD-input also the receive channel detects only pulses, but no DC-radiation. In general carrier based remote control signals (as RC5®, RC6® or NEC® - codes) can be received and used especially for a teach mode for learning RC codes. Pin #5 – SD Shutdown Shutdown With a few exemptions as TFDU4100 and TFDU4202 all Vishay Semiconductors IrDA-compliant transceivers feature a shutdown input. When set active the devices go into a shutdown mode with the RXD output floating with a weak pull-up. To shut down TFDU4100 and TFDU4202 see the special data sheets. FIR and VFIR devices it is recommended to reset the transceivers by setting the SD active to force the device directly into a programmed mode before starting a communication. Often the start-up conditions in circuits are not defined very well. Therefore it is advisable to force the transceiver into a desired condition than to rely on a default state. In case of programmable transceivers as the MIR, Pin #6 – VCC Analog Supply Voltage In nearly all Vishay Semiconductors transceivers the supply voltages for the LED and the transceiver can be applied separately. This has the advantage that only the transceiver with a small operating current has to be connected to the regulated power supply whereas the much higher LED drive current is supplied by the unregulated source, resulting in less cost for the Pin #7 – Mode The mode pin is used in FIR devices as e.g. TFDU6102 to change the mode from SIR to FIR statically. This pin can also be used to monitor the oper2 power supply. The supply voltage should be filtered with a low pass as shown in the circuit diagram. A combination of a Tantalum capacitor and a ceramic capacitor is recommended. Especially when EMI immunity is an issue, care should be taken for the RFquality of the ceramic capacitor. ation mode (SIR or FIR) of the device, which is set dynamically by using SD and TXD lines. If not used, leave this pin open. Maximum capacitive load: 50 pF. Note: Any IrDA receiver must be able to handle 1.6 μs input signals www.vishay.com 94 Document Number: 82610 Rev. 2.0, 20-Sep-06 Reference Layouts and Circuit Diagrams Vishay Semiconductors Pin #7 – Vlogic Digital Supply Voltage Some of the Vishay Semiconductors transceivers have the opportunity to apply an external reference for the logic input and output levels. If a Vlogic – voltage is specified, this can be either connected to Vcc or can be separately supplied by a reference voltage to adapt input thresholds and output levels to the logic levels for optimum noise suppression especially when using low I/O voltages. The input threshold is about half of the applied Vlogic and the output swing is defined by Vlogic. If not different from Vcc this pin can be directly connected to Vcc. Pin #8 – GND Ground This is the reference for all applied voltages. Especially when working with FIR and VFIR frequencies the standard rules for ground wiring in RF circuits should be observed. For testing basic parameters the described reference layout should be used. Switching times, delays, noise immunity and even sensitivity can suffer from bad grounding. Longer signal lines in particular should not be used without termination. See e.g. “The Art of Electronics” Paul Horowitz, Winfield Hill, 1989, Cambridge University Press, ISBN 0521370957. Encoder and Decoder Circuits The VISHAY transceivers are designed to operate according to the IrDA standard, this means with dedicated pulse duration for transmitter and receiver. Many controllers (PC, mobile phone and microprocessor families) support the IrDA standard. SIR with RS232 is supported by the VISHAY – ENDEC TOIM4232. For a circuit diagram see this data sheet. See also the supplier list in the application note “Sources for Accessories”. Optical Windows Optical windows should be designed not to truncate the beam shape of transceivers. On the other hand the window design also can be used to minimize interference with background light and other disturbances. For type related window design and general information regarding windows materials and suppliers see the application note “Window Size in Housings”. Supplier references are in the note “Sources for Accessories”. Document Number: 82610 Rev. 2.0, 20-Sep-06 www.vishay.com 95