SPICE Device Model SQ1431EH P-Channel 30 V (D-S

SPICE Device Model SQ1431EH
www.vishay.com
Vishay Siliconix
P-Channel 30 V (D-S) 175 °C MOSFET
DESCRIPTION
CHARACTERISTICS
The attached SPICE model describes the typical electrical
characteristics of the p-channel vertical DMOS. The
subcircuit model is extracted and optimized over the - 55 °C
to 125 °C temperature ranges under the pulsed 0 V to 10 V
gate drive. The saturated output impedance is best fit at the
gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used
to model the gate charge characteristics while avoiding
convergence difficulties of the switched Cgd model. All
model parameter values are optimized to provide a best fit
to the measured electrical data and are not intended as an
exact physical interpretation of the device.
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the - 55 °C to + 125 °C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse
Recovery Characteristics
SUBCIRCUIT MODEL SCHEMATIC
D
CGD
R1
3
M2
Gy
G
RG
Gx
+ –
ETCV
CGS
DBD
M1
S
Note
• This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer
to the appropriate datasheet of the same number for guaranteed specification limits.
S12-1633-Rev. A, 16-Jul-12
1
Document Number: 62545
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SPICE Device Model SQ1431EH
www.vishay.com
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SIMULATED MEASURED
DATA
DATA
SYMBOL
TEST CONDITIONS
Gate Threshold Voltage
VGS(th)
VDS = VGS, ID = - 250 μA
1.7
-
Drain-Source On-State Resistancea
RDS(on)
VGS = - 10 V, ID = - 2 A
0.126
0.125
VGS = - 4.5 V, ID = - 1.6 A
0.240
0.230
UNIT
Static
V

Forward Transconductancea
gfs
VDS = - 10 V, ID = - 2 A
3
3
S
Diode Forward Voltage
VSD
IS = - 1.2 A
- 0.85
- 0.85
V
167
164
42
44
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
VDS = - 25 V, VGS = 0 V, f = 1 MHz
Reverse Transfer Capacitance
Crss
29
28
Total Gate Charge
Qg
3.4
4.2
Gate-Source Charge
Qgs
0.70
0.70
Gate-Drain Charge
Qgd
1
1
VDS = - 15 V, VGS = - 10 V, ID = - 2.2 A
pF
nC
Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
S12-1633-Rev. A, 16-Jul-12
2
Document Number: 62545
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SPICE Device Model SQ1431EH
www.vishay.com
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ = 25 °C, unless otherwise noted)
1.0
8
0.8
ID - Drain Current (A)
ID - Drain Current (A)
TJ = 125 °C
VGS = 10 V, 8 V, 7 V, 6 V, 5 V
6
4
VGS = 4 V
0.6
0.4
TJ = - 55 °C
2
0.2
TJ = 25 °C
0.0
0
0
1
2
3
4
0
5
1
2
VDS - Drain-to-Source Voltage (V)
4
5
300
1.0
250
0.6
C - Capacitance (pF)
0.8
RDS(on) - On-Resistance (Ω)
3
VGS - Gate-to-Source Voltage (V)
VGS = 4.5 V
0.4
0.2
200
Ciss
150
100
Coss
50
Crss
VGS = 10 V
0
0.0
0
2
4
6
8
0
10
ID - Drain Current (A)
5
10
15
20
25
30
VDS - Drain-to-Source Voltage (V)
10
100
8
VDS = 15 V
10
IS - Source Current (A)
VGS - Gate-to-Source Voltage (V)
ID = 2.2 A
6
4
TJ = 150 °C
TJ = 25 °C
1
0.1
2
0
0.01
0
1
2
3
4
5
0
Qg - Total Gate Charge (nC)
0.3
0.6
0.9
1.2
1.5
VSD - Source-to-Drain Voltage (V)
Note
• Dots and squares represent measured data.
S12-1633-Rev. A, 16-Jul-12
3
Document Number: 62545
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Revision: 12-Mar-12
1
Document Number: 91000