GS84036CGT-250/200/166/150 128K x 36 4Mb Sync Burst SRAM TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipelined operation • Single Cycle Deselect (SCD) operation • 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipelined mode • Byte Write (BW) and/or Global Write (GW) operation • Common data inputs and data outputs • Clock control, registered, address, data, and control • Internal self-timed write cycle • Automatic power-down for portable applications • RoHS-compliant 100-lead TQFP package Functional Description Applications The GS84036CGT is a 4,718,592-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. The GS84036CGT is available in a JEDEC standard 100-lead TQFP package. 250 MHz–150 MHz 3.3 V VDD 3.3 V and 2.5 V I/O counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the BGA). Holding the FT mode pin/bump low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined mode, activating the rising-edge-triggered Data Output Register. SCD Pipelined Reads The GS84036CGT is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. Byte Write and Global Write Byte write operation is performed by using byte write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address Core and Interface Voltages The GS84036CGT operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to de-couple output noise from the internal circuit. Parameter Synopsis Pipeline 3-1-1-1 Flow Through 2-1-1-1 Rev: 1.00 9/2014 tCycle tKQ Curr tKQ tCycle Curr –250 4.0 2.5 225 5.5 5.5 180 –200 5.5 3.0 195 6.5 6.5 160 –166 6.0 3.5 185 7.0 7.0 155 –150 6.7 3.8 160 7.5 7.5 145 Unit ns ns MHz ns ns MHz 1/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology GS84036CGT-250/200/166/150 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS84036A 100-Pin TQFP Pinout (Package T) DQPC DQC DQC VDDQ DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A VSS DQC DQC DQC DQC VSS VDDQ DQC DQC FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating. Rev: 1.00 9/2014 2/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology GS84036CGT-250/200/166/150 TQFP Pin Description Symbol Type Description A 0, A 1 I Address field LSBs and Address Counter preset Inputs A I Address Inputs BA In Byte Write signal for data inputs DQA; active low BB In Byte Write signal for data inputs DQB; active low BC In Byte Write signal for data inputs DQC; active low BD In Byte Write signal for data inputs DQD; active low BW I Byte Write—Writes all enabled bytes; active low CK I Clock Input Signal; active high GW I Global Write Enable—Writes all bytes; active low E 1, E 3 I Chip Enable; active low E2 I Chip Enable; active high G I Output Enable; active low ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low DQA I/O Byte A Data Input and Output pins DQB I/O Byte B Data Input and Output pins DQ I/O Byte C Data Input and Output pins DQD I/O Byte D Data Input and Output pins DQPA I/O 9th Data I/O Pin; Byte A DQPB I/O 9th Data I/O Pin; Byte B DQPC I/O 9th Data I/O Pin; Byte C DQPD I/O 9th Data I/O Pin; Byte D ZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply NC - No Connect Rev: 1.00 9/2014 3/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology GS84036CGT-250/200/166/150 GS84036CGT Block Diagram Register A0–An D Q A0 A0 D0 A1 Q0 A1 D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q D Register GW BW BA D Q Register D 36 Q BB 36 4 Register D Q D Q D Q Register Register D Q Register BC BD Register D Q Register E1 E3 E2 D Q Register D Q FT G ZZ 1 Power Down DQxn–DQxn Control Note: Only x36 version shown for simplicity. Rev: 1.00 9/2014 4/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology GS84036CGT-250/200/166/150 Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Output Register Control FT Power Down Control ZZ State Function L Linear Burst H Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB Note: There is a pull-up device on the FT pin and a pull-down device on the ZZ pin , so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Rev: 1.00 9/2014 Note: The burst counter wraps to initial state on the 5th clock. 5/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology GS84036CGT-250/200/166/150 Byte Write Truth Table Function GW BW BA BB BC BD Notes Read H H X X X X 1 Write No Bytes H L H H H H 1 Write byte a H L L H H H 2, 3 Write byte b H L H L H H 2, 3 Write byte c H L H H L H 2, 3, 4 Write byte d H L H H H L 2, 3, 4 Write all bytes H L L L L L 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.00 9/2014 6/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology GS84036CGT-250/200/166/150 Synchronous Truth Table Operation Address Used State Diagram Key E1 E2 E3 ADSP ADSC ADV W DQ3 Deselect Cycle, Power Down None X L X H X L X X High-Z Deselect Cycle, Power Down None X L L X X L X X High-Z Deselect Cycle, Power Down None X L X H L X X X High-Z Deselect Cycle, Power Down None X L L X L X X X High-Z Deselect Cycle, Power Down None X H X X X L X X High-Z Read Cycle, Begin Burst External R L H L L X X X Q Read Cycle, Begin Burst External R L H L H L X F Q Write Cycle, Begin Burst External W L H L H L X T D Read Cycle, Continue Burst Next CR X X X H H L F Q Read Cycle, Continue Burst Next CR H X X X H L F Q Write Cycle, Continue Burst Next CW X X X H H L T D Write Cycle, Continue Burst Next CW H X X X H L T D Read Cycle, Suspend Burst Current X X X H H H F Q Read Cycle, Suspend Burst Current H X X X H H F Q Write Cycle, Suspend Burst Current X X X H H H T D Write Cycle, Suspend Burst Current H X X X H H T D Notes: 1. X = Don’t Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.00 9/2014 7/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology GS84036CGT-250/200/166/150 Simplified State Diagram X Deselect W R Simple Burst Synchronous Operation Simple Synchronous Operation W X R R First Write First Read CR CW W X CR R R X Burst Write Burst Read X CR CW CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes ADSP is tied high and ADV is tied low. Rev: 1.00 9/2014 8/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology GS84036CGT-250/200/166/150 Simplified State Diagram with G X Deselect W R W X R R First Write CR CW W CW W X First Read X CR R Burst Write R CR CW W Burst Read X CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.00 9/2014 9/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology GS84036CGT-250/200/166/150 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage in VDDQ Pins –0.5 to 4.6 V VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 ( 4.6 V max.) V VIN Voltage on Other Input Pins –0.5 to VDD +0.5 ( 4.6 V max.) V IIN Input Current on Any Pin +/–20 mA IOUT Output Current on Any I/O Pin +/–20 mA PD Package Power Dissipation 1.5 W TSTG Storage Temperature –55 to 125 o TBIAS Temperature Under Bias –55 to 125 o C C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges Parameter Symbol Min. Typ. Max. Unit 3.3 V Supply Voltage VDD 3.0 3.3 3.6 V 3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V Notes Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.00 9/2014 10/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology GS84036CGT-250/200/166/150 Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 2.0 — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.8 V 1 VDDQ3 I/O Input High Voltage VIHQ3 2.0 — VDDQ + 0.3 V 1,3 VDDQ3 I/O Input Low Voltage VILQ3 –0.3 — 0.8 V 1,3 VDDQ2 I/O Input High Voltage VIHQ2 0.6*VDD — VDDQ + 0.3 V 1,3 VDDQ2 I/O Input Low Voltage VILQ2 –0.3 — 0.3*VDD V 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Recommended Operating Temperatures Parameter Symbol Min. Typ. Max. Unit Notes Ambient Temperature (Commercial Range Versions) TA 0 25 70 C 2 Ambient Temperature (Industrial Range Versions) TA –40 25 85 C 2 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 50% tKC VDD + 2.0 V VSS 50% 50% VDD VSS – 2.0 V 50% tKC Rev: 1.00 9/2014 VIL 11/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology GS84036CGT-250/200/166/150 Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF Note: These parameters are sample tested. AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDDQ/2 Output load Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50 30pF* VDDQ/2 * Distributed Test Jig Capacitance Rev: 1.00 9/2014 12/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology GS84036CGT-250/200/166/150 DC Electrical Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA ZZ Input Current IIN1 VDD VIN VIH 0 V VIN VIH –1 uA –1 uA 1 uA 100 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V — Output High Voltage VOH3 IOH = –8 mA, VDDQ = 3.135 V 2.4 V — Output Low Voltage VOL IOL = 8 mA — 0.4 V Operating Currents -250 Test Conditions Operating Current Device Selected; All other inputs VIH or VIL Output open Standby Current ZZ VDD – 0.2 V — Deselect Current Device Deselected; All other inputs VIH or VIL — Rev: 1.00 9/2014 -150 Symbol 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C Pipeline IDD IDDQ 195 30 215 30 170 25 190 25 160 25 180 25 140 20 160 20 mA Flow Through IDD IDDQ 155 25 175 25 140 20 160 20 135 20 155 20 130 15 150 15 mA Pipeline ISB 25 45 25 45 25 45 25 45 mA Flow Through ISB 25 45 25 45 25 45 25 45 mA Pipeline IDD 65 85 65 85 65 85 60 80 mA Flow Through IDD 65 85 65 85 65 85 60 80 mA Mode (x36) -166 13/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Unit Parameter -200 © 2014, GSI Technology GS84036CGT-250/200/166/150 Pipeline Flow Through Parameter Symbol Clock Cycle Time tKC -250 -200 -166 -150 Min Max Min Max Min Max Min Max 4.0 — 5.5 — 6.0 — 6.7 — Unit AC Electrical Characteristics ns Clock to Output Valid tKQ — 2.5 — 3.0 — 3.5 — 3.8 ns Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — ns Clock to Output in Low-Z tLZ1 1.5 — 1.5 — 1.5 — 1.5 — ns Setup time tS 1.2 — 1.4 — 1.5 — 1.5 — ns Hold time tH 0.2 — 0.4 — 0.5 — 0.5 — ns Clock Cycle Time tKC 5.5 — 6.5 — 7.0 — 7.5 — ns Clock to Output Valid tKQ — 5.5 — 6.5 — 7.0 — 7.5 ns Clock to Output Invalid tKQX 2.0 — 2.0 — 2.0 — 2.0 — ns 1 2.0 — 2.0 — 2.0 — 2.0 — ns Clock to Output in Low-Z tLZ Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — ns Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — ns Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — ns Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — ns Clock to Output in High-Z tHZ 1 1.5 2.5 1.5 3.0 1.5 3.0 1.5 3.0 ns G to Output Valid tOE — 2.5 — 3.0 — 3.5 — 3.8 ns G to output in Low-Z tOLZ1 0 — 0 — 0 — 0 — ns G to output in High-Z tOHZ1 — 2.5 — 3.0 — 3.0 — 3.0 ns ZZ setup time tZZS2 5 — 5 — 5 — 5 — ns ZZ hold time tZZH2 1 — 1 — 1 — 1 — ns ZZ recovery tZZR 20 — 20 — 20 — 20 — ns Notes: 1. These parameters are sampled and are not 100% tested 2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.00 9/2014 14/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology GS84036CGT-250/200/166/150 Pipeline Mode Timing Begin Read A Cont Cont Single Read Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Single Write tKL tKH tKC Deselect Burst Read CK ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An A B C tS GW tS tH BW tH tS Ba–Bd tS Deselected with E1 tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH E3 G tS tOE DQa–DQd Rev: 1.00 9/2014 tOHZ Q(A) tKQ tH D(B) tKQX tLZ tHZ Q(C) 15/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q(C+1) Q(C+2) Q(C+3) © 2014, GSI Technology GS84036CGT-250/200/166/150 Flow Through Mode Timing Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect tKL tKH tKC CK ADSP Fixed High tS tH tS tH initiated read ADSC ADSC tS tH ADV tS tH A0–An A B C tS tH GW tS tH BW tS tH Ba–Bd tS Deselected with E1 tH E1 tS tH E2 and E3 only sampled with ADSC E2 tS tH E3 G tH tS tOE DQa–DQd Rev: 1.00 9/2014 tOHZ Q(A) D(B) tKQ tLZ tHZ tKQX Q(C) Q(C+1) Q(C+2) 16/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q(C+3) Q(C) © 2014, GSI Technology GS84036CGT-250/200/166/150 Sleep Mode Timing Diagram tKH tKC tKL CK Setup Hold ADSP ADSC tZZR tZZS tZZH ZZ Application Tips Single and Dual Cycle Deselect SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. Rev: 1.00 9/2014 17/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology GS84036CGT-250/200/166/150 Description A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 — 0.20 D Terminal Dimension 21.9 22.0 22.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch — 0.65 — L Foot Length 0.45 0.60 0.75 L1 Lead Length — 1.00 — Y Coplanarity Lead Angle e D D1 Symbol Pin 1 TQFP Package Drawing (Package GT) L c L1 Min. Nom. Max b A1 A2 0.10 Y 0 — 7 E1 E Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.00 9/2014 18/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology GS84036CGT-250/200/166/150 Ordering Information for GSI Synchronous Burst RAMs Org Part Number1 Type Package Speed2 (MHz/ns) TA3 128K x 36 GS84036AGT-250 Pipeline/Flow Through RoHS-compliant TQFP 250/6.5 C 128K x 36 GS84036AGT-200 Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 C 128K x 36 GS84036AGT-166 Pipeline/Flow Through RoHS-compliant TQFP 166/7.0 C 128K x 36 GS84036AGT-150 Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 C 128K x 36 GS84036AGT-250I Pipeline/Flow Through RoHS-compliant TQFP 250/6.5 I 128K x 36 GS84036AGT-200I Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 I 128K x 36 GS84036AGT-166I Pipeline/Flow Through RoHS-compliant TQFP 166/7.0 I 128K x 36 GS84036AGT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84036CGT-250T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. C = Commercial Temperature Range. I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. 9Mb Sync SRAM Datasheet Revision History Rev. Code: Old; New 84036CGT_r1 Rev: 1.00 9/2014 Types of Changes Page /Revisions;Reason Format or Content • Creation of datasheet 19/19 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology