64M x 9, 32M x 18 576Mb SIO Low Latency DRAM

GS4576S09/18L
144-Ball BGA
Commercial Temp
Industrial Temp
64M x 9, 32M x 18
576Mb SIO Low Latency DRAM (LLDRAM II )
533 MHz–300 MHz
2.5 V VEXT
1.8 V VDD
1.5 V or 1.8 V VDDQ
Features
Introduction
• Pin- and function-compatible with Micron RLDRAM® II
• 533 MHz DDR operation (1.067Gb/s/pin data rate)
• 38.4 Gb/s peak bandwidth (x18 at 533 MHz clock frequency)
• 32M x 18 and 64M x 9 organizations available
• 8 banks
• Reduced cycle time (15 ns at 533 MHz)
• Address Multiplexing (Nonmultiplexed address option
available)
• SRAM-type interface
• Programmable Read Latency (RL), row cycle time, and burst
sequence length
• Balanced Read and Write Latencies in order to optimize data
bus utilization
• Data mask for Write commands
• Differential input clocks (CK, CK)
• Differential input data clocks (DKx, DKx)
• On-chip DLL generates CK edge-aligned data and output
data clock signals
• Data valid signal (QVLD)
• 32 ms refresh (16K refresh for each bank; 128K refresh
command must be issued in total each 32 ms)
• 144-ball BGA package
• HSTL I/O (1.5 V or 1.8 V nominal)
• 25–60 matched impedance outputs
• 2.5 V VEXT, 1.8 V VDD, 1.5 V or 1.8 V VDDQ I/O
• On-die termination (ODT) RTT
• Commerical and Industrial Temperature
Commercial (+0° TC +95°C)
Industrial (–40° TC +95°C)
The GSI Technology 576Mb Low Latency DRAM 
(LLDRAM II) is a high speed memory device designed for
high address rate data processing typically found in networking
and telecommunications applications. The 8-bank architecture
and low tRC allows access rates formerly only found in
SRAMs.
Rev: 1.03 11/2013
The Double Data Rate (DDR) I/O interface provides high
bandwidth data transfers, clocking out two beats of data per
clock cycle at the I/O balls. Source-synchronous clocking can
be implemented on the host device with the provided freerunning data output clock.
Commands, addresses, and control signals are single data rate
signals clocked in by the True differential input clock
transition, while input data is clocked in on both crossings of
the input data clock(s).
Read and Write data transfers always in short bursts. The burst
length is programmable to 2, 4 or 8 by setting the Mode
Register.
The device is supplied with 2.5 V VEXT and 1.8 V VDD for the
core, and 1.5 V or 1.8 V for the HSTL output drivers.
Internally generated row addresses facilitate bank-scheduled
refresh.
The device is delivered in an efficent BGA 144-ball package.
1/63
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
64M x 9 Mb Ball Assignments—144-Ball BGA—Top View
1
2
3
4
A
VREF
VSS
VEXT
B
VDD
DNU3
C
VTT
D
5
6
7
8
9
10
11
12
VSS
VSS
VEXT
TMS
TCK
DNU3
VSS
VSS
Q0
D0
VDD
DNU3
DNU3
VDDQ
VDDQ
Q1
D1
VTT
A221
DNU3
DNU3
VSS
VSS
QK0
QK0
VSS
E
A21
DNU3
DNU3
VDDQ
VDDQ
Q2
D2
A20
F
A5
DNU3
DNU3
VSS
VSS
Q3
D3
QVLD
G
A8
A6
A7
VDD
VDD
A2
A1
A0
H
BA2
A9
VSS
VSS
VSS
VSS
A4
A3
J
NF2
NF2
VDD
VDD
VDD
VDD
BA0
CK
K
DK
DK
VDD
VDD
VDD
VDD
BA1
CK
L
REF
CS
VSS
VSS
VSS
VSS
A14
A13
M
WE
A16
A17
VDD
VDD
A12
A11
A10
N
A18
DNU3
DNU3
VSS
VSS
Q4
D4
A19
P
A15
DNU3
DNU3
VDDQ
VDDQ
Q5
D5
DM
R
VSS
DNU3
DNU3
VSS
VSS
Q6
D6
VSS
T
VTT
DNU3
DNU3
VDDQ
VDDQ
Q7
D7
VTT
U
VDD
DNU3
DNU3
VSS
VSS
Q8
D8
VDD
V
VREF
ZQ
VEXT
VSS
VSS
VEXT
TDO
TDI
Notes:
1. Reserved for future use. This pin may be connected to ground.
2. No function. This pin may have parasitic characteristics of a clock input signal. It may be connected to GND.
3. Do not use. This pin may have parasitic characteristics of an I/O. It may be connected to GND.
Rev: 1.03 11/2013
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© 2011, GSI Technology
GS4576S09/18L
32M x 18 Ball Assignments—144-Ball BGA—Top View
1
2
3
4
A
VREF
VSS
VEXT
B
VDD
D4
C
VTT
D
5
6
7
8
9
10
11
12
VSS
VSS
VEXT
TMS
TCK
Q4
VSS
VSS
Q0
D0
VDD
D5
Q5
VDDQ
VDDQ
Q1
D1
VTT
A221
D6
Q6
VSS
VSS
QK0
QK0
VSS
E
A212
D7
Q7
VDDQ
VDDQ
Q2
D2
A20
F
A5
D8
Q8
VSS
VSS
Q3
D3
QVLD
G
A8
A6
A7
VDD
VDD
A2
A1
A0
H
BA2
A9
VSS
VSS
VSS
VSS
A4
A3
J
NF3
NF3
VDD
VDD
VDD
VDD
BA0
CK
K
DK
DK
VDD
VDD
VDD
VDD
BA1
CK
L
REF
CS
VSS
VSS
VSS
VSS
A14
A13
M
WE
A16
A17
VDD
VDD
A12
A11
A10
N
A18
D14
Q14
VSS
VSS
Q9
D9
A19
P
A15
D15
Q15
VDDQ
VDDQ
Q10
D10
DM
R
VSS
QK1
QK1
VSS
VSS
Q11
D11
VSS
T
VTT
D16
Q16
VDDQ
VDDQ
Q12
D12
VTT
U
VDD
D17
Q17
VSS
VSS
Q13
D13
VDD
V
VREF
ZQ
VEXT
VSS
VSS
VEXT
TDO
TDI
Notes:
1. Reserved for future use. This pin may be connected to GND.
2. Reserved for future use. This pin may have parasitic characteristics of an address input signal. It may be connected to GND.
3. No function. This pin may have parasitic characteristics of a clock input signal. It may be connected to GND.
Rev: 1.03 11/2013
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Ball Descriptions
Symbol
Type
Description
A0–A21
Input
Address Inputs—A0–A21 define the row and column addresses for Read and Write Operations. During
a Mode Register Set (MRS), the address inputs define the register settings. They are sampled at the
rising edge of CK.
BA0–B2
Input
Bank Address inputs—Select to which internal bank a command is being applied.
CK, CK
Input
Input Clock—CK and CK are differential input clocks. Addresses and commands are latched on the
rising edge of CK. CK is ideally 180º out of phase with CK.
CS
Input
Chip Select—CS enables the command decoder when Low and disables it when High. When the
command decoder is disabled, new commands are ignored, but internal operations continue.
D0–D17
Input
Data Input—The D signals form the 18-bit input data bus. During Write commands, the data is sampled
at both edges of DK.
DK, DK
Input
Input Data Clock—DK and DK are the differential input data clocks. All input data is referenced to both
edges of DK. DK is ideally 180º out of phase with DK. In both the x9 and x18 devices, all Ds are
referenced to DK and DK.
DM
Input
Input Data Mask—The DM signal is the input mask signal for Write data. Input data is masked when DM
is sampled High. DM is sampled on both edges of DK. Tie signal to ground if not used.
TCK
Input
IEEE 1149.1 clock input—This ball must be tied to VSS if the JTAG function is not used.
TMS, TDI
Input
IEEE 1149.1 test inputs—These balls may be left as no connects if the JTAG function is not used.
WE, REF
Input
Command Inputs—Sampled at the positive edge of CK, WE and REF define (together with CS) the
command to be executed.
VREF
Input
Input Reference Voltage—Nominally VDDQ/2. Provides a reference voltage for the input buffers.
ZQ
I/O
External Impedance (25–60)—This signal is used to tune the device outputs to the system data bus
impedance. Q output impedance is set to 0.2 * RQ, where RQ is a resistor from this signal to ground.
Connecting ZQ to GND invokes the Minimum Impedance mode. Connecting ZQ to VDD invokes the
maximum Impedance mode. Refer to the Mode Register Definition diagrams (Mode Register Bit 8 (M8))
to activate or deactivate this function.
Q0–Q17
QKx, QKx
Rev: 1.03 11/2013
Output
Data Output—The Q signals form the 18-bit output data bus. During Read commands, the data is
referenced to both edges of QK.
Output
Output Data Clocks—QKx and QKx are opposite polarity, output data clocks. They are free running,
and during Reads, are edge-aligned with data output from the LLDRAM II. QKx is ideally 180º out of
phase with QKx. For the x18 device, QK0 and QK0 are aligned with Q0–Q8, while QK1 and QK1 are
aligned with Q9–Q17. For the x9 device, all Qs are aligned with QK0 and QK0.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Ball Descriptions (Continued)
Symbol
Type
QVLD
Output
Data Valid—The QVLD pin indicates valid output data. QVLD is edge-aligned with QKx and QKx.
TDO
Output
IEEE 1149.1 Test Output—JTAG output. This ball may be left as no connect if the JTAG function is not
used.
VDD
Supply
Power Supply—Nominally, 1.8 V. See the DC Electrical Characteristics and Operating Conditions
section for range.
VDDQ
Supply
DQ Power Supply—Nominally, 1.5 V or 1.8 V. Isolated on the device for improved noise immunity. See
the DC Electrical Characteristics and Operating Conditions section for range.
VEXT
Supply
Power Supply—Nominally, 2.5 V. See the DC Electrical Characteristics and Operating Conditions
section for range.
VSS
Supply
Ground
VTT
—
A22
—
Reserved for Future Use—This signal is not connected and may be connected to ground.
DNU
—
Do Not Use—These balls may be connected to ground.
NF
—
No Function—These balls can be connected to ground.
Rev: 1.03 11/2013
Description
Power Supply—Isolated termination supply. Nominally, VDDQ/2. See the DC Electrical Characteristics
and Operating Conditions section for range.
5/63
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Operations
Initialization
A specific power-up and initialization sequence must be observed. Other sequences may result in undefined operations or
permanent damage to the device.
Power-up:
1. Apply power (VEXT, VDD, VDDQ, VREF, VTT) . Start clock after the supply voltages are stable. Apply VDD and VEXT before or
at the same time as VDDQ1. Apply VDDQ before or at the same time as VREF and VTT. The chip starts internal initlization
only after both voltages approach their nominal levels. CK/CK must meet VID(DC) prior to being applied2. Apply only
NOP commands to start. Ensuring CK/CK meet VID(DC) while loading NOP commands guarantees that the LLDRAM II
will not receive damaging commands during initialization.
2. Idle with continuing NOP commands for 200s (MIN).
3. Issue three or more consecutive MRS commands: two or more dummies plus one valid MRS. The consecutive MRS
commands will reset internal logic of the LLDRAM II. tMRSC does not need to be met between these consecutive
commands. Address pins should be held Low during the dummy MRS commands.
4. tMRSC after the valid MRS, issues an AUTO REFRESH command to all 8 banks in any order (along with 1024 NOP
commands) prior to normal operation. As always, tRC must be met between any AUTO REFRESH and any subsequent
valid command to the same bank.
Notes:
1. It is possible to apply VDDQ before VDD. However, when doing this, the Ds, DM, Qs and all other pins with an output driver,
will go High instead of tri-stating. These pins will remain High until VDD is at the same level as VDDQ. Care should be taken to
avoid bus conflicts during this period.
2.
If VID(DC) on CK/CK can not be met prior to being applied to the LLDRAM II, placing a large external resistor from CS to VDD
is a viable option for ensuring the command bus does not receive unwanted commands during this unspecified state.
Rev: 1.03 11/2013
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Power–Up Initialization Sequence
VEXT
VDD
VDDQ
VREF
VTT
200us Min
Mode Initialization
tMRSC
Refresh
All Banks(5)
tCK
tCKH
1024 Cycles NOP Cycles Min
tCKL
CK
CK
tDK
tDKL
tDKH
DK
DK
Command
ADDR
NOP
NOP
MRS
MRS
MRS
CODE(1,2)
CODE(1,2)
CODE(2)
NOP
AREF
NOP
AC
ADDR
Bank 0
BA
AREF
Bank 7
Valid
DM
D
Notes:
1.
2.
3.
4.
5.
Recommend all address pins held Low during dummy MRS commands.
A10–A17 must be Low.
DLL must be reset if tCK or VDD are changed.
CK and CK must be separated at all times to prevent bogus commands from being issued.
The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP commands) does not matter. As is required for any operation,
tRC must be met between an AUTO REFRESH command and a subsequent VALID command to the same bank.
Rev: 1.03 11/2013
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Power–Up Initialization Flow Chart
Step
1
VDD and VEXT ramp
2
VDDQ ramp
3
Apply VREF and VTT
4
Apply stable CK/CK and DK/DK
5
Wait at least 200s
6
Issue MRS command—A10–A17 must be Low
7
Issue MRS command—A10–A17 must be Low
8
Desired load mode register with A10–A17 Low
9
Assert NOP for tMRSC
10
Issue AUTO REFRESH to bank 0
11
Issue AUTO REFRESH to bank 1
12
Issue AUTO REFRESH to bank 2
13
Issue AUTO REFRESH to bank 3
14
Issue AUTO REFRESH to bank 4
15
Issue AUTO REFRESH to bank 5
16
Issue AUTO REFRESH to bank 6
17
Issue AUTO REFRESH to bank 7
18
Wait 1024 NOP commands*
19
Valid command
Voltage rails can
be applied
simultaneously
MRS commands
must be on
consecutive
clock cycles
*Note:
The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP commands) does not matter. As is required for any
operation, tRC must be met between an AUTO REFRESH command and a subsequent VALID command to the same bank.
Rev: 1.03 11/2013
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
DLL Reset
Mode Register Bit 7 (M7) selects DLL Reset as is shown in the Mode Register Definition tables. The default setting for M7 is
Low—DLL disabled. Once M7 is set High, 1024 cycles (5s at 200 MHz) are needed before a Read command can be issued. The
delay allows the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result
in a violation of the tCKQK parameter. A reset of the DLL is necessary if tCK or VDD is changed after the DLL has been enabled.
To reset the DLL, set M7 is Low. After waiting tMRSC, an MRS command should be issued to set M7 High. 1024 clock cycles
must pass before loading the next Read command.
Driver Impedance Mapping
The LLDRAM II is equipped with programmable impedance output buffers. Setting Mode Register Bit 8 (M8) High during the
MRS command activates the output impedance control. Programmable impedance output buffers allow the user to match the driver
impedance to the PCB trace impedance. To adjust the impedance, an external resistor (RQ) is connected between the ZQ ball and
VSS. The value of the resistor must be five times the desired impedance (e.g., a 300 resistor produces an output impedance of
60). RQ values of 125–300 are supported, allowing an output impedance range of 25–60 (+/- 15 %).
The drive impedance of uncompensated output transistors can change over time due to changes in supply voltage and die
temperature. When drive impedance control is enabled in the MRS, the value of RQ is periodically sampled and needed impedance
updates are made automatically. Updates do not affect normal device operation or signal timing.
When Bit M8 is set Low during the MRS command, the output compensation circuits are still active but reference an internal
resistance reference. The internal reference is imprecise and subject to temperature and voltage variations so output buffers are set
to a nominal output impedance of 50, but are subject to a ±30 percent variance over Commercial temperature range.
Rev: 1.03 11/2013
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© 2011, GSI Technology
GS4576S09/18L
On–Die Termination (ODT)
Mode Register Bit 9 (M9) set to 1 during an MRS command enables ODT. With ODT on, the Ds, Qs, and DM are terminated to
VTT with a resistance, RTT. Command, address, QVLD, and clock signals are not terminated. The diagram below shows the
equivalent circuit of a D receiver with ODT. When a Q begins to drive after a Read command is issued, the ODT function is briefly
switched off. When a Q stops driving at the end of a data transfer, ODT is switched back on. D and DM pins are always terminated.
On–Die Termination DC Parameters
Description
Symbol
Min
Max
Units
Notes
Termination Voltage
VTT
0.95 * VREF
1.05 * VREF
V
1, 2

3
RTT
On–Die Termination
125
185
Notes:
1. All voltages referenced to VSS (GND).
2. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
3. The RTT value is measured at 95°C TC.
On–Die Termination–Equivalent Circuit
VTT
SW
RTT
Receiver
D
VREF
Rev: 1.03 11/2013
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© 2011, GSI Technology
GS4576S09/18L
Read NOP Read On-Die Termination Burst Length 2, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
RC = 4
CK
CK
CMD
RD
NOP
RD
ADDR
A
A
BA
BA0
BA2
NOP
NOP
NOP
NOP
NOP
NOP
RL = 4
QKx
QKx
QVLD
Q0a
Q
ODT
Rev: 1.03 11/2013
ODT ON
ODT OFF
Q0b
Q2a
ODT ON
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ODT OFF
Q2b
ODT ON
© 2011, GSI Technology
GS4576S09/18L
Read-Write On-Die Termination Burst Length 2, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
CK
CMD
RD
WT
ADDR
A
A
BA
BA0
BA1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WL = 5
DK
DK
DM
D1a
D
D1b
QKx
QKx
RL = 4
Q
Q0a
Q0b
QVLD
ODT
Rev: 1.03 11/2013
ODT ON
ODT OFF
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ODT ON
© 2011, GSI Technology
GS4576S09/18L
Read Burst On-die Termination Burst Length 2, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
RC = 4
CK
CK
CMD
RD
RD
RD
ADDR
A
A
A
BA
BA0
BA1
BA2
NOP
NOP
NOP
NOP
NOP
NOP
RL = 4
QKx
QKx
QVLD
Q0a
Q
ODT
Rev: 1.03 11/2013
ODT ON
Q0b
Q1a
Q1b
ODT OFF
13/63
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Q2a
Q2b
ODT ON
© 2011, GSI Technology
GS4576S09/18L
Commands
Valid control commands are listed below. Any input commands not shown are illegal or reserved. All inputs must meet specified
setup and hold times around the true crossing of CK.
Description of Commands
Command
Description
Notes
DSEL/NOP
The NOP command is used to perform a no operation to the LLDRAM II, which essentially deselects the
chip. Use the NOP command to prevent unwanted commands from being registered during idle or wait
states. Operations already in progress are not affected. Output values depend on command history.
1
MRS
The Mode Register is set via the address inputs A0–A17. See the Mode Register Definition diagrams for
further information. The MRS command can only be issued when all banks are idle and no bursts are in
progress.
—
READ
The Read command is used to initiate a burst read access to a bank. The value on the BA0–BA2 inputs
selects the bank, and the address provided on inputs A0–An selects the data location within the bank.
2
WRITE
The Write command is used to initiate a burst write access to a bank. The value on the BA0–BA2 inputs
selects the bank, and the address provided on inputs A0–An selects the data location within the bank.
Input data appearing on the Ds is written to the memory array subject to the DM input logic level
appearing coincident with the data. If the DM signal is registered Low, the corresponding data will be
written to memory. If the DM signal is registered High, the corresponding data inputs will be ignored (that
is, this part of the data word will not be written).
2
AREF
The AREF command is used during normal operation of the LLDRAM II to refresh the memory content
of a bank. The command is non-persistent, so it must be issued each time a refresh is required. The
value on the BA0–BA2 inputs selects the bank. The refresh address is generated by an internal refresh
controller, effectively making each address bit a “Don’t Care” during the AREF command.
See the Auto Refresh section for more details.
—
Notes:
1. When the chip is deselected, internal NOP commands are generated and no commands are accepted.
2. For the value of “n”, see Address Widths at Different Burst Lengths table.
Operation
Command
CS
WE
REF
A0–An
BA0–BA2
Notes
Command Table
Device Deselect/No Operation
DSEL/NOP
H
X
X
X
X
1
MRS
MRS
L
L
L
CODE
X
1, 3
Read
READ
L
H
H
A
BA
1, 2
Write
WRITE
L
L
H
A
BA
1, 2
Auto Refresh
AREF
L
H
L
X
BA
1
Notes:
1. X= Don’t Care; H = Logic High; L = Logic Low; A = Valid Address; BA = Valid Bank Address.
2. For the value of “n”, see Address Widths at Different Burst Lengths table.
3. Only A0–A17 are used for the MRS command.
Rev: 1.03 11/2013
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© 2011, GSI Technology
GS4576S09/18L
State Diagram
Initialization
Sequence
DSEL/
NOP
Write
Read
MRS
AREF
Notes:
Automatic Sequence
Command Sequence
Rev: 1.03 11/2013
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© 2011, GSI Technology
GS4576S09/18L
Mode Register Set
Mode Register Set controls the operating modes of the memory, including configuration, burst length, test mode, and I/O options.
During an MRS command, the address inputs A0–A17 are sampled and stored in the Mode Register. Except during initialization to
force internal reset, after a valid MRS command, tMRSC must be met before any command except NOP can be issued to the
LLDRAM II. All banks must be idle and no bursts may be in progress when an MRS command is loaded.
Note: Changing the burst length configuration may scramble previously written data. A burst length change must be assumed to
invalidate all stored data.
Mode Register Set
CK
CK
CS
WE
REF
CODE
A(17:0)
A(18:20)
BA(2:0)
Rev: 1.03 11/2013
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© 2011, GSI Technology
GS4576S09/18L
Mode Register Definition in Nonmultiplexed Address Mode
A17
...
A10 A9
17–10
Reserved
1
9
ODT
A8
A7
A6
8
7
6
IM
A5
5
2
DLL NA
AM
A4
4
A3
A2
A1
3
2
1
BL
0
0
Off (default)
1
On
M8
Drive Impedance
0
Internal 505 (default)
1
External (ZQ)
Address Bus
Mode Register (Mx)
Config
On Die
Termination
M9
A0
M2
M1
M0
Configuration
0
0
0
13 (default)
0
0
1
13
0
1
0
2
0
1
1
3
1
0
0
43
M7
DLL Reset
0
DLL reset4 (default)
1
0
1
5
1
DLL enabled
1
1
0
Reserved
1
1
1
Reserved
M5
Address MUX
0
Nonmulitplexed (default)
1
Multiplexed
M4
M3
Burst
Length
0
0
2 (default)
0
1
4
1
0
8
1
1
Reserved
Notes:
1. A10–A17 must be set to zero; A18–An = “Don’t Care”.
2. A6 not used in MRS.
3. BL = 8 is not available.
4. DLL RESET turns the DLL off.
5. +/–30% over rated temperature range.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Configuration Tables
The relationship between cycle time and read/write latency is selected by the user. The configuration table below lists valid
configurations available via Mode Register bits M0, M1, and M2 and the clock frequencies supported for each setting. Write
Latency is equal to the Read Latency plus one in each configuration to reduce bus conflicts.
Cycle Time and Read/Write Latency Configuration Table
Parameter
Configuration
Units
12
2
3
42, 3
5
tRC
4
6
8
3
5
tCK
tRL
4
6
8
3
5
tCK
tWL
5
7
9
4
6
tCK
Valid Frequency Range
266–175
400–175
533–175
200–175
333–175
MHz
Notes:
1. tRC < 20 ns in any configuration is only available with –18 and –24 speed grades.
2. BL= 8 is not available.
3. The minimum tRC is typically 3 cycles, except in the case of a Write followed by a Read to the same bank. In this instance the minimum
tRC is 4 cycles.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Burst Length
Read and Write data transfers occur in bursts of 2, 4, or 8 beats. Burst Length is programmed by the user via Mode Register Bit 3
(M3) and Bit 4 (M4). The Read Burst Length diagrams illustrate the different burst lengths with respect to a Read Command.
Changes in the burst length affect the width of the address bus.
Note: Changing the burst length configuration may scramble previously written data. A burst length change must be assumed to
invalidate all stored data.
Read Burst Lengths
Example BL=2
CK
CK
Command
READ
QKx
QKx
QVLD
RL = 5
Q
Q0
Q1
Example BL=4
CK1
CK1
Command1
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
QKx1
QKx1
QVLD1
RL = 5
Q1
Q0
Q1
Q2
Q3
Example BL=8
CK2
CK2
Command2
READ
NOP
NOP
NOP
NOP
NOP
QKx2
QKx2
QVLD2
RL = 5
Q2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Address Widths at Different Burst Lengths
Configuration
Burst Length
Rev: 1.03 11/2013
x9
x 18
2
A0–A21
A0–A20
4
A0–A20
A0–A19
8
A0–A19
A0–A18
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Write
Write data transfers are launched with a Write command, as shown below. A valid address must be provided during the Write
command.
During Write data transfers, each beat of incoming data is registered on crossings of DK and DK until the burst transfer is
complete. Write Latency (WL) that is always one cycle longer than the programmed Read Latency (RL), so the first valid data
registered at the first True crossing of the DK clocks WL cycles after the Write command.
Since the input and output buses are separated, any Write burst may be followed by a subsequent Read command without
encountering external data bus contention. The Write-to-Read timing diagrams illustrate the timing requirements for a Write
followed by a Read. Setup and hold times for incoming D relative to the DK edges are specified as tDS and tDH. Input data may be
masked a High on an associated DM pin. The setup and hold times for the DM signal are tDS and tDH.
Write Command
CK
CK
CS
WE
REF
ADDRESS
A
BANK ADDRESS
BA
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GS4576S09/18L
Write Burst Length 2, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
RC = 4
CK
CK
CMD
WR
WR
WR
WR
WR
WR
WR
WR
WR
ADDR
A
A
A
A
A
A
A
A
A
BA
BA0
BA1
BA2
BA3
BA0
BA4
BA5
BA6
BA7
WL = 5
DK
DK
DM
D
D0a
D0b
D1a
D1b
D2a
D2b
D3a
D3b
Write Burst Length 4, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
RC = 4
CK
CK
CMD
WR
NOP
WR
NOP
WR
NOP
WR
NOP
WR
ADDR
A
A
A
A
A
BA
BA0
BA1
BA0
BA3
BA0
WL = 5
DK
DK
DM
D
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D0a
D0b
D0c
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
D0d
D1a
D1b
D1c
D1d
© 2011, GSI Technology
GS4576S09/18L
Write-Read Burst Length 2, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
RL = 4
CK
CK
CMD
WR
RD
RD
ADDR
A
A
A
BA
BA0
BA1
BA2
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WL = 5
DK
DK
DM
D
D0a
Q
D0b
Q1a
Q1b
Q2a
Q2b
QVLD
QKx
QKx
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GS4576S09/18L
Write-Read Burst Length 4, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK
CK
CMD
WR
RD
WR
RD
ADDR
A
A
A
A
BA0
BA1
BA2
BA3
BA
NOP
NOP
NOP
NOP
NOP
NOP
WL = 5
DK
DK
DM
D0a
D
D0b
D0c
D0d
D2a
D2b
D2c
D2d
Q1a
Q1b
Q1c
Q1d
Q3a
Q3b
Q3c
RL = 4
QKx
QKx
Q
Q3d
QVLD
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Read
Read data transfers are launched with a Read command, as shown below. Read Addresses must provided with the Read command.
Each beat of a Read data transfer is edge-aligned with the QKx signals. After a programmable Read Latency, data is available at the
outputs. One half clock cycle prior to valid data on the read bus, the data valid signal (QVLD) is driven High. QVLD is also edgealigned with the QKx signals. The QK clocks are free-running.
The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the skew between QK0 and the last valid data
edge generated at the Q signals associated with QK0 (tQKQ0 is referenced to Q0–Q8). tQKQ1 is the skew between QK1 and the last
valid data edge generated at the Q signals associated with QK1 (tQKQ1 is referenced to Q9–Q17). tQKQx is derived at each QKx clock
edge and is not cumulative over time. tQKQ is defined as the skew between either QK differential pair and any output data edge.
At the end of a burst transfer, assuming no other commands have been initiated, output data (Q) will go High-Z. The QVLD signal
transitions Low on the beat of a Read burst. Note that if CK/CK violates the VID(DC) specification while a Read burst is occurring,
QVLD remains High until a dummy Read command is issued. Back-to-back Read commands are possible, producing a continuous
flow of output data.
The data valid window specification is referenced to QK transitions and is defined as: tQHP – (tQKQ [MAX] + |tQKQ [MIN]|). See the
Read Data Valid Window section for illustration.
Any Read transfer may be followed by a subsequent Write command. The Read-to-Write timing diagram illustrates the timing
requirements for a Read followed by a Write.
Read Command
CK
CK
CS
WE
REF
ADDRESS
A
BANK ADDRESS
BA
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GS4576S09/18L
Read Burst Length 2, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
RC = 4
CK
CK
CMD
RD
RD
RD
RD
RD
RD
RD
RD
RD
ADDR
A
A
A
A
A
A
A
A
A
BA
BA0
BA1
BA2
BA3
BA0
BA7
BA6
BA5
BA4
RL = 4
QKx
QKx
QVLD
Q
Q0a
Q0b
Q1a
Q1b
Q2a
Q2b
Q3a
Q3b
Q0a
Read Burst Length 4, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
RC = 4
CK
CK
CMD
RD
NOP
RD
NOP
RD
NOP
RD
NOP
RD
ADDR
A
A
A
A
A
BA
BA0
BA1
BA0
BA1
BA3
RL = 4
QKx
QKx
QVLD
Q
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Q0a
Q0b
Q0c
Q0d
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Q1a
Q1b
Q1c
Q1d
Q0a
© 2011, GSI Technology
GS4576S09/18L
Read-Write Burst Length 2, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK
CK
CMD
WR
RD
RD
ADDR
A
A
A
BA
BA0
BA1
BA2
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WL = 5
DK
DK
DM
D
D0a
D0b
RL = 4
QKx
QKx
Q
Q1a
Q1b
Q2a
Q2b
QVLD
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GS4576S09/18L
Read-Write Burst Length 4, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
CK
CK
CMD
RD
WR
RD
ADDR
A
A
A
BA
BA0
BA1
BA2
NOP
NOP
NOP
NOP
NOP
WL = 5
DK
DK
DM
D
D1a
D1b
D1c
D1d
RL = 4
QKx
QKx
Q
Q0a
Q0b
Q0c
Q0d
Q2a
Q2b
Q2c
QVLD
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Auto Refresh
The Auto Refresh (AREF) command launches a REFRESH cycle on one row in the bank addressed. Refresh row addresses are
generated by an internal refresh counter, so address inputs are Don’t Care, but a bank addresses (BA 2:0) must be provided during
the AREF command. A refresh may be contining in one bank while other commands, including other AREF commands, are
launched in other banks. The delay between the AREF command and a READ, WRITE or AREF command to the same bank must
be at least tRC.
The entire memory must be refreshed every 32 ms (tREF). This means that this 576Mb device requires 128K refresh cycles at an
average periodic interval of 0.24s MAX (actual periodic refresh interval is 32 ms/16K rows/8 = 0.244s). To improve efficiency,
eight AREF commands (one for each bank) can be launched at periodic intervals of 1.95s (32 ms/16K rows = 1.95s). The Auto
Refresh Cycle diagram illustrates an example of a refresh sequence.
Auto Refresh (AREF) Command
CK
CK
CS
WE
REF
ADDRESS
BA
BANK ADDRESS
Auto Refresh Cycle
CK
CK
CMD
AREF
AREF
Bank
BA0
BA3
Rev: 1.03 11/2013
NOP
AREF
BA4
28/63
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Address Multiplexing
LLDRAM II defaults to “broadside” addressing at power up, meaning, it registers all address inputs on a single clock transition.
However, for most configurations of the device, considerable efficiency can be gained by operating in Address Multiplexed mode,
cutting the address pin count on the host device in half. In Multiplexed Address mode, the address is loaded in two consecutive
clock transitions. Broadside Addressing only improves Continuous Burst mode data transfer efficiency of Burst Length 2 (BL = 2)
configuration.
In Address Multiplex mode, bank addresses are loaded on the same clock transition as Command and the first half of the address,
Ax. The 576Mb Address Mapping in Multiplexed Address Mode table and Cycle Time and Read/Write Latency Configuration in
Mulitplexed Mode table show the addresses needed for both the first and second clock transitions (Ax and Ay, respectively). The
AREF command does not require an address on the second clock transition, as only the Bank Address are loaded for refresh
commands. Therefore, AREF commands may be issued on consecutive clocks, even when in Address Multiplex mode.
Setting Mode Register Bit 5 (M5) to 1 in the Mode Register activates the Multiplexed Address mode. Once this bit is set
subsequent MRS, READ, and WRITE operate as described in the Multiplexed Address Mode diagram.
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GS4576S09/18L
Power-Up Multiplexed Address Mode
VEXT
VDD
VDDQ
VREF
VTT
200us Min
tMRSC
tMRSC
tCK
Refresh 1024 NOP cycles Min
All Banks(9)
tCKL
tCKH
CK
CK
tDK
tDKH
tDKL
DK
DK
Command
ADDR
NOP
NOP
MRS
MRS
CODE(1,2)
CODE(1,2)
MRS
CODE(2,3)
MRS
Ax(2,4)
NOP
RF0
RF7
NOP
AC
Valid(5)
Ay(2)
Bank 0
Bank
Rev: 1.03 11/2013
NOP
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Bank 7
Valid(5)
© 2011, GSI Technology
GS4576S09/18L
MRS Command In Multiplexed Mode
The Mode Register Set command stores the data for controlling the RAM into the Mode Register. The register allows the user to
modify Read and Write pipeline length, burst length, test mode, and I/O options. The Multiplexed MRS command requires two
cycles to complete The Ax address is sampled on the true crossing of clock with the MRS Command. The Ay address and a
required NOP command are captured on the next next crossing of clock. After issuing a valid MRS command, tMRSC must be met
before any READ, WRITE, MRS, or AREF command can be issued to the LLDRAM II. This statement does not apply to the
consecutive MRS commands needed for internal logic reset during the initialization routine. The MRS command can only be
issued when all banks are idle and no bursts are in progress.
Note: The data written by the prior burst length is not guaranteed to be accurate when the burst length of the device is changed.
MRS Command in Multiplexed Mode
MRS
CK
CK
CS
WE
REF
A(9:0)
Ax
Ay
A(18:10)
BA(2:0)
Notes:
1. Recommended that all address pins held Low during dummy MRS commands.
2. A10–A18 must be Low.
3. Set address A5 High. This enbles the part to enter Multiplexed Address mode when in Non-Multiplexed mode operation. Multiplexed
Address mode can also be entered at some later time by issuing an MRS command with A5 High. Once address Bit A5 is set High, tMRSC
must be satisfied before the two-cycle multiplexed mode MRS command is issued.
4. Address A5 must be set High. This and the following step set the desired mode register once the LLDRAM II is in Multiplexed Address
mode.
5. Any command or address.
6. The above sequence must be followed in order to power up the LLDRAM II in the Multiplexed Address mode.
7. DLL must be reset if tCK or VDD are changed.
8. CK and CK must separated at all times to prevent bogus commands from being issued.
9. The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP commands) does not matter. As is required for any
operation, tRC must be met between an AUTO REFRESH command and a subsequent VALID command to the same bank.
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GS4576S09/18L
Mode Register Definition in Multiplexed Address Mode
Ax
Ay
18–10
Reserved
M9
A9
A18...A10
A18...A10
1
9
ODT
Off (default)
1
On
Drive Impedance
0
Internal 503 (default)
1
External (ZQ)
A9
8
IM
7
A8
6
A5
5
5
DLL NA
AM
A4
A3
4
3
A4
2
BL
A0
A3
1
0
Mode Register (Mx)
Config
On Die
Termination
0
M8
A8
M2
M1
M0
Configuration
0
0
0
12 (default)
0
0
1
12
0
1
0
2
0
1
1
3
1
0
0
42
M7
DLL Reset
0
DLL reset4 (default)
1
0
1
5
1
DLL enabled
1
1
0
Reserved
1
1
1
Reserved
M5
Address MUX
0
Nonmulitplexed (default)
1
Multiplexed
M4
M3
Burst
Length
0
0
2 (default)
0
1
4
1
0
8
1
1
Reserved
Notes:
1. A10–A18 must be set to zero.
2. BL = 8 is not available.
3. +/–30% over rated temperature range.
4. DLL RESET turns the DLL off.
5. Ay8 not used in MRS.
6. BA0–BA2 are “Don’t Care”.
7. Addresses A0, A3, A4, A5, A8, and A9 must be set as shown in order to activate the Mode Register in the Multiplexed Address mode.
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GS4576S09/18L
576Mb Address Mapping in Multiplexed Address Mode
Burst
Length
Data Width
Ball
2
x18
4
8
2
x9
4
8
Address
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
A20
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
A20
A1
A2
A21
A6
A7
A19
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
A20
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
Notes:
X= Don’t Care.
Configuration in Mulitplexed Mode
In Multiplexed Address mode, the Read and Write latencies are increased by one clock cycle. However, the LLDRAM II cycle
time remains the same as when in Nonmultiplexed Address mode.
Cycle Time and Read/Write Latency Configuration in Mulitplexed Mode
Parameter
Configuration
Units
12
2
3
42, 3
5
tRC
4
6
8
3
5
tCK
tRL
5
7
9
4
6
tCK
tWL
6
8
10
5
7
tCK
Valid Frequency Range
266–175
400–175
533–175
200–175
333–175
MHz
Notes:
1. tRC < 20 ns in any configuration is only available with –24 and –18 speed grades.
2. BL = 8 is not available.
3. The minimum tRC is typically 3 cycles, except in the case of a Write followed by a Read to the same bank. In this instance the minimum tRC
is 4 cycles.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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GS4576S09/18L
Write Command in Multiplexed Mode
Address Multiplexed Write data transfers are launched with a Write command, as shown below. A valid address must be provided
during the Write command. The Ax address must be loaded on the same true clock crossing used to load the Write command and
the Bank address. The Ay address and a NOP command must be provided at the next clock crossing.
During Write data transfers, each beat of incoming data is registered on crossings of DK and DK until the burst transfer is
complete. Write Latency (WL) is always one cycle longer than the programmed Read Latency (RL).
A Write burst may be followed by a Read command (assuming tRC is met). The Write-to-Read timing diagrams illustrate the
timing requirements for a Write followed by a Read. Setup and hold times for incoming D relative to the DK edges are specified as
tDS and tDH. Input data may be masked high on an associated DM pin. The setup and hold times for the DM signal are tDS and
tDH.
Write Command in Multiplexed Mode
WRITE
CK
CK
CS
WE
REF
ADDRESS
Ax
BANK ADDRESS
BA
Ay
Write Burst Length 4, Configuration 1 in Multiplexed Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
RC = 4
CK
CK
CMD
WR
NOP
WR
NOP
WR
NOP
WR
NOP
WR
ADDR
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
BA
BA0
BA1
BA0
BA3
BA0
WL = 6
DK
DK
DM
D
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D0a
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
D0b
D0c
D0d
D1a
D1b
© 2011, GSI Technology
GS4576S09/18L
Read Command in Multiplexed Mode
Address Multiplexed Read data transfers are launched with a Read command, as shown below. A valid address must be provided
during the READ command. The Ax address must be loaded on the same True clock crossing used to load the READ command
and the Bank address. The Ay address and a NOP command must be provided at the next clock crossing.
Each beat of a Read data transfer is edge-aligned with the QKx signals. After a programmable Read Latency, data is available at
the outputs. One half clock cycle prior to valid data on the read bus, the data valid signal (QVLD) is driven High. QVLD is also
edge-aligned with the QKx signals. The QK clocks are free-running.
The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the skew between QK0 and the last valid
data edge generated at the Q signals associated with QK0 (tQKQ0 is referenced to Q0–Q8). tQKQ1 is the skew between QK1 and
the last valid data edge generated at the Q signals associated with QK1 (tQKQ1 is referenced to Q9–Q17). tQKQx is derived at
each QKx clock edge and is not cumulative over time. tQKQ is defined as the skew between either QK differential pair and any
output data edge.
At the end of a burst transfer, assuming no other commands have been initiated, output data (Q) will go High–Z. The QVLD signal
transitions Low on the beat of a Read burst. Note that if CK/CK violates the VID(DC) specification while a Read burst is occurring,
QVLD remains High until a dummy Read command is issued. Back-to-back Read commands are possible, producing a continuous
flow of output data.
The data valid window specification is referenced to QK transitions and is defined as: tQHP – (tQKQ [MAX] + |tQKQ [MIN]|). See
the Read Data Valid Window section.
Any Read transfer may be followed by a subsequent Write command. The Read-to-Write timing diagram illustrates the timing
requirements for a Read followed by a Write.
Read Command in Mulitplexed Mode
READ
CK
CK
CS
WE
REF
Rev: 1.03 11/2013
ADDRESS
Ax
BANK ADDRESS
BA
Ay
35/63
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Read Burst Length 4, Configuration 1 in Multiplexed Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
CK
CMD
RD
NOP
RD
NOP
RD
NOP
RD
NOP
RD
ADDR
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
BA
BA0
QKx
BA1
BA2
BA0
BA1
RL = 5
QKx
Q
Q0a
Q0b
Q0c
Q0d
Q1a
Q1b
Q1c
QVLD
Rev: 1.03 11/2013
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Refresh Commands in Multiplexed Address Mode
The AREF command launches a REFRESH cycle on one row in the bank addressed. Refresh row addresses are generated by an
internal refresh counter. so address inputs are Don’t Care, but Bank addresses (BA 2:0) must be provided during the AREF
command. A refresh may be continuing in one bank while other commands, including other AREF commands, are launched in
other banks. The delay between the AREF command and a READ, WRITE or AREF command to the same bank must be at least
tRC.
The entire memory must be refreshed every 32 ms (tREF). This means that this 576Mb device requires 128K refresh cycles at an
average periodic interval of 0.24s MAX (actual periodic refresh interval is 32 ms/16K rows/8 = 0.244s). To improve efficiency,
eight AREF commands (one for each bank) can be launched at periodic intervals of 1.95s (32 ms/16K rows = 1.95s). The Auto
Refresh Cycle diagram illustrates an example of a refresh sequence.
Unlike READ and WRITE commands in Address Multiplex mode, all the information needed to execute an AREF command (the
AREF command and the Band Address (BA 2:0)) is loaded in a single clock crossing, another AREF command (to a different
bank) may be loaded on the next clock crossing.
Consecutive Refresh Operations with Multiplexed Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
AREF
AREF
AREF
AREF
AREF
AREF
AREF
AREF
T10
T11
CK
CK
CMD
AC1
NOP
ADDR
Ax
Ay
BA
BAn
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
AC1
NOP
Ax
Ay
BAn
Notes:
1.
2.
Any command.
Bank n is chosen so that tRC is met.
Rev: 1.03 11/2013
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Absolute Maximum Ratings
Absolute Maximum Voltage
(All voltages reference to VSS)
Parameter
Min
Max
Unit
I/O Voltage
–0.3
VDDQ + 0.3
V
Voltage on VEXT supply
–0.3
+2.8
V
Voltage on VDD supply relative to VSS
–0.3
+2.1
V
Voltage on VDDQ supply relative to VSS
–0.3
+2.1
V
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Absolute Maximum Temperature
Parameter
Temperature
Range
Symbol
Min.
Max.
Unit
Notes
Storage Temperature
—
TSTG
–55
+150
C°
1
—
+110
C°
2
—
+110
C°
2
Reliability junction temperature
Commercial
Industrial
TJ
Notes:
1. Max storage case temperature; TSTG is measured in the center of the package.
2. Temperatures greater than 110 C° may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at or above this is not implied. Exposure to the absolute maximum ratings condtions for extended periods may affect reliability of
the part.
Rev: 1.03 11/2013
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Recommended Operating Temperature and Thermal Impedance
Like any other semiconcuctor device, the LLDRAM II must be operated within the temperature specifications shown in the
Temperature Limits table for the device to meet datasheet specifications. The thermal impedance characteristics of the device are
are listed below. In applications where the ambient temperature or PCB temperature are too high, use of forced air and/or heat
sinks may be required in order to satisfy the case temperature specifications.
Temperature Limits
Temperature
Range
Parameter
Symbol
Commercial
Operating junction temperature
Industrial
Commercial
Operating case temperature
Industrial
TJ
TC
Min.
Max.
Unit
Notes
0
+100
C°
1
–40
+100
C°
1
0
+95
C°
2, 3
–40
+95
C°
2, 3, 4
Notes:
1. Junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow.
2. Maximum operating case temperature, TC, is measured in the center of the package.
3. Device functionality is not guaranteed if the device exceeds maximum TC during operation.
4. Junction and case temperature specifications must be satisfied.
Thermal Impedance
Package
Test PCB
Substrate
JA (C°/W)
Airflow = 0 m/s
 JA (C°/W)
Airflow = 1 m/s
 JA (C°/W)
Airflow = 2 m/s
JB (C°/W)
 JC (C°/W)
BGA
2-layer
TBD
TBD
TBD
TBD
TBD
4-layer
22.4
19.0
16.2
5.3
1.7
Notes:
1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. The minimal metalization of a 2-layer
board tends to minimize the utility of the junction-to-board heat path. The 4-layer test fixture PCB is intended to highlight the effect of
connection to power planes typically found in the PCBs used in most applications. Be advised that a good thermal path to the PCB can
result in cooling or heating of the RAM depending on PCB temperature.
Rev: 1.03 11/2013
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Recommended DC Operating Conditions and Electrical Characteristics
Description
Conditions
Symbol
Min.
Max.
Unit
Notes
Supply Voltage
—
VEXT
2.38
2.63
V
—
Supply Voltage
—
VDD
1.7
1.9
V
2
Isolated Output Buffer Supply
—
VDDQ
1.4
VDD
V
2, 3
Reference Voltage
—
VREF
0.49 * VDDQ
0.51 * VDDQ
V
4, 5, 6
Termination Voltage
—
VTT
0.95 * VREF
1.05 * VREF
V
7, 8
Input High (logic 1) voltage
—
VIH(DC)
VREF + 0.1
VDDQ + 0.3
V
2
Input Low (logic 0) voltage
—
VIL(DC)
VSS – 0.3
VREF – 0.1
V
2
Ouput High Current
VOUT = VDDQ/2
IOH
(VDDQ/2)/(1.15 * RQ/5)
(VDDQ/2)/(0.85 * RQ/5)
A
9, 10, 11
Ouput Low Current
VOUT = VDDQ/2
IOL
(VDDQ/2)/(1.15 * RQ/5)
(VDDQ/2)/(0.85 * RQ/5)
A
9, 10, 11
Clock Input Leakage Current
0 V  VIN VDD
ILC
–5
5
A
—
Input Leakage Current
0 V  VIN VDD
ILI
–5
5
A
—
Output Leakage Current
0 V  VIN VDDQ
ILO
–5
5
A
—
Reference Voltage Current
—
IREF
–5
5
A
—
Notes:
1. All voltages referenced to VSS (GND). This note applies to the entire table.
2. Overshoot VIH(AC)  VDD+ 0.7 V for t  tCK/2. Undershoot: VIL(AC)  –0.5 V for t  tCK/2. During normal operation VDDQ must not exceed
VDD. Control input signals may not have pulse widthts less than tCK/2 or operate at frequencies exceeding tCK (MAX).
3. VDDQ can be set to a nominal 1.5 V ± 0.1 V or 1.8 V ± 0.1 V supply.
4. Typically the value of VREF is expected to be 0.5 * VDDQ of the transmitting device. VREF is expected to track variations in VDDQ.
5. Peak-to-Peak AC noise on VREF must not exceed ±2% of VREF(DC).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise 
(non-common mode) on VREF may not exceed ±2% of the DC value. Thus, from VDDQ/2, VREF is allowed ±2% VDDQ/2 for DC error and an
addtional ±2% VDDQ/2 for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor.
7. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
8. On-die termination may be selected using Mode Register Bit 9 (M9). A resistance RTT from each data input signal to the nearest VTT can be
enabled. RTT = 125–185at 95° C TC.
9. IOH and IOL are defined as absolute values and are measured at VDDQ/2. IOH flows from the device, IOL flows into the device.
10. If Mode Register Bit 8 (M8) is 0, use RQ = 250in the equation in lieu of presence of an external impedance matched resistor.
11. For VOL and VOH, refer to the LLDRAM II IBIS models.
Rev: 1.03 11/2013
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
DC Differential Input Clock Logic Levels
Parameter
Symbol
Min.
Max.
Unit
Notes
Clock input voltage level: CK and CK
VIN(DC)
–0.3
VDDQ + 0.3
V
1–4
Clock input differential voltage: CK and CK
VID(DC)
0.2
VDDQ + 0.6
V
1–5
Notes:
1. DKx and DKx have the same requirements as CK and CK.
2. All voltages referenced to VSS (GND).
3. The CK and CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross. The input reference level for
signals other than CK/CK is VREF.
4. The CK and CK input slew rate must be  2 V/ns ( 4 V/ns if measured differentially).
5. VID is the magnitude of the difference between the input level on CK and the input level on CK.
Recommended AC Operating Conditions and Electrical Characteristics
Input AC Logic Levels
Parameter
Symbol
Min.
Max.
Unit
Notes
Input High (logic 1) Voltage
VIH
VREF + 0.2
—
V
1, 2, 3
Input Low (logic 0) Voltage
VIL
—
VREF – 0.2
V
1, 2, 3
Notes:
1. All voltages referenced to VSS (GND).
2. The AC and the DC input level specifications are defined in the HSTL standard (that is, the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above (see drawing below) the DC
input Low (High) level).
3. The minimum slew rate for the input signals used to test the device is 2 V/ns in the range between VIL(AC) and VIH(AC).
Nominal tAS/ tCS/ tDS and tAH/ tCH/ tDH Slew Rate
VDDQ
VIH(AC)MIN
VSWING(AC) (MIN)
VIH(DC)MIN
VREF
VIL(DC)MAX
VIL(AC)MAX
VSS
Rev: 1.03 11/2013
41/63
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
AC Differential Input Clock Levels
Parameter
Symbol
Min.
Max.
Unit
Notes
Clock input differential voltage: CK and CK
VID(AC)
0.4
VDDQ + 0.6
V
1–5
Clock input crossing point voltage: CK and CK
VIX(AC)
VDDQ/2 – 0.15
VDDQ/2 + 0.15
V
1–4, 6
Notes:
1. DKx and DKx have the same requirements as CK and CK.
2. All voltages referenced to VSS (GND).
3. The CK and CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross. The input reference level for
signals other than CK/CK is VREF.
4. The CK and CK input slew rate must be  2 V/ns ( 4 V/ns if measured differentially).
5. VID is the magnitude of the difference between the input level on CK and the input level on CK.
6. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same.
Differential Clock Input Requirements
VIN(DC) MAX
Maximum Clock Level
CK
VIX(AC)MAX
VDDQ/2 + 0.15
VDDQ/2
1
VDDQ/2 – 0.15
VID(DC)2
VID(AC)3
VIX(AC)MIN
CK
VIN(DC) MIN
Minimum Clock Level
Notes:
1. CK and CK must cross within this region.
2. CK and CK must meet at least VID(DC)MIN when static and centered around VDDQ/2.
3. Minimum peak-to-peak swing.
4. It is a violation to tristate CK and CK after the part is initialized.
Rev: 1.03 11/2013
42/63
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Input Slew Rate Derating
The Address and Command Setup and Hold Derating Values shown in the following table should be added to the default tAS/tCS/
tDS and tAH/tCH/tDH specifications when the slew rate of any of these input signals is less than the 2 V/ns.
To determine the setup and hold time needed for a given slew rate, add the tAS/tCS default specification to the “tAS/tCS VREF to
CK/CK Crossing” and the tAH/tCH default specification to the "tAH/tCH CK/CK Crossing to VREF" derated values in the Address
and Command Setup and Hold Derating Values table. The derated data setup and hold values can be determined the same way
using the “tDS VREF to CK/CK Crossing” and “tDH to CK/CK Crossing to VREF” values in the Data Setup and Hold Derating
Values table. The derating values apply to all speed grades.
The setup times in the table relate to a rising signal. The time from the rising signal crossing VIH(AC)MIN to the CK/CK cross point
is static and must be maintained across all slew rates. The derated setup timing describes the point at which the rising signal crosses
VREF(DC) to the CK/CK cross point. This derated value is calculated by determining the time needed to maintain the given slew
rate and the delta between VIH(AC)MIN and the CK/CK cross point. All these same values are also valid for falling signals (with
respect to VIL(AC)MAX and the CK/ CK cross point).
The hold times in the table relate to falling signals. The time from the CK/CK cross point to when the signal crosses VIH(DC) MIN is
static and must be maintained across all slew rates. The derated hold timing describes the delta between the CK/CK cross point to
when the falling signal crosses VREF(DC). This derated value is calculated by determining the time needed to maintain the given
slew rate and the delta between the CK/CK cross point and VIH(DC). The hold values are also valid for rising signals (with respect
to VIL(DC)MAX and the CK and CK cross point).
Note: The above descriptions also pertain to data setup and hold derating when CK/CK are replaced with DK/DK.
Rev: 1.03 11/2013
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Command/Address
Slew Rate (V/ns)
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
Rev: 1.03 11/2013
tAH/tCH
CK/CK crossing to
VIH(DC)MIN
Units
Address and Command Setup and Hold Derating Values
0
5
11
18
25
33
43
54
67
82
100
CK/CK Differential Slew Rate: 2.0 V/ns
–100
0
–100
3
–100
6
–100
9
–100
13
–100
17
–100
22
–100
27
–100
34
–100
41
–100
50
–50
–50
–50
–50
–50
–50
–50
–50
–50
–50
–50
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
30
35
41
48
55
63
73
84
97
112
130
CK/CK Differential Slew Rate: 1.5 V/ns
–70
30
–70
33
–70
36
–70
39
–70
43
–70
47
–70
52
–70
57
–70
64
–70
71
–70
80
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
60
65
71
78
85
93
103
114
127
142
160
CK/CK Differential Slew Rate: 1.0 V/ns
–40
60
–40
63
–40
66
–40
69
–40
73
–40
77
–40
82
–40
87
–40
94
–40
101
–40
110
10
10
10
10
10
10
10
10
10
10
10
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tAS/tCS VREF to
CK/CK crossing
tAS/tCS VIH(AC)MIN
CK/CK crossing
tAH/tCH
CK/CK crossing to VREF
44/63
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
tDS
CK/CK crossing to
VIH(DC)MIN
Units
Data Setup and Hold Derating Values
DK/DK Differential Slew Rate: 2.0 V/ns
–100
0
–100
3
–100
6
–100
9
–100
13
–100
17
–100
22
–100
27
–100
34
–100
41
–100
50
–50
–50
–50
–50
–50
–50
–50
–50
–50
–50
–50
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
30
35
41
48
55
63
73
84
97
112
130
DK/DK Differential Slew Rate: 1.5 V/ns
–70
30
–70
33
–70
36
–70
39
–70
43
–70
47
–70
52
–70
57
–70
64
–70
71
–70
80
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
60
65
71
78
85
93
103
114
127
142
160
DK/DK Differential Slew Rate: 1.0 V/ns
–40
60
–40
63
–40
66
–40
69
–40
73
–40
77
–40
82
–40
87
–40
94
–40
101
–40
110
10
10
10
10
10
10
10
10
10
10
10
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Data Slew Rate (V/ns)
tDS VREF to CK/CK
crossing
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0
5
11
18
25
33
43
54
67
82
100
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
Rev: 1.03 11/2013
tDS VIH(AC)MIN CK/CK
crossing
tDS
CK/CK crossing to VREF
45/63
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Capacitance
Description
Symbol
Address/control input capacitance
CI
Input/Output capacitance
(D, Q, DM, and QK, QK)
CO
Clock capacitance (CK/CK and DK/DK)
CCK
JTAG pins
CJTAG
Conditions
TA = 25° C; f = 100 MHz
VDD = VDDQ = 1.8 V
Min.
Max.
Unit
1.0
2.0
pF
3.0
4.5
pF
1.5
2.5
pF
1.5
4.5
pF
Notes:
1. Capacitance is not tested on the ZQ pin.
2. JTAG Pins are tested at 50 MHz.
Description
Condition
Symbol
-18
-24
-25
-33
Standby Current
tCK = idle, All banks idle; No inputs
toggling.
ISB1 (VDD) x9/x18
TBD
TBD
TBD
TBD
ISB1 (VEXT)
TBD
TBD
TBD
TBD
Active Standby Current
CS = 1, No commands; Bank address
incremented and half address/data change
once every four clock cycles.
ISB2 (VDD) x9/x18
TBD
TBD
TBD
TBD
ISB2 (VEXT)
TBD
TBD
TBD
TBD
IDD1 (VDD) x9/x18
TBD
TBD
TBD
TBD
Operational Current
BL = 2, Sequential bank access; Bank
transitions once every tRC; Half address
transitions once every tRC; Read followed
by Write sequence; Continuous data during
Write Commands.
IDD1 (VEXT)
TBD
TBD
TBD
TBD
IDD2 (VDD) x9/x18
TBD
TBD
TBD
TBD
Operational Current
BL = 4, Sequential bank access; Bank
transitions once every tRC; Half address
transitions once every tRC; Read followed
by Write sequence; Continuous data during
Write Commands.
IDD2 (VEXT)
TBD
TBD
TBD
TBD
IDD3 (VDD) x9/x18
TBD
TBD
TBD
TBD
Operational Current
BL = 8, Sequential bank access; Bank
transitions once every tRC; Half address
transitions once every tRC. Read followed
by Write sequence; Continuous data during
Write Commands.
IDD3 (VEXT)
TBD
TBD
TBD
TBD
Burst Refresh Current
Eight bank cyclic refresh; Continuous
address/data; Command bus remains in
refresh for all eight banks.
IREF1 (VDD) x9/x18
TBD
TBD
TBD
TBD
IREF1 (VEXT)
TBD
TBD
TBD
TBD
Distributed Refresh Current
Single bank refresh; Sequential bank
access; Half address transitions once every
tRC; Continuous data.
IREF2 (VDD)x9/x18
TBD
TBD
TBD
TBD
IREF2 (VEXT)
TBD
TBD
TBD
TBD
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Units
IDD Operating Conditions
mA
mA
mA
mA
mA
mA
mA
© 2011, GSI Technology
GS4576S09/18L
Description
Condition
Symbol
-18
-24
-25
-33
Operating Burst Write Current
Example
BL= 2; Cyclic bank access; Half of address
bits change every clock cycle; Continuous
data; Measurement is taken during
continuous Write.
IDD2W (VDD) x9/x18
TBD
TBD
TBD
TBD
IDD2W (VEXT)
TBD
TBD
TBD
TBD
Operating Burst Write Current
Example
BL= 4; Cyclic bank access; Half of address
bits change every two clock cycles;
Continuous data; Measurement is taken
during continuous Write.
IDD4W (VDD )x9/x18
TBD
TBD
TBD
TBD
IDD4W (VEXT)
TBD
TBD
TBD
TBD
Operating Burst Write Current
Example
BL= 8; Cyclic bank access; Half of address
bits change every four clock cycles;
Continuous data; Measurement is taken
during continuous Write.
IDD8W (VDD) x9/x18
TBD
TBD
TBD
TBD
IDD8W (VEXT)
TBD
TBD
TBD
TBD
Operating Burst Read
Current Example
BL= 2; Cyclic bank access; Half of address
bits change every clock cycle; Continuous
data; Measurement is taken during
continuous Read.
IDD2R (VDD)x9/x18
TBD
TBD
TBD
TBD
IDD2R (VEXT)
TBD
TBD
TBD
TBD
Operating Burst Read
Current Example
BL= 4; Cyclic bank access; Half of address
bits change every two clock cycles;
Continuous data; Measurement is taken
during continuous Read.
IDD4R (VDD) x9/x18
TBD
TBD
TBD
TBD
IDD4R (VEXT)
TBD
TBD
TBD
TBD
Operating Burst Read
Current Example
BL= 8; Cyclic bank access; Half of address
bits change every four clock cycles;
Continuous data; Measurement is taken
during continuous Read.
IDD8R (VDD) x9/x18
TBD
TBD
TBD
TBD
IDD8R (VEXT)
TBD
TBD
TBD
TBD
Units
IDD Operating Conditions (Continued)
mA
mA
mA
mA
mA
mA
Notes:
1. IDD specifications are tested after the device is properly initialized and is operating at worst-case rated temperature and voltage specifications.
2.
3.
4.
5.
6.
Definitions of IDD Conditions:
3a. Low is defined as VIN  VIL(AC) MAX.
3b. High is defined as VIN  VIH(AC) MIN.
3c. Stable is defined as inputs remaining at a High or Low level.
3d. Floating is defined as inputs at VREF = VDDQ/2.
3e. Continuous data is defined as half the D or Q signals changng between High and Low every half clock cycle (twice per clock).
3f. Continuous address is defined as half the address signals changing between High and Low every clock cycles (once per clock).
3g. Sequential bank access is defined as the bank address incrementing by one every tRC.
3h. Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL = 2 this is every clock, for BL = 4 this
is every other clock, and for BL = 8 this is every fourth clock.
CS is High unless a Read, Write, AREF, or MRS command is registered. CS never transitions more than once per clock cycle.
IDD parameters are specified with ODT disabled.
Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operations are tested for the full voltage range specified.
IDD tests may use a VIL-to-VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK), and
parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test
the device is 2 V/ns in the range between VIL(AC) andVIH(AC).
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© 2011, GSI Technology
GS4576S09/18L
AC Electrical Characteristics
–18
–24
–25
–33
Min
Max
Min
Max
Min
Max
Min
Max
Notes
Symbol
Units
Parameter
1.875
5.7
2.5
5.7
2.5
5.7
3.3
5.7
ns
—
ns
—
Clock
Input Clock Cycle Time
tCK
Input data clock cycle time
tDK
tCK
tCK
tCK
tCK
Clock jitter: period
tJITPER
–100
100
–150
150
–150
150
–200
200
ps
5, 6
Clock jitter: cycle-to-cycle
tJITCC
—
200
—
300
—
300
—
400
ps
—
Clock High Time
tCKH
tDKH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
—
Clock Low Time
tCKL
tDKL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
—
Clock to input data clock
tCKDK
–0.3
0.3
–0.45
0.5
–0.45
0.5
–0.45
1.2
ns
—
Mode register set cycle time
to any command
tMRSC
6
—
6
—
6
—
6
—
tCK
—
tAS/tCS
0.3
—
0.4
—
0.4
—
0.5
—
ns
—
tDS
0.17
—
0.25
—
0.25
—
0.3
—
ns
—
tAH/tCS
0.3
—
0.4
—
0.4
—
0.5
—
ns
—
tDH
0.17
—
0.25
—
0.25
—
0.3
—
ns
—
Output data clock High time
tQKH
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCKH
—
Output data clock Low time
tQKL
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCKL
—
Half–clock period
tQHP
MIN
(tQKH, tQKL)
—
MIN
(tQKH, tQKL)
—
MIN
(tQKH, tQKL)
—
MIN
(tQKH, tQKL)
—
—
—
QK edge to clock edge skew
tCKQK
–0.2
0.2
–0.25
0.25
–0.25
0.25
–0.3
0.3
ns
—
QK edge to output data
edge
tQKQ0,
tQKQ1
–0.12
0.12
–0.2
0.2
–0.2
0.2
–0.25
0.25
ns
7
tQKQ
–0.22
0.22
–0.3
0.3
–0.3
0.3
–0.35
0.35
ns
8
QK edge to QVLD
tQKVLD
–0.22
0.22
–0.3
0.3
–0.3
0.3
–0.35
0.35
ns
—
Data Valid Window
tDVW
tDVW (MIN)
—
tDVW (MIN)
—
tDVW (MIN)
—
tDVW (MIN)
—
—
9
Setup Times
Address/command and input
setup time
Data–in and data mask to
DK set up time
Hold Times
Address/command and input
hold time
Data-in and data mask to
DK setup time
Data and Data Strobe
QK edge to any output data
edge
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
AC Electrical Characteristics (Continued)
–18
–24
–25
–33
Min
Max
Min
Max
Min
Max
Min
Max
Notes
Symbol
Units
Parameter
—
0.24
—
0.24
—
0.24
—
0.24

10
Refresh
Average Periodic Refresh
Interval
tREFI
Notes:
1. All timing parameters are measured relative to the crossing point of CK/CK, DK/DK and to the crossing point with VREF of the command,
address, and data signals.
2. Outputs measured with equivalent load:
VTT
50 
Q
Test Point
10 pF
3.
Tests for AC timing IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the
related specifications and device operations are tested for the full voltage range specified.
4. AC timing may use a VIL– to–VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing
point for CK/CK), and parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew
rate for the input signals used to test the device is 2 V/ns in the rance between VIL(AC) and VIH(AC).
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Frequency drift is not allowed.
7. tQKQ0 is referenced to Q0–Q8. tQKQ1 is referenced to Q9–Q17.
8. tQKQ takes in to account the skew between any QKx and any Q.
9. tDVW (MIN) tQHP – (tQKQx [MAX] + |tQKQx [MIN]|)
10. To improve efficiency, eight AREF commands (one for each bank) can be posted to the LLDRAM II on consecutive cycles at periodic
intervals of 1.95 s
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GS4576S09/18L
Read Data Valid Window for x18 Device
tQHP1
QK0
tQHP1
QK0
B"1"
Q_Lower_0
B"0"
B"0"
Q_Lower_1
B"1"
B"1"
Q_Lower_2
B"0"
B"0"
Q_Lower_3
B"1"
B"1"
Q_Lower_4
B"0"
B"0"
Q_Lower_5
B"1"
B"1"
Q_Lower_6
B"0"
B"0"
Q_Lower_7
B"1"
B"1"
Q_Lower_8
B"0"
tQKQ0(Min)
tQKQ0(Min)
tQKQ0(Max)
Q_Lower
tQKQ0(Min)
tQKQ0(Max)
X"ZZZ"
QK1
tDVW3
tDVW3
X"155"
X"0AA"
tQHP1
tQHP1
X"ZZZ"
QK1
Q_Upper_9
B"0"
Q_Upper_10
B"1"
B"1"
Q_Upper_11
B"0"
B"0"
B"1"
B"1"
Q_Upper_12
B"0"
B"0"
Q_Upper_13
Q_Upper_14
B"1"
B"1"
B"0"
B"0"
Q_Upper_15
B"1"
B"1"
Q_Upper_16
B"0"
B"0"
Q_Upper_17
B"1"
tQKQ1(Min)
tQKQ1(Min)
tQKQ1(Max)
Q_Upper
X"ZZZ"
tQKQ1(Min)
tQKQ0(Max)
tDVW3
tDVW3
X"0AA"
X"155"
X"ZZZ"
Notes:
1. tQHP is defined as the lesser of tQKH or tQKL.
2. tQKQ0 is referenced to Q0–Q8.
3. Minimum data valid window (tDVW) can be expressed as tQHP – (tQKQx [MAX] + |tQKQx [MIN]|).
4. tQKQ1 is referenced to Q9–Q17.
5. tQKQ takes into account the skew between any QKx and any Q.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Read Burst Timing
tCKH
tCKL
tCK
CK
CK
tCKQK
QKx
tQKL
tQKH
QKx
tQKVLD
tQKVLD
QVLD
tQKQmin
tQKQmax
Q
Q0
tDVW
Q1
Q2
Q3
IEEE 1149.1 Serial Boundary Scan (JTAG)
LLDRAM II includes an IEEE 1149.1 (JTAG) serial boundary scan Test Access Port (TAP). JTAG ports are generally used to
verify the connectivity of the device once it has been mounted on a Printed Circuit Board (PCB). The port operates in accordance
with IEEE Standard 1149.1-2001 (JTAG). Because the ZQ pin is actually an analog output, to ensure proper boundary-scan testing
of the ZQ pin, Mode Register Bit 8 (M8) needs to be set to 0 until the JTAG testing of the pin is complete. Note that upon power
up, the default state of Mode Register Bit 8 (M8) is Low.
Whenever the JTAG port is used prior to the initialization of the LLDRAM II device, such as when initial conectivity testing is
conducted, it is critical that the CK and CK pins meet VID(DC) or that CS be held High from power-up until testing begins. Failure
to do so can result in inadvertent MRS commands being loaded and causing unexpected test results. Alternately a partial
initialization can be conducted that consists of simply loading a single MRS command with desired MRS Register settings. JTAG
testing may then begin as soon as tMRSC is satisfied. JTAG testing can be conducted after full initilization as well.
The input signals of the test access port (TDI, TMS, and TCK) are referenced to the VDD as a supply, while the output driver of the
TAP (TDO) is powered by VDDQ.
The JTAG test access port incorporates a standardTAP controller from which the Instruction Register, Boundary Scan Register,
Bypass Register, and ID Code Register can be selected. Each of these functions of the TAP controller are described below.
Disabling the JTAG Feature
Use of the JTAG port is never required for RAM operation. To disable the TAP controller, TCK must be tied Low (VSS) to prevent
clocking of the device. TDI and TMS are internally pulled up and may be unconnected or they can be connected to VDD directly or
through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state, which will not
interfere with the operation of the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK.
All of the states in the TAP Controller State Diagram are entered through the serial input of the TMS pin. A “0” in the diagram
represents a Low on the TMS pin during the rising edge of TCK while a “1” represents a High on TMS.
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GS4576S09/18L
Test Data-In (TDI)
The TDI ball is used to serially input test instructions and data into the registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP Controller State Diagram. TDI is connected to the Most Significant Bit
(MSB) of any register (see the TAP Controller Block Diagram).
Test Data-Out (TDO)
The TDO output ball is used to serially clock test instructions and data out from the registers. The TDO output driver is only active
during the Shift-IR and Shift-DR TAP controller states. In all other states, the TDO pin is in a High-Z state. The output changes on
the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register (see the TAP Controller Block
Diagram).
TAP Controller
The TAP controller is a finite state machine that uses the state of the TMS pin at the rising edge of TCK to navigate through its
various modes of operation. See the TAP Controller State Diagram. Each state is described in detail below.
Test-Logic-Reset
The test-logic-reset controller state is entered when TMS is held High for at least five consecutive rising edges of TCK. As long as
TMS remains High, the TAP controller will remain in the test-logic-reset state. The test logic is inactive during this state.
Run-Test/Idle
The run-test/idle is a controller state in between scan operations. This state can be maintained by holding TMS Low. From here
either the data register scan, or subsequently, the instruction register scan can be selected.
Select-DR-Scan
Select-DR-scan is a temporary controller state. All test data registers retain their previous state while here.
Capture-DR
The Capture-DR state is where the data is parallel-loaded into the test data registers. If the Boundary Scan Register is the currently
selected register, then the data currently on the pins is latched into the test data registers.
Shift-DR
Data is shifted serially through the data register while in this state. As new data is input through the TDI pin, data is shifted out of
the TDO pin.
Exit1-DR, Pause-DR, and Exit2-DR
The purpose of Exit1-DR is used to provide a path to return back to the run-test/idle state (through the Update-DR state). The
Pause-DR state is entered when the shifting of data through the test registers needs to be suspended. When shifting is to reconvene,
the controller enters the Exit2-DR state and then can re-enter the Shift-DR state.
Update-DR
When the EXTEST instruction is selected, there are latched parallel outputs of the boundary scan shift register that only change
state during the Update-DR controller state.
Instruction Register States
The instruction register states of the TAP controller are similar to the data register states. The desired instruction is serially shifted
into the instruction register during the Shift-IR state and is loaded during the Update-IR state.
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GS4576S09/18L
Loading Instruction Code and Shifting Out Data
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
8-bit Instruction Code
TCK
TMS
TDI
TAP State
Logic-Reset
Idle
Select-DR
Select-IR
Capture-IR
Shift-IR
Shift-IR
Exit 1-IR
Pause-IR
Pause-IR
T18
T19
TDO
Loading Instruction Code and Shifting Out Data (Continued)
T10
T11
T12
T13
T14
T15
T16
T17
n-bit Register between TDI and TDO
TCK
TMS
TDI
TAP State
Exit 2-IR
Update-IR
Select-DR
Capture-DR
Shift-DR
Shift-DR
Shift-DR
Exit 1-DR
Update-DR
Idle
TDO
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GS4576S09/18L
JTAG Tap Controller State Diagram
1
0
Test Logic Reset
0
Run Test Idle
1
Select DR-scan 1
Select IR-scan
0
0
1
1
Capture-DR
Capture-IR
0
0
Shift-IR
Shift-DR
0
1
Exit1-DR
1
Exit1-IR
Pause-IR
0
1
Exit2-DR
0
1
0
Exit2-IR
1
1
Update-DR
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1
0
Pause-DR
1
0
1
0
0
1
0
Update-IR
1
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
0
© 2011, GSI Technology
GS4576S09/18L
TAP Controller Block Diagram
Bypass Regsiter
7
TDI
Selection
circuitry
6
5
4
3
2
1
0
0
Instruction Regsiter
31 30 29
.
.
.
2
1
0
1
0
Selection
circuitry
TDO
Identification Regsiter
x1
.
.
.
.
.
2
Boundary Scan Regsiter
TCK
TAP Controller
TMS
Note:
x= 112 for all configurations
Performing a TAP RESET
A reset is performed by forcing TMS High (VDDQ) for five rising edges of TCK. This RESET does not affect the operation of the
LLDRAM II and may be performed while the LLDRAM II is operating.
At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the LLDRAM II test
circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
Instruction Register
Eight-bit instructions can be serially loaded into the instruction register. This register is loaded during the Update-IR state of the
TAP controller. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the Capture-IR state, the two LSBs are loaded with a binary “01” pattern to allow for fault isolation
of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is
a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the LLDRAM II with
minimal delay. The bypass register is set Low (VSS) when the BYPASS instruction is executed.
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GS4576S09/18L
Boundary Scan Register
The Boundary Scan Register is connected to all the input and bidirectional balls on the LLDRAM II. Several bits are also included
in the scan register for reserved balls. The LLDRAM II has a 113-bit register.
The Boundary Scan Register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state.
The Boundary Scan Register table shows the order in which the bits are connected. Each bit corresponds to one of the balls on the
LLDRAM II package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE command is loaded in
the instruction register. The IDCODE is hardwired into the LLDRAM II and can be shifted out when the TAP controller is in the
shift-DR state. The ID register has a vendor code and other information described in the table below.
Identification Register Definitions
Instruction Field
Revision number (31:28)
Device ID (27:12)
GSI JEDEC ID code (11:1)
ID register presence indicator (0)
Bit Size
Bit Size
abcd
ab = die revision
cd = 00 for x9, 01 for x18
00jkidef10100111
def = 000 for 288Mb, 001 for 576Mb
i = 0 for common I/O, 1 for separate I/O
jk = 01 for LLDRAM II
01011011001
Allows unique identification of LLDRAM II vendor
1
Indicates the presence of an ID register
TAP Instruction Set
Overview
Many different instructions (256) are possible with the 8-bit instruction register. All combinations used are listed in the Instruction
Codes table. These six instructions are described in detail below. The remaining instructions are reserved and should not be used.
The TAP controller used in this LLDRAM II is fully compliant to the 1149.1 convention.
Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.
EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary Scan Register cells at output
balls are used to apply a test vector, while those at input balls capture test results. Typically, the first test vector to be applied using
the EXTEST instruction will be shifted into the Boundary Scan Register using the PRELOAD instruction. Thus, during the
Update-IR state of EXTEST, the output driver is turned on, and the PRELOAD data is driven onto the output balls.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the
TAP controller is given a test logic reset state.
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GS4576S09/18L
High-Z
The High-Z instruction places all LLDRAM II outputs into a High-Z state, and causes the bypass register to be connected between
TDI and TDO when the TAP Controller is in the Shift DR state.
CLAMP
When the CLAMP instruction is loaded into the instruction register, the data driven by the output balls are determined from the
values held in the Boundary Scan Register. Additionally, it causes the bypass register to be connected between TDI and TDO
when the TAP Controller is in the Shift DR state.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is captured in the Boundary Scan Register.
The user must be aware that the TAP controller clock can only operate at a frequency up to 50 MHz, while the LLDRAM II clock
operates significantly faster. Because there is a large difference between the clock frequencies, it is possible that during the
Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition
(metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results
may not be possible.
To ensure that the Boundary Scan Register will capture the correct value of a signal, the LLDRAM II signal must be stabilized long
enough to meet the TAP controller’s capture setup plus hold time (tCS + tCH). The LLDRAM II clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the value of the CK and CK captured in the Boundary Scan Register.
Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the Boundary
Scan Register between the TDI and TDO balls.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is
placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple
devices are connected together on a board.
Reserved for Future Use
The remaining instructions are not implemented but are reserved for future use. Do not use these instructions.
TAP Timing
T0
T1
T2
T3
T4
T5
tTLTH
tTHTL
tTHTH
Test Clock (TCK)
tTHMX
tMVTH
Test Mode Select (TMS)
tTHDX
tDVTH
Test Data-In (TDI)
tTLOX
tTLOV
Test Data-Out (TDO)
Rev: 1.03 11/2013
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
TAP Input AC Logic Levels
Description
Symbol
Min
Max
Units
Input High (logic 1) Voltage
VIH
VREF + 0.3
—
V
Input Low (logic 0) Voltage
VIL
—
VREF – 0.3
V
TAP AC Electrical Characteristics
Description
Symbol
Min
Max
Units
Clock
Clock Cycle Time
tTHTH
20
—
ns
Clock Frequency
tTF
—
50
MHz
Clock High Time
tTHTL
10
—
ns
Clock Low Time
tTLTH
10
—
ns
TDI/TDO Times
TCK Low to TDO Unknown
tTLOX
0
—
ns
TCK Low to TDO Valid
tTLOV
—
10
ns
TDI Valid to TCK High
tDVTH
5
—
ns
TCK High to TDI Invalid
tTHDX
5
—
ns
Setup Times
TMS Setup
tMVTH
5
—
ns
Capture Setup
tCS
5
—
ns
Hold Times
TMS Setup
tTHMX
5
—
ns
Capture Setup
tCH
5
—
ns
Note:
tCS and tCH refer to the set up and hold time requirements of latching data from the Boundary Scan Register.
Rev: 1.03 11/2013
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
TAP DC Electrical Characteristics and Operating Conditions
Description
Condition
Symbol
Min
Max
Units
Notes
Input High (logic 1) Voltage
—
VIH
VREF + 0.15
VDD + 0.3
V
1, 2
Input High (logic 0) Voltage
—
VIL
VSS – 0.3
VREF – 0.15
V
1, 2
Input Leakage Current
Output disabled,
0 VVIN VDDQ
ILI
–5.0
5.0

—
Output Leakage Current
0 VVIN VDD
ILO
–5.0
5.0

—
Output Low Voltage
IOLC = 100 
VOL1
—
0.2
V
1
Output Low Voltage
IOLT = 2mA
VOL2
—
0.4
V
1
Output High Voltage
IOHC = 100 
VOH1
VDDQ – 0.2
—
V
1
Output High Voltage
IOHT= 2mA
VOH2
VDDQ – 0.4
—
V
1
Notes:
1. All voltages referenced to VSS (GND).
2.
Overshoot = VIH(AC) VDD + 0.7 V for t tTHTH/2; undershoot = VIL(AC)– 0.5 V for t tTHTH/2; during normal operation, VDDQ must
not exceed VDD.
Scan Register Sizes
Register Name
Bit Size
Instruction
8
Bypass
1
ID
32
Boundary Scan
113
JTAG TAP Instruction Codes
Instruction
Code
EXTEST
0000 0000
Captures I/O ring contents; Places the Boundary Scan Register between TDI and TDO. Data
driven by output balls are determined from values held in the Boundary Scan Register.
IDCODE
0010 0001
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect LLDRAM II operations.
SAMPLE/PRELOAD
0000 0101
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. This
operation does not affect LLDRAM II operations.
CLAMP
0000 0111
Selects the bypass register to be connected between TDI and TDO. Data driven by output balls are
determined from values held in the Boundary Scan Register.
HIGH-Z
0000 0011
Selects the bypass register to be connected between TDI and TDO. All outputs are forced into
High-Z.
BYPASS
1111 1111
Places Bypass Register between TDI and TDO.This operation does not affect LLDRAM II
operations.
Rev: 1.03 11/2013
Description
59/63
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Boundary Scan Exit Order
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Ball
K1
K2
L2
L1
M1
M3
M2
N1
P1
N3
N3
N2
N2
P3
P3
P2
P2
R2
R3
T2
T2
T3
T3
U2
U2
U3
U3
V2
U10
U10
U11
U11
T10
T10
T11
T11
R10
R10
Bit #
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
Ball
R11
R11
P11
P11
P10
P10
N11
N11
N10
N10
P12
N12
M11
M10
M12
L12
L11
K11
K12
J12
J11
H11
H12
G12
G10
G11
E12
F12
F10
F10
F11
F11
E10
E10
E11
E11
D11
D10
Bit #
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
—
Ball
C11
C11
C10
C10
B11
B11
B10
B10
B3
B3
B2
B2
C3
C3
C2
C2
D3
D3
D2
D2
E2
E2
E3
E3
F2
F2
F3
F3
E1
F1
G2
G3
G1
H1
H2
J2
J1
—
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: [email protected]
Rev: 1.03 11/2013
60/63
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Package Dimensions—144-Bump BGA (Package L)
A1
1 2 3 4 5 6 7 8 9 10 11 12
10.60 CTR.
0.73±0.1
10° TYP.
SEATING PLANE
0.012 A
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
8.80
Ø0.51 (144x)
A1
0.80 TYP.
0.49±0.05
12 11 10 9 8 7 6 5 4 3 2 1
1.0 TYP.
17.00 CTR
18.50±0.10
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
18.1 CTR
1.20 MAX
0.8 TYP
0.34 MIN
8.8 CTR
11.00±0.10
Rev: 1.03 11/2013
Note: All dimensions in millimeters.
61/63
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Ordering Information for GSI LLDRAM IIs
Org
Part Number1
Type
Package
Speed
(tCK/tRC)
T2
64M x 9
GS4576S09L-18
SIO LLDRAM II
144-ball BGA
533/15
C
64M x 9
GS4576S09L-24
SIO LLDRAM II
144-ball BGA
400/15
C
64M x 9
GS4576S09L-25
SIO LLDRAM II
144-ball BGA
400/20
C
64M x 9
GS4576S09L-33
SIO LLDRAM II
144-ball BGA
300/20
C
32M x 18
GS4576S18L-18
SIO LLDRAM II
144-ball BGA
533/15
C
32M x 18
GS4576S18L-24
SIO LLDRAM II
144-ball BGA
400/15
C
32M x 18
GS4576S18L-25
SIO LLDRAM II
144-ball BGA
400/20
C
32M x 18
GS4576S18L-33
SIO LLDRAM II
144-ball BGA
300/20
C
64M x 9
GS4576S09GL-18
SIO LLDRAM II
RoHS-compliant 144-ball BGA
533/15
C
64M x 9
GS4576S09GL-24
SIO LLDRAM II
RoHS-compliant 144-ball BGA
400/15
C
64M x 9
GS4576S09GL-25
SIO LLDRAM II
RoHS-compliant 144-ball BGA
400/20
C
64M x 9
GS4576S09GL-33
SIO LLDRAM II
RoHS-compliant 144-ball BGA
300/20
C
32M x 18
GS4576S18GL-18
SIO LLDRAM II
RoHS-compliant 144-ball BGA
533/15
C
32M x 18
GS4576S18GL-24
SIO LLDRAM II
RoHS-compliant 144-ball BGA
400/15
C
32M x 18
GS4576S18GL-25
SIO LLDRAM II
RoHS-compliant 144-ball BGA
400/20
C
32M x 18
GS4576S18GL-33
SIO LLDRAM II
RoHS-compliant 144-ball BGA
300/20
C
64M x 9
GS4576S09L-18I
SIO LLDRAM II
144-ball BGA
533/15
I
64M x 9
GS4576S09L-24I
SIO LLDRAM II
144-ball BGA
400/15
I
64M x 9
GS4576S09L-25I
SIO LLDRAM II
144-ball BGA
400/20
I
64M x 9
GS4576S09L-33I
SIO LLDRAM II
144-ball BGA
300/20
I
32M x 18
GS4576S18L-18I
SIO LLDRAM II
144-ball BGA
533/15
I
32M x 18
GS4576S18L-24I
SIO LLDRAM II
144-ball BGA
400/15
I
32M x 18
GS4576S18L-25I
SIO LLDRAM II
144-ball BGA
400/20
I
32M x 18
GS4576S18L-33I
SIO LLDRAM II
144-ball BGA
300/20
I
64M x 9
GS4576S09GL-18I
SIO LLDRAM II
RoHS-compliant 144-ball BGA
533/15
I
64M x 9
GS4576S09GL-24I
SIO LLDRAM II
RoHS-compliant 144-ball BGA
400/15
I
64M x 9
GS4576S09GL-25I
SIO LLDRAM II
RoHS-compliant 144-ball BGA
400/20
I
Note:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS4576S09-533T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.03 11/2013
62/63
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS4576S09/18L
Ordering Information for GSI LLDRAM IIs (Continued)
Org
Part Number1
Type
Package
Speed
(tCK/tRC)
T2
64M x 9
GS4576S09GL-33I
SIO LLDRAM II
RoHS-compliant 144-ball BGA
300/20
I
32M x 18
GS4576S18GL-18I
SIO LLDRAM II
RoHS-compliant 144-ball BGA
533/15
I
32M x 18
GS4576S18GL-24
SIO LLDRAM II
RoHS-compliant 144-ball BGA
400/15
I
32M x 18
GS4576S18GL-25I
SIO LLDRAM II
RoHS-compliant 144-ball BGA
400/20
I
32M x 18
GS4576S18GL-33I
SIO LLDRAM II
RoHS-compliant 144-ball BGA
300/20
I
Note:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS4576S09-533T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
576Mb LLDRAM II Datasheet Revision History
DS/DateRev. Code: Old;
New
4576Sxx_r1
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
4576Sxx_r1.01
• Various changes to prepare for public release
• (Rev.101b: Corrected mechanical drawing)
• (Rev1.01c: Editorial updates)
• (Rev1.01d: Updated NOP commands from 3000 to 2048)
• (Rev1.01e: Added Termal Impedance numbers for 4-layer
substrate)
• (Rev1.01f: Changed all VSSQ references to VSS)
4576Sxx_r1.02
• Changed DLL Reset to 1024 cycles (page 9)
• Corrected typos/wording errors in TAP section
• (Rev1.02a: Changed NOP time from 2048 and 1024)
4576Sxx_r1.03
• Updated to reflect MP status
Rev: 1.03 11/2013
63/63
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology