GS8160ExxBT-xxxV 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation • 1.8 V or 2.5 V core power supply • 1.8 V or 2.5 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package • RoHS-compliant 100-lead TQFP package available Functional Description Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register. DCD Pipelined Reads The GS8160ExxBT-xxxV is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. Ne w De sig Applications The GS8160ExxBT-xxxV is an 18,874,368-bit (16,777,216-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. ct Features 250 MHz–150 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O n— Di sco nt inu ed Pr od u 100-Pin TQFP Commercial Temp Industrial Temp No t Re co m me nd ed for Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or Pipeline 3-1-1-1 Flow Through 2-1-1-1 Rev: 1.04 9/2008 Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS8160ExxBT-xxxV operates on a 1.8 V or 2.5 V power supply. All input are 1.8 V or 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V or 2.5 V compatible. Parameter Synopsis -250 -200 -150 Unit tKQ tCycle 3.0 4.0 3.0 5.0 3.8 6.7 ns ns Curr (x18) Curr (x32/x36) 280 330 230 270 185 210 mA mA tKQ tCycle 5.5 5.5 6.5 6.5 7.5 7.5 ns ns Curr (x18) Curr (x32/x36) 210 240 185 205 170 190 mA mA 1/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV n— Di sco nt inu ed Pr od u ct A A E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS8160E18BT-xxxV 100-Pin TQFP Pinout NC NC NC Ne w me nd ed for A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC A A A A1 A0 NC NC VSS VDD A A A A A A A A A Re co LBO m A No t VSS NC NC DQB DQB VSS VDDQ DQB DQB FT VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC De sig VDDQ 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating. Rev: 1.04 9/2008 2/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV n— Di sco nt inu ed Pr od u ct A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS8160E32BT-xxxV 100-Pin TQFP Pinout NC DQC DQC VDDQ Ne w me nd ed for NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC A A A A1 A0 NC NC VSS VDD A A A A A A A A A Re co LBO m A No t FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD NC De sig VSS DQC DQC DQC DQC VSS VDDQ DQC DQC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating. Rev: 1.04 9/2008 3/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV n— Di sco nt inu ed Pr od u ct A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS8160E36BT-xxxV 100-Pin TQFP Pinout DQPC DQC DQC VDDQ Ne w me nd ed for DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA A A A A1 A0 NC NC VSS VDD A A A A A A A A A Re co LBO m A No t FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD De sig VSS DQC DQC DQC DQC VSS VDDQ DQC DQC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating. Rev: 1.04 9/2008 4/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV TQFP Pin Description Type Description A 0, A 1 I Address field LSBs and Address Counter preset Inputs A I Address Inputs DQA DQB DQC DQD I/O n— Di sco nt inu ed Pr od u ct Symbol Data Input and Output pins NC No Connect BW I Byte Write—Writes all enabled bytes; active low BA, BB, BC, BD I Byte Write Enable for DQA, DQB Data I/Os; active low CK I Clock Input Signal; active high GW I Global Write Enable—Writes all bytes; active low E1 I Chip Enable; active low E2 I G I ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active high FT I LBO I VDD I VSS I VDDQ I Chip Enable; active high De sig Output Enable; active low me nd ed for Ne w Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground No t Re co m Output driver power supply Rev: 1.04 9/2008 5/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV GS8160ExxBT-xxxV Block Diagram Register D Q A0 A0 D0 Q0 A1 D1 Q1 Counter Load n— Di sco nt inu ed Pr od u A1 ct A0–An A LBO ADV Memory Array CK ADSC ADSP Q Register GW BW BA D Q Register D D 36 Q BB 36 D Ne w D Q Register BD Q Register D De sig Q BC Q Register D Register 4 Register me nd ed for D Q Register E1 E2 E3 D Q Register FT G 0 Power Down No t ZZ Q Re co m D DQx1–DQx9 Control Note: Only x36 version shown for simplicity. Rev: 1.04 9/2008 6/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV Mode Pin Functions Burst Order Control LBO Output Register Control FT Power Down Control ZZ State Function L Linear Burst H Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB ct Pin Name n— Di sco nt inu ed Pr od u Mode Name Note: There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table. Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 me nd ed for Note: The burst counter wraps to initial state on the 5th clock. Ne w 1st address A[1:0] A[1:0] A[1:0] A[1:0] De sig A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. No t Re co m BPR 1999.05.18 Rev: 1.04 9/2008 7/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV GW BW BA BB BC BD Notes Read H H X X X X 1 Write No Bytes H L H H H H 1 Write byte a H L L Write byte b H L H Write byte c H L H Write byte d H L H Write all bytes H L L ct Function n— Di sco nt inu ed Pr od u Byte Write Truth Table H H H 2, 3 L H H 2, 3 H L H 2, 3, 4 H H L 2, 3, 4 L L L 2, 3, 4 No t Re co m me nd ed for Ne w De sig Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.04 9/2008 8/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV Operation E1 None X L Deselect Cycle, Power Down None X L Deselect Cycle, Power Down None X L Deselect Cycle, Power Down None X L Deselect Cycle, Power Down None X H Read Cycle, Begin Burst External R L Read Cycle, Begin Burst External R L Write Cycle, Begin Burst External W L Read Cycle, Continue Burst Next CR X Read Cycle, Continue Burst Next CR Write Cycle, Continue Burst Next CW Write Cycle, Continue Burst Next CW Read Cycle, Suspend Burst Current Read Cycle, Suspend Burst Current Write Cycle, Suspend Burst DQ3 L X X High-Z X L X X High-Z H L X X X High-Z L X L X X X High-Z X X X L X X High-Z H L L X X X Q H L H L X F Q H L H L X T D X X H H L F Q ADSP ADSC X H X L X X X X X H L F Q X X X H H L T D H X X X H L T D X X X H H H F Q H X X X H H F Q Current X X X H H H T D Current H X X X H H T D Ne w H me nd ed for Write Cycle, Suspend Burst W E3 De sig Deselect Cycle, Power Down ADV E2 n— Di sco nt inu ed Pr od u State Address Diagram Used Key ct Synchronous Truth Table No t Re co m Notes: 1. X = Don’t Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.04 9/2008 9/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV Simplified State Diagram ct X W R R R First Write CR De sig CW Ne w W First Read X CR R R X Burst Write me nd ed for Simple Burst Synchronous Operation Simple Synchronous Operation W X n— Di sco nt inu ed Pr od u Deselect Burst Read X CR CW CR No t Re co m Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.04 9/2008 10/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV Simplified State Diagram with G ct X W R W X n— Di sco nt inu ed Pr od u Deselect R R First Write CR First Read CW X CR W Burst Write me nd ed for X Ne w De sig CW W R CR CW R W Burst Read X CW CR No t Re co m Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.04 9/2008 11/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV Absolute Maximum Ratings (All voltages reference to VSS) Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage on VDDQ Pins –0.5 to VDD VI/O Voltage on I/O Pins VIN Voltage on Other Input Pins IIN Input Current on Any Pin IOUT Output Current on Any I/O Pin PD Package Power Dissipation TSTG Storage Temperature TBIAS Temperature Under Bias n— Di sco nt inu ed Pr od u ct Symbol V –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V –0.5 to VDD +0.5 (≤ 4.6 V max.) V +/–20 mA +/–20 mA 1.5 W –55 to 125 o –55 to 125 o C C De sig Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges (1.8 V/2.5 V Version) Symbol Min. Typ. Max. Unit VDD1 1.7 1.8 2.0 V VDD2 2.3 2.5 2.7 V 1.8 V VDDQ I/O Supply Voltage VDDQ1 1.7 1.8 VDD V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 VDD V 1.8 V Supply Voltage me nd ed for 2.5 V Supply Voltage Ne w Parameter Notes No t Re co m Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.04 9/2008 12/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.3*VDD 1 n— Di sco nt inu ed Pr od u Parameter ct VDDQ2 & VDDQ1 Range Logic Levels V Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Recommended Operating Temperatures Parameter Symbol Ambient Temperature (Commercial Range Versions) TA Ambient Temperature (Industrial Range Versions) TA Min. Typ. Max. Unit Notes 0 25 70 °C 2 –40 25 85 °C 2 De sig Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. VSS 50% VSS – 2.0 V Re co m 20% tKC Capacitance 20% tKC VDD + 2.0 V me nd ed for VIH Overshoot Measurement and Timing Ne w Undershoot Measurement and Timing 50% VDD VIL (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 8 10 pF Input/Output Capacitance CI/O VOUT = 0 V 12 14 pF No t Parameter Note: These parameters are sample tested. Rev: 1.04 9/2008 13/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDDQ/2 Output load Fig. 1 DQ DC Electrical Characteristics IIL FT, ZZ Input Current IIN Output Leakage Current IOL * Distributed Test Jig Capacitance Test Conditions Min Max VIN = 0 to VDD –1 uA 1 uA VDD ≥ VIN ≥ 0 V –100 uA 100 uA Output Disable, VOUT = 0 to VDD –1 uA 1 uA Symbol Test Conditions Min Max VOH1 IOH = –4 mA, VDDQ = 1.7 V VDDQ – 0.4 V — VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V — VOL1 IOL = 4 mA — 0.4 V VOL2 IOL = 8 mA — 0.4 V De sig Input Leakage Current (except mode pins) VDDQ/2 Ne w Symbol 30pF* 50Ω Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Parameter n— Di sco nt inu ed Pr od u Output Load 1 ct Figure 1 Parameter 1.8 V Output High Voltage 2.5 V Output High Voltage 1.8 V Output Low Voltage No t Re co m 2.5 V Output Low Voltage me nd ed for DC Output Characteristics (1.8 V/2.5 V Version) Rev: 1.04 9/2008 14/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV Operating Currents -250 Device Selected; All other inputs ≥VIH or ≤ VIL Output open Operating Current Symbol 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C Pipeline IDD IDDQ 290 40 300 40 240 30 250 30 190 20 200 20 mA Flow Through IDD IDDQ 220 20 230 20 190 15 200 15 175 15 185 15 mA Pipeline IDD IDDQ 260 20 270 20 215 15 225 15 170 15 180 15 mA Flow Through IDD IDDQ 200 10 210 10 175 10 185 10 160 10 170 10 mA Pipeline ISB 40 50 40 50 40 50 mA Flow Through ISB 40 50 40 50 40 50 mA Pipeline IDD 85 90 75 80 60 65 mA Flow Through IDD 60 65 50 55 50 55 mA Mode (x32/ x36) (x18) Standby Current ZZ ≥ VDD – 0.2 V Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL — — Unit No t Re co m me nd ed for Ne w De sig Notes: 1. IDD and IDDQ apply to any combination of VDD and VDDQ operation. 2. All parameters listed are worst case scenario. ct Test Conditions -150 –40 to 85°C n— Di sco nt inu ed Pr od u Parameter -200 0 to 70°C Rev: 1.04 9/2008 15/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV AC Electrical Characteristics Clock to Output Valid tKQ Clock to Output Invalid tKQX Clock to Output in Low-Z tLZ1 Setup time tS Hold time tH -150 Unit Min Max Min Max Min Max 4.0 — 5.0 — ct tKC -200 6.7 — ns n— Di sco nt inu ed Pr od u Clock Cycle Time -250 — 3.0 — 3.0 — 3.8 ns 1.5 — 1.5 — 1.5 — ns 1.5 — 1.5 — 1.5 — ns 1.5 — 1.5 — 1.5 — ns 0.2 — 0.4 — 0.5 — ns 5.5 — 6.5 — 7.5 — ns — 5.5 — 6.5 — 7.5 ns 2.0 — 2.0 — 2.0 — ns 2.0 — 2.0 — 2.0 — ns 1.5 — 1.5 — 1.5 — ns 0.5 — 0.5 — 0.5 — ns 1.3 — 1.3 — 1.5 — ns 1.7 — 1.7 — 1.7 — ns De sig Flow Through Symbol 1.5 2.5 1.5 3.0 1.5 3.0 ns Clock Cycle Time tKC Clock to Output Valid tKQ Clock to Output Invalid tKQX 1 Clock to Output in Low-Z tLZ Setup time tS Hold time tH Clock HIGH Time tKH Clock LOW Time tKL Clock to Output in High-Z tHZ1 G to Output Valid tOE — 2.5 — 3.0 — 3.8 ns G to output in Low-Z tOLZ1 0 — 0 — 0 — ns G to output in High-Z ZZ setup time tOHZ1 ZZ recovery — 2.5 — 3.0 — 3.8 ns 2 5 — 5 — 5 — ns 2 1 — 1 — 1 — ns tZZR 20 — 20 — 20 — ns tZZS tZZH me nd ed for ZZ hold time Ne w Pipeline Parameter No t Re co m Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.04 9/2008 16/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV Pipeline Mode Timing (DCD) Read A Cont Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont tKC CK ADSP tS ADSC initiated read tH ADSC tS tH ADV tS tH Ao–An A B C tS GW tS tH BW Ba–Bd tS tH tS E2 and E3 only sampled with ADSC tH tH G me nd ed for E2 E3 tS tOE Hi-Z tOHZ Q(A) tKQ tH D(B) tHZ tLZ tKQX Q(C) Q(C+1) Q(C+2) Q(C+3) No t Re co m DQa–DQd Deselected with E1 Ne w E1 De sig tH tS tS n— Di sco nt inu ed Pr od u tKL tKH Deselect Deselect ct Begin Rev: 1.04 9/2008 17/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV Flow Through Mode Timing (DCD) Read A Cont Deselect Write B Read C tKH tKC CK ADSP tS tH ADSC initiated read ADSC tH tS tS ADV tS tH A B C tS tH tS tH BW Ba–Bd tS tH tS tH E2 tS tH E3 E2 and E3 only sampled with ADSP and ADSC Re co m G Deselected with E1 E1 masks ADSP me nd ed for E1 Ne w tH tS tH De sig GW E1 masks ADSP tH tS tOE tKQ tOHZ Q(A) tKQX tHZ tLZ D(B) Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C) No t DQa–DQd Deselect Fixed High tS tH Ao–An Read C+1 Read C+2 Read C+3 Read C n— Di sco nt inu ed Pr od u tKL ct Begin Rev: 1.04 9/2008 18/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. n— Di sco nt inu ed Pr od u ct Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing tKH tKC tKL CK Setup Hold ADSP De sig ADSC tZZS Ne w ZZ tZZR tZZH Application Tips No t Re co m me nd ed for Single and Dual Cycle Deselect SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs (like this one) do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. Rev: 1.04 9/2008 19/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV TQFP Package Drawing (Package T) A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 — 0.20 D Terminal Dimension 21.9 22.0 22.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch — 0.65 — L Foot Length 0.45 0.60 0.75 L1 Lead Length — 1.00 — Y Coplanarity θ Lead Angle n— Di sco nt inu ed Pr od u Min. Nom. Max e b A2 Y De sig A1 0.10 0° — 7° E1 E No t Re co m me nd ed for Ne w Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. D D1 Description c Pin 1 Symbol L1 θ ct L Rev: 1.04 9/2008 20/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV TA3 250/5.5 C TQFP 200/6.5 C 1.8 V or 2.5 V TQFP 150/7.5 C DCD 1.8 V or 2.5 V TQFP 250/5.5 C GS8160E32BT-200V DCD 1.8 V or 2.5 V TQFP 200/6.5 C 512K x 32 GS8160E32BT-150V DCD 1.8 V or 2.5 V TQFP 150/7.5 C 512K x 36 GS8160E36BT-250V DCD 1.8 V or 2.5 V TQFP 250/5.5 C 512K x 36 GS8160E36BT-200V DCD 1.8 V or 2.5 V TQFP 200/6.5 C 512K x 36 GS8160E36BT-150V DCD 1.8 V or 2.5 V TQFP 150/7.5 C 1M x 18 GS8160E18BT-250IV DCD 1.8 V or 2.5 V TQFP 250/5.5 I 1M x 18 GS8160E18BT-200IV DCD 1.8 V or 2.5 V TQFP 200/6.5 I 1M x 18 GS8160E18BT-150IV DCD 1.8 V or 2.5 V TQFP 150/7.5 I 512K x 32 GS8160E32BT-250IV DCD 1.8 V or 2.5 V TQFP 250/5.5 I 512K x 32 GS8160E32BT-200IV DCD 1.8 V or 2.5 V TQFP 200/6.5 I 512K x 32 GS8160E32BT-150IV DCD 1.8 V or 2.5 V TQFP 150/7.5 I 512K x 36 GS8160E36BT-250IV DCD 1.8 V or 2.5 V TQFP 250/5.5 I 512K x 36 GS8160E36BT-200IV DCD 1.8 V or 2.5 V TQFP 200/6.5 I 512K x 36 GS8160E36BT-150IV DCD 1.8 V or 2.5 V TQFP 150/7.5 I 1M x 18 GS8160E18BGT-250V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 C 1M x 18 GS8160E18BGT-200V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 C 1M x 18 GS8160E18BGT-150V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 C 512K x 32 GS8160E32BGT-250V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 C 512K x 32 GS8160E32BGT-200V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 C 512K x 32 GS8160E32BGT-150V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 C 512K x 36 GS8160E36BGT-250V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 C 512K x 36 GS8160E36BGT-200V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 C 512K x 36 GS8160E36BGT-150V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 C 1M x 18 GS8160E18BGT-250IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 I Type Voltage Options Package 1M x 18 GS8160E18BT-250V DCD 1.8 V or 2.5 V TQFP 1M x 18 GS8160E18BT-200V DCD 1.8 V or 2.5 V 1M x 18 GS8160E18BT-150V DCD 512K x 32 GS8160E32BT-250V 512K x 32 Ne w De sig n— Di sco nt inu ed Pr od u Part Number1 Re co m Org ct Speed2 (MHz/ns) me nd ed for Ordering Information for GSI Synchronous Burst RAMs No t 1M x 18 GS8160E18BGT-200IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160E18BT-150IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.04 9/2008 21/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV Ordering Information for GSI Synchronous Burst RAMs (Continued) Part Number1 Type Voltage Options Package Speed2 (MHz/ns) TA3 1M x 18 GS8160E18BGT-150IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 I 512K x 32 GS8160E32BGT-250IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 I 512K x 32 GS8160E32BGT-200IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 I 512K x 32 GS8160E32BGT-150IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 I 512K x 36 GS8160E36BGT-250IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 I 512K x 36 GS8160E36BGT-200IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 I n— Di sco nt inu ed Pr od u ct Org No t Re co m me nd ed for Ne w De sig 512K x 36 GS8160E36BGT-150IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160E18BT-150IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.04 9/2008 22/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS8160ExxBT-xxxV 18Mb Sync SRAM Datasheet Revision History Types of Changes Format or Content • Creation of new datasheet GS8160EVxxB_r1 Content GS8160ExxB-xxxV_r_01; GS8160ExxB-xxxV_r1_02 Content GS8160ExxB-xxxV_r_02; GS8160ExxB-xxxV_r1_03 Content GS8160ExxB-xxxV_r_03; GS8160ExxB-xxxV_r1_04 Content • Changed part numbering due to change in product nomenclature • Updated Truth Tables (pg. 8, 9) • Removed Status column from Ordering Information table, Removed Preliminary banner • Updated for MP status No t Re co m me nd ed for Ne w De sig GS8160EVxxB_r1; GS8160ExxB-xxxV_r_01 ct Page;Revisions;Reason n— Di sco nt inu ed Pr od u DS/DateRev. Code: Old; New Rev: 1.04 9/2008 23/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology