GS8662S08/09/18/36E-250/200/167 250 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 72Mb Burst of 2 SigmaSIO™ DDR-II SRAM 165-Bump BGA Commercial Temp Industrial Temp A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous device. It employs dual input register clock inputs, K and K. The device also allows the user to manipulate the output register clock input quasi independently with dual output register clock inputs, C and C. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Each Burst of 2 SigmaSIO DDR-II SRAM also supplies Echo Clock outputs, CQ and CQ, which are synchronized with read data output. When used in a source synchronous clocking scheme, the Echo Clock outputs can be used to fire input registers at the data’s destination. Each internal read and write operation in a SigmaSIO DDR-II B2 RAM is two times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. Therefore, the address field of a SigmaSIO DDR-II B2 is always one address pin less than the advertised index depth (e.g., the 8M x 8 has a 4M addressable index). De sig SigmaSIO™ DDR-II Family Overview Clocking and Addressing Schemes n— Di sco nt inu ed Pr od u • Simultaneous Read and Write SigmaSIO™ DDR-II Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • DLL circuitry for wide output data valid window and future frequency scaling • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ mode pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • Pin-compatible with future 144Mb devices • 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available ct Features me nd ed for Ne w GS8662S08/09/18/36 are built in compliance with the SigmaSIO DDR-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Parameter Synopsis -200 -167 tKHKH 4.0 ns 5.0 ns 6.0 ns tKHQV 0.45 ns 0.45 ns 0.5 ns No t Re co m -250 Rev: 1.07 8/2012 1/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 8M x 8 SigmaQuad SRAM—Top View 2 3 4 5 6 7 8 9 10 11 A CQ SA SA R/W NW1 K NC LD SA SA CQ B NC NC NC SA NC K NW0 SA NC Q3 C NC NC NC VSS SA D NC D4 NC VSS VSS E NC NC Q4 VDDQ VSS F NC NC NC VDDQ VDD G NC D5 Q5 VDDQ VDD H DOFF VREF VDDQ VDDQ VDD J NC NC NC VDDQ VDD K NC NC NC VDDQ VDD L NC Q6 D6 VDDQ M NC NC NC N NC D7 NC P NC NC R TDO TCK ct 1 n— Di sco nt inu ed Pr od u NC SA VSS NC NC D3 VSS VSS VSS NC NC NC VSS VSS VDDQ NC D2 Q2 VSS VDD VDDQ NC NC NC VSS VDD VDDQ NC NC NC VSS VDD VDDQ VDDQ VREF ZQ VSS VDD VDDQ NC Q1 D1 VSS VDD VDDQ NC NC NC VSS VSS VSS VDDQ NC NC Q0 VSS VSS VSS VSS VSS NC NC D0 VSS SA SA SA VSS NC NC NC me nd ed for Ne w De sig SA Q7 SA SA C SA SA NC NC NC SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch No t Re co m Note: NW0 controls writes to D0:D3. NW1 controls writes to D4:D7. Rev: 1.07 8/2012 2/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 8M x 9 SigmaQuad SRAM—Top View 2 3 4 5 6 7 8 9 10 11 A CQ SA SA R/W NC K NC LD SA SA CQ B NC NC NC SA NC K BW SA NC Q4 C NC NC NC VSS SA D NC D5 NC VSS VSS E NC NC Q5 VDDQ VSS F NC NC NC VDDQ VDD G NC D6 Q6 VDDQ VDD H Doff VREF VDDQ VDDQ VDD J NC NC NC VDDQ VDD K NC NC NC VDDQ VDD L NC Q7 D7 VDDQ M NC NC NC N NC D8 NC P NC NC R TDO TCK ct 1 n— Di sco nt inu ed Pr od u NC SA VSS NC NC D4 VSS VSS VSS NC NC NC VSS VSS VDDQ NC D3 Q3 VSS VDD VDDQ NC NC NC VSS VDD VDDQ NC NC NC VSS VDD VDDQ VDDQ VREF ZQ VSS VDD VDDQ NC Q2 D2 VSS VDD VDDQ NC NC NC VSS VSS VSS VDDQ NC NC Q1 VSS VSS VSS VSS VSS NC NC D1 VSS SA SA SA VSS NC NC NC me nd ed for Ne w De sig SA Q8 SA SA C SA SA NC D0 Q0 SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch No t Re co m Note: BW controls writes to D0:D7 Rev: 1.07 8/2012 3/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 4M x 18 SigmaQuad SRAM—Top View 2 3 4 5 6 7 8 9 10 11 A CQ VSS/SA (144Mb) SA R/W BW1 K NC LD SA SA CQ B NC Q9 D9 SA NC C NC NC D10 VSS SA D NC D11 Q10 VSS VSS E NC NC Q11 VDDQ VSS F NC Q12 D12 VDDQ VDD G NC D13 Q13 VDDQ VDD H DOFF VREF VDDQ VDDQ VDD J NC NC D14 VDDQ VDD K NC NC Q14 VDDQ L NC Q15 D15 M NC NC N NC D17 P NC NC R TDO TCK n— Di sco nt inu ed Pr od u ct 1 BW0 SA NC NC Q8 SA SA VSS NC Q7 D8 VSS VSS VSS NC NC D7 VSS VSS VDDQ NC D6 Q6 VSS VDD VDDQ NC NC Q5 VSS VDD VDDQ NC NC D5 VSS VDD VDDQ VDDQ VREF ZQ VSS VDD VDDQ NC Q4 D4 VDD VSS VDD VDDQ NC D3 Q3 VDDQ VSS VSS VSS VDDQ NC NC Q2 D16 VSS VSS VSS VSS VSS NC Q1 D2 Q16 VSS SA SA SA VSS NC NC D1 Q17 SA SA C SA SA NC D0 Q0 SA SA SA C SA SA SA TMS TDI me nd ed for Ne w De sig K 11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch No t Re co m Note: BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. Rev: 1.07 8/2012 4/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 2M x 36 SigmaQuad SRAM—Top View 2 3 4 5 6 7 8 9 10 11 A CQ VSS/SA (288Mb) SA R/W BW2 K BW1 LD SA VSS/SA (144Mb) CQ B Q27 Q18 D18 SA BW3 C D27 Q28 D19 VSS SA D D28 D20 Q19 VSS VSS E Q29 D29 Q20 VDDQ VSS F Q30 Q21 D21 VDDQ VDD G D30 D22 Q22 VDDQ VDD H DOFF VREF VDDQ VDDQ VDD J D31 Q31 D23 VDDQ VDD K Q32 D32 Q23 VDDQ L Q33 Q24 D24 M D33 Q34 N D34 D26 P Q35 D35 R TDO TCK n— Di sco nt inu ed Pr od u ct 1 BW0 SA D17 Q17 Q8 SA SA VSS D16 Q7 D8 VSS VSS VSS Q16 D15 D7 VSS VSS VDDQ Q15 D6 Q6 VSS VDD VDDQ D14 Q14 Q5 VSS VDD VDDQ Q13 D13 D5 VSS VDD VDDQ VDDQ VREF ZQ VSS VDD VDDQ D12 Q4 D4 VDD VSS VDD VDDQ Q12 D3 Q3 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 D25 VSS VSS VSS VSS VSS D10 Q1 D2 Q25 VSS SA SA SA VSS Q10 D9 D1 Q26 SA SA C SA SA Q9 D0 Q0 SA SA SA C SA SA SA TMS TDI me nd ed for Ne w De sig K 11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch No t Re co m Notes: 1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 2. BW2 controls writes to D18:D26. BW3 controls writes to D27:D35. Rev: 1.07 8/2012 5/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 Pin Description Table Description Type Comments SA Synchronous Address Inputs Input — NC No Connect — — R/W Read/Write Contol Pin Input Write Active Low; Read Active High NW0–NW1 Synchronous Nybble Writes BW0–BW1 Synchronous Byte Writes BW0–BW3 Synchronous Byte Writes K Input Clock C Output Clock TMS Test Mode Select TDI Test Data Input TCK Test Clock Input TDO Test Data Output VREF HSTL Input Reference Voltage ZQ n— Di sco nt inu ed Pr od u ct Symbol Active Low x08 Version Input Active Low x18 Version Input Active Low x36 Version Input Active High Input Active High Input — Input — Input — Output — Input — Output Impedance Matching Input Input — K Input Clock Input Active Low C Output Clock Output Active Low DOFF DLL Disable — Active Low LD Synchronous Load Pin — Active Low CQ Output Echo Clock Output Active Low Output Echo Clock Output Active High Synchronous Data Inputs Input Synchronous Data Outputs Output Power Supply Supply 1.8 V Nominal Isolated Output Buffer Supply Supply 1.8 or 1.5 V Nominal Power Supply: Ground Supply — me nd ed for Ne w De sig Input CQ Dn Qn VDD VDDQ Re co m VSS No t Notes: 1. C, C, K, or K cannot be set to VREF voltage. 2. NC = Not Connected to die or any other pin Rev: 1.07 8/2012 6/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 Background n— Di sco nt inu ed Pr od u ct Separate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control protocol like that offered on the SigmaCIO devices. Therefore, while SigmaQuad SRAMs allow a user to operate both data ports at the same time, they force alternating loads of read and write addresses. SigmaSIO SRAMs allow continuous loads of read or write addresses like SigmaCIO SRAMs, but in a separate I/O configuration. Like a SigmaQuad SRAM, a SigmaSIO DDR-II SRAM can execute an alternating sequence of reads and writes. However, doing so results in the Data In port and the Data Out port stalling with nothing to do on alternate transfers. A SigmaQuad device would keep both ports running at capacity full time. On the other hand, the SigmaSIO device can accept a continuous stream of read commands and read data or a continuous stream of write commands and write data. The SigmaQuad device, by contrast, restricts the user from loading a continuous stream of read or write addresses. The advantage of the SigmaSIO device is that it allows twice the random address bandwidth for either reads or writes than could be acheived with a SigmaQuad version of the device. SigmaCIO SRAMs offer this same advantage, but do not have the separate Data In and Data Out pins offered on the SigmaSIO SRAMs. Therefore, SigmaSIO devices are useful in psuedo dual port SRAM applications where communication of burst traffic between two electrically independent busses is desired. De sig Each of the three SigmaQuad Family SRAMs—SigmaQuad, SigmaCIO, and SigmaSIO—supports similar address rates because random address rate is determined by the internal performance of the RAM. In addition, all three SigmaQuad Family SRAMs are based on the same internal circuits. Differences between the truth tables of the different devices proceed from differences in how the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application at hand. me nd ed for Ne w Burst of 2 SigmaSIO DDR-II SRAM DDR Read The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A high on the R/W pin begins a read cycle. The two resulting data output transfers begin after the next rising edge of the K clock. Data is clocked out by the next rising edge of the C if it is active. Otherwise, data is clocked out at the next rising edge of K. The next data chunk is clocked out on the rising edge of C, if active. Otherwise, data is clocked out on the rising edge of K. No t Re co m Burst of 2 SigmaSIO DDR-II SRAM DDR Write The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A low on the R/W pin, begins a write cycle. Data is clocked in by the next rising edge of K and then the rising edge of K. Rev: 1.07 8/2012 7/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 Special Functions n— Di sco nt inu ed Pr od u ct Byte Write and Nybble Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18 version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence. Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NWx” may be substituted in all the discussion above. Example x18 RAM Write Sequence using Byte Write Enables Data In Sample Time BW0 BW1 Beat 1 0 1 Beat 2 1 0 Beat 1 D9–D17 Written Unchanged Ne w D0–D8 De sig Resulting Write Operation D0–D8 D9–D17 Data In Don’t Care Don’t Care Data In Beat 2 D0–D8 D9–D17 Unchanged Written No t Re co m me nd ed for Output Register Control SigmaSIO DDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs. Rev: 1.07 8/2012 8/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 Example Four Bank Depth Expansion Schematic R/W3 LD3 LD2 R/W1 LD1 R/W0 LD0 A0–An K Bank 1 A A R/W R/W LD LD K D K D Q Q1–Qn C Bank 3 A A R/W R/W LD LD K D K Q C D Q C No t Re co m Note: For simplicity BWn is not shown. Q Bank 2 me nd ed for C C De sig Bank 0 Ne w D1–Dn n— Di sco nt inu ed Pr od u ct R/W2 Rev: 1.07 8/2012 9/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 Burst of 2 SigmaSIO DDR-II SRAM Depth Expansion Write B Read C Write D Read E Write F Read G Read H Read J NOP K B C D E F LD Bank 1 LD Bank 2 R/W Bank 1 R/W Bank 2 BWx Bank 1 BWx Bank 2 B+1 H J F+1 B D Bank 1 G n— Di sco nt inu ed Pr od u Address ct K F D+1 D D Bank 2 C Bank 1 C Bank 1 De sig Q Bank 1 CQ Bank 1 E+1 H H+1 Ne w CQ Bank 1 E C Bank 2 C Bank 2 me nd ed for Q Bank 2 CQ Bank 2 C+1 G G+1 No t Re co m CQ Bank 2 C Rev: 1.07 8/2012 10/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology J GS8662S08/09/18/36E-250/200/167 FLXDrive-II Output Driver Impedance Control Separate I/O Burst of 2 Sigma SIO-II SRAM Truth Table LD R/W Current Operation K↑ (tn) K↑ (tn) K↑ (tn) K↑ (tn) X 1 X Deselect V 0 1 Read V 0 0 Write D D Q Q K↑ (tn+1) K↑ (tn+1) K↑ (tn+1) K↑ (tn+1) X — Hi-Z — X — Q0 Q1 D0 D1 Hi-Z — De sig A n— Di sco nt inu ed Pr od u ct HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. No t Re co m me nd ed for Ne w Notes: 1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care” 2. “—” indicates that the input requirement or output state is determined by the next operation. 3. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations. 4. D0 and D1 indicate the first and second pieces of input data transferred during Write operations. 5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when preceded by a Read command. 6. CQ is never tristated. 7. Users should not clock in metastable addresses. Rev: 1.07 8/2012 11/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 x18 Byte Write Clock Truth Table BW Current Operation D D K↑ (tn+1) K↑ (tn+2) K↑ (tn) K↑ (tn+1) K↑ (tn+2) T T Write Dx stored if BWn = 0 in both data transfers D1 D2 T F Write Dx stored if BWn = 0 in 1st data transfer only D1 X F T Write Dx stored if BWn = 0 in 2nd data transfer only X D2 F F Write Abort No Dx stored in either data transfer X X n— Di sco nt inu ed Pr od u ct BW x36 Byte Write Enable (BWn) Truth Table BW2 BW1 BW0 D27–D35 D18–D26 D9–D17 D0–D8 1 1 1 1 Don’t Care Don’t Care Don’t Care Don’t Care 0 1 1 1 Don’t Care Don’t Care Don’t Care Data In 1 0 1 1 Don’t Care Don’t Care Data In Don’t Care 0 0 1 1 Don’t Care Don’t Care Data In Data In 1 1 0 1 Don’t Care Data In Don’t Care Don’t Care 0 1 0 1 Don’t Care Data In Don’t Care Data In 1 0 0 1 Don’t Care Data In Data In Don’t Care 0 0 0 1 Don’t Care Data In Data In Data In 1 1 0 1 1 0 0 0 1 1 0 1 1 0 Re co m me nd ed for Ne w BW3 De sig Notes: 1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”. 2. If one or more BWn = 0, then BW = “T”, else BW = “F”. 0 Data In Don’t Care Don’t Care Don’t Care 1 0 Data In Don’t Care Don’t Care Data In 1 0 Data In Don’t Care Data In Don’t Care 1 0 Data In Don’t Care Data In Data In 0 0 Data In Data In Don’t Care Don’t Care 0 0 Data In Data In Don’t Care Data In 0 0 0 Data In Data In Data In Don’t Care 0 0 0 Data In Data In Data In Data In No t 1 Rev: 1.07 8/2012 12/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 x8 Nybble Write Enable (NWn) Truth Table NW0 D9–D17 D0–D8 1 1 Don’t Care Don’t Care 0 1 Don’t Care Data In 1 0 Data In 0 0 Data In ct NW1 n— Di sco nt inu ed Pr od u Don’t Care No t Re co m me nd ed for Ne w De sig Data In Rev: 1.07 8/2012 13/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 Absolute Maximum Ratings (All voltages reference to VSS) Description Value Unit VDD Voltage on VDD Pins –0.5 to 2.9 V VDDQ Voltage in VDDQ Pins –0.5 to VDD VREF Voltage in VREF Pins VI/O Voltage on I/O Pins VIN Voltage on Other Input Pins IIN Input Current on Any Pin IOUT Output Current on Any I/O Pin TJ Maximum Junction Temperature TSTG Storage Temperature n— Di sco nt inu ed Pr od u ct Symbol V –0.5 to VDDQ V –0.5 to VDDQ +0.3 (≤ 2.9 V max.) V –0.5 to VDDQ +0.3 (≤ 2.9 V max.) V +/–100 mA dc +/–100 mA dc o 125 C oC –55 to 125 Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component. De sig Recommended Operating Conditions Power Supplies Supply Voltage Min. Typ. Max. Unit VDD 1.7 1.8 1.9 V VDDQ 1.4 — 1.9 V 0.68 — 0.95 V me nd ed for I/O Supply Voltage Reference Voltage Symbol Ne w Parameter VREF Note: The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power down sequence must be the reverse. VDDQ must not exceed VDD. For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up. Re co m Operating Temperature Symbol Min. Typ. Max. Unit Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C No t Parameter Rev: 1.07 8/2012 14/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 Thermal Impedance Test PCB Substrate θ JA (C°/W) Airflow = 0 m/s θ JA (C°/W) Airflow = 1 m/s θ JA (C°/W) Airflow = 2 m/s θ JB (C°/W) θ JC (C°/W) 165 BGA 4-layer 16.3 13.4 12.4 6.2 1.5 ct Package HSTL I/O DC Input Characteristics Parameter Symbol DC Input Logic High VIH (dc) DC Input Logic Low VIL (dc) Note: Compatible with both 1.8 V and 1.5 V I/O drivers Min Max Units Notes VREF + 0.1 VDDQ + 0.3 mV 1 –0.3 VREF – 0.1 mV 1 De sig HSTL I/O AC Input Characteristics n— Di sco nt inu ed Pr od u Notes: 1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number. 2. Please refer to JEDEC standard JESD51-6. 3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to the PCB can result in cooling or heating of the RAM depending on PCB temperature. Symbol Min Max Units Notes AC Input Logic High VIH (ac) VREF + 0.2 — mV 3,4 AC Input Logic Low VIL (ac) — VREF – 0.2 mV 3,4 VREF (ac) — 5% VREF (DC) mV 1 Ne w Parameter VREF Peak to Peak AC Voltage me nd ed for Notes: 1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other. 3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers. 4. See AC Input Definition drawing below. Re co m HSTL I/O AC Input Definitions VREF VIL (ac) No t VIH (ac) Rev: 1.07 8/2012 15/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKHKH VDD + 1.0 V VSS n— Di sco nt inu ed Pr od u 50% ct 50% VDD VSS – 1.0 V 20% tKHKH VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 3.3 V) Parameter Symbol Input Capacitance CIN Output Capacitance COUT Note: This parameter is sample tested. Parameter Max. input slew rate Unit VIN = 0 V 4 5 pF VOUT = 0 V 6 7 pF Conditions VDDQ 0V 2 V/ns VDDQ/2 me nd ed for Input reference level Max. Ne w Input high level Input low level Typ. De sig AC Test Conditions Test conditions VDDQ/2 Output reference level Note: Test conditions as specified with output loading as shown unless otherwise noted. Re co m AC Test Load Diagram No t DQ Rev: 1.07 8/2012 50Ω RQ = 250 Ω (HSTL I/O) VREF = 0.75 V VT = VDDQ/2 16/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 Input and Output Leakage Characteristics Symbol Test Conditions Min. Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA Doff IINDOFF VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL –100 uA –2 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDDQ –2 uA n— Di sco nt inu ed Pr od u ct Parameter Notes 2 uA 2 uA 2 uA Programmable Impedance HSTL Output Driver DC Electrical Characteristics Parameter Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Symbol Min. Max. Units Notes VOH1 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V 1, 3 VOL1 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V 2, 3 VOH2 VDDQ – 0.2 VDDQ V 4, 5 VOL2 Vss 0.2 V 4, 6 No t Re co m me nd ed for Ne w De sig Notes: 1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω). 2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω). 3. Parameter tested with RQ = 250Ω and VDDQ = 1.5 V or 1.8 V 4. 0Ω ≤ RQ ≤ ∞Ω 5. IOH = –1.0 mA 6. IOL = 1.0 mA Rev: 1.07 8/2012 17/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 Operating Currents Parameter Symbol Test Conditions Operating Current (x36): DDR IDD Operating Current (x18): DDR -167 Notes –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min 750 mA 775 mA 650 mA 675 mA 550 mA 575 mA 2, 3 IDD VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min 700 mA 725 mA 600 mA 625 mA 525 mA 550 mA 2, 3 Operating Current (x9): DDR IDD VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min 700 mA 725 mA 575 mA 600 mA 525 mA 550 mA 2, 3 Operating Current (x8): DDR IDD VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min 700 mA 725 mA 575 mA 600 mA 525 mA 550 mA 2, 3 Standby Current (NOP): DDR ISB1 270 mA 280 mA 255 mA 265 mA 245 mA 255 mA 2, 4 n— Di sco nt inu ed Pr od u 0 to 70°C Device deselected, IOUT = 0 mA, f = Max, All Inputs ≤ 0.2 V or ≥ VDD – 0.2 V Notes: De sig Power measured with output pins floating. Minimum cycle, IOUT = 0 mA Operating current is calculated with 50% read cycles and 50% write cycles. Standby Current is only after all pending read and write burst operations are completed. No t Re co m me nd ed for Ne w 1. 2. 3. 4. -200 ct -250 Rev: 1.07 8/2012 18/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 -250 Symbol -200 -167 Min Max Min Max 8.4 5.0 8.4 0.2 — — Clock tKHKH tCHCH 4.0 tTKC Variable tKCVar — K, K Clock High Pulse Width C, C Clock High Pulse Width tKHKL tCHCL 1.6 K, K Clock Low Pulse Width C, C Clock Low Pulse Width tKLKH tCLCH 1.6 K to K High C to C High tKHKH tCHCH 1.8 K to K High C to C High tKHKH tCHCH 1.8 K, K Clock High to C, C Clock High tKHCH 0 DLL Lock Time tKCLock K Static to DLL reset Max Units 8.4 ns 0.2 — 0.2 ns 2.0 — 2.4 — ns — 2.0 — 2.4 — ns — 2.2 — 2.7 — ns — 2.2 — 2.7 — ns 1.8 0 2.3 0 2.8 ns 1024 — 1024 — 1024 — cycle tKCReset 30 — 30 — 30 — ns K, K Clock High to Data Output Valid C, C Clock High to Data Output Valid tKHQV tCHQV — 0.45 — 0.45 — 0.5 ns 3 K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold tKHQX tCHQX –0.45 — –0.45 — –0.5 — ns 3 K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid tKHCQV tCHCQV — 0.45 — 0.45 — 0.5 ns tKHCQX tCHCQX –0.45 — –0.45 — –0.5 — ns tCQHQV — 0.30 — 0.35 — 0.40 ns 7 tCQHQX –0.30 — –0.35 — –0.40 — ns 7 tCQHCQH tCQHCQH 1.55 — 1.95 — 2.45 — ns tKHQZ tCHQZ — 0.45 — 0.45 — 0.5 ns 3 tKHQX1 tCHQX1 –0.45 — –0.45 — –0.5 — ns 3 Address Input Setup Time tAVKH 0.5 — 0.6 — 0.7 — ns Control Input Setup Time tIVKH 0.5 — 0.6 — 0.7 — ns Data Input Setup Time tDVKH 0.35 — 0.4 — 0.5 — ns CQ, CQ High Output Valid CQ, CQ High Output Hold CQ Phase Distortion Re co m K Clock High to Data Output High-Z C Clock High to Data Output High-Z me nd ed for K, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold Ne w Output Times K Clock High to Data Output Low-Z C Clock High to Data Output Low-Z No t Setup Times Rev: 1.07 8/2012 n— Di sco nt inu ed Pr od u 6.0 De sig K, K Clock Cycle Time C, C Clock Cycle Time Min ct Parameter Notes AC Electrical Characteristics 19/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 5 6 2 © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 Parameter -250 Symbol -200 -167 Min Max Min Max Min Max Units Notes AC Electrical Characteristics (Continued) Hold Times tKHAX 0.5 — 0.6 — 0.7 — ns Control Input Hold Time tKHIX 0.5 — 0.6 — 0.7 — ns Data Input Hold Time tKHDX 0.35 — 0.4 — 0.5 — ns n— Di sco nt inu ed Pr od u ct Address Input Hold Time No t Re co m me nd ed for Ne w De sig Notes: 1. All Address inputs must meet the specified setup and hold times for all latching clock edges. 2. Control signals are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36). 3. If C, C are tied high, K, K become the references for C, C timing parameters 4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and temperatures. 5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 6. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. 7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands and test setup variations. Rev: 1.07 8/2012 20/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 K Controlled Read-First Timing Diagram Read A Write B Read C Read E Deselect Deselect KHKL KHKH KLKH K ct KH#KH AVKH KHAX A Address B C IVKH KHIX IVKH KHIX LD R/W n— Di sco nt inu ed Pr od u K D E IVKH KHIX B BWx B+1 DVKH KHDX B D A Q CQ CQHQV KHQV C C+1 KHQX D D+1 CQHQX No t Re co m me nd ed for CQ A+1 Ne w KHCQV KHCQX KHQZ De sig KHQX1 B+1 Rev: 1.07 8/2012 21/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 K Controlled Write-First Timing Diagram NOP Write A Read B Read C Write D Write E Deselect KHKL KHKH KLKH K ct KH#KH AVKH KHAX A Address IVKH B C KHIX LD IVKH n— Di sco nt inu ed Pr od u K KHIX R/W D E KHIX IVKH A BWx A+1 D D+1 E E+1 D D+1 E E+1 KHDX DVKH A A+1 De sig D Q KHCQX Ne w KHCQV B B+1 KHCQX KHCQV KHQV KHQX C KHQZ C+1 CQHQX CQHQV me nd ed for CQ KHQX1 No t Re co m CQ Rev: 1.07 8/2012 22/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 C Controlled Read-First Timing Diagram Read A Write B Read C Read D Deselect Deselect KHKL KHKH KLKH K AVKH KHAX A Address B C n— Di sco nt inu ed Pr od u ct KHKH# K D IVKH KHIX LD IVKH KHIX R/W KHIX IVKH B BWx B+1 KHDX DVKH CLCH KHCH CHCL CHCH Ne w C B+1 De sig B D CHCH# C me nd ed for CHQX1 Q CQ A CHQZ A+1 CHQV C CHQX C+1 D D+1 CHCQX CHCQV CQHCV CQHQX No t Re co m CQ Rev: 1.07 8/2012 23/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 C Controlled Write-First Timing Diagram NOP Write A Read B Write C Write D Read E Deselect KHKL KHKH KLKH K ct KH#KH KHAX AVKH A Addr IVKH B C KHIX LD IVKH n— Di sco nt inu ed Pr od u K KHIX R/W D E KHIX IVKH A BWx A+1 C C+1 D D+1 C C+1 D D+1 KHDX DVKH A D A+1 C KLKH Q CQ CQ JTAG Port Operation me nd ed for Ne w C De sig KHKL KHKH KH#KH CHQX1 CHQZ CHQX CHQV B B+1 CQHQV CQHQX Re co m Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. No t Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. Rev: 1.07 8/2012 24/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 JTAG Pin Descriptions Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. n— Di sco nt inu ed Pr od u ct Pin TDI Test Data In In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDO Test Data Out Out Output that is active depending on the state of the TAP state machine. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. JTAG Port Registers De sig Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. me nd ed for Ne w Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. No t Re co m Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.07 8/2012 25/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 · · · · · · · n— Di sco nt inu ed Pr od u · ct JTAG TAP Block Diagram Boundary Scan Register · · 1 · 2 1 0 0 108 0 Bypass Register Instruction Register TDI TDO ID Code Register · · ·· 2 1 0 De sig 31 30 29 Control Signals TMS Test Access Port (TAP) Controller Ne w TCK GSI Technology JEDEC Vendor ID Code Not Used 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 1 X No t Bit # Re co m ID Register Contents Presence Register me nd ed for Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Rev: 1.07 8/2012 X X X X X X X X X X X X X X X X X X 0 26/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 0 0 1 1 0 1 1 0 0 1 © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 Tap Controller Instruction Set n— Di sco nt inu ed Pr od u ct Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. JTAG Tap Controller State Diagram Test Logic Reset 1 0 0 Run Test Idle 1 Select DR 1 Select IR 0 0 1 De sig Shift DR Ne w 1 me nd ed for 1 0 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR 1 Update DR 1 Capture IR 0 0 Pause IR 1 Exit2 IR 0 1 0 0 Update IR 1 0 No t Re co m 1 Capture DR 0 1 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Rev: 1.07 8/2012 27/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 n— Di sco nt inu ed Pr od u ct SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. De sig Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. Ne w IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. me nd ed for SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Re co m JTAG TAP Instruction Set Summary Instruction Code EXTEST SAMPLE-Z RFU Rev: 1.07 8/2012 Notes 000 Places the Boundary Scan Register between TDI and TDO. 1 001 Preloads ID Register and places it between TDI and TDO. 1, 2 No t IDCODE Description 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z except CQ. 1 011 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 28/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 JTAG TAP Instruction Set Summary 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 GSI private instruction. 1 RFU 110 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 BYPASS 111 Places Bypass Register between TDI and TDO. n— Di sco nt inu ed Pr od u ct SAMPLE/ PRELOAD 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Test Port Input Low Voltage Test Port Input High Voltage TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output CMOS Low Ne w Test Port Output Low Voltage Test Port Output CMOS High Min. Max. Unit Notes VILJ –0.3 0.3 * VDD V 1 VIHJ 0.6 * VDD VDD +0.3 V 1 IINHJ –300 1 uA 2 IINLJ –1 100 uA 3 IOLJ –1 1 uA 4 VOHJ VDD – 200 mV — V 5, 6 VOLJ — 0.4 V 5, 7 VOHJC VDD – 100 mV — V 5, 8 VOLJC — 100 mV V 5, 9 De sig TMS, TCK and TDI Input Leakage Current Symbol No t Re co m me nd ed for Notes: 1. Input Under/overshoot voltage must be –1 V < Vi < VDDn +1 V not to exceed V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ ≤ VIN ≤ VDDn 3. 0 V ≤ VIN ≤ VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDD supply. 6. IOHJ = –2 mA 7. IOLJ = + 2 mA 8. IOHJC = –100 uA 9. IOLJC = +100 uA Rev: 1.07 8/2012 29/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 JTAG Port AC Test Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDDQ/2 Output reference level VDDQ/2 JTAG Port AC Test Load DQ ct Conditions n— Di sco nt inu ed Pr od u Parameter 50Ω 30pF* VDDQ/2 * Distributed Test Jig Capacitance Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. JTAG Port Timing Diagram tTKC tTKH TCK TDI De sig tTH tTS tTKL tTH TMS tTKQ me nd ed for TDO Ne w tTS tTH tTS Parallel SRAM input Parameter Re co m JTAG Port AC Electrical Characteristics Symbol Min Max Unit tTKC 50 — ns TCK Low to TDO Valid tTKQ — 20 ns TCK High Pulse Width tTKH 20 — ns TCK Low Pulse Width tTKL 20 — ns TDI & TMS Set Up Time tTS 10 — ns TDI & TMS Hold Time tTH 10 — ns No t TCK Cycle Time Rev: 1.07 8/2012 30/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 JTAG Port AC Electrical Characteristics Symbol Max TCK Cycle Time tCHCH 50 — ns TCK High Pulse Width tCHCL 20 — ns TCK Low Pulse Width tCLCH 20 — ns TMS Input Setup Time tMVCH 5 — ns TMS Input Hold Time tCHMX 5 — ns TDI Input Setup Time tDVCH 5 — ns TDI Input Hold Time tCHDX 5 — ns SRAM Input Setup Time tSVCH 5 — ns SRAM Input Hold Time tCHSX 5 — ns Clock Low to Output Valid tCLQV 0 10 ns Unit No t Re co m me nd ed for Ne w De sig n— Di sco nt inu ed Pr od u Min. ct Parameter Rev: 1.07 8/2012 31/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 Package Dimensions—165-Bump FPBGA (Package E) A1 CORNER TOP VIEW BOTTOM VIEW Ø0.10 M C Ø0.25 M C A B Ø0.40~0.60 (165x) ct 1 2 3 4 5 6 7 8 9 10 11 A1 CORNER 1.0 14.0 Ne w 10.0 15±0.05 0.20(4x) No t Re co m C 1.0 0.36~0.46 1.50 MAX. SEATING PLANE B 1.0 A B C D E F G H J K L M N P R me nd ed for 0.20 C A De sig 17±0.05 1.0 A B C D E F G H J K L M N P R n— Di sco nt inu ed Pr od u 11 10 9 8 7 6 5 4 3 2 1 Rev: 1.07 8/2012 32/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 Part Number1 Type Package Speed (MHz) TA2 2M x 36 GS8662S36E-250 SigmaSIO DDR-II SRAM 165-bump BGA 250 C 2M x 36 GS8662S36E-200 SigmaSIO DDR-II SRAM 165-bump BGA 200 C 2M x 36 GS8662S36E-167 SigmaSIO DDR-II SRAM 165-bump BGA 167 C 2M x 36 GS8662S36E-250I SigmaSIO DDR-II SRAM 165-bump BGA 250 I 2M x 36 GS8662S36E-200I SigmaSIO DDR-II SRAM 165-bump BGA 200 I 2M x 36 GS8662S36E-167I SigmaSIO DDR-II SRAM 165-bump BGA 167 I 4M x 18 GS8662S18E-250 SigmaSIO DDR-II SRAM 165-bump BGA 250 C 4M x 18 GS8662S18E-200 SigmaSIO DDR-II SRAM 165-bump BGA 200 C 4M x 18 GS8662S18E-167 SigmaSIO DDR-II SRAM 165-bump BGA 167 C 4M x 18 GS8662S18E-250I SigmaSIO DDR-II SRAM 165-bump BGA 250 I 4M x 18 GS8662S18E-200I SigmaSIO DDR-II SRAM 165-bump BGA 200 I 4M x 18 GS8662S18E-167I SigmaSIO DDR-II SRAM 165-bump BGA 167 I 8M x 9 GS8662S09E-250 SigmaSIO DDR-II SRAM 165-bump BGA 250 C 8M x 9 GS8662S09E-200 SigmaSIO DDR-II SRAM 165-bump BGA 200 C 8M x 9 GS8662S09E-167 SigmaSIO DDR-II SRAM 165-bump BGA 167 C 8M x 9 GS8662S09E-250I SigmaSIO DDR-II SRAM 165-bump BGA 250 I 8M x 9 GS8662S09E-200I SigmaSIO DDR-II SRAM 165-bump BGA 200 I 8M x 9 GS8662S09E-167I SigmaSIO DDR-II SRAM 165-bump BGA 167 I 8M x 8 GS8662S08E-250 SigmaSIO DDR-II SRAM 165-bump BGA 250 C 8M x 8 GS8662S08E-200 SigmaSIO DDR-II SRAM 165-bump BGA 200 C 8M x 8 GS8662S08E-167 SigmaSIO DDR-II SRAM 165-bump BGA 167 C 8M x 8 GS8662S08E-250I SigmaSIO DDR-II SRAM 165-bump BGA 250 I 8M x 8 GS8662S08E-200I SigmaSIO DDR-II SRAM 165-bump BGA 200 I 8M x 8 GS8662S08E-167I SigmaSIO DDR-II SRAM 165-bump BGA 167 I 2M x 36 GS8662S36GE-250 SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 250 C 2M x 36 GS8662S36GE-200 SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 200 C 2M x 36 GS8662S36GE-167 SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 167 C 2M x 36 GS8662S36GE-250I SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 250 I GS8662S36GE-200I SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 200 I GS8662S36GE-167I SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 167 I GS8662S18GE-250 SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 250 C 2M x 36 n— Di sco nt inu ed Pr od u De sig Ne w me nd ed for No t 2M x 36 4M x 18 ct Org Re co m Ordering Information—GSI SigmaSIO DDR-II SRAM Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8662S36E-200T. 2. C = Commercial Temperature Range. I = Industrial Temperature Range. Rev: 1.07 8/2012 33/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 Ordering Information—GSI SigmaSIO DDR-II SRAM Part Number1 Type Package Speed (MHz) TA2 4M x 18 GS8662S18GE-200 SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 200 C 4M x 18 GS8662S18GE-167 SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 167 C 4M x 18 GS8662S18GE-250I SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 250 I 4M x 18 GS8662S18GE-200I SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 200 I 4M x 18 GS8662S18GE-167I SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 167 I 8M x 9 GS8662S09GE-250 SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 250 C 8M x 9 GS8662S09GE-200 SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 200 C 8M x 9 GS8662S09GE-167 SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 167 C 8M x 9 GS8662S09GE-250I SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 250 I 8M x 9 GS8662S09GE-200I SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 200 I 8M x 9 GS8662S09GE-167I SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 167 I 8M x 8 GS8662S08GE-250 SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 250 C 8M x 8 GS8662S08GE-200 SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 200 C 8M x 8 GS8662S08GE-167 SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 167 C 8M x 8 GS8662S08GE-250I SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 250 I 8M x 8 GS8662S08GE-200I SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 200 I 8M x 8 GS8662S08GE-167I SigmaSIO DDR-II SRAM RoHS-compliant 165-bump BGA 167 I De sig n— Di sco nt inu ed Pr od u ct Org No t Re co m me nd ed for Ne w Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8662S36E-200T. 2. C = Commercial Temperature Range. I = Industrial Temperature Range. Rev: 1.07 8/2012 34/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology GS8662S08/09/18/36E-250/200/167 SigmaSIO DDR-II Revision History File Name Format/Content Description of changes Content 8662Sxx_r1_01; 8662Sxx_r1_02 Content 8662Sxx_r1_02; 8662Sxx_r1_03 Content 8662Sxx_r1_03; 8662Sxx_r1_04 Content 8662Sxx_r1_04; 8662Sxx_r1_05 Content Content 8662Sxx_r1_06; 8662Sxx_r1_07 Content Updated MAX tKHKH • Updated tKHKH, tKHCH in AC Char table • Added tKHKH and CQ Phase Distortion to AC Char table • Added CZ data • Updated I/O supply voltage data • Updated power-up sequence information • (Rev1.04a: Pin P11 on x9 changed from NC to Q0 (typo)) • Changed status to PQ • Added VREF note to Pin Description table • Updated FLXDrive-II Output Driver Impedance Control section • Removed Preliminary banner due to production status • (Rev1.06a: Editorial updates) • Removed 333 & 300 MHz bins No t Re co m me nd ed for Ne w De sig 8662Sxx_r1_05; 8662Sxx_r1_06 Added RoHS-compliant package information n— Di sco nt inu ed Pr od u 8662Sxx_r1; 8662Sxx_r1_01 ct Creation of datasheet 8662Sxx_r1 Rev: 1.07 8/2012 35/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology