Circuit - Davicom Semiconductor Inc.

5
4
3
2
1
D
D
DM5886
C
~ 4 Channel 960H Video Decoder
~ Integrate multichannel decoders
with functional mixer
C
B
B
A
A
DAVICOM Semiconductor,Inc.
Title
DM5886_REF
5
4
3
Size
A4
DM5886
Date:
Monday, November 24, 2014
2
Document Number
Rev
2.0
1
Sheet
1
of
3
3
VDD_3V3
VDD_1V8
VDD_1V8VD
20
19
12
27
4
78
60
41
94
110
128
5
2
VDD_1V8A
C6
C7
C8
4
J2
2
4
3
2
1
R1
C2
39
13
INA0
R2
A_G
0.1uF
34
28
11
1
120
53
68
84
102
J1
RCA JACK_0
1
SADD1/DQ0
SADD0/DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
39
VDD_1V8VD
3
L2
5
4
+ C10
C11
C12
C13
C14
J3
RCA JACK_0
1
A_G
R3
47uF/16V 0.1uF 0.1uF 0.1uF 0.1uF
17
0.1uF
39
3
VDD_1V8PLL
A_G
4
BEAD
C17
C18
J4
RCA JACK_0
1
J5
47uF/16V 0.1uF 0.1uF
4
3
2
1
A_G
R5
C15
39
14
INB0
3
5
A_G
4
J6
RCA JACK_0
1
A_G
R7
C21
18
C22
0.1uF
39
3
A_G
4
J7
RCA JACK_0
1
A_G
R9
J8
21
1
INA2
R10
A_G
2
3
2
oCCIRD_0[7]
oCCIRD_0[6]
oCCIRD_0[5]
oCCIRD_0[4]
oCCIRD_0[3]
oCCIRD_0[2]
oCCIRD_0[1]
oCCIRD_0[0]
OPIXCLK
C23
39
A_G
4
INB1
R8
A_G
2
+ C20
47uF/16V 0.1uF 0.1uF
oCCIRD_1[7]
oCCIRD_1[6]
oCCIRD_1[5]
oCCIRD_1[4]
oCCIRD_1[3]
oCCIRD_1[2]
oCCIRD_1[1]
oCCIRD_1[0]
OPIXCLK_1
C19
39
S-VIDEO
BEAD
0.1uF
39
VDD_3V3
3
3V3
5
4
J9
RCA JACK_0
1
A_G
R11
BEAD
+ C25
25
C26
C27
C28
C29
0.1uF
39
3
J10
RCA JACK_0
1
J11
A_G
R13
C31
39
22
INB2
R14
A_G
2
4
0.1uF
3
39
VD0_7
VD0_6
VD0_5
VD0_4
VD0_3
VD0_2
VD0_1
VD0_0
Note:
~ HD Mode : VD0[7:0] & VD1[7:0] & VD0_CLK走線盡量等長
~ SD Mode :1. VD0[7:0] & VD0_CLK走線盡量等長
VD1_CLK
VD0[7:0]
2. VD1[7:0] & VD1_CLK走線盡量等長
VD0_CLK
DM5886
ACLKR
ASYNR
ADATR
ADATM
ACLKP/CCIRIN[7]
ASYNP/CCIRIN[6]
ADATP/CCIRIN[5]
IRQ/CCIRIN[4]/ALINKI
CCIRIN[3]/ALINKO
111
112
113
114
116
117
118
119
122
ACLKR
ASYNR
ADATR
ADATM
ACLKP
ASYNP
ADATP
C
U2
ALINKI
ALINKO
SDRAM_A[0]
SDRAM_A[1]
SDRAM_A[2]
SDRAM_A[3]
SDRAM_A[4]
SDRAM_A[5]
SDRAM_A[6]
SDARM_A[7]
SDRAM_A[8]
SDRAM_A[9]
SDRAM_A[10]
SDRAM_A[11]
SDRAM_BA[0]
SDRAM_BA[1]
SDRAM_RAS
SDRAM_CAS
SDRAM_WE
SDRAM_CLK
1
3
2
5
4
J12
RCA JACK_0
1
A_G
R15
X1
C33
39
26
S-VIDEO
2
L6
98
99
100
101
103
104
105
106
108
VD1[7:0]
R12
A_G
47uF/16V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
4
VD1_7
VD1_6
VD1_5
VD1_4
VD1_3
VD1_2
VD1_1
VD1_0
INA3
C30
A_G
C
85
86
87
88
90
91
92
93
95
C24
39
S-VIDEO
2
L5
D
0.1uF
39
VDD_1V8A
L4
SDRAM_DQ0
SDRAM_DQ1
SDRAM_DQ2
SDRAM_DQ3
SDRAM_DQ4
SDRAM_DQ5
SDRAM_DQ6
SDRAM_DQ7
SDRAM_DQ8
SDRAM_DQ9
SDRAM_DQ10
SDRAM_DQ11
SDRAM_DQ12
SDRAM_DQ13
SDRAM_DQ14
SDRAM_DQ15
R6
A_G
2
+ C16
INA1
R4
A_G
A_G
L3
C9
39
S-VIDEO
2
BEAD
38
39
40
45
46
47
48
49
56
57
58
59
61
62
63
64
BEAD
R16
R17
A_G
75
C35 2.2uF
A_G
A_G
J13
A_G
1
2
3
PHONEJACK
C36
10pF
X1
27MHZ
1M
0.1uF
A_G
C32
82
INB3
3
C5
2.2uF
XO
C34
83
10pF
1
C4
AVDD_2
AVDD_1
C3
VDDA
VDDA
+ C1
47uF/16V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
VDDV
VDDV
VDDV
VDDV
BEAD
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
3
L1
D
1
VDD_1V8PLL
VDD_1V8
VDDO
VDDO
VDDO
VDDO
VDDO
1V8
3V3
5
6
R22
AINN
R19R20
AIN1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
R18
R21
RP1
22R
RP3
22R
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
23
24
25
26
29
30
31
32
33
34
22
35
20
21
18
17
16
38
22R
22R
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
BA0
BA1
RAS
CAS
WE
CLK
1.2K1.2K
SI2CLK
SI2CD
4.7K
J14
1 A_G
2
3
PHONEJACK
A_G
R23
J15
A_G
R24
C37
2.2uF
7
AIN2
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
A[11]
SDR_CLK
WE
CAS
RAS
BA0
BA1
4.7K
1 A_G
2
3
PHONEJACK
B
C38
2.2uF
8
AIN3
4.7K
A_G
A_G
J16
1
2
3
PHONEJACK
C39
2.2uF
9
C40
2.2uF
10
R27
4.7K
R25
AIN4
43
42
66
67
79
80
69
70
71
72
74
75
54
76
77
50
51
52
109
96
SCL
SDA
39
15
19
6
12
46
52
SDRAM_A[0]
SDRAM_A[1]
SDRAM_A[2]
SDRAM_A[3]
SDRAM_A[4]
SDRAM_A[5]
SDRAM_A[6]
SDARM_A[7]
SDRAM_A[8]
SDRAM_A[9]
SDRAM_A[10]
SDRAM_A[11]
SDRAM_CLK
SDRAM_WE
SDRAM_CAS
SDRAM_RAS
SDRAM_BA[0]
SDRAM_BA[1]
1 A_G
2
3
PHONEJACK
A_G
R26
C41
A_G
NC/RFU
VSS
VSS
VSS
VDD
VDD
VDD
VDDq
VDDq
VDDq
VDDq
CKE
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
RP2
22R
RP4
22R
SDRAM_DQ0
SDRAM_DQ1
SDRAM_DQ2
SDRAM_DQ3
SDRAM_DQ4
SDRAM_DQ5
SDRAM_DQ6
SDRAM_DQ7
SDRAM_DQ8
SDRAM_DQ9
SDRAM_DQ10
SDRAM_DQ11
SDRAM_DQ12
SDRAM_DQ13
SDRAM_DQ14
SDRAM_DQ15
40
28
41
54
1
14
27
3
9
43
49
37
EM639165(8M x 16 bit)
3V3
8M x 16bitSDRAM INTERFACE
B
Put the SDRAM as tight as possible to DM5886
4.7K
J17
UDQM
LDQM
CS
VSSq
VSSq
VSSq
VSSq
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
Device ID Table
AIN5
MPP4/CCIRIN[2]
MPP3//CCIRIN[1]
MPP2/IPIXCLK
MPP1/CCIRIN[0]
124
125
126
127
C0
SDRAM_DQ1 L
SDRAM_DQ0 L
3V3
C2 C4 C6
L
H
H
H
H
L
3V3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TEST_EN
121
RESET
R28
R29
37
NC/4.7K
55
36
44
65
73
81
89
97
107
115
123
VSSA
VSSA
HRSTZ
4
3
AGND
VSSV
VSSV
VSSV
24
23
16
15
35
30
8.2nF
AOUT
NC
NC
NC
NC
C42
2
10uF/6.3V
RCA JACK
2
33
32
31
29
A_G
AVSS_2
AVSS_1
4.7K
J18
1
SDRAM_DQ1
A_G
NC/4.7K
SDRAM_DQ0
R30
R31
4.7K
4.7K
A_G
A_G
A_G
VDD_1V8PLL
~ DM5885 PLL power supply co-lay
~ Please set value 0x0c at Reg 0x6A when using DM5885
A
A
DAVICOM Semiconductor,Inc.
Title
DM5886_REF
5
4
3
2
Size
A2
MAIN CHIP
Document Number
Date:
Monday, November 24, 2014
Rev
2.0
1
Sheet
2
of
3
5
VER
D
4
DATE
ENGINEER
3
2
1
NOTE
1.0
03/25/2013 CONNOR HONG
NEW CIRCUIT DM5886
2.0
08/30/2013 CONNOR HONG
Add DM5885 PLL power supply circuit
2.1
11/24/2014 CONNOR HONG
Modify Device ID trapping table: L/NC->L
D
C
C
B
B
A
A
DAVICOM Semiconductor,Inc.
Title
DM5886_REF
5
4
3
Size
A4
HISTORY
Date:
Monday, November 24, 2014
2
Document Number
Rev
2.0
3
Sheet
1
of
3