DM5885 - Davicom Semiconductor Inc.

DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
DAVICOM Semiconductor, Inc.
DM5885
720H Decoder Mix 4 NTSC/PAL Channels
to One SD or HD Signal
DATA SHEET
Final
Version: DM5885-DS-F01
August 19, 2015
Final
Doc No: DM5885-DS-F01
August 19, 2015
1
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
REVISION HISTORY:
Date
Revision
Description
2012/02/02
1.1
Initial release
2012/02/04
1.2
Terminal assignment modified (pin28 ~ pin32)
Application schematics modified
Final
Doc No: DM5885-DS-F01
August 19, 2015
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Table of Contents
INTRODUCTION .....................................................................................................................6
FEATURES ....................................................................................................................................... 7
APPLICATIONS ................................................................................................................................. 8
TERMINAL ASSIGNMENT ........................................................................................................9
TERMINAL FUNCTIONS.................................................................................................................... 10
BLOCK DIAGRAM ................................................................................................................. 21
VIDEO DECODER .................................................................................................................. 22
VIDEO INTERFACE .......................................................................................................................... 22
Multi-channel Time Division Multiplexing ............................................................................ 23
4-CH VIDEO DECODER ................................................................................................................... 25
VIDEO DECODER UNIT .................................................................................................................... 26
Video Synchronization .......................................................................................................... 26
Automatic Gain Control ........................................................................................................ 26
Y/C Separation ...................................................................................................................... 27
UV demodulation .................................................................................................................. 27
Luma/Chroma Processor ...................................................................................................... 27
Video Interface ..................................................................................................................... 27
Fast Switch Parameter RAM ................................................................................................. 27
FILTER RESPONSE ........................................................................................................................... 28
Anti-alias LPF ......................................................................................................................... 28
Decimation filter ................................................................................................................... 28
Luma notch filter .................................................................................................................. 29
Chroma band pass filter........................................................................................................ 29
Y sharpness filter .................................................................................................................. 30
UV demodulation low pass filter .......................................................................................... 31
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
AUDIO CODEC ...................................................................................................................... 32
DIGITAL AUDIO FORMAT ................................................................................................................. 34
EXTENDED DIGITAL AUDIO FORMAT ................................................................................................. 35
PLL ...................................................................................................................................... 36
HOST INTERFACE.................................................................................................................. 37
VIDEO MIXER ....................................................................................................................... 38
OUTPUT FORMAT .......................................................................................................................... 39
VIDEO MIXER BLOCK ...................................................................................................................... 40
Video Source ......................................................................................................................... 40
Channel Switch Block ............................................................................................................ 40
Capture interface .................................................................................................................. 41
Mixer Core ............................................................................................................................ 46
Mix-Out Interface ................................................................................................................. 46
Chip-Level Output Unit ......................................................................................................... 51
INTERNAL CONTROL REGISTERS............................................................................................ 52
SYSTEM CONTROL.......................................................................................................................... 52
VIDEO ADC .................................................................................................................................. 65
PLL ............................................................................................................................................. 72
AUDIO ADC/DAC ......................................................................................................................... 75
VIDEO DECODER ............................................................................................................................ 83
AGC ....................................................................................................................................... 84
Video Detection Misc............................................................................................................ 85
Color Killer ............................................................................................................................ 86
2D Comb Filter ...................................................................................................................... 86
VIDEO MIXER .............................................................................................................................. 109
MIXER OUTSEL CONFIGURATION TABLE.............................................................................. 132
Final
Doc No: DM5885-DS-F01
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
ELECTRICAL SPECIFICATIONS .............................................................................................. 137
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE .............................. 137
Recommended Operating Conditions ................................................................................ 138
Crystal Specifications .......................................................................................................... 139
ELECTRICAL CHARACTERISTICS........................................................................................................ 139
DC ELECTRICAL CHARACTERISTICS .................................................................................................. 139
Analog Processing and A/D Converters .............................................................................. 140
Timing ................................................................................................................................. 140
PACKAGING ....................................................................................................................... 144
ORDERING INFORMATION.................................................................................................. 145
DISCLAIMER.............................................................................................................................. 145
PRODUCTS ............................................................................................................................... 145
CONTACT WINDOWS................................................................................................................. 145
Final
Doc No: DM5885-DS-F01
August 19, 2015
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Introduction
The DM5885 is a 4-channel video decoder which converts 4 channels of 6.5 MHz analog
CVBS signals to 4 channels of digital 27 MHz CCIR656 signals. The DM5885 integrates
two internal PLLs, and decodes 720H videos using the same (27MHz) external clock
source. The DM5885 also features a patented fast switch function. With the fast switch
function, the DM5885 can decode up to 8 analog CVBS with little frame rate loss.
The DM5885 includes two SD mixers and one HD mixer. Each SD/HD mixer can
multiplex up to 4 video sources. In addition to two SD CCIR656 outputs or one HD
SMPTE 274M output, the DM5885 mixer can output four D1 videos through one TDM4
interface. The mixers support image mirror and H partition functions. Both interlaced and
progressive digital video outputs are supported.
The DM5885 also includes five audio ADCs and one audio DAC.
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Features
Video Decoder
 Accepts NTSC (M,J), PAL (B, D, G, H, I, M, Nc)
 Hardware Fast Switch function
 Fast Switch also controllable by software or external pin
 Software channel ID in active region
 Four 10-bits video ADCs with built in 6.5 MHz analog low pass filter
 Automatic gain control for Luminance and Chrominance
 Programmable brightness, contrast, saturation, hue, and sharpness
 5-H comb filter for YC separation
 Chrominance line filter for PAL phase error
 DLL for video synchronization, supports 27MHz crystal within +/-1000 ppm variance
 Advanced video synchronization for weak and noisy CVBS. Supports video signal
transmitted by 500-meter long cable
 Up to 2 CCIR656 output interfaces which could be configured as 2 sets of CCIR656
(27MHz) or 2 sets of TDM2 (54MHz) or 1 set of TDM4 (108MHz)
 Support line lock camera
Audio Codecs
 Five audio ADCs and one audio DAC are integrated
 Master I2S/DSP playback, record and audio-mixing
 Supports extended I2S/DSP format transmitting up to 16 audio channels using one
data pin
 16-bit or 8-bit 48/24/16/8 KHz PCM format
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Video Mixer
 Two SD mixers and one HD mixer. Each mixer supports up to 4 channels
 Two SD CCIR656 outputs (27MHz) or one HD SMPTE 274M output (74.25MHz)
 One TDM4 (108MHz) output
 One optional TDM4 input as mixer video sources.
 Various mixing combinations. Special H partition supported
 Video mirror supported
 Support both interlaced and progressive mixer output
 16-bit SDRAM interface
Miscellaneous
 Use a single external 27MHz crystal to support 720H video
 Two programmable PLLs integrated
 Slave I2C bus
 Ultra low power consumption. Under 500mW for normal operation. Under 50mW for
suspend mode.
 128-pin LQFP package (14mmx14mm)
 1.8V core power, 3.3V analog power and 1.8V analog power
Applications
Suggested applications include
 DVR
 Car DVR
 Video capture card
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Terminal Assignment
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
DQ11
DQ10
VDDI
oCCIRD_1[0]
oCCIRD_1[1]
oCCIRD_1[2]
VDDA
AOUT
VSSA
VSSA
AINN
AIN1
AIN2
AIN3
AIN4
AIN5
VDDA
VDDV
oCCIRD_1[3]
VSS
oCCIRD_1[4]
oCCIRD_1[5]
oCCIRD_1[6]
INA0
INB0
VSSV
VSSV
INA1
INB1
VDDV
VDDV
INA2
INB2
AGND
VSSV
oCCIRD_1[7]
VDDO
XO
XI
DM5885
VSS
DQ9
DQ8
VDDI
SDR_CLK
A[11]
A[9]
128 Pin LQFP_14x14
A[8]
VSS
A[7]
A[6]
A[5]
A[4]
VDDO
oPIXCLK
MI2CLK
VSS
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
A[3]
A[2]
A[1]
NC
VDDI
A[0]
A[10]
BA[1]
BA[0]
VSS
iPIXCLK
VDDO
RAS
CAS
WE
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
SI2CLK
SI2CD
VDDI
VSS
AVSS_2
AVDD_2
NC
DQ2
DQ1/SADD[0]
DQ0/SADD[1]
TEST_EN
INA3
INB3
VDDV
NC
NC
NC
AVDD_1
AVSS_1
VSS
oCCIRD_0[7]
oCCIRD_0[6]
oCCIRD_0[5]
oCCIRD_0[4]
VDDO
oCCIRD_0[3]
oCCIRD_0[2]
oCCIRD_0[1]
oCCIRD_0[0]
VSS
DQ12
DQ13
VDDI
ACLKR
ASYNR
ADATR
ADATM
VSS
ACLKP
ASYNP
ADATP
DQ14
VDDO
HRSTZ
DQ15
VSS
MPP4
MPP3
MPP2
MPP1
VDDI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Final
Doc No: DM5885-DS-F01
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Terminal Functions
Analog Video/Audio Interface Pins
Pin Name
Pin Number
Type
INA0
13
A
INB0
14
A
INA1
17
A
INB1
18
A
INA2
21
A
INB2
22
A
INA3
25
A
INB3
26
A
AIN1
6
A
CVBS input A of channel 0 or
S-VIDEO Y of channel 0
CVBS input B of channel 0 or
S-VIDEO Y of channel 0
CVBS input A of channel 1 or
S-VIDEO C of channel 0
CVBS input B of channel 1 or
S-VIDEO C of channel 0
CVBS input A of channel 2 or
S-VIDEO Y of channel 1
CVBS input B of channel 2 or
S-VIDEO Y of channel 1
CVBS input A of channel 3 or
S-VIDEO C of channel 1
CVBS input B of channel 3 or
S-VIDEO C of channel 1
Audio input of channel 1
AIN2
7
A
Audio input of channel 2
AIN3
8
A
Audio input of channel 3
AIN4
9
A
Audio input of channel 4
AIN5
10
A
Audio input of channel 5
AINN
5
A
Audio input negative control
AOUT
2
A
Audio output
Final
Doc No: DM5885-DS-F01
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Description
10
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Digital Video/Audio Interface Pins
Pin Name
Pin Number
98,99,100,
oCCIRD_0[7:0] 101,103,104,
105,106
85,86,87,
oCCIRD_1[7:0]
88,90,91,
92,93
76,58,75,
74,72,71
A[11:0]
70,69,64
63,62,59
122,119,109,
108,96,95,
DQ[15:2]
80,79,49,
48,47,46,
45,40
Type
O
IO
Description
Video data output of channel 0 or
SMPTE 274M Y bus output or
TDM2/TDM4 Output Data Bus
Video data output of channel 1 or
SMPTE 274M C bus output or
TDM2/TDM4 Output Data Bus
IO
SDRAM ADDRESS Bus
IO
SDRAM DATA Bus
DQ0/SADD[1]
38
IO
DQ1/SADD[0]
39
IO
SDR_CLK
77
IO
SDRAM DATA Bus DQ[0],
MSB of I2C Device ID strapping
SDRAM DATA Bus DQ[1],
LSB of I2C Device ID strapping
SDRAM CLOCK
BA[1:0]
57,56
IO
SDRAM BANK Select
WE
50
O
SDRAM Control: WE
CAS
51
O
SDRAM Control: CAS
RAS
52
O
SDRAM Control: RAS
ACLKR
111
O
Audio serial clock output of record.
ASYNR
112
O
Audio serial sync output of record.
ADATR
113
O
Audio serial data output of record.
ADATM
114
O
Audio serial data output of mixing
ACLKP
116
O
Audio serial clock output of playback
ASYNP
117
O
Audio serial sync output of playback
ADATP
118
I
Audio serial data input of playback
Final
Doc No: DM5885-DS-F01
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
GPIO
Pin Name
Pin Number
Type
MPP4
124
IO
MPP3
125
IO
MPP2
126
IO
MPP1
127
IO
Description
FLD/ACTIVE/NOVID/FASTSW_SEL of channel
4
FLD/ACTIVE/NOVID/FASTSW_SEL of channel
3
FLD/ACTIVE/NOVID/FASTSW_SEL of channel
2
FLD/ACTIVE/NOVID/FASTSW_SEL of channel
1
System Control Pins
Pin Name
Pin Number
Type
Description
HRSTZ
121
I
XI
82
I
XO
83
O
oPIXCLK
67
O
TEST_EN
37
I
System reset.
Crystal 27 MHz connection or Oscillator clock
input.
For crystal 27 MHz connection.
27/54/108MHz or SMPTE 274M 74.25MHz clock
output
Test enable, please connect it to ground
SI2CD
42
IO
Slave I2C data
SI2CLK
43
I
Slave I2C clock
iPIXCLK
54
I
CCIR656 27MHz or TMD 108 MHz clock input.
MI2CLK
66
IO
Final
Doc No: DM5885-DS-F01
August 19, 2015
Master i2c clock (open drain)
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Power, Ground and NC Pins
Pin Name
Pin Number
Type
VDDA
1,11
P
1.8V Power for analog audio DAC
VSSA
3,4
G
Ground for analog audio DAC
VDDV
12,19,20,27
P
1.8V Power for video ADC
VSSV
15,16,24
G
AGND
23
G
AVDD_1
31
P
Ground for video ADC
Analog ground (used as signal input reference,
CH_AGND)
1.8V Power for analog clock PLL1
AVSS_1
32
G
Ground for analog clock PLL1
AVDD_2
34
P
1.8V Power for analog clock PLL2
AVSS_2
35
41,60,78,94,
110,128
53,68,84,
102,120
36,44,55,65,
73,81,89,97,
107,115,123
28,29,30,33
61
G
Ground for analog clock PLL2
P
1.8V Power for internal logic.
P
3.3V Power for output driver
G
Ground for internal logic and output driver
VDDI
VDDO
VSS
NC
Final
Doc No: DM5885-DS-F01
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Description
Not Connected
13
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Pin Usage of ITDM Video Input
Settings
CCIRINPINOPT=0
Clock
iPIXCLK (pin 54)
ITDM
Video
In
Data Bus
oCCIRD_1[7:0]
[7:0]
Pin Usage of Video Output
1
Video Out
Final
Doc No: DM5885-DS-F01
August 19, 2015
2
oCCIRD_0[7:0]
SD: CCIR656/TDM2/TDM4
HD: Y component
oCCIRD_1[7:0]
(Only when ITDM is disabled)
SD: CCIR656/TDM2/TDM4
HD: C component
14
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
 Alternative assignment
(PINCFG = 2’h3 @ REG 6A)
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
BA[1]
oPIXCLK1
VDDI
oCCIRD_1[0]
oCCIRD_1[1]
oCCIRD_1[2]
VDDA
AOUT
VSSA
VSSA
AINN
AIN1
AIN2
AIN3
AIN4
AIN5
VDDA
VDDV
oCCIRD_1[3]
VSS
oCCIRD_1[4]
oCCIRD_1[5]
oCCIRD_1[6]
INA0
INB0
VSSV
VSSV
INA1
INB1
VDDV
VDDV
INA2
INB2
AGND
VSSV
oCCIRD_1[7]
VDDO
XO
XI
DM5885
128 Pin LQFP_14x14
(Alternative assignment)
VSS
A[3]
A[2]
VDDI
SDR_CLK
A[11]
A[9]
A[8]
VSS
A[7]
A[6]
A[5]
A[4]
VDDO
A[1]
A[0]
VSS
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
DQ15
DQ14
DQ13
DQ12
VDDI
DQ11
DQ10
DQ9
DQ8
VSS
A[10]
VDDO
RAS
CAS
WE
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
SI2CLK
SI2CD
VDDI
DQ2
DQ1/SADD[0]
DQ0/SADD[1]
TEST_EN
VSS
AVSS_2
AVDD_2
NC
INA3
INB3
VDDV
NC
NC
NC
AVDD_1
AVSS_1
VSS
oCCIRD_0[7]
oCCIRD_0[6]
oCCIRD_0[5]
oCCIRD_0[4]
VDDO
oCCIRD_0[3]
oCCIRD_0[2]
oCCIRD_0[1]
oCCIRD_0[0]
VSS
oPIXCLK
BA[0]
VDDI
ACLKR
ASYNR
ADATR
ADATM
VSS
ACLKP
ASYNP
ADATP
ALINKI
VDDO
HRSTZ
ALINKO
VSS
MPP4
MPP3
MPP2/iPIXCLK
MPP1
VDDI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
 Terminal functions of alternative assignment
(PINCFG = 2’h3 @ REG 6A)
Final
Doc No: DM5885-DS-F01
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Analog Video/Audio Interface Pins
Pin Name
Pin number
Type
INA0
13
A
INB0
14
A
INA1
17
A
INB1
18
A
INA2
21
A
INB2
22
A
INA3
25
A
INB3
26
A
AIN1
AIN2
AIN3
AIN4
AIN5
AINN
AOUT
6
7
8
9
10
5
2
A
A
A
A
A
A
A
Final
Doc No: DM5885-DS-F01
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Description
CVBS input A of channel 0 or
S-VIDEO Y of channel 0
CVBS input B of channel 0 or
S-VIDEO Y of channel 0
CVBS input A of channel 1 or
S-VIDEO C of channel 0
CVBS input B of channel 1 or
S-VIDEO C of channel 0
CVBS input A of channel 2 or
S-VIDEO Y of channel 1
CVBS input B of channel 2 or
S-VIDEO Y of channel 1
CVBS input A of channel 3 or
S-VIDEO C of channel 1
CVBS input B of channel 3 or
S-VIDEO C of channel 1
Audio input of channel 1
Audio input of channel 2
Audio input of channel 3
Audio input of channel 4
Audio input of channel 5
Audio input negative control
Audio output
16
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Digital Video/Audio Interface Pins
Pin Name
oCCIRD_0[7:0]
oCCIRD_1[7:0]
A[11:0]
DQ[15:2]
Pin number
98,99,100,
101,103,104
105,106
85,86,87,
88,90,91,
92,93
76,54,75,74,
72,71,70,69,
80,79,67,66
64,63,62,61,
59,58,57,56,
49,48,47,46,
45,40,
Type
O
O
Video data output of channel 0 or
SMPTE 274M Y bus output or
TDM2/TDM4 Output Data Bus
Video data output of channel 1 or
SMPTE 274M C bus output or
TDM2/TDM4 Output Data Bus
IO
SDRAM ADDRESS Bus
IO
SDRAM DATA Bus
DQ0/SADD[1]
38
I
DQ1/SADD[0]
39
I
SDR_CLK
BA[1:0]
WE
CAS
RAS
ACLKR
ASYNR
ADATR
ADATM
77
96,109
50
51
52
111
112
113
114
O
IO
O
O
O
O
O
O
O
ACLKP
116
IO
ASYNP
117
IO
ADATP
118
IO
ALINKI
119
IO
ALINKO
122
IO
Final
Doc No: DM5885-DS-F01
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Description
SDRAM DATA Bus DQ[0],
MSB of I2C Device ID strapping
SDRAM DATA Bus DQ[1],
LSB of I2C Device ID strapping
SDRAM CLOCK
SDRAM BANK Select
SDRAM Control : WE
SDRAM Control : CAS
SDRAM Control : RAS
Audio serial clock output of record
Audio serial sync output of record.
Audio serial data output of record
Audio serial data output of mixing
Audio serial clock output of playback or
TDM2/TDM4 Input/output Data Bus[7]
Audio serial sync output of playback or
TDM2/TDM4 Input/output Data Bus[6]
Audio serial data input of playback or
TDM2/TDM4 Input/output Data Bus[5]
Interrupt request output,
Audio Multi-chip serial input or
TDM2/TDM4 Input/output Data Bus[4]
Audio Multi-chip serial output or
TDM2/TDM4 Input/output Data Bus[3]
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
GPIO
Pin Name
Pin number
Type
MPP4
124
IO
MPP3
125
IO
MPP2/iPIXCLK
126
IO
MPP1
127
IO
Description
FLD/ACTIVE/NOVID/FASTSW_SEL of
channel 4 or
TDM2/TDM4 Input/output Data Bus[2]
FLD/ACTIVE/NOVID/FASTSW_SEL of
channel 3 or
TDM2/TDM4 Input/output Data Bus[1]
FLD/ACTIVE/NOVID/FASTSW_SEL of
channel 2 or
TDM2/TDM4 Input/output Clock
FLD/ACTIVE/NOVID/FASTSW_SEL of
channel 1 or
TDM2/TDM4 Input/output Data Bus[0]
System Control Pins
Pin Name
Pin number
Type
HRSTZ
121
I
XI
82
I
XO
83
O
oPIXCLK
108
O
oPIXCLK1
95
O
TEST_EN
SI2CD
SI2CLK
37
42
43
I
IO
I
Final
Doc No: DM5885-DS-F01
August 19, 2015
Description
System reset
Crystal 27MHz connection or Oscillator
clock input.
Crystal 27MHz connection
27/54/108MHz or SMPTE 274M 74.25MHz
clock output.
27/54/108MHz or SMPTE 274M 74.25MHz
clock output
Test enable, please connect it to ground
Slave I2C data
Slave I2C clock
18
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Power, Ground and NC Pins
Pin Name
Pin number
Type
VDDA
VSSA
VDDV
VSSV
1,11
3,4
12,19,20,27
15,16,24
P
G
P
G
AGND
23
G
AVDD_1
AVSS_1
AVDD_2
AVSS_2
31
32
34
35
41,60,78,94,
110,128
53,68,84,
102,120
36,44,55,65,
73,81,89,97,
107,115,123
28,29,30,33
P
G
P
G
1.8V Power for analog audio DAC
Ground for analog audio DAC
1.8V Power for video ADC
Ground for video ADC
Analog ground (used as signal input
reference, CH_AGND)
1.8V Power for analog clock PLL1
Ground for analog clock PLL1
1.8V Power for analog clock PLL2
Ground for analog clock PLL2
P
1.8V Power for internal logic
P
3.3V Power for output driver
G
Ground for internal logic and output driver
VDDI
VDDO
VSS
NC
Final
Doc No: DM5885-DS-F01
August 19, 2015
Description
Not Connected
19
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Pin Usage of ITDM Video Input
Settings
CCIRINPINOPT=1
Clock
MPP2/iPIXCLK (pin 126)
ITDM
Video
In
Data
Bus
Pin no. {116, 117, 118, 119,
122, 124, 125, 127}
[7:0]
Pin Usage of Video Output
Video Out
Final
Doc No: DM5885-DS-F01
August 19, 2015
1 oCCIRD_0[7:0]
SD: CCIR656/TDM2/TDM4
HD: Y component
2 oCCIRD_1[7:0]
SD: CCIR656/TDM2/TDM4
HD: C component
3 (a) Only when ITDM is disabled
(b) set CCIROPINOPT=1
(c) supporting SD:
CCIR656/TDM2/TDM4
Data Bus[7:0]:
Pin no. {116, 117, 118, 119,122,
124, 125, 127}
20
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Block Diagram
16/32 bit SDRAM IF
1xHD / 2xSD Mixer
VIN1A
VIN1B
M
U
X
Video Decoder
ADC
VIN2A
VIN2B
VIN3A
VIN3B
M
U
X
VD0[7:0] / HD_Y
Video Decoder
VD1[7:0] / HD_C
OTDM
IF
M
U
X
VD3[7:0]
Video Decoder
ADC
VIN4A
VIN4B
M
U
X
AIN1
AIN2
AIN3
AIN4
AIN5
AOUT
Final
Doc No: DM5885-DS-F01
August 19, 2015
MIX_TDMO/
MIX_TDMI
Video Decoder
5x Audio ADC
Audio DAC
VD2[7:0]
I2S IF
Audio
Mix
Audio cas
IF
ACLKR/ASYNR/
ADATR
ADATM
ACLKP/ASYNP
ADATP
ALINKO
ALINKI
21
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Video Decoder
Video Interface
The DM5885 outputs 27MHz CCIR656 with 720x480/720x576 resolution. For these
video outputs, SAV (Start of Active Video) and EAV (End of Active Video) are inserted to
indicate active video interval. Each channel uses one output port to transmit video data,
that is, luminance and chrominance data are transmitted through the same port. The
output timing diagram is shown below.
CLK
CCIR_n[7:0]
FFh
00h
00h
XY
80h
EAV code
4 data cycles
10h
80h
10h
Horizontal Blanking
FFh
00h
00h
XZ
Cb0
Y0
Cr0
Y1
SAV code
4 data cycles
Cb2
Y2
Cr2
Y3
Cbn
Yn
Crn
Yn+1
FFh
00h
Active Horizontal Line
HACITVE
The number of data cycles in active horizontal line will vary according to the output
format. The active horizontal line contains 1440 cycles.
SAV and EAV indicate the active video interval. The values of the first three bytes in
SAV and EAV are invariant preamble: 0xFF, 0x00, and 0x00. Different values are
designated to the last byte according to different conditions: Field, V time, and H time.
The MSB of this byte is always set to 1 and it’s followed by three bits to represent the
condition of F, V, and H respectively. The last four bits are used as protection bits. The
detailed code sequences of SAV and EAV are illustrated in the following table.
FVH
Value
Condition
SAV/EAV Code Sequence
Field
V time
H time
F
V
H
Byte 0
Byte 1
Byte 2
Byte 3
Odd
Odd
Odd
Odd
Even
Even
Even
Even
Active
Active
Blank
Blank
Active
Active
Blank
Blank
SAV
EAV
SAV
EAV
SAV
EAV
SAV
EAV
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x80
0x9D
0xAB
0xB6
0xC7
0xDA
0xEC
0xF1
Final
Doc No: DM5885-DS-F01
August 19, 2015
22
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Multi-channel Time Division Multiplexing
The DM5885 supports 2/4-channel time division multiplexed output format. Thus two or
four video channels can be transmitted through one output port. The clock rate should
be two or four times of the original sampling rate according to the number of channels to
be multiplexed.
The basic case is the non-multiplexed output. The clock rate follows the original data
rate (27 MHz). The timing diagram is illustrated below.
CLK1X
tlw thw
CCIR
00
00
FF
tsu th
XY
Y0
Cb0
Cr0
When two-channel multiplexing is selected, two times of the original clock rate is used
(54 MHz). The timing diagram is illustrated below.
CLK2X
CH0
FF
CH1
00
00
Cb20
Y20
tlw thw
TDM2X
FF
Cb20
CH0
Final
Doc No: DM5885-DS-F01
August 19, 2015
XY
00
Cr20
tsu
Y20
00
Cb0
Y21
th
Cr20
XY
Y21
Cb0
CH1
23
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
When four-channel multiplexing is selected, four times of the original clock rate is used
(108 MHz). The timing diagram is illustrated below.
CLK4X
CH0
FF
00
CH1
Cb0
CH2
Cr0
Y0
Y17
Cr16
Y16
CH3
Cr32
FF
Cb0
CH0
Y16
00
Cr32
CH2
CH1
Cb34
Y33
tlw thw
TDM4X
XY
00
Y0
tsu th
Cr16
Y33
00
Cr0
Y17
XY
Cb34
CH3
In the Multi-channel Time Division Multiplexing mode, channel IDs are used to indicate
the corresponding channels. Channel IDs are defined as the last four bits in SAV/EAV
code sequence (i.e. the originally-defined protection bits). The relationship between
SAV/EAV code sequence and channel ID is illustrated in the following table.
Condition
Field
V time
FVH Value
H time
F
V
H
EAV/SAV Code Sequence
Byte 0
Byte 1
Byte 3
Byte 2
Ch0
Odd
Odd
Odd
Odd
Even
Even
Even
Even
Active
Active
Blank
Blank
Active
Active
Blank
Blank
SAV
EAV
SAV
EAV
SAV
EAV
SAV
EAV
Final
Doc No: DM5885-DS-F01
August 19, 2015
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Ch1
Ch2
Ch3
0x80 0x81 0x82 0x83
0x90 0x91 0x92 0x93
0xA0 0xA1 0xA2 0xA3
0xB0 0xB1 0xB2 0xB3
0xC0 0xC1 0xC2 0xC3
0xD0 0xD1 0xD2 0xD3
0xE0 0xE1 0xE2 0xE3
0xF0 0xF1 0xF2 0xF3
24
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
4-CH Video Decoder
gain1A
VIN1A
VADC 0
A
VIN1B
A
CCIR
sel_1
Video decoder 0
oCCIRD_0
B
gain1B
gain2A
A
CCIR
VIN2A
VADC 1
B
Video decoder 1
oCCIRD_1
B
sel_2
VIN2B
gain2B
gain3A
VIN3A
VADC 2
A
VIN3B
A
CCIR
sel_3
Video decoder 2
oCCIRD_2
B
gain3B
gain4A
A
CCIR
VIN4A
VADC 3
B
Video decoder 3
oCCIRD_3
B
sel_4
VIN4B
gain4B
The DM5885 contains four video decoders supporting up to 8 CVBS inputs.
Each CVBS has its own gain amplifier. For each pair of VINA and VINB, a 2-to-1 MUX
selects one CVBS source and passes this source to one video analog-to-digital
converter (VADC). The DM5885 has 4 VADCs and 4 video decoders (VD). The VADCs
and VDs are organized as 2 banks as shown in the above figure. Each bank can be
independently configured to operate at 27MHz.
Final
Doc No: DM5885-DS-F01
August 19, 2015
25
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Video Decoder Unit
V
Video Interface
BT.656 or BT.1302
U
C
UV Demod
AGC+CAGC
C_sv
Y_cvbs
Video
Synchronization
CVBS
B
Y
Y/C Separation
2D Comb Filter
A
Luma/Chroma Processor
Gain Adjust
CCIR
SV
Fast Switch Parameter
RAM
Video Decoder
Fast Switch
Select
The DM5885 video decoder contains a Video Synchronization block, an AGC block, an
YC separation block, a UV Demodulation block, a Luma/Chroma Processor block and a
BT 656 output block. A patented Fast Switch is also included.
In addition to CVBS, the DM5885 video decoder supports S-Video as well.
Video Synchronization
Video Synchronization performs video detection function. It automatically detects
NTSC(M), NTSC(443), PAL(B,D,G,H,I), PAL(M), PAL(N), PAL(60). A smart video
detection algorithm has been adopted. Therefore the DM5885 can perform fast and
stable video synchronization even if the input signal is weak or the external crystal is
with error as large as +/- 1000 ppm.
Automatic Gain Control
Automatic Gain Control (AGC) block performs both Luma AGC and Chroma AGC
(CGAC). After video synchronization, Luma AGC adjusts input Luma level to the
standard level (1Vpp). A further CAGC is performed after Luma AGC for signal with
different Luma and Chroma attenuation.
Final
Doc No: DM5885-DS-F01
August 19, 2015
26
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Y/C Separation
Y/C Separation is for CVBS input only. After this block CVBS signal is separated into
Luma and Chroma components. A 5-H 2D comb filter is adapted in the Y/C separation
block.
UV demodulation
After Y/C separation, the UV demodulation block performs UV demodulation to the
Chroma component. The phase and frequency of the UV demodulation is from a color
burst subcarrier tracking block for both NTSC and PAL mode. A UV demodulation LPF is
also adopted to filter out chroma noise.
Luma/Chroma Processor
This block contains a programmable Luma sharpness filter. Hue, Saturation, Brightness
and Contrast adjustment are also supported. The adjusted video is then transformed
from YUV to YCbCr domain for CCIR656 output interface.
Video Interface
The DM5885 video decoder supports 27MHz BT.656 video output format. A horizontal
cropping function also included in this block.
Fast Switch Parameter RAM
The DM5885 features a patented hardware video source fast switch function. The Fast
Switch block has a table which stores video characteristic. Each time HW switches to a
previously tracked video source it could complete video synchronization within several
lines. With this feature, the DM5885 can decode up to 8 CVBS with little frame rate loss.
Final
Doc No: DM5885-DS-F01
August 19, 2015
27
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Filter response
Anti-alias LPF
Decimation filter
Final
Doc No: DM5885-DS-F01
August 19, 2015
28
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Luma notch filter
Chroma band pass filter
Final
Doc No: DM5885-DS-F01
August 19, 2015
29
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Y sharpness filter

NTSC

PAL
Final
Doc No: DM5885-DS-F01
August 19, 2015
30
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
UV demodulation low pass filter
Final
Doc No: DM5885-DS-F01
August 19, 2015
31
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Audio CODEC
The audio codec in the DM5885 consists of five audio ADCs, one audio DAC, one audio
mixer, one I2S/DSP decoder and two I2S/DSP encoders as shown below. The I2S/DSP
decoder and encoders always operate in the master mode.
Audio Codec
ACLKR
I2S/DSP Encoder
(master)
ADATR
I2S/DSP Encoder
(master)
ASYNR
ADATM
ASYNR
ACLKR
AIN1
AIN2
AIN3
AIN4
AIN5
X
X
DAGC_GAIN1
MIXGAIN_1
X
X
DAGC_GAIN2
MIXGAIN_2
X
X
DAGC_GAIN3
MIXGAIN_3
X
X
DAGC_GAIN4
MIXGAIN_4
X
X
AADC
AADC
AADC
AADC
AADC
ADAC_SRC
MIXER
MUX
DAGC_GAIN5
MIXGAIN_5
X
ADAC
AOUT
DAGC_GAIN_P
X
MIXGAIN_P
ACLKP
ASYNP
ADATP
Final
Doc No: DM5885-DS-F01
August 19, 2015
I2S/DSP Decoder
(master)
32
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
The I2S/DSP decoder is used for playback of digital input. It generates ACLKP and
ASYNP signals and accepts serial data via ADATP from a slave device. The levels of
the five analog audio inputs (AIN1 ~ AIN5) are programmable via the registers
DAGC_GAIN1, DAGC_GAIN2, DAGC_GAIN3, DAGC_GAIN4 and DAGC_GAIN5. The
six input audio sources can be mixed by the used-defined ratio specified by registers
MIXGAIN_1, MIXGAIN_2, MIXGAIN_3, MIXGAIN_4, MIXGAIN_5, MIXGAIN_P. The
mixed audio can be output through I2S/DSP encoder or DAC.
The codec provides three interfaces for audio output. The audio DAC can output analog
audio for any one of the six input audio sources or the mixed audio. The analog output
level is adjustable via register DAGC_GAIN_P. Two I2S/DSP encoders are present to
output digital audio signal. The first one generates ACLKR, ASYNR and ADATR to
output the 4 recorded audio inputs. The second encoder uses ADATM and shares the
other two signals (ACLKR and ASYNR) to output the mixed audio.
Final
Doc No: DM5885-DS-F01
August 19, 2015
33
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Digital Audio Format
The 3 digital audio interfaces (decoder for playback and encoder for record or mixing)
follow the standard I2S or DSP protocol as shown below. Only master mode (codec
being the master) is supported.
I2S Format
1/fs
ASYN
ACLK
ADAT
Data 1
Data 2
MSB
LSB
8 or 16 bits
DSP Format
1/fs
ASYN
ACLK
Data 1
ADAT
Data 2
MSB
LSB
8 or 16 bits
Final
Doc No: DM5885-DS-F01
August 19, 2015
34
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Extended Digital Audio Format
The digital audio encoders also support an extended I2S/DSP format to carry multiple
audio channels through a single ADAT pin as shown below.
Extended I2S Format
(Illustrate the case when the number of channels is 8)
1/fs
ASYNR
ACLKR
ADATR / ADATM
Data 0
Data 1
Data 2
Data 3
Data 4
MSB
Data 5
Data 6
Data 7
LSB
8 or 16 bits
Extended DSP Format
(Illustrate the case when the number of channels is 8)
1/fs
ASYNR
ACLKR
ADATR / ADATM
Data 0
Data 1
Data 2
Data 3
MSB
Data 4
Data 5
Data 6
Data 7
LSB
8 or 16 bits
Final
Doc No: DM5885-DS-F01
August 19, 2015
35
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
PLL
The DM5885 has two internal PLLs to generate the system and pixel clocks. A
27MHz is required for the PLLs.
The default PLL setting is shown in the following table.
Crystal In clock
(MHz)
PLL out (MHz)
Function
PLL1
27
144
System/pixel clock
PLL2
27
74.25
SMPTE 274M
pixel clock
PLL default operated clock
The PLL parameters for various system configurations are shown in the following table.
Crystal(MHz)
PLL
out(MHz)
M
N
OD
27
27
27
27
27
144
108
144
108
74.25
64(62+2)
16(14+2)
64(62+2)
16(14+2)
22(20+2)
6(4+2)
2(0+2)
6(4+2)
2(0+2)
2(0+2)
1
1
1
1
2
PLL1
PLL2
Final
Doc No: DM5885-DS-F01
August 19, 2015
36
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Host Interface
In the DM5885, I2C is used for setting configuration and parameters, for example,
brightness, contrast, saturation, hue, and sharpness control. The typical timing diagram
of I2C write and read access is illustrated in the following figure.
SI2CLK
1
2
8
9
1
2
8
1
9
8
2
9
SI2CD
START
ACK
WRITE ADDRESS
REG ADDRESS
ACK
WRITE DATA
ACK
STOP
Write operation of I2C bus
SI2CLK
1
2
8
9
1
2
8
1
9
2
8
1
9
2
8
9
SI2CD
START
WRITE ADDRESS
ACK
REG ADDRESS
ACK
STOP
START
READ ADDRESS
ACK
READ DATA
ACK STOP
Read operation of I2C bus
1
1
0
Write/Read Address
Slave Address
0
0
SADD[1] SADD[0]
R/W
0: Write; 1: Read
The external Pull-up/Pull-down resisters connected to the pins “DQ0” and “DQ1” indicate
the device address SADD[1] and SADD[0]. When pull-up resistor is connected to DQ0 or
DQ1, it indicates SADD[1] or SADD[0] with a high value. Otherwise when pull-down
resistor is connected to DQ0 or DQ1, it indicates SADD[1] or SADD[0] with a low value.
SADD[1:0]=2’h0
SADD[1:0]=2’h1
SADD[1:0]=2’h2
SADD[1:0]=2’h3
Final
Doc No: DM5885-DS-F01
August 19, 2015
Write Address
Read Address
C0
C2
C4
C6
C1
C3
C5
C7
37
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Video Mixer
The video mixer in the DM5885 is composed of four capture interfaces, two mixer cores,
one SDRAM controller and two mix-out interfaces (MIX_CCIROUT_X) as shown below.
The MIX_CCIROUT_0 is the main output interface, while an auxiliary path (through
MIX_CCIROUT_1) is available for SD mode when OUTSEL is configured as 4 or 5.
SDRAM
VDOUT_0
CHSEL_0
OUT_SEL
SDRAM Controller
INV_H0
OUT_SEL
VDOUT_1
Video
Source
Channel
Switch
Scaler
Mirror
CH0
Capture I/F
CH0
CHSEL_1
OUT_SEL
INV_H1
CH1
VDOUT_2
Video
Source
Channel
Switch
Scaler
Mirror
CH1
CH2
MX_SD_0
MIX_
CCIROUT_
0
Mixer_Core_0
(HD/SD)
CH3
MX_HD_Y
MX_HD_C
Capture I/F
VDOUT_3
CHSEL_2
Video
Source
Channel
Switch
OUT_SEL
Scaler
INV_H2
Mirror
CH2
Capture I/F
CH1
ITDM_0
CHSEL_3
OUT_SEL
INV_H3
Scaler
Mirror
CH2
ITDM_1
MIX_
CCIROUT_
1
Mixer_Core_1
(SD only)
MX_SD_1
CH3
ITDM_2
ITDM_3
Video
Source
Channel
Switch
CH3
Capture I/F
OUT_SEL
MX_SD_1 is valid only when
the value of OUT_SEL is 4 or 5.
Video Mixer
Block Diagram of Video Mixer
Final
Doc No: DM5885-DS-F01
August 19, 2015
38
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Output format
In addition to 27MHz BT.656 with 720x480/720x576 resolution, the DM5885 mixer can
support 74.25MHz SMPTE 274M 1920x1080 interface.
SMPTE 274M contains 16-bit data bus and 1-bit clock bus. Thus two output ports are
used for one HD format. Here luminance and chrominance data are transmitted through
different ports. The output timing diagram is shown below.
CLK
CCIR_n[7:0]
FFh
00h
00h
XY
10h
10h
10h
10h
FFh
00h
00h
XZ
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Yn-3
CCIR_n+1[7:0]
FFh
00h
00h
XY
80h
80h
80h
80h
FFh
00h
00h
XZ
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
Cb6
Cr6
Cbn-3 Crn-3 Cbn-1 Crn-1
EAV code
4 data cycles
Horizontal Blanking
SAV code
4 data cycles
Yn-2
Yn-1
Yn
FFh
00h
FFh
00h
Active Horizontal Line
HACITVE
For 1920x1080 HD video outputs, the active horizontal line contains 1920 cycles. The
definition of SAV and EAV code sequences is the same as that in 720H video outputs.
Final
Doc No: DM5885-DS-F01
August 19, 2015
39
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Video Mixer Block
Video Source
The video mixer accepts eight input sources (VDOUT_0 ~ VDOUT_3, ITDM_0 ~
ITDM_3). The input source VDOUT_X, digital version of the input CVBS, comes from the
internal video decoder. As shown in the figure, users are flexible to select any one from
the input CVBS pair for VDOUT_X by programming the control registers (SW_sel_1,
SW_sel_2) of the analog MUX. The ITDM_X is the decoded TDM input for a specific
Channel ID.
VIN1A
V
A
D
C
VIN1B
VIN2A
VIN2B
VIN3A
V
A
D
C
VIN3B
VIN4A
VIN4B
Video
Decoder
0
VDOUT_0
Video
Decoder
1
VDOUT_1
Video
Decoder
2
VDOUT_2
Video
Decoder
3
VDOUT_3
Analog
MUX
ITDM_0
ITDM_1
TDM Input
(144/108/72/54 MHz)
ITDM
ITDM_2
ITDM_3
Video Source of Video Mixer
Channel Switch Block
There are four capture interfaces in the video mixer. Within each capture interface, a
channel switch is used to select the desired video source. This selection is fully
programmable by registers CHSEL_0, CHSEL_1, CHSEL_2 and CHSEL_3, allowing
any one of the eight mixer inputs to be selected. The following table determines the
mapping between CHSEL_X and the selected video.
CHSEL_X
Selected
Video
0
1
2
3
4
5
6
7
VDOUT_0
VDOUT_1
VDOUT_2
VDOUT_3
ITDM_0
ITDM_1
ITDM_2
ITDM_3
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Capture interface
The following figure is the block diagram of channel video capture interface. The video
source is selected by the channel switch for the specific channel. Video signal detection
detects valid signal and format. It is then horizontally cropped, scaled, and horizontally
mirrored if necessary. The detailed functions of these modules are described in the
following sections.
Video Signal Detection
Video signal detection module detects if valid video signal exists. A timeout watchdog
module monitors the time used by the detection module. If valid signal is detected within
the pre-set time limit, the flag ‘NOVID_x’ is set to 0. Otherwise, it is set to ‘1’.
The module also detects the format of the channel signal. ‘H720_DET_x’ is 1 when
720H video source is detected. ‘L625_DET_x’ is 1 when PAL video source is detected.
‘L525_DET_x’ is 1 when NTSC video source is detected.
Horizontal Cropping
The input video source can be cropped horizontally for output. It is illustrated in the
following figure. ‘Crop_start_point’, which indicates the position to start cropping, is set in
the registers 0xC3 to 0xC6. ‘Crop_start_point’ can be specified for each channel.
‘Crop_length’, which indicates the length for cropping, is set in the registers 0xA4 and
0xA5. The same value is used for all channels. If 1/4 horizontal scaling is performed in
any channel, it should be set to a multiple of 4. Otherwise, if 1/2 horizontal scaling is
performed in any channel; it should be set to a multiple of 2.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Scaler
DM5885 supports several kinds of partition modes. It can be configured with the register
‘OUT_SEL’ (0xA0). According to the mode selection, the output of each channel should
be scaled to be combined to a new frame for output. The following figure shows the
settings of ‘OUT_SEL’ and the corresponding output formats. Here 720H NTSC video
source is used as an example.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
The following table shows the scaling ratios at the horizontal direction and the vertical
direction with different ‘OUT_SEL’ settings.
OUT_SEL
CH0
CH1
CH2
CH3
0
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
H
V
H
V
H
V
H
V
1
1
1/2
1
1/2
-
2
1
1/2
1/2
1/2
1/2
1/2
-
3
1/2
1/2
1/4
1
1/2
1/2
1/4
1
4
1
1
-
5
1/2
1
1/2
1
-
8
1
1
1
1
1
1
1
1
When horizontal scaling is performed, decimation filter is applied on input samples. The
filtered samples are then decimated according to the scaling ratio. The following figure
shows the frequency response of the decimation filter at the horizontal scaling process.
0
-5
Gain (dB)
-10
-15
-20
-25
-30
0
Final
Doc No: DM5885-DS-F01
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0.5
1
1.5
2
2.5
3
3.5
Frequency (MHz)
4
4.5
5
5.5
6
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
When the display width is a quarter of the original width, in addition to 1/4 down scaling
at the horizontal direction, 1/4 input frame cropping can be chose. The most significant
four bits of the register ‘Mirror Config’ (0xBD) are used to indicate the input frame
cropping. When ‘H_x_L’ is set to 1, the left quarter of channel x is cut for display. When
‘H_x_R’ is set to 1, the right quarter of channel x is cut for display. When ‘H_x_L’ and
‘H_x_R’ are both set to 0, 1/4 down scaling is performed. The following figure illustrates
the settings of ‘H_x_L’ and ‘H_x_R’.
Please note that 1/4 input frame cropping can only be supported at SD mode and
‘OUT_SEL’ is set to 3.
Vertical scaling uses simple line dropping algorithm. No averaging operation is
performed. The following figure illustrates the process. Top field is used for output.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Mirror
When horizontal mirroring is performed, the samples at each line are left-right
flipped. Please note that horizontal mirroring is only supported at SD mode. Each output
channel can be assigned to be mirrored or not. The last four bits of the register ‘Mirror
Config’ (0xBD) are used to indicate the mirrored output channels. When ‘INV_Hx’ is set
to 1, the output picture of channel x is mirrored at the horizontal direction. The following
figure illustrates the result of horizontal mirroring.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Mixer Core
There are two mixer cores mixing up to four video data (CH0, CH1, CH2 and CH3)
coming from the capture interface. The mixed video is then stored into the SDRAM. The
Mixer_Core_0 is a full-function mixer supporting both HD and SD resolution.
Mixer_Core_1 is a secondary mixer which is only valid for SD mode when OUTSEL is
programmed as 4 or 5. The mixing process is determined by the value of the register
OUTSEL as shown in the following figure.
Mix-Out Interface
The mix-out interface retrieves mixed video from the SDRAM. The mixed video then
goes to the chip-level output unit to form a variety of output combinations. Users are
flexible to specify the output format as progressive or interlaced. The MIX_CCIROUT_0
is the main mixer output unit supporting both SD and HD resolution. For SD mode,
MX_SD_0 is output. In case of HD mode, MX_HD_Y is output for luminance and
MX_HD_C is output for chrominance. Another mixed video MX_SD_1 from
MIX_CCIROUT_1 is available if OUTSEL is configured as 4 or 5. MX_SD_1 is always of
SD resolution. The combined usage of MIX_CCIROUT_0 and MIX_CCIROUT_1 is
shown in the following figure.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
H/4
H/2
CH0
CH1
V/2
CH0
CH2
CH3
V/2
CH1
CH0
H/2
OUTSEL=4'h1
(2-v-split)
CH0
OUTSEL=4'h4
(Bypass)
V
H/2
H/2
CH0
CH1
CH2
CH3
OUTSEL=4'h0
(4-split)
SD
Mode
CH1
H/4
CH0
CH1
H/2
CH2
OUTSEL=4'h2
(3-split)
OUTSEL=4'h3
(H-split)
OUTSEL=4'h5
(2-h-split)
H
H
CH0
CH1
HD
Mode
HD_V
V
CH2
CH3
HD_H
OUTSEL=4'h8
(HD-4-split)
OUT_SEL=0~5 : SD mode (H=720, V=480 or 576)
OUT_SEL=8 : HD mode (HD_H=1920, HD_V=1080 or 1152)
Other values
: prohibited
Value of OUTSEL and the Corresponding Partition Type
MX_SD_0
MX_SD_1
CH0
CH1
OUTSEL=4'h4
OUTSEL=4'h5
CH0
CH1
CH2
CH3
The Combined Usage of the two Mixer Outputs
(Only Valid When OUTSEL=4 or OUTSEL=4)
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Video Rendering
The output frame is divided into several partitions according to ‘OUT_SEL’. The following
table shows the coordinates of left-top point and right-bottom point of the partitions with
different values of ‘OUT_SEL’. The input video width is denoted as W and the input
video height is denoted as H.
0
1
0
0
0
1
2
Partition 0
Partition 1
Partition 2
Partition 3
3
1
1
2
3
0
0
0
1
2
3
1
2
OUT_SEL
=0
OUT_SEL
=1
OUT_SEL
=2
OUT_SEL
=3
OUT_SEL
=4
OUT_SEL
=5
OUT_SEL
=8
(0,0)
(0,0)
(0,0)
(W/4,0)
(0,0)
(0,0)
(0,0)
(W/2,H/2)
(W,H/2)
(W,H/2)
(3W/4,H/2)
(W,H)
(W/2,H)
(W,H)
(W/2,0)
(0,H/2)
(0,H/2)
(0,0)
-
(W/2,0)
(W,0)
(W,H/2)
(W,H)
(W/2,H)
(W/4,H)
-
(W,H)
(2W,H)
(0,H/2)
-
(W/2,H/2)
(W/4,H/2)
-
-
(0,H)
(W/2,H)
-
(W,H)
(3W/4,H)
-
-
(W,2H)
(W/2,H/2)
-
-
(3W/4,0)
-
-
(W,H)
(W,H)
-
-
(W,H)
-
-
(2W,2H)
The output of each channel will be rendered within the active region of the
corresponding partition. The active region in each partition can be specified by defining
its top-left coordinate (COR_Xn, COR_Yn). The length of the active region is the crop
length multiplied by the scaling ratio. The vertical coordinate of the right-bottom point of
the active region is the same as that of the corresponding partition. Channel output is
horizontally shifted if the horizontal coordinate of the top-left point of the active region is
different from that of the corresponding partition. However, if the vertical coordinate of
the top-left point of the active region is different from that of the corresponding partition,
pixel lines outside the active region are discarded. The following figure illustrated the
relationship between partitions and active regions.
Several rules should be followed when specifying the coordinate (COR_Xn, COR_Yn).
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
1. The active region should not be outside the corresponding partition. If we define the
coordinate of the left-top point of the partition to be (S_Xn,S_Yn) and the partition
width to be PWn, the following condition should be satisified:
COR_Xn + Crop_length*H_scaling_ratio <= S_Xn + PWn
2. The settings of COR_Xn of the partitions, which have the same S_Xn, should also be
the same.
3. If S_Yn is 0, COR_Yn should also be 0.
4. The settings of COR_Yn of partitions, which have the same S_Yn, should also be the
same.
COR_XBR and COR_YBR specify the active region of the whole frame. It is
recommended that it is set to the right-bottom point of the whole frame.
When the active region is smaller than the corresponding partition, the spacing in the
region is regarded as split line. The color of the split line spacing can be assigned by the
registers: ‘Split_line_Y’, ‘Split_line_CB’, and ‘Split_line_CR’ (0xD6 to 0xD8). The default
color is white.
The following figure illustrates an example. The size of input and output video is
720x480 and ‘OUT_SEL’ is set to 3. The crop length is set to 704 and it creates
horizontal split lines. COR_X0 and COR_X2 are set to 184 for center alignment.
COR_X3 is set to 544 for right alignment. COR_Y2 is set to 244 to create a vertical split
line with spacing of 4 pixels.
The following figure illustrates another example. The size of input and output video is
720x480 and ‘OUT_SEL’ is set to 8 (HD mode). The crop length is set to 704 and it
creates horizontal split lines. COR_X1 and COR_X3 are set to 736 for center alignment.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
COR_Y2 and COR_Y3 are set to 488 to create a vertical split line with spacing of 8
pixels.
If the input channel is not valid, the corresponding output video will be displayed as blue
panel. The following figure shows this condition. The display color of invalid video can
also be designed with three registers: ‘Blue_panel_Y’, ‘Blue_panel_CB’, and
‘Blue_panel_CR’ (0xD3 to 0xD5). The default color is blue.
Please note that the above settings about video rendering are the same whether the
output format is progressive.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Chip-Level Output Unit
Three video output ports are available at chip level. The following figure depicts the data
path of output ports.
The output ports are flexible in use. It can be programmed to output various output
combinations. As shown in the figure, the register CCIROMXm_n is used to select up to
4 output videos from 6 possible sources. By programming register CCIROTMD_X, user
can specify whether single channel (CCIR656/BT.1302), 2-channel TDM (@54 MHz), 4channel TDM (@108 MHz) or HD video is to be output. When HD video is selected,
luminance component is output through oCCIRD_0 while chrominance component is
output through oCCIRD_1.
CCIROTMD_0
(0x68[5:4], Video-Out Format Select 0)
0: CCIR656
1: 54 / 72 MHz TDM Out (2 channels)
2: 108 /144 MHz TDM Out (4 channels)
3: Luma of HD Mode Mixer Out
CCIROTMD_0
CCIROMX0_0
0
VDOUT_0
CCIROMX0_1
VDOUT_1
TDM Out
54 / 72
MHz
VDOUT_1
CCIROUT_0
VDOUT_2
CCIROMX0_2
VDOUT_3
0
VDOUT_0
CCIROMX1_1
1
oCCIRD_0[7:0]
(chip I/Os)
2
MX_SD_0
TDM Out
54 / 72
MHz
CCIROTMD_1
(0x68[7:6], Video-Out Format Select 1)
0: CCIR656
1: 54 / 72 MHz TDM Out (2 channels)
2: 108 /144 MHz TDM Out (4 channels)
3: Chroma of HD Mode Mixer Out
1
CCIROUT_1
VDOUT_2
CCIROMX1_2
TDM Out
108 / 144
MHz
CCIROTMD_1
CCIROMX1_0
VDOUT_3
TDM Out
108 / 144
MHz
2
oCCIRD_1[7:0]
(chip I/Os)
MX_SD_0
CCIROMX0_3
CCIROMX1_3
3
MX_SD_1
3
MX_SD_1
MX_HD_Y
MX_HD_C
CCIR_OUT0
CCIR_OUT1
CCIROMXm_n
[2:0]
MUX Output
0
VDOUT_0
1
VDOUT_1
2
VDOUT_2
3
VDOUT_3
4
MX_SD_0
5
MX_SD_1
Video-Out Source Select
(0x71 ~ 0x74, 0x9E ~ 0x9F)
<Note>
(1) VDOUT_0 ~ VDOUT_3 are from Video Decoder 0 ~ Video Decoder 3 respectively.
MX_SD_0, MX_SD_1, MX_HD_C and MX_HD_C are from the video mixer.
(2) MX_HD_Y and MX_HD_C are valid only when (OUT_SEL=4'd8).
Data Path of Chip-Level Video Output Unit
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Internal Control Registers
System Control
Address= 8’h64
System Control Page
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
1
PAGE_3
PAGE_2
PAGE_1
PAGE_0
PAGE_0: VD space 0, to access VD_0 register please program this bit to 1.
PAGE_1: VD space 1, to access VD_1 register please program this bit to 1.
PAGE_2: VD space 2, to access VD_2 register please program this bit to 1.
PAGE_3: VD space 3, to access VD_3 register please program this bit to 1.
In case of register read, only one of the four bits can be set to 1.
Address= 8’h65
System Reset
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
RSTZ
TRSTZ
TRSTZ: When 1, reset whole chip except SW PLL, GPIO and Device ID setting. (WO)
RSTZ:
When 1, reset all video decoders, mixer, TDM and audio interface. It also
resets video decoder configurations.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h66
Global INT Mask
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
VDMAS
K_3
VDMAS
K_2
VDMAS
K_1
VDMAS
K_0
VDMASK_0: Enable INT from VD_0.
VDMASK_1: Enable INT from VD_1.
VDMASK_2: Enable INT from VD_2.
VDMASK_3: Enable INT from VD_3.
Address= 8’h67
Global INT Status
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
VDINT_3
VDINT_2
VDINT_1
VDINT_0
VDINT_0: VD_0 INT status. (RO)
VDINT_1: VD_1 INT status. (RO)
VDINT_2: VD_2 INT status. (RO)
VDINT_3: VD_3 INT status. (RO)
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h68
CCIR656 IO Control
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
2’h0
2’h0
0
0
0
0
CCIROTMD_1
CCIROTMD_0
CCIROE
_3
CCIROE
_2
CCIROE
_1
CCIROE
_0
CCIROE_0: Chip CCIR656_0 related 9 pins output enable.
When 1, output mode. When 0, input mode.
CCIROE_1: Chip CCIR656_1 related 9 pins output enable.
When 1, output mode. When 0, input mode.
CCIROE_2: Chip CCIR656_2 related 9 pins output enable.
When 1, output mode. When 0, input mode.
CCIROE_3: Chip CCIR656_3 related 9 pins output enable.
When 1, output mode. When 0, input mode.
CCIROTMD_0: Chip CCUROUT_0 output Mode type.
2’h0: CCIR656 output mode.
2’h1: 54Mhz TDM mode with D1 resolution for each channel.
2’h2: 108Mhz TDM mode with D1 resolution for each channel.
2’h3: HD Mixer mode with Y data bus.
CCIROTMD_1: Chip CCUROUT_1 output Mode type.
2’h0: CCIR656 output mode.
2’h1: 54Mhz TDM mode with D1 resolution for each channel.
2’h2: 108Mhz TDM mode with D1 resolution for each channel.
2’h3: HD Mixer mode with C data bus.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h69
PIXCLK Polarity
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
OPIXCL
K3_INV
OPIXCL
K2_INV
OPIXCL
K1_INV
OPIXCL
K0_INV
OPIXCL
K4_INV
IPIXCLK
_INV
IPIXCLK
OE
IPIXCLK_OE: The polarity of pin No.54.
When 1: pin No.54 is output pin and drives VD_INT signals to pin.
When 0: pin No.54 is input pin and receives iTDM pixclk.
IPIXCLK_INV: When 1, inverse iTDM pixclk to internal logic.
OPIXCLK4_INV: When 1, inverse output pixclk of CCIROUT_4.
OPIXCLK0_INV: When 1, inverse output pixclk of CCIROUT_0.
OPIXCLK1_INV: When 1, inverse output pixclk of CCIROUT_1.
OPIXCLK2_INV: When 1, inverse output pixclk of CCIROUT_2.
OPIXCLK3_INV: When 1, inverse output pixclk of CCIROUT_3.
Address= 8’h6A
IC Mode Control
7-bit
6-bit
5-bit
4-bit
0
0
0
0
3-bit
2-bit
1-bit
0-bit
2’h2
2’h0
PINCFG
CLKADCOPT
CLKADCOPT: The VADC_1 input clock selection. (108MHz)
2’h0: The default value, sources from PLL1.
2’h1: Clock sources from PLL2.
2’h2: Clock source from chip pin NO.126.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
PINCFG: IC pin mode option.
Set 2’h0 for Video decoder x4 without Mixer.
Set 2’h1 for Video decoder x4 with Mixer.
Set 2’h3 for Video decoder x4 with Mixer. (Alternative pin assignment)
Address= 8’h6B
Output Pixclk Delay Configuration
7-bit
6-bit
0
5-bit
4-bit
3’h0
DLYMUX_PIXCLK1
3-bit
2-bit
0
1-bit
0-bit
3’h0
DLYMUX_PIXCLK0
DYLMUX_PIXCLK0: Programmable pixclk delay of CCIROUT_0.
(3’h0: zero delay  3’h7: max delay, add 0.6ns at every step)
DYLMUX_PIXCLK1: Programmable pixclk delay of CCIROUT_1.
(3’h0: zero delay  3’h7: max delay, add 0.6ns at every step)
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h6C
VD Power Down
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
VDPWD
N_3
VDPWD
N_2
VDPWD
N_1
VDPWD
N_0
VDPWDN_0: When 1, VD 0 into power down mode.
VDPWDN_1: When 1, VD 1 into power down mode.
VDPWDN_2: When 1, VD 2 into power down mode.
VDPWDN_3: When 1, VD 3 into power down mode.
Address= 8’h6D
VD Power On Rstz
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
VMPRS
T
VDPRST
3
VDPRST
2
VDPRST
1
VDPRST
0
VDPRST0: Write 1, reset VD 0.
VDPRST1: Write 1, reset VD 1.
VDPRST2: Write 1, reset VD 2.
VDPRST3: Write 1, reset VD 3.
VMPRST0: Write 1, reset Mixer.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h6E
IP Test Mode
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SW_VA
DCBYP
EN
SW_VA
DCTSTE
N
SW_PLL
BYPEN
SW_PLL
TSTEN
SW_MBI
SPATEN
VADCSEL
SW_MBISTPATEN: When 1, drive MBIST detail signal to chip IO pins.
SW_PLLTSTEN: When 1, drive PLL out clocks to chip IO pins.
SW_PLLBYPEN: When 1, bypass internal PLL out source.
SW_VADCTSTEN: When 1, drive VADCSEL indicated ADC outputs to chip IO pins.
SW_VADCBYPEN: When 1, bypass VADCBYPOPT indicated ADC with chip input ADC
signals.
VADC_SEL: valid for SW_VADCTSTEN
3’h0: VADC_doutA=VADC_dout1, VADC_doutB=VADC_dout2
3’h1: VADC_doutA=VADC_dout3, VADC_doutB=VADC_dout4
3’h2: VADC_doutA= VADCMX0_0 =>[VADC_dout1/VADC_dout2] mux
VADC_doutA= VADCMX0_1 =>[VADC_dout3/VADC_dout4] mux
3’h3: will drive VADC_0 analog IP Do [15:1], selected signal to
[VADC_doutA, VADC_doutB]
3’h4: will drive VADC_1 analog IP Do [15:1], selected signal to
[VADC_doutA, VADC_doutB]
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h6F
MBIST Status
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
BISTGO
MBDON
E
MBERR
_4
MBERR
_3
MBERR
_2
MBERR
_1
MBERR
_0
MBERR_0: When 1, memory of group 0 has error, Set by HW, write 1 to clear.
MBERR_1: When 1, memory of group 1 has error, Set by HW, write 1 to clear.
MBERR_2: When 1, memory of group 2 has error, Set by HW, write 1 to clear.
MBERR_3: When 1, memory of group 3 has error, Set by HW, write 1 to clear.
MBERR_4: When 1, memory of group 4 has error, Set by HW, write 1 to clear.
MBDONE: MBIST has finished self-test, Set by HW, write 1 to clear.
BISTGO: Write 1to start MBIST logic. HW auto clear this bit after MBIST done.
Address= 8’h70
ITDM Control
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
CCIRITMD
CCIRINE
N
CCIRINEN: When 1, enable ITDM function.
CCIRITMD: Video source from iTDM mode selected.
2’b00: CCIR656 .
2’b01: 54 TDM digital signal.
2’b1x: 108 TDM digital signal.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h71
CCIROUT_0 Otdm Configuration 1
7-bit
6-bit
0
5-bit
4-bit
3’h1
3-bit
2-bit
0
1-bit
0-bit
3’h0
CCIROMX0_1
CCIROMX0_0
CCIROMX0_0: The mux of CCIROUT_0’s channel 0 at OTDM mode.
CCIROMX0_1: The mux of CCIROUT_0’s channel 1 at OTDM mode.
Address= 8’h72
CCIROUT_0 Otdm Configuration 2
7-bit
6-bit
0
5-bit
4-bit
3’h3
3-bit
2-bit
0
1-bit
0-bit
3’h2
CCIROMX0_3
CCIROMX0_2
CCIROMX0_2: The mux of CCIROUT_0’s channel 2 at OTDM mode.
CCIROMX0_3: The mux of CCIROUT_0’s channel 3 at OTDM mode.
Address= 8’h73
CCIROUT_1 Otdm Configuration 1
7-bit
6-bit
0
5-bit
3’h1
CCIROMX1_1
4-bit
3-bit
0
2-bit
1-bit
0-bit
3’h0
CCIROMX1_0
CCIROMX1_0: The mux of CCIROUT_1’s channel 0 at OTDM mode.
CCIROMX1_1: The mux of CCIROUT_1’s channel 1 at OTDM mode.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h74
CCIROUT_1 Otdm Configuration 2
7-bit
6-bit
0
5-bit
4-bit
3-bit
3’h3
2-bit
1-bit
0
0-bit
3’h2
CCIROMX1_3
CCIROMX1_2
CCIROMX1_2: The mux of CCIROUT_1’s channel 2 at OTDM mode.
CCIROMX1_3: The mux of CCIROUT_1’s channel 3 at OTDM mode.
Address= 8’h75
IO/Clock Configuration
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
VMCLKSEL
ACLKP
OE
IRQOE
IRQOE: If using DQ14 as IRQ, set this bit as ‘1’
Otherwise, this bit is “don’t care”
ACLKPOE: Set as ‘1’ when I2S playback is to be enabled.
VMCLKSEL: Clock selection for video mixer.
2’h0: Mixer clock sources from internal PLL (PLL1). (Normal operation)
2’h1: Mixer clock sources from PLL1 with frequency divided by 2.
2’h2: Mixer clock sources from external pin No.126.
2’h3: Mixer clock sources from external pin No.126 with frequency divided
by 2.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h77
CHIP Status
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
PWRON
PWRON: Power On status. (RO)
Address= 8’h78
I2C Master Configuration
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
8’hB8
CH device address
CH0~CH3: i2c slave device address. (R/W)
-DM5885 device address will be {4’hC,4’h0}
-I2CMaster_0: device address will be {4’hC,4’h2}
-I2CMaster_1: device address will be {4’hC,4’h4}
-I2CMaster_2: device address will be {4’hC,4’h6}
-I2CMaster_3: device address will be {4’hC,4’h8}
-For broadcast I2CMaster_CH0~I2CMaster_CH3, device address
{4’HC,4’HE}
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h79
I2CM status
7-bit
6-bit
5-bit
0
0
MI2CRD
CMD
4-bit
3-bit
2-bit
1-bit
0-bit
2’h0
0
0
0
0
MI2CSEL
CHNAC
K3
CHNAC
K2
CHNAC
K1
CHNAC
K0
CHNACK0: CH0 I2C fail (RO, WC) .
CHNACK1: CH1 I2C fail (RO, WC) .
CHNACK2: CH2 I2C fail (RO, WC) .
CHNACK3: CH3 I2C fail (RO, WC) .
MI2CSEL: The device address is 0xCA and select which channel will be set.
-I2CMaster_CH0: device address will be {4’hC 4’ha} & {MI2CSEL=2’b00}.
-I2CMaster_CH1: device address will be {4’hC 4’ha} & {MI2CSEL=2’b01}.
-I2CMaster_CH2: device address will be {4’hC 4’ha} & {MI2CSEL=2’b10}.
-I2CMaster_CH3: device address will be {4’hC 4’ha} & {MI2CSEL=2’b11}.
MI2CRDCMD: When 1, the MI2C restart command enable.
Address= 8’h7F
SW FAST SWITCH
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
OFASTS
W_OPT
OFASTS
W_SEL3
OFASTS
W_SEL2
OFASTS
W_SEL1
OFASTS
W_SEL0
OFASTW_SEL0:valid when VD0 REG04[4]=1 and OFASTSW_OPT=1
set 0, select VIN1A as VD0 CVBS source
set 1, select VIN1B as VD0 CVBS source
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
OFASTW_SEL1:valid when VD1 REG04[4]=1 and OFASTSW_OPT=1
set 0, select VIN2A as VD1 CVBS source
set 1, select VIN2B as VD1 CVBS source
OFASTW_SEL2:valid when VD2 REG04[4]=1 and OFASTSW_OPT=1
set 0, select VIN3A as VD2 CVBS source
set 1, select VIN3B as VD2 CVBS source
OFASTW_SEL3:valid when VD3 REG04[4]=1 and OFASTSW_OPT=1
set 0, select VIN4A as VD3 CVBS source
set 1, select VIN4B as VD3 CVBS source
OFASTSW_OPT: valid when REG04[4]=1
Set 0, VD0-VD3 SW FASTSW control signal from OFASTSW_SEL0OFASTSW_SEL3
Set 1, VD0-VD3 SW FASTSW control signal from input pin
MPP0~MPP3
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Video ADC
Address= 8’h80
Video ADC 0 Configuration 1
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SWGAIN
_0
pd_v2
pd_v1
SW_sel_
2
SW_sel_
1
pd_v1: Power down VIN1A & VIN1B, active high.
pd_v2: Power down VIN2A & VIN2B, active high.
SWGAIN_0: Software programs VADC 0’s gain setting, active high. When low, the
VADC 0’ gain setting programmed by Hardware auto.
SW_sel_1: Software select active CVBS input. (0: VIN1A, 1: VIN1B)
SW_sel_2: Software select active CVBS input. (0: VIN2A, 1: VIN2B)
Address= 8’h81
Video ADC 0 Configuration 2
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
4’hA
0
0
0
0
bias_vadc12
SvideoC
_2B
SvideoC
_2A
SvideoC
_1B
SvideoC
_1A
bias_vadc12: VADC 0’s bias setting.
SvideoC_1A: Channel VIN1A chroma clamping. When 1, the analog clamping level is
set to 50% for chroma signal processing.
SvideoC_1B: Channel VIN1B chroma clamping. When 1, the analog clamping level is
set to 50% for chroma signal processing.
SvideoC_2A: Channel VIN2A chroma clamping. When 1, the analog clamping level is
set to 50% for chroma signal processing.
SvideoC_2B: Channel VIN2B chroma clamping. When 1, the analog clamping level is
set to 50% for chroma signal processing.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h82
Video ADC 0 Configuration 3
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SW_gain1B
SW_gain1A
SW_gain1A: VIN1A’s gain value, valid when REG80[2]=1.
SW_gain1B: VIN1B’s gain value, valid when REG80[2]=1.
Minimum gain is set by 4’h0. Maximum gain is set by 4’hf.
The characteristic is the same as REG83
Address= 8’h83
Video ADC 0 Configuration 4
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SW_gain2B
SW_gain2A
SW_gain2A: VIN2A’s gain value, valid when REG80[2]=1.
SW_gain2B: VIN2B’s gain value, valid when REG80[2]=1.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h84
Video ADC 0 Configuration 5
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
clmp1B
clmp1A
Clmp1A: VIN1A’s clamp value.
Clmp1B: VIN1B’s clamp value.
The clamp can be used to adjust the sync tip value to the nominal value of 20.
Address= 8’h85
Video ADC 0 Configuration 6
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
Clmp2B
clmp2A
Clmp2A: VIN2A’s clamp value.
Clmp2B: VIN2B’s clamp value.
Address= 8’h86
Video ADC 1 Configuration 1
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SWGAIN
_1
pd_v4
pd_v3
SW_sel_
4
SW_sel_
3
pd_v3: Power down VIN3A & VIN3B, active high.
pd_v4: Power down VIN4A & VIN4B, active high.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
SWGAIN_1: Software programs VADC 1’s gain setting, active high. When low, the
VADC 1’ gain setting programmed by Hardware auto.
SW_sel_3: Software select active CVBS input. (0: VIN3A, 1: VIN3B)
SW_sel_4: Software select active CVBS input. (0: VIN4A, 1: VIN4B)
Address= 8’h87
Video ADC 1 Configuration 2
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
4’hA
0
0
0
0
bias_vadc34
SvideoC
_4B
SvideoC
_4A
SvideoC
_3B
SvideoC
_3A
bias_vadc34: VADC 1’s bias setting.
SvideoC_3A: Channel VIN3A chroma clamping. When 1, the analog clamping level is
set to 50% for chroma signal processing.
SvideoC_3B: Channel VIN3B chroma clamping. When 1, the analog clamping level is
set to 50% for chroma signal processing.
SvideoC_4A: Channel VIN4A chroma clamping. When 1, the analog clamping level is
set to 50% for chroma signal processing.
SvideoC_4B: Channel VIN4B chroma clamping. When 1, the analog clamping level is
set to 50% for chroma signal processing.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h88
Video ADC 1 Configuration 3
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SW_gain3B
SW_gain3A
SW_gain3A: VIN3A’s gain value, valid when REG86[2]=1.
SW_gain3B: VIN3B’s gain value, valid when REG86[2]=1.
Address= 8’h89
Video ADC 1 Configuration 4
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SW_gain4B
SW_gain4A
SW_gain4A: VIN4A’s gain value, valid when REG86[2]=1.
SW_gain4B: VIN4B’s gain value, valid when REG86[2]=1.
Address= 8’h8A
Video ADC 1 Configuration 5
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
Clmp3B
Clmp3A
Clmp3A: VIN3A’s clamp value.
Clmp3B: VIN3B’s clamp value.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h8B
Video ADC 1 Configuration 6
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
1-bit
0-bit
Clmp4B
Clmp4A
Clmp4A: VIN4A’s clamp value.
Clmp4B: VIN4B’s clamp value.
Address= 8’h8C
Video ADC LPF Option
7-bit
6-bit
5-bit
4-bit
0
0
0
0
3-bit
2-bit
2’h0
2’h0
lpf_34
lpf_12
lpf_12: VADC 0 LPF selected.
lpf_34: VADC 1 LPF selected.
lpf_xx: 2’h0: 6MHz
2’h1: 9MHz
Others: bypass
Address= 8’h8D
VADC Clk Delay Configuration 1
7-bit
6-bit
0
5-bit
3’h0
DLYMUX_ANA34
Final
Doc No: DM5885-DS-F01
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4-bit
3-bit
0
2-bit
1-bit
0-bit
3’h0
DLYMUX_ANA12
70
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
DLYMUX_ANA12: Programmable delay of digcore aclk_out0 from aclk_0.
(3’h0: zero delay  3’h7: max delay, add 0.6ns at every step)
DLYMUX_ANA34: Programmable delay of digcore aclk_out1 from aclk_1.
(3’h0: zero delay  3’h7: max delay, add 0.6ns at every step)
Address= 8’h8E
VADC Clk Delay Configuration 2
7-bit
6-bit
0
5-bit
4-bit
3-bit
3’h0
2-bit
0
1-bit
0-bit
3’h0
DLYMUX_ANA54
DLYMUX_ANA27
DLYMUX_ANA27: Programmable delay of digcore aclk27_out from aclk27.
(3’h0: zero delay  3’h7: max delay, add 0.6ns at every step)
DLYMUX_ANA54: Programmable delay of digcore aclk54_out from aclk54.
(3’h0: zero delay  3’h7: max delay, add 0.6ns at every step)
Address= 8’h8F
VADC Digcore Config
7-bit
6-bit
5-bit
4-bit
3-bit
0
0
0
0
0
2-bit
1-bit
0-bit
3’h0
DLYMUX_VD
DLYMUX_VD: Programmable delay of VD clk.
(3’h0: zero delay  3’h7: max delay, add 0.6ns at every step)
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
PLL
Formula:
CLK_OUT = XIN * (M+2)/[(N+2)*OD*2]
Where CLK_OUT: PLL output frequency
XIN: PLL input frequency.
M: The numerator of PLL formula.
[N, OD]: The denominator of PLL formula.
Attention:
1. 100MHz <= CLK_OUT * OD <= 250MHz
2. 1MHz <= XIN/(N+2)<=25MHz
3. OD >=1
Truth Table:
PD
0
0
Don’t Care
Don’t Care
Other
BP
0
0
1
Don’t Care
OE
0
0
0
1
CLK_OUT
CLK_OUT
XIN
XIN
0
Undefined
PD: Power down control; Active high.
BP: Bypass XIN to CLK_OUT; Active high.
OE: CLK_OUT enable pin, Active low.
Address= 8’h90
SW PLL Control
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SWPLL2
SWPLL1
SWPLL
RST
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
SWPLL1: set PLL1 input configuration from SWPLL1_XX set, otherwise hard wired with
chip default vale. (108MHz)
SWPLL2: set PLL2 input configuration from SWPLL2_XX set, otherwise hard wired with
chip default vale. (74.25MHz)
SWPLLRST: set 1, chip will enter a reset mode waiting for PLL stable in 1ms. After that,
SW needs to re-program all register setting except PLL configuration.
Address= 8’h91
SW PLL Config
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SWPLL2
_OE
SWPLL1
_OE
SWPLL2
_PD
SWPLL2
_BP
SWPLL1
_PD
SWPLL1
_BP
2-bit
1-bit
0-bit
SWPLL1_BP: PLL1_BP SW program source.
SWPLL1_PD: PLL1_PD SW program source.
SWPLL2_BP: PLL2_BP SW program source.
SWPLL2_PD: PLL2_PD SW program source.
SWPLL1_OE: PLL1_OE SW program source.
SWPLL2_OE: PLL2_OE SW program source.
Address= 8’h92
SWPLL1 M
7-bit
6-bit
5-bit
4-bit
3-bit
8’h0
SWPLL1_M[7:0]
SWPLL1_M: PLL1_M SW program source.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h93
SWPLL1_N
7-bit
6-bit
5-bit
0
0
0
4-bit
3-bit
2-bit
1-bit
0-bit
2-bit
1-bit
0-bit
2-bit
1-bit
0-bit
5’h0
SWPLL1
_M[8]
SWPLL1_N
SWPLL1_N: PLL1_N SW program source
Address= 8’h94
SWPLL2_M
7-bit
6-bit
5-bit
4-bit
3-bit
8’h0
SWPLL2_M[7:0]
SWPLL2_M: PLL2_M SW program source
Address= 8’h95
SWPLL2_N
7-bit
6-bit
5-bit
0
0
0
4-bit
SWPLL2
_M[8]
3-bit
5’h0
SWPLL2_N
SWPLL2_N: PLL2_N SW program source
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h96
SWPLL_OD
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
4’h0
4’h0
SWPLL2_OD
SWPLL1_OD
0-bit
SWPLL1_OD: PLL1_OD SW program source
SWPLL2_OD: PLL2_OD SW program source
DM5885 PLL SETTINGS Ref: 27MHz
Ref: 27MHz
108 MHz
74.25 MHz
M
14
20
N
0
0
OD
1
2
PD
0
0
OE
0
0
BP
0
0
Audio ADC/DAC
Address= 8’hF0
Audio ADC/DAC Test Mode
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
ADAC_
mute
ADAC_r
eset
ADAC_p
d
AADC_t
est
AADC_r
eset
AADC_reset: Audio ADC reset. (R/W: Active high)
AADC_test: Audio ADC test pin.
ADAC_pd: Audio DAC power down. (R/W: Active high)
ADAC_reset: Audio DAC reset. (R/W: Active high)
ADAC_mute: Audio DAC mute. (R/W: Active high)
Final
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Address= 8’hF1
Audio DAGC Config 1
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
4’h0
4’h0
AADC_DAGC_2
AADC_DAGC_1
0-bit
AADC_DAGC_1: Audio ADC 1 digital gain control.
AADC_DAGC_2: Audio ADC 2 digital gain control.
ADAC_DAGC_X[3:0], MIXGAIN_X[3:0]
Final
Doc No: DM5885-DS-F01
August 19, 2015
Set
Real Gain
dB
Set
Real Gain
dB
4’h0
0
-
4’h8
1.00
0
4’h1
0.125
-18.06
4’h9
1.25
1.94
4’h2
0.25
-12.04
4’hA
1.5
3.52
4’h3
0.375
-8.52
4’hB
1.75
4.86
4’h4
0.5
-6.02
4’hC
2.00
6.02
4’h5
0.625
-4.08
4’hD
2.25
7.04
4’h6
0.75
-2.50
4’hE
2.50
7.96
4’h7
0.875
-1.16
4’hF
2.75
8.79
76
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’hF2
Audio DAGC Configuration 2
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
4’h0
4’h0
AADC_DAGC_4
AADC_DAGC_3
0-bit
AADC_DAGC_3: Audio ADC 3 digital gain control.
AADC_DAGC_4: Audio ADC 4 digital gain control.
Address= 8’hF3
Audio DAGC Configuration 3
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
4’h0
4’h0
AADC_DAGC_P
AADC_DAGC_5
0-bit
AADC_DAGC_5: Audio ADC 5 digital gain control.
AADC_DAGC_P: Audio ADC digital gain control, source is selected from REGF8:
ADAC_SRC .
Address= 8’hF4
Audio ADC Format
7-bit
6-bit
5-bit
4-bit
0
0
0
0
AADC_
MULCH
3-bit
2-bit
1-bit
0-bit
2’h0
0
0
AADC_FSRATE
AADC_I
2SMOD
E
AADC_I2SMODE: (Digital I2S/DSP record interface): (master only)
1’b0: I2S mode
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
1’b1: DSP mode
AADC_FSRATE: (Digital I2S/DSP record interface)
2’b00: 48KHz
2’b01: 24KHz
2’b10: 16KHz
2’b11: 8KHz
AADC_MULCH: When 1, out 5 channels in record path.
When 0, out 2 channels in record path.
Address= 8’hF5
MIX Gain Configuration 1
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
4’h0
4’h0
MIXGAIN_2
MIXGAIN_1
0-bit
MIXOUT =
AIN1 * ADC_DAGC_1 * MIXGAIN_1 + AIN2 * ADC_DAGC_2 * MIXGAIN_2 +
AIN3 * ADC_DAGC_3 * MIXGAIN_3 + AIN4 * ADC_DAGC_4 * MIXGAIN_4 +
AIN5 * ADC_DAGC_5 * MIXGAIN_5 + ADATP * MIXGAIN_P
Address= 8’hF6
MIX Gain Configuration 2
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
4’h0
4’h0
MIXGAIN_4
MIXGAIN_3
0-bit
Refer to REG F5
Final
Doc No: DM5885-DS-F01
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’hF7
MIX Gain Configuration 3
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
4’h0
4’h0
MIXGAIN_P
MIXGAIN_5
0-bit
Refer to REG F5
Address= 8’hF8
Audio DAC Format
7-bit
6-bit
5-bit
0
3’h0
ADAC_T
IME
ADAC_SRC
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
ADAC_I
2SMOD
E
ADAC_P
RCH
ADAC_FSRATE
ADAC_PRCH: When ADAC selecting the playback input source and PLAY_PRCH=0,
ADAC chooses the playback left channel. Otherwise use playback right
channel.
ADAC_I2SMODE: (Digital I2S/DSP playback interface): (mater only).
1’b0: I2S mode
1’b1: DSP mode.
ADAC_FSRATE: (Digital I2S/DSP playback interface):
2’b00: 48KHz
2’b01: 24KHz
2’b10: 16KHz
2’b11: 8KHz
DAC_SRC:
3’h0: ADATP (playback)
Final
Doc No: DM5885-DS-F01
August 19, 2015
79
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
3’h1: MIXOUT
3’h2: AIN_1
3’h3: AIN_2
3’h4: AIN_3
3’h5: AIN_4
3’h6: AIN_5
ADAC_TIME:
When 1, use ADAC_FSRATE, ADAC mode to generate ACLKP/ASYNP.
Otherwise share the same timing signals with ACLKR/ASYNR.
Address= 8’hF9
Audio ADC/DAC Test Mode
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
AADC_p
d5
AADC_p
d4
AADC_p
d3
AADC_p
d2
AADC_p
d1
1-bit
0-bit
AADC_pdX: Power down of Audio ADC X, active high.
Address= 8’hFA
Audio ADC/DAC Bias
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
4’h0
4’h0
ADAC_bias
AADC_bias
ADAC_bias: Audio DAC’s bias setting.
AADC_bias: Audio ADC’s bias setting.
Final
Doc No: DM5885-DS-F01
August 19, 2015
80
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’hFB
Audio ADC/DAC Test Mode
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
3’h0
0
0
0
AADCSEL
SW_AU
DIOTST
EN
1-bit
0-bit
2’h0
VADCBYPOPT
VADCBYPOPT: Video ADC bypass source option
2’b00: external A/B channel mode.
2’b01: external only A channel mode.
2’b10: external ADI mode.
SW_AUDIOTSTEN: When 1, chip enter to Audio Test mode, and drives Audio
ADC/DAC test signal to I/O pins.
AADCSEL: Under Audio ADC test mode.
3’h0: AADC_1[15:0] selected to output pins.
3’h1: AADC_2[15:0] selected to output pins.
3’h2: AADC_3[15:0] selected to output pins.
3’h3: AADC_4[15:0] selected to output pins.
3’h4: AADC_5[15:0] selected to output pins.
Final
Doc No: DM5885-DS-F01
August 19, 2015
81
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’hFD
I2S Data Width
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1
0
0
0
0
0
FCLK_E
N
I2SDAT
AWIDTH
1-bit
0-bit
2’h0
FCLK_EN: Audio clock enable, active low.
I2SDATAWIDTH: 0: The I2S/DSP interface uses 16-bit data.
1: The I2S/DSP interface uses 8-bit data.
Address= 8’hFE
Audio Record 2
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
ADATR_
2EN
ADATR_2EN: Set as 1 to enable audio record channel 2 (using MI2CD1)
Address= 8’hFF
REVNUM
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
8’h65
REVNUM
Final
Doc No: DM5885-DS-F01
August 19, 2015
82
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Video Decoder
HSYNC signal:
BLANK TIP
HSYNC_LEVEL
HSYNCTH
SYNC TIP
HSYNC
signal
HSYNC_LEVEL=SYNC TIP + HSYNCTH
Address= 8’h00
VD Control
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
1
0
1
0
BBRSTZ
IFLDFA
STSW
FASTS
WEN
S_Video
ADC_A
ADI_AD
C
EN
SRSTZ
SRSTZ: SW reset video decoder, WO
EN: Enable Video decoding function
S_Video: input signal is S-Video
FASTSWEN: Enable fast switch function
IFLDFASTSW: Set 1 : Fast switch boundary at every field end. Only Valid when
REG04[3] : 1’b0.
Set 0: Fast switch boundary at frame end.
BBRSTZ: BB reset only, WO
Final
Doc No: DM5885-DS-F01
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h01
WATCHSEL
7-bit
6-bit
5-bit
4-bit
4’hf
3-bit
2-bit
0
0
3-bit
2-bit
1-bit
0-bit
2’b01
AGC_LMT
AGC_LMT: Analog AGC range
AGC
Address= 8’h02
AGC
7-bit
6-bit
5-bit
4-bit
4’h0
1
AGC_gain
1-bit
0-bit
0
1
1
AGC_DT
RACKE
N
HWAGC
EN
SYNCC
AGCEN
2-bit
1-bit
0-bit
SYNCCAGCEN: Set 1, enable CAGC gain update.
HWAGCEN: Hardware AGC enable
AGC_DTRACKEN: Dynamic sync tip tracking enable
AGC_gain: SW set AGC gain, RW
Address= 8’h03
AGCDOWN_TH
7-bit
6-bit
5-bit
4-bit
3-bit
8’h63
AGCDOWNTH[7:0]
AGCDOWNTH: ADC couldn’t larger than 867, if it is, will decrease the agc_gain.
Final
Doc No: DM5885-DS-F01
August 19, 2015
84
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h04
AGCDOWN_TH
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
0
0
0
1
0
0
FASTSWOPT
OFASTS
W
1-bit
0-bit
2’h3
AGCDOWNTH[9:8]
OFASTSW: Set 1: FASTSW control from input PIN(MPOUT).
Set 0: FASTSW source from internal logic related to FASTSWOPT, RW
FASTSWOPT: Set fast switch frame length ((FASTSWOPT+1)x8), RW
Video Detection Misc
Address= 8’h05
HSYNCTH
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
8’h30
HSYNCTH
HSYNCTH:
Set horizontal sync threshold level
Address= 8’h06
Vdet_misc
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
1
0
1
1
BLACK
OUT
SETUP_
7.5IRE
OCCIRE
N
ColorPO
UT
MONOU
T
MUKSEL
ColorPOUT: Set 1, VD will drive Color panel when no video signal detected, otherwise
drive black panel. Color panel setting see 0x2A[6:4]
Final
Doc No: DM5885-DS-F01
August 19, 2015
85
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
OCCIREN: Set 1, VD will out CCIR656
SETUP_7.5IRE: Set 1, add 7.5 IRE to the BLANK_TIP
BLACKOUT: Set 1, VD will drive black panel or blue panel when no video signal
detected.
MONOUT: force CCIR656 Cb=128, Cr=128
Color Killer
Address= 8’h08
ColorKill TH
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
8’h20
CBDIFFTH[7:0]
CBDIFFTH:
Set the color burst difference threshold
2D Comb Filter
Address= 8’h09
Com2D_CFG
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
FORCE_
VCOMB
NOTCH
FLTSEL
DIS_VC
OMB
FORCE_
MONO
DIS_VCOMB: Set 1 to disable vertical comb filter
NOTCHFLTSEL: Set 0, use the wide band notch filter
Set 1, use the narrow band notch filter
FORCE_MONO: Set 1 to force the MONO signal mode.
Final
Doc No: DM5885-DS-F01
August 19, 2015
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h0C
PAL SW CFG
7-bit
6-bit
5-bit
4-bit
3-bit
2’h0
2-bit
1-bit
0
0-bit
0
Y_SHARP_GAIN
PALSW
OPT
PALSWOPT: Set 1 to use standard pal switch define to demodulation.
For line lock camera, set this bit to 1.
Y_SHARP_GAIN:
2’h0 : no sharpness function
2’h1: sharpness gain 0.5
2’h2: sharpness gain 1
2’h3: sharpness gain 2
Address= 8’h10
VD Decoder status
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
PAL_Nc
PALI,B,B1,G
,H,D/
PAL_N
PAL_M
PAL_60
NTSC443
NTSCJ/NTSCM
COLOR
KILL_52
5
COLOR
KILL_62
5
The register show the video decoded status
RO. Set 1 to enable SW force mode.
Final
Doc No: DM5885-DS-F01
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87
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h11
VD_STS
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
CLKLO
CK_STS
T
DET_NO
NILT
DET_NONILT: RO. Detect the non-interlaced signal format.
CLKLOCK_STST: RO. Clock offset lock status
Address= 8’h12
DAGC_LMT
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
4’h3
4’hf
CLKOFF_LOCK
DAGC_LMT
0-bit
DAGC_LMT: Digital AGC range
CLKOFF_LOCK: Clock offset locking function. 4’h0: always tracking
Others: clock offset lock within CLKOFF_LOCK * 8 ppm.
Address= 8’h13
VD_CFG
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
1
1
0
1
0
0
1
SWFAR
54MD
HWFAR
54OPT
GAINLO
CK_OPT
CLKOFF
DIS
CBADJ
BLANK_
SHIFTE
N
ALINEL
OCK
CLKOFF
_TRACK
EN
CLKOFF_TRACKEN: CLKOFFSET tracking enable
Final
Doc No: DM5885-DS-F01
August 19, 2015
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
ALINELOCK: active line lock option, fixed line start position.
BLANK_SHIFTEN: set 1, blank level will be modified according to color burst mean
value per line.
CBADJ: Color burst adjust
CLKOFFDIS: Disable clock offset tracking function
GAINLOCK_OPT: Enable gain locking function after 16 frame decoded.
HWFAR54OPT: Set 1, FAR4FS will operate in 54Mhz when detecting 4.43 subcarrier
SWFAR54MD: Software force FAR4FS operate in 54Mhz.
Address= 8’h14
VD_CFG
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
1
0
1
VDETOP
T
LTRACK
OPT
CLKLO
CKOPT
LLCFASTMD
CLKLOCKOPT:
Set 0 : Always tracking clock offset when
abs(clkoffset)> CLKOFF_LOCK (REG12[7:4])
Set 1 : keep tracking until first time
abs(clkoffset)< CLKOFF_LOCK(REG12[7:4])
LTRACKOPT:
Set 1: Hardware continues active line (video) decoding when miss
valid HSYNC signal until video loss.
Set 0: Hardware performs active line (video) decoding until valid
HSYNC signal detected.
VDETOPT:
Set 1: using rising edge of HSYNC signal as line detection timing.
Set0: using falling edge of HSYNC signal as line detection timing.
For long cable application, set this bit to 1.
LLCFASTMD[1:0]:
Line lock Auto Detection stable period. Valid when REG3B[5]=1.
Final
Doc No: DM5885-DS-F01
August 19, 2015
89
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Set 0: check line lock mode right after decode started
Set 1: check line lock mode after 8 frames decoded.
Set 2, 3: check line lock mode after 16 frames decoded.
Address= 8’h15
CLKOFF_CTL
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
1
1
0
0
CLKFRA
CEN
FIXHSY
NC_MD
L
SWFIXC
LOCKO
FF
SWFIXCLOCKOFF: Set 1, SW fixed clock offset. Force clock offset value=
{REG25[4:0],REG24[7:0],REG23[7:0]}.
FIXHSYNC_MDL: Set 1, fixed the HSYNC_LEVEL to be REG05 HSYNCTH.
CLKFRACEN: Set 1, enable fraction clock offset tracking.
Address= 8’h17
CTI gain
7-bit
6-bit
0
0
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
6’d10
HMIDTR
ACK
HMIDTRACK: Set 1: tracking BLANK TIP each line at Front Porch Blanking position
(REG4B[7:0]).
Set 0: tracking BLANK TIP at CVBS serration period.
Final
Doc No: DM5885-DS-F01
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h18
LOWTRACK
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
FSHYBC
OPT
DISCOL
KILL
NONINT
EN
CAGCO
PT
TRHSYN
COPT
LOWTR
ACK
TRHSYN
CTH
TRHSYNCTH: Set 1: enable HW auto update HSYNCTH during video detection.
Set 0: use fix HSYNCTH (REG05[7:0]) during video detection.
LOWTRACK: Set 1: tracking SYNC TIP per line(s) from LOWLEVEL TRACKER.
Set 0: tracking SYNC TIP at CVBS serration period.
TRHSYNCOPT: Set 1: use fix HSYNCTH (REG05) during video detection
Set 0: enable HW auto update HSYNCTH during video detection.
CAGCOPT: Set 1 to enable color AGC.
NONINTEN: Set 1 to enable auto detect non-interlaced signal.
DISCOLKILL: Set 1 to disable auto detect color kill mode
FSHYBCOPT: ONLY valid under FASTSWEN.
Set 1: Keep previous tracked HSYNCTH
Set 0: use REG05 as HSYNCTH
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h20
AGC gain
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
DAGC Gain
AAGC Gain
AAGC Gain: Analog AGC gain setting, RO
DAGC Gain: Digital AGC gain setting, RO
Address= 8’h21
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SYNC_TIP[7:0]
SYNC_TIP: RO
Address= 8’h22
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
BLANK_TIP[7:0]
BLANK_TIP: RO
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h23
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
CLKOFF[7:0]
CLKOFF: RO, internal 2’s compliment clock offset tracking status. Unit (ppm)
Address= 8’h24
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
CLKOFF[15:8]
CLKOFF: RO, internal 2’s compliment clock offset tracking status. Unit (ppm)
Address= 8’h25
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SYNC_TIP[20:16]
SYNC_TIP: RO
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h26
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
BLANK_TIP[9:8]
SYNC_TIP[9:8]
BLANK_TIP: RO
SYNC_TIP: RO
Address= 8’h29
Blue Panel Select
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
PALBLP
ANL
NTSCBL
PANL
PALBLPANL:
Valid when REG06[3]=1. When no signal, SW sets PAL blue panel
out.
NTSCBLPANL:
Valid when REG06[3]=1. When no signal, SW sets NTSC blue panel
out.
When PALBPANL=0, NTSCBLPANL=0. HW takes PAL as default
mode.
Address= 8’h2A
VD_MISC
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
0
0
0
0
0
0
ColorOut
Final
Doc No: DM5885-DS-F01
August 19, 2015
1-bit
0-bit
2’h2
MPP_OPT
94
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
MPP_OPT: (Enable when GPOSEL (REG7A[7]) = 1’b1)
2’h0: drive field info to pin.
2’h1: drive Active info to pin.
2’h2: drive NOVID info to pin.
2’h3: drive FASTSW_SEL info to pin.
VD_MPP signal pin out:
(VD0,VD1,VD2,VD3)( MI2CD0, MI2CD1, MI2CD2, MI2CD3)
ColorOut: valid when REG06[3]=1 and REG06[0]=1.
3’h0: blue panel
3’h1: red panel
3’h2: white panel
3’h3: green panel
3’h4: magenta panel
3’h7: color rotation mode, blue  red 
white  green  magenta  black  blue…
Color Process
Address= 8’h2B
COLOR_EXT
7-bit
6-bit
0
0
5-bit
4-bit
2’h1
3-bit
2-bit
1-bit
0-bit
0
0
0
1
NTSC_C
CIREXT
EXT_CO
LOR
CCIRBL
ANKOP
T
EXT_COLOR: Set 1, Y/Cb/Cr value from 8’h1~8’hfe
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
NTSC_CCIREXT: Set 1 in NTSC mode, CCIR656 output 487 active line.
CCIRBLANKOPT: Set 1: output blanking period close to standard CCIR656.
Set 0: with short V blank lines before active field start.
Address= 8’h2C
Hue
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
2-bit
1-bit
0-bit
8’h0
Hue[7:0]
Hue:
Hue[9:0] = {REG33[1:0],REG2C[7:0]}
10’h0~10’h3ff 
0~360 degree
Address= 8’h2D
Saturation
7-bit
6-bit
5-bit
4-bit
3-bit
8’h10
Saturation
Saturation: unsigned, Range : 0 ~ 15.9375
8’hff : maximum, about x16 color intensity.
8’h00: (no color)
Final
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Address= 8’h2E
Contrast
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
2-bit
1-bit
0-bit
8’h80
Contrast
Contrast: unsigned, Range : 0~2
8’hff: maximum (x2) contrast
8’h80: original signal (x1)
8’h00: minimum contrast
Address= 8’h2F
Brightness
7-bit
6-bit
5-bit
4-bit
3-bit
8’h00
Brightness
Brightness: singed
8’h7f: brightest
8’h80: darkest
Final
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Address= 8’h30
INT Mask
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
MDCHG
_1_MAS
K
VLOST_
1_MASK
VDET_1
_MASK
MDCHG
_0_MAS
K
VLOST_
0_MASK
VDET_0
_MASK
VDET_0_MASK: Set 1, enable register 0x31 VDET_0 interrupt function, RW
VLOST_0_MASK: Set 1, enable register 0x31 VLOST_0 interrupt function, RW
MDCHG_0_MASK: Set 1 enable register 0x31 MDCHG_0 interrupt function, RW
VDET_1_MASK: Set 1 to enable register 0x31 VDET_1 interrupt function, RW
VLOST_1_MASK: Set 1 enable register 0x31 VLOST_1 interrupt function, RW
MDCHG_1_MASK:Set 1 enable register 0x31 MDCHG_1 interrupt function, RW
Address= 8’h31
INT status
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
MDCHG
_1
VLOST_
1
VDET_1
MDCHG
_0
VLOST_
0
VDET_0
VDET_0: when detect video signal, the interrupt set, set by HW, set 1 to clear
VLOST_0: when lose video signal, the interrupt set, set by HW, set 1 to clear
MDCHG_0: when detect video signal change, the interrupt set, set by HW, set 1 to clear
VDET_1: valid for fast switch mode channel B, when detect video signal, the interrupt
set, set by HW, set 1 to clear
VLOST_1: valid for fast switch mode channel B, when lose video signal, the interrupt set,
set by HW, set 1 to clear
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
MDCHG_1: valid for fast switch mode channel B, when detect video signal change
format, the interrupt set, set by HW, set 1 to clear
Address= 8’h33
HUE
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
Hue[9:8]
Hue: Hue[9:0] = {REG33[1:0],REG2C[7:0]}
10’h0~10’h3ff 
0~360 degree
Address= 8’h34
FIELD OPTION
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
FIELD_I
NV
FIELD_
ONLY
FIELD_ONLY: CCIR656 signal output field 0 only
FILED_INV: Inverse output CCIR656 signal field
Address= 8’h35
Chroma Average
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
1
CAVNTS
CMD
CAVPAL
MD
CAVNTSCMD: Set 1, enable NTSC mode Cb/Cr line average.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Set 0, disable.
CAVPALMD: Set 1, enable PAL mode Cb/Cr line average.
Set 0, disable.
Address= 8’h36
MASK CCIR656 LINE
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
1
MASKA
LL
PAL_M
SK3
PAL_MSK3: Set 1, it will mask field 0 and 1 last lines according to REG37
MASKALL:
mask all active
Address= 8’h37
MASK LINE
7-bit
6-bit
0
5-bit
3’h3
MSK_LINE_F1
4-bit
3-bit
0
2-bit
1-bit
0-bit
3’h3
MSK_LINE_F0
MSK_LINE_F0:
When REG36[0] = 1, Mask Field 0 last number of active lines (0-7)
MSK_LINE_F1:
When REG36[0] = 1, Mask Field 1 last number of active lines (0-7)
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h38
MONO TH
7-bit
6-bit
5-bit
1
0
0
4-bit
3-bit
2-bit
1-bit
0-bit
5’d31
MONO_
EN
MONO_TH
MONO_TH: MONO mode AGC threshold. AGC max value 30. when set MONO_TH 31.
AGC will always less than MONO_TH.
MONO_EN:
Set 0, when no valid color burst detected.
Output CCIR656 Y through Notch filter.
Set 1, when no valid color burst detected. Output CCIR656
Y through Notch filer if AGC_GAIN>=MONO_TH, otherwise output
CCIR656 Y with ADC data.
When No valid color burst detected (color kill mode). Output
CCIR656 Cb/Cr with 128 (no color).
Address= 8’h39
COLOR BURST DETECT
7-bit
6-bit
0
5-bit
4-bit
3-bit
2-bit
1-bit
3’h4
4’h5
COLBSTCYC
COLBSTHSEL
0-bit
COLBSTHSEL:Color Burst detection threshold.
4’h0:COLBSTH = 0.125*(BLANK TIP – SYNC TIP)
4’h1:COLBSTH = 0.25*(BLANK TIP – SYNC TIP)
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
4’h2:COLBSTH = 0.375*(BLANK TIP – SYNC TIP)
4’h3:COLBSTH = 0.5*(BLANK TIP – SYNC TIP)
4’h4:COLBSTH = 0.09375*(BLANK TIP – SYNC TIP)
4’h5:COLBSTH = 0.078125*(BLANK TIP – SYNC TIP)
4’h6:COLBSTH = 0.0625*(BLANK TIP – SYNC TIP)
4’h7:COLBSTH = 0.03125*(BLANK TIP – SYNC TIP)
4’h8:COLBSTH = 0
When color burst peak to peak value larger than COLBSTHSEL, it’s
been considered a good color burst signal cycle.
COLBSTCYC:
When COLBSTCYC numbers of valid color bust cycle detected, VD
will decode video with color and Color AGC will optionally started.
Otherwise will enter color kill mode.
Address= 8’h3A
CAGC
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
1
0
0
0
0
0
0
0
CAGCE
N
CAGCL
OCKOP
cagc_gain
cagc_gain: RO. Chroma gain value. [5:2] integer, [1:0] fractional.
(max 15.75, min 1)
CAGCLOCKOPT: Set 1, enable color AGC tracking until CAGC gain stable.
Set 0, color AGC tracking for first 15 video decoded frames.
CAGCEN : Set 1, enable color AGC.
Final
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Address= 8’h3B
Line Lock Camera
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
CAMLO
CKOPT
LOCKC
AM_DET
HLOCK
DET1
1-bit
0-bit
ACTSHIFT
ACTSHIFT: Active region shift, 2’s compliment (-16~15)
HLOCKDET1: Set 1, to enable auto-detect Line Lock camera.
LOCKCAM_DET: RO, Line lock camera detected. (RO)
CAMLOCKOPT: Set 1, when line lock camera used.
Address= 8’h3C
LLOCKTH
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
8’d20
LLOCKTH
LLOCKTH:
Line Lock auto detection threshold, valid only when 0x3B[5]=1.
When REG13[1]=1, line boundary difference within a field larger than
LLOCKTH, Line Lock Camera detected.
Note: when clock offset tracking unstable and REG13[1]=1, line boundary
difference might be large within a field.
Final
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Address= 8’h3D
VD_CFG
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
ORSTO
PT
OBFOV
F
OBFUD
F
LLFAR4
FSOPT1
LLFAR4
FSOPT
LLFAR4FSOPT: Set 1, decode video chroma without clock offset compensation.
Set 0, decode video chroma after clock offset compensation.
Set this bit to one for Line Lock Camera.
LLFAR4FSOPT1: Set 1, Auto adjust the active region related to clock offset.
When force line lock mode, set this bit to 1;
OBFUDF:
RO. CCIR output buffer under flow.
OBFOVF:
RO. CCIR output buffer over flow.
ORSTOPT:
Set 1, Reset CCIR output buffer when output buffer overflow or underflow.
Address= 8’h3D
OUT BUFFER
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
8’h1a
OBFTH
OBFTH: CCIR656 output buffer ready threshold.
Once CCIR656 output buffer count is larger than
OBFTH, starts output CCIR656 active region.
PS. CCIR656 output buffer max length is 48, set OBFTH around middle level
of buffer length.
Final
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Address= 8’h40
CCIROUT TYP EN
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
H_SAV_
ACT
CROPE
N
FLDCHI
DEN
EAVCHI
DEN
SWCHID
EN
SWCHIDEN: Valid when REG00[5]=1(FASTSWEN). Add SW channel ID
in first 4 data of active line, valid at fast switch mode.(field/frame)
EAVCHIDEN: Valid when REG00[5]=1(FASTSWEN) Add channel ID in EAV[3:0] and
SAV[3:0], valid at fasts switch mode. (field/frame)
FLDCHIDEN: Valid when REG00[6:5]=2’h3 (IFLDFASTSW, FASTSWEN), output CVBS
source A to field 0, output CVBS source B to field 1.
CROPEN: Video cropping function enable.
H_SAV_ACT: Set 1, HSYNC signal will include SAV data, otherwise HSYNC signal
only at active region.
Address= 8’h41
Cropping Register
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
2’h0
2’h3
2’h0
2’h0
H_STR[9:8]
H_ACT[9:8]
V_STR[9:8]
V_ACT[9:8]
H_STR[9:8]:
It defined the number of pixels start after SAV.
H_ACT[9:8]:
It defined the number of active region.
V_STR[9:8]:
It defined VSYNC start after active region line.
V_ACT[9:8]:
It defined the number of VSYNC during active region.
H_STR + H_ACT < total number of pixels per line.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
V_STR + V_ACT < total number of lines per field.
Address= 8’h42
Cropping Register
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
2-bit
1-bit
0-bit
2-bit
1-bit
0-bit
2-bit
1-bit
0-bit
8’h0
H_STR[7:0]
Address= 8’h43
Cropping Register
7-bit
6-bit
5-bit
4-bit
3-bit
8’hC0
H_ACT[7:0]
Address= 8’h44
Cropping Register
7-bit
6-bit
5-bit
4-bit
3-bit
8’h0
V_STR[7:0]
Address= 8’h45
Cropping Register
7-bit
6-bit
5-bit
4-bit
3-bit
8’d240
V_ACT[7:0]
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h46
Cb/Cr Slicer
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
1
3’h2
SLICER
_EN
SLICER_RANGE
0-bit
SLICER_EN: CB/CR coring function enable.
SLICER_RANGE: Coring range (0 ~7). When 128 – SLICER_RANGE < (CB/CR) <
128+SLICER_RANGE, force the Chroma value to 128.
Address= 8’h4B
BLANK1TIP
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
8’hdc
BLANK1TIP
BLANK1TIP: valid when REG17[7]. Line Blanking sample position.
Address= 8’h4C
HSYNCLOWCYC
7-bit
6-bit
0
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
7’d20
HSYNCLOWCYC
HSYNCLOWCYC: When low level (signal smaller than HSYNC LEVEL) signal exists
over HSYNCLOWCYC, it’s considered as a HSYNC signal
Candidate.
Final
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Address= 8’h4D
LMARG27
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
1-bit
0-bit
8’h30
LMARG27
LMARG27: Sync signal detect margin after video detect.
Address= 8’h4E
MARG27
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
8’h30
MARG27
MARG27: Sync signal detect margin before video detect.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Video Mixer
Address= 8’hA0
Mixer Configuration
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0
0
0
0
4’h0
VMSLO
PT
VDSLOP
T
PALEXT
CCIRPR
OG0
OUT_SEL_0
0-bit
OUT_SEL_0: Mixer configuration select table. Valid for both Mixer_0 and Mixer_1.
4'h0
SD
Mode
4'h1
4'h2
0
0
1
0
2
3
1
1
4'h3
2
1
0
2
4'h4
3
0
4'h5
0
1
4'h8
HD
Mode
0
1
2
3
CCIRPROG0: when 1, enable mixer output from interlaced to progressive format
PALEXT: Only valid when OUT_SEL_0 = 4’h8.
When 1. output PAL SMPTE 274M resolution from 1920x1080 to 1920x1152.
Otherwise, output PAL SMPTE 274M resolution to 1920x1080
VDSLOPT: when 1, enable auto reset mixer video capture interface while internal CVBS
VD detecting signal loss.
VMSLOPT: when 1, enable auto rest mixer video capture interface while mixer video
capture interface detecting invalid CCIR656 signal.
Final
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Address= 8’hA1
Mixer Out Enable
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SOUT_E
N1
SOUT_E
N0
SOUT_EN0: Mixer 0 enable.
SOUT_EN1: Mixer 1 enable. Only valid when SD mixer out and OUTSEL_0 =4’h4 /4’h5.
Address= 8’hA2
Mixer Mode detect
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
PALMD
MODEC
HG
MDCHG
RST
SWFOR
CEMD
SWFORCEMD: when 1, will disable Mixer auto mode PAL/NTSC detect function.
(Output format depends on REGA2[7] by SW)
MDCHGRST: when 1, Mixer will auto reset if MODECHGE detected.
MODECHG: (RO) when 1 indicates the system change mode change from NTSC to PAL
or from PAL to NTSC.
PALMD: when SWFORCEMD=0 (PALMD RO), PALMD is a status of Mixer PAL/NTSC
auto detect result.
When SWFORCEMD=1 (PALMD RW), set PALMD to 0 force NTSC mode, set
PALMD to 1 force PAL mode.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’hA3
Mixer Output format Configuration
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
NTSC_C
CIREXT
_0
BLUEO
UT
BLUEOUT: Set 1 mixer output blue panel when no valid signal. See REGD3~REGD5 for
blue panel configuration.
NTSC_CCIREXT_0: valid under SD NTSC mode.
When 1. Mixer output 487 active line video.
Otherwise. Mixer output 480 active line video.
Address= 8’hA4
CCIR Input Line Length
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
0
0
0
0
0
0
1-bit
0-bit
2’h2
CCIRINLEN[9:8]
Address= 8’hA5
CCIR Input Line Length
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
8’hD0
CCIRINLEN[7:0]
CCIRINLEN[9:0]: Mixer capture interface cropping length. For 720H video, it might be
set to 720 or 704 or any multiple of 4. default 720.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’hA6
Mixer Output partition Config
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
CORVL
D_3
CORVL
D_2
CORVL
D_1
CORVL
D_0
CORVLD_0: set 1 to enable output partition 0 Left-Top coordinate(COR_X0,COR_Y0).
valid OUTSEL_0 = 4’h0, 4’h1, 4’h2, 4’h3, 4’h4, 4’h5 and 4’h8
CORVLD_1: set 1 to enable output partition 1 Left-Top coordinate(COR_X1,COR_Y1).
valid OUTSEL_0 = 4’h0, 4’h1, 4’h2, 4’h3, 4’h5 and 4’h8
CORVLD_2: set 1 to enable output partition 2 Left-Top coordinate(COR_X2,COR_Y2).
valid OUTSEL_0 = 4’h0, 4’h2, 4’h3, and 4’h8
CORVLD_3: set 1 to enable output partition 3 Left-Top coordinate(COR_X3,COR_Y3).
valid OUTSEL_0 = 4’h0, 4’h3 and 4’h8
Default value: SD mixer out  NTSC 720x480 and OUT_SEL_0 = 4’h0.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Please refer to the following figure.
COR_X0[9:0]: X coordinate of partition 0 Left-Top point.
Default value: 10’d0 (10’h0)
COR_Y0[9:0]: Y coordinate of partition 0 Left-Top point.
Default value: 10’d0 (10’h0)
COR_X1[9:0]: X coordinate of partition 1 Left-Top point.
Default value: 10’d360 (10’h168)
COR_Y1[9:0]: Y coordinate of partition 1 Left-Top point.
Default value: 10’d0 (10’h0)
COR_X2[9:0]: X coordinate of partition 2 Left-Top point.
Default value: 10’d0 (10’h0)
COR_Y2[9:0]: Y coordinate of partition 2 Left-Top point.
Default value: 10’d240 (10’hF0)
COR_X3[9:0]: X coordinate of partition 3 Left-Top point.
Default value: 10’d360 (10’h168)
COR_Y3[9:0]: Y coordinate of partition 3 Left-Top point.
Default value: 10’d240 (10’hF0)
Final
Doc No: DM5885-DS-F01
August 19, 2015
[COR_X0,COR_Y0]
[0,0]
[COR_X1,COR_Y1]
[360,0]
0
1
[COR_X2,COR_Y2]
[0,240]
[COR_X3,COR_Y3]
[360,240]
2
3
113
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’hA7
Mixer Output partition Coordinate
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
2’h0
2’h1
2’h0
2’h0
COR_Y1[9:8]
COR_X1[9:8]
COR_Y0[9:8]
COR_X0[9:8]
Please refer to the figure in register 0xA6.
Address= 8’hA8
Mixer Output partition Coordinate
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
1-bit
0-bit
8’h0
COR_X0[7:0]
Please refer to the figure in register 0xA6.
Address= 8’hA9
Mixer Output partition Coordinate
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
8’h0
COR_Y0[7:0]
Please refer to the figure in register 0xA6.
Final
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Address= 8’hAA
Mixer Output partition Coordinate
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
1-bit
0-bit
1-bit
0-bit
8’h68
COR_X1[7:0]
Please refer to the figure in register 0xA6.
Address= 8’hAB
Mixer Output partition Coordinate
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
8’h0
COR_Y1[7:0]
Please refer to the figure in register 0xA6.
Address= 8’hAC
Mixer Output partition Coordinate
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
2’h0
2’h1
2’h0
2’h0
COR_Y3[9:8]
COR_X3[9:8]
COR_Y2[9:8]
COR_X2[9:8]
Please refer to the figure in register 0xA6.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’hAD
Mixer Output partition Coordinate
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
1-bit
0-bit
1-bit
0-bit
8’h0
COR_X2[7:0]
Please refer to the figure in register 0xA6.
Address= 8’hAE
Mixer Output partition Coordinate
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
8’hF0
COR_Y2[7:0]
Please refer to the figure in register 0xA6.
Address= 8’hAF
Mixer Output partition Coordinate
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
8’h68
COR_X3[7:0]
Please refer to the figure in register 0xA6.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’hB0
Mixer Output partition Coordinate
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
1-bit
0-bit
8’hF0
COR_Y3[7:0]
Please refer to the figure in register 0xA6.
Address= 8’hB1
Mixer Output partition Coordinate
7-bit
6-bit
5-bit
4-bit
3-bit
3’h1
0
2-bit
3’h2
0
COR_YBR[10:8]
COR_XBR[10:8]
COR_XBR[9:0]: X coordinate of partition 0 Bottom-Right point. Default 720.
COR_YBR[9:0]: Y coordinate of partition 0 Bottom-Right point. Default 480.
Address= 8’hB2
Mixer Out Region End Point Config 2
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
8’hD0
COR_XBR[7:0]
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’hB3
Mixer Out Region End Point Config 3
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
8’hE0
COR_YBR[7:0]
Address= 8’hB8
Mixer channel Enable
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SWVLDI
N3
SWVLDI
N2
SWVLDI
N1
SWVLDI
N0
CHEN3
CHEN2
CHEN1
CHEN0
According to OUTSEL_0, set related channel enable signal.
CHEN0: Set 1, channel 0 enable.
CHEN1: Set 1, Channel 1 enable.
CHEN2: Set 1, Channel 2 enable.
CHEN3: Set 1, Channel 3 enable.
SWVLDINX: Set 1, it will disable auto PAL/NTSC mode detect function in video capture
interface X and bypass input CCIR656 signal to the mixer as valid signal.
Address= 8’hB9
Channel Select
7-bit
6-bit
0
5-bit
3’h1
CHSEL_1
Final
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4-bit
3-bit
0
2-bit
1-bit
0-bit
3’h0
CHSEL_0
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
CHSEL_0: select 1 out of 8 video sources for channel 0.
CHSEL_1: select 1 out of 8 video sources for channel 1.
Address= 8’hBA
Channel Select
7-bit
6-bit
5-bit
4-bit
3-bit
3’h3
0
2-bit
1-bit
0-bit
3’h2
0
CHSEL_3
CHSEL_2
CHSEL_2: select 1 out of 8 video sources for channel 2.
CHSEL_3: select 1 out of 8 video sources for channel 3.
CHSEL_X
3’h0
3’h1
3’h2
3’h3
3’h4
3’h5
3’h6
3’h7
MUXOUT
Analog
CVBS0
Analog
CVBS1
Analog
CVBS2
Analog
CVBS3
Digital
ITDM
CHID:
0
Digital
ITDM
CHID:
1
Digital
ITDM
CHID:
2
Digital
ITDM
CHID:
3
Address= 8’hBD
Mirror
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
H_3_R
H_3_L
H_1_R
H_1_L
INV_H3
INV_H2
INV_H1
INV_H0
INV_H0: enable channel 0 mirror function. (Only valid in SD mode)
INV_H1: enable channel 1 mirror function. (Only valid in SD mode)
INV_H2: enable channel 2 mirror function. (Only valid in SD mode)
INV_H3: enable channel 3 mirror function. (Only valid in SD mode)
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
H_X_L: only valid in SD OUTSEL_0=4’h3 (H partition)
when 1. channel/partition X will crop original video Left 1/4 image.
H_X_R: only valid in SD OUTSEL_0=4’h3 (H partition)
when 1. channel/partition X will crop original video Right 1/4 image.
{H_X_R,H_X_L}=2’b1x, output Right 1/4 original image
=2’b01, output Left 1/4 original image
=2’b00, perform 1/4 horizontal downscaling from original image.
Address= 8’hBE
SW force Progressive Input format
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SWPRGI
N_3
SWPRGI
N_2
SWPRGI
N_1
SWPRGI
N_0
SWPRGIN0: Take channel 0 video as progressive video, in spite of field flag.
SWPRGIN1: Take channel 1 video as progressive video, in spite of field flag.
SWPRGIN2: Take channel 2 video as progressive video, in spite of field flag.
SWPRGIN3: Take channel 3 video as progressive video, in spite of field flag.
Address= 8’hBF
SDRAM Burst Length Config
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
BRLEN
OPT3
BRLEN
OPT2
BRLEN
OPT1
BRLEN
OPT0
BRLENOP0: Channel 0 SDRAM burst length option.
BRLENOP1: Channel 1 SDRAM burst length option.
BRLENOP2: Channel 2 SDRAM burst length option.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
BRLENOP3: Channel 3 SDRAM burst length option.
BRLENOPTX: When 1: SDRAM burst length = 1/2 of channel partition length
When 0: SDRAM burst length = 1/4 of channel partition length
If partition length is NOT a multiple of 4, set BRLENTOPTX to 1.
Address= 8’hC0
Detected Valid Enable
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
1
1
1
1
WDOGE
N_3
WDOGE
N_2
WDOGE
N_1
WDOGE
N_0
WDOGEN_0: channel 0 capture interface watch dog enable.
WDOGEN_1: channel 1 capture interface watch dog enable.
WDOGEN_2: channel 2 capture interface watch dog enable.
WDOGEN_3: channel 3 capture interface watch dog enable.
When 1, enable channel watch dog counter. Watch dog counter will counts up
until capture interface detect valid video. When watch dog counter reaches a certain of
time (refer WDOGCNT_x), channel detection flag will be cleared (NOVID_x clear to 1)
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’hC1
Detected Valid Config 1
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
4’h0
4’h0
WDOGCNT_1
WDOGCNT_0
0-bit
WDOGCNT_0: channel 0 watch dog timer time out option.
WDOGCNT_1: channel 1 watch dog timer time out option.
When watch dog count over (WDOGCNT_x+1) * 378ms, watch dog
counter time out asserted.
Address= 8’hC2
Detected Valid Config 2
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
4’h0
4’h0
WDOGCNT_3
WDOGCNT_2
0-bit
WDOGCNT_2: channel 2 watch dog timer time out option.
WDOGCNT_3: channel 3 watch dog timer time out option.
Address= 8’hC3
CCIRIN_0 CROP START
7-bit
6-bit
5-bit
0
0
0
4-bit
3-bit
2-bit
1-bit
0-bit
5’h0
CROPLEN_0
CROPLEN_0: channel 0 capture interface cropping start point.
Final
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Address= 8’hC4
CCIRIN_1 CROP START
7-bit
6-bit
5-bit
0
0
0
4-bit
3-bit
2-bit
1-bit
0-bit
1-bit
0-bit
1-bit
0-bit
5’h0
CROPLEN_1
CROPLEN_1: channel 1 capture interface cropping start point.
Address= 8’hC5
CCIRIN_2 CROP START
7-bit
6-bit
5-bit
0
0
0
4-bit
3-bit
2-bit
5’h0
CROPLEN_2
CROPLEN_2: channel 2 capture interface cropping start point.
Address= 8’hC6
CCIRIN_3 CROP START
7-bit
6-bit
5-bit
0
0
0
4-bit
3-bit
2-bit
5’h0
CROPLEN_3
CROPLEN_3: channel 3 capture interface cropping start point.
Final
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Address= 8’hC8
Mixer Channel Status
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
1
1
1
1
NOVID_
3
NOVID_
2
NOVID_
1
NOVID_
0
NOVID_0: 0 indicates valid channel 0 video detected. (RO)
NOVID_1: 0 indicates valid channel 1 video detected. (RO)
NOVID_2: 0 indicates valid channel 2 video detected. (RO)
NOVID_3: 0 indicates valid channel 3 video detected. (RO)
Address= 8’hCB
Capture Interface 0 Status
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
L525_D
ET_0
L625_D
ET_0
H720_D
ET_0
RO.
H720_DET_X: 1 indicates 720H video detected. (RO)
L625_DET_X: 1 indicates PAL (625 line) video detected. (RO)
L525_DET_X: 1 indicates NTSC (525 line) video detected. (RO)
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’hCC
Capture Interface 1 Status
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
L525_D
ET_1
L625_D
ET_1
H720_D
ET_1
RO.
Address= 8’hCD
Capture Interface 2 Status
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
L525_D
ET_2
L625_D
ET_2
H720_D
ET_2
RO.
Address= 8’hCE
Capture Interface 3 Status
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
L525_D
ET_3
L625_D
ET_3
H720_D
ET_3
RO.
Final
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Address= 8’hCF
SDRAM CLK Option
7-bit
6-bit
5-bit
4-bit
0
0
0
0
3-bit
2-bit
1-bit
0-bit
4’h0
SDRCL
KINV
DLYMUX_SDRCLK
DLYMUX_SDRCLK: Adjust the SDRAM clk delay timing.
Please refer to the following table for the delay time.
DLYMUX
SDRCLK
4’h0
4’h1
4’h2
4’h3
4’h4
4’h5
4’h6
4’h7
Delay
Time(ns)
0
0.35
1.01
1.39
2.03
2.38
3.09
3.42
DLYMUX
SDRCLK
4’h8
4’h9
4’hA 4’hB 4’hC 4’hD
4’hE
4’hF
Delay
Time(ns)
4.07
4.44
5.07
7.04
7.34
5.42
6.09
6.43
SDRCLKINV: Set 1, inverse the SDRAM clk for adjusted timing.
Address= 8’hD0
SDRAM Config 0
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
8’h0
MODEREG[7:0]
Final
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Address= 8’hD1
SDRAM Config 1
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
3’h0
5’h0
COLSIZEOPT
MODEREG[12:8]
1-bit
0-bit
MODEREG: The setting of Mode Register for SDRAM.
MODEREG
Function
12
11 10
RFU*
9
WBL
8
7
Test
Mode
6
5
4
CAS Latency
3
BT
2
1
0
Burst Length
*Note: RFU(Reserved for future use) should stay “0” during MRS cycle.
Burst Length: MODEREG[2:0]
This table specifies the data length of column access using the
MODEREG[2:0] and selects the Burst Length to be 1, 2, 4, 8, or full page.
Burst Length 2
1
0
1
0
0
0
2
0
0
1
4
0
1
0
8
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Full Page
1
1
1
BT(Burst Type): MODEREG[3]
Burst Type can be one of two modes, Interleave Mode or Sequential Mode.
0: Sequential, 1: Interleave.
CAS Latency: MODEREG[6:4]
This table specifies the number of clock cycles from the assertion of the Read
command to the first read data.
CAS Latency
Reserved
Reserved
Final
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6
0
0
5
0
0
4
0
1
127
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
2 clocks
0
1
0
3 clocks
0
1
1
Reserved
1
X
X
Test Mode: MODEREG[8:7]
These two bits must be programmed to 2’h0 in normal operation.
WBL(Write Burst Length): MODEREG[9]
This bit is used to select the write burst mode.
WBL
0
1
Write Burst Mode
Burst-Read-Burst-Write
Burst-Read-Single-Write
COLSIZEOPT: Set the SDRAM size (64MB or 128MB).
3’b000: Reserved for future use
3’b001: Reserved for future use
3’b010: 16bit, 128MB
3’b1xx: 16bit, 64MB
Recommend settings:
64MB
128MB
REGD0: 8’h37
REGD1: 8’hE0
CSR settings
REGD0: 8’h37
REGD1: 8’h40
Address= 8’hD2
SDRAM Config 2
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SDRCL
KZOPT
SDRWIN
IOPT
RWGOO
D
SDRTST
RDY
SDR32M
D
SDRTST
AUTOP
RECHA
RGEOP
T
SELFRE
SH
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
AUTOPRECHARGEOPT: SDRAM auto pre-charge.
SDRTST: SDRAM self-test enable.
SDRTSTRDY: (RO), In SDRAM self test mode, 1: Test ready, 0: Test still not ready.
RWGOOD: (RO), In SDRAM self test mode, 1: Good, 0: No Good
SDRCLKZOPT: SDRAM operated option. (Set 1 when at HD mode)
Address= 8’hD3
Blue Panel Y Config
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
2-bit
1-bit
0-bit
8’h29
NOVID_Y_REG
Blue Panel: Luminance(Y) value, default Blue color
Address= 8’hD4
Blue Panel CB Config
7-bit
6-bit
5-bit
4-bit
3-bit
8’hF0
NOVID_CB_REG
Blue Panel: Chrominance (Cb) value, default Blue color
Final
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Address= 8’hD5
Blue Panel CR Config
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
2-bit
1-bit
0-bit
1-bit
0-bit
8’h6E
NOVID_CR_REG
Blue Panel: Chrominance (Cr) value, default Blue color
Address= 8’hD6
Split Line Y
7-bit
6-bit
5-bit
4-bit
3-bit
8’hEB
PAD_Y
Mixer Output Split Line: Luminance(Y) value, default white color
Address= 8’hD7
Split Line CB
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
8’h80
PAD_CB
Mixer Output Split Line: Chrominance (Cb) value, default white color
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’hD8
Split Line CR
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
8’h80
PAD_CR
Mixer Output Split Line: Chrominance (Cr) value, default white color
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Mixer OUTSEL Configuration Table
SEL
Type
NTSC 720
PAL 720
w c0 a3 02
w c0 a3 02
w c0 a4 02
w c0 a4 02
w c0 a5 d0
w c0 a5 d0
w c0 a6 0f
w c0 a6 0f
w c0 a7 10
w c0 a7 10
w c0 a8 00
w c0 a8 00
w c0 a9 00
w c0 a9 00
w c0 aa 68
w c0 aa 68
w c0 ab 00
w c0 ab 00
w c0 ac 10
w c0 ac 54
w c0 ad 00
w c0 ad 00
w c0 ae F0
w c0 ae 20
w c0 af 68
w c0 af 68
w c0 b0 F0
w c0 b0 20
w c0 b1 12
w c0 b1 22
w c0 b2 D0
w c0 b2 D0
w c0 b3 E0
w c0 b3 40
SD Mode
0
0
2
Final
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3
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1
0
1
2
0
1
Final
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w c0 a3 02
w c0 a3 02
w c0 a4 02
w c0 a4 02
w c0 a5 d0
w c0 a5 d0
w c0 a6 03
w c0 a6 03
w c0 a7 00
w c0 a7 40
w c0 a8 00
w c0 a8 00
w c0 a9 00
w c0 a9 00
w c0 aa 00
w c0 aa 00
w c0 ab F0
w c0 ab 20
w c0 b1 12
w c0 b1 22
w c0 b2 D0
w c0 b2 D0
w c0 b3 E0
w c0 b3 40
w c0 a3 02
w c0 a3 02
w c0 a4 02
w c0 a4 02
w c0 a5 d0
w c0 a5 d0
w c0 a6 07
w c0 a6 07
w c0 a7 00
w c0 a7 40
w c0 a8 00
w c0 a8 00
w c0 a9 00
w c0 a9 00
w c0 aa 00
w c0 aa 00
w c0 ab F0
w c0 ab 20
w c0 ac 01
w c0 ac 05
w c0 ad 68
w c0 ad 68
w c0 ae F0
w c0 ae 20
w c0 b1 12
w c0 b1 22
w c0 b2 D0
w c0 b2 D0
w c0 b3 E0
w c0 b3 40
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
3
1
0
2
4
0
Final
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w c0 a3 02
w c0 a3 02
w c0 a4 02
w c0 a4 02
w c0 a5 d0
w c0 a5 d0
w c0 a6 0f
w c0 a6 0f
w c0 a7 00
w c0 a7 00
w c0 a8 B4
w c0 a8 B4
w c0 a9 00
w c0 a9 00
w c0 aa 00
w c0 aa 00
w c0 ab 00
w c0 ab 00
w c0 ac 20
w c0 ac 24
w c0 ad B4
w c0 ad B4
w c0 ae F0
w c0 ae 20
w c0 af 1C
w c0 af 1C
w c0 b0 00
w c0 b0 00
w c0 b1 12
w c0 b1 22
w c0 b2 D0
w c0 b2 D0
w c0 b3 E0
w c0 b3 40
w c0 a3 02
w c0 a3 02
w c0 a4 02
w c0 a4 02
w c0 a5 d0
w c0 a5 d0
w c0 a6 01
w c0 a6 01
w c0 a7 00
w c0 a7 00
w c0 a8 00
w c0 a8 00
w c0 a9 00
w c0 a9 00
w c0 b1 12
w c0 b1 22
w c0 b2 D0
w c0 b2 D0
w c0 b3 E0
w c0 b3 40
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
5
0
1
w c0 a3 02
w c0 a3 02
w c0 a4 02
w c0 a4 02
w c0 a5 d0
w c0 a5 d0
w c0 a6 03
w c0 a6 03
w c0 a7 10
w c0 a7 10
w c0 a8 00
w c0 a8 00
w c0 a9 00
w c0 a9 00
w c0 aa 68
w c0 aa 68
w c0 ab 00
w c0 ab 00
w c0 b1 12
w c0 b1 22
w c0 b2 D0
w c0 b2 D0
w c0 b3 E0
w c0 b3 40
HD Mode
8
Final
Doc No: DM5885-DS-F01
August 19, 2015
0
1
2
3
w c0 a6 0f
w c0 a6 0f
w c0 a7 20
w c0 a7 20
w c0 a8 00
w c0 a8 00
w c0 a9 00
w c0 a9 00
w c0 aa D0
w c0 aa D0
w c0 ab 00
w c0 ab 00
w c0 ac 64
w c0 ac A8
w c0 ad 00
w c0 ad 00
w c0 ae E0
w c0 ae 1C
w c0 af D0
w c0 af D0
w c0 b0 E0
w c0 b0 1C
w c0 b1 35
w c0 b1 45
w c0 b2 A0
w c0 b2 A0
w c0 b3 C0
w c0 b3 38
135
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
8
0
1
2
3
w c0 a6 0f
w c0 a7 20
w c0 a8 00
w c0 a9 00
PAL EXT
w c0 aa D0
w c0 ab 00
w c0 ac A8
w c0 ad 00
w c0 ae 40
w c0 af D0
w c0 b0 40
w c0 b1 45
w c0 b2 A0
w c0 b3 80
Final
Doc No: DM5885-DS-F01
August 19, 2015
136
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Electrical Specifications
Absolute Maximum Ratings Over Operating Free-Air
Temperature Range
Supply voltage range
IOVDD to DGND
-0.5V to 4.6V
DVDD to DGND
-0.5V to 2.5V
PLL_AVDD to PLL_AGND
-0.5V to 2.5V
CH1_AVDD to CH1_AGND
-0.5V to 2.5V
Digital input voltage range,
Vl to DGND
Input voltage range, XTAL1
to PLL_GND
Analog input voltage range
Al to CH1_AGND
Digital Output voltage
range, VO to DGND
Operating free-air
temperature, TA
Final
Doc No: DM5885-DS-F01
August 19, 2015
-0.5V to 4.6V
-0.5V to 2.5V
-0.2V to 2.0V
-0.5V to 4.6V
-65C to 150C
137
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Recommended Operating Conditions
IODVDD
DVDD
PLL_AVDD
Audio
VI(P-P)
VIH
VIL
VIH_XTAL
Digital I/O supply voltage
Digital supply voltage
Analog PLL supply
voltage
Analog core supply
voltage
Analog input voltage (accoupling necessary)
Analog input voltage (accoupling necessary)
Digital input voltage high
Digital input voltage low
XTAL input voltage high
VIL_XTAL
XTAL input voltage low
IOH
IOL
IOH_SCLK
High-level output current
Low-level output current
SCLK high-level output
current
SCLK low-level output
current
Operating free-air
temperature
CH1_AVDD
VI(P-P)
IOL_SCLK
TA
Final
Doc No: DM5885-DS-F01
August 19, 2015
MIN
2.97
1.62
TYP
3.3
1.8
MAX
3.63
1.98
UNIT
V
V
1.62
1.8
1.98
V
1.7
1.8
1.9
V
1.0
V
5
0.8
V
V
0.25
1.5
2
-0.3
0.7
PLL_AVDD
-40
V
0.3
PLL_AVDD
2
-2
mA
mA
4
mA
-4
mA
85
V
o
C
138
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Crystal Specifications
CRYSTAL
SPECIFICATIONS
Frequency
Frequency tolerance
MIN
NOM
MAX
UNIT
27.0/36.0
100
MHz
ppm
Electrical Characteristics
DVDD = 1.8 V, PLL_AVDD = 1.8 V, CH1_AVDD = 1.8 V, IOVDD = 3.3 V
For minimum/maximum values: TA = -40C to 85C, and for typical values: TA = 25C
unless otherwise noted
DC Electrical Characteristics
PARAMETER
TEST
CONDITIONS
(see NOTE 1)
IDD(IO_D) Digital I/O supply current
IDD(D)
Digital core supply
current
IDD(PLL_A) Analog PLL supply
current
IDD(CH1-A) IDD(A)
Analog ADC/DAC supply current
PTOT
Total power dissipation,
normal mode
PDOWN Total power dissipation,
power-down mode
Ci
Input capacitance
VOH
Output voltage high
Color bar input
Color bar input
VOL
IOL = -2 mA
Output voltage low
TYP
MAX
UNIT
31.2
66.7
mA
212
297
mA
12
Color bar input
99.3
Color bar input
684.5
Color bar input
By design
IOH = 2 mA
VOH_SCLK SCLK output voltage
IOH = 4 mA
high
VOL_SCLK SCLK output voltage low IOL = -2 mA
IIH
High-level input current
VI = VIH
IIL
Low-level input current
VI = VIL
NOTE 1: Measured with a load of 15 pf.
Final
Doc No: DM5885-DS-F01
August 19, 2015
MIN
mA
952.3
mW
15.3
mW
8
pF
0.8
IOVDD
V
0.22
IOVDD
2.3
V
V
0.6
50
50
V
A
A
139
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Analog Processing and A/D Converters
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
Zi
Input impedance, analog
By design
500
video inputs
Ci
Input capacitance, analog
By design
10
video inputs
Vi(pp)
Input voltage range *
0.25
1
Ccoupling = 0.1 F
12
G
Gain control range
DNL
DC differential non-linearity
A/D only
2
INL
DC integral non-linearity
A/D only
3
Fr
Frequency response
6 MHz
-0.9
-3
SNR
Signal-to-noise ratio
6 MHz, 1.0 Vp-p
50
NS
Noise spectrum
50% flat field
50
DP
Differential phase
1.5
DG
Differential gain
0.5%
* The 0.75-V maximum applies to the sync-chroma amplitude, not sync-white. The
recommended termination resistors are 37.4 .
UNIT
k
pF
V
dB
LSB
LSB
dB
dB
dB

Timing
Power-on Reset Timing
PLL_AVDD
DVDD
IO_DVDD
t1
RESETB
Normal Operation
Reset
t2
t3
Data
SDA
SCL
NO.
t1
t2
t3
PARAMETER
Delay time between power supplies active and reset
RESETB pulse duration
2
Delay time between end of reset to I C active
Final
Doc No: DM5885-DS-F01
August 19, 2015
MIN
20
500
500
MAX
-
UNIT
ms
ns
ns
140
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Clocks, Video Data, Sync timing
Data Format : CCIR656 output
PARAMETER
PIXCLK High pulse duration
PIXCLK Low pulse duration
CCIR656 data out setup time
CCIR656 data out hold time
SYMBOL
thw
tlw
tsu
th
MIN
18.5
18.5
18.5
18.5
TYP
MAX
UNIT
ns
ns
ns
ns
Output:CCIR656
PIXCLK
(27MHz)
CCIR656
(27MHz)
thw
tlw
FF
00
tsu
th
00
XY
Cb0
Y0
Cr0
Figure 3-2 . Clocks, CCIR656 Output Data Timing
Data Format : CCIR656 input
PARAMETER
PIXCLK High pulse duration
PIXCLK Low pulse duration
CCIR656 data out setup time
CCIR656 data out hold time
Final
Doc No: DM5885-DS-F01
August 19, 2015
SYMBOL
thw
tlw
tsu
th
MIN
18.5
18.5
18.5
18.5
TYP
MAX
UNIT
ns
ns
ns
ns
141
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
I2C Host Port Timing
PARAMETER
TEST CONDITIONS
MIN
t1
Bus free time between STOP
and START
t2
Setup time for a (repeated)
START condition
t3
Hold time (repeated) START
condition
t4
Setup time for STOP condition
t5
Data setup time
t6
Data hold time
t7
Rise time I2CD and I2CLK
signal
t8
Fall time I2CD and I2CLK signal
Cb
Capacitive load for each bus
line
fI2C
I2C clock frequency
STOP
TYP
MAX UNIT
1.3
s
0.6
s
0.6
s
0.6
200
0
s
ns
ns
50
250
ns
250
START
START
ns
120
pF
400
kHz
STOP
SI2CD
t1
t5
t6
t7
t8
t2
t3
t4
SI2CLK
Write Address
SADD[0] Pull low
SADD[1] Pull low
SADD[0] Pull high
SADD[1] Pull low
SADD[0] Pull low
SADD[1] Pull high
SADD[0] Pull high
SADD[1] Pull high
SI2CLK
1
2
8
9
1
2
Read Address
C0
C1
C2
C3
C4
C5
C6
C7
8
9
1
2
8
9
SI2CD
START
SI2CLK
1
WRITE ADDRESS
2
8
9
ACK
1
2
REG ADDRESS
8
9
ACK
1
2
DATA
8
9
1
ACK
2
STOP
8
9
SI2CD
START
WRITE ADDRESS
Final
Doc No: DM5885-DS-F01
August 19, 2015
ACK
REG ADDRESS
ACK STOP START
READ ADDRESS
ACK
DATA
NOACK STOP
142
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
AC Characteristic of Digital Audio Interface
ADATP
Input
Valid
tod
ACLK
tlw
tsu
th
thw
Output
Valid
ADATR/ADATM
ASYNR
Min
tlw
thw
tod
tsu
th
clock low time
clock high time
output delay time
input setup time
input hold time
Final
Doc No: DM5885-DS-F01
August 19, 2015
Typ
Max
Unit
ns
ns
ns
ns
ns
143
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Packaging
Final
Doc No: DM5885-DS-F01
August 19, 2015
144
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Ordering Information
Part Number
Pin Count
DM5885EP
128
Package
LQFP
(Pb-Free and
Halogen-Free)
Disclaimer
The information appearing in this publication is
believed to be accurate. Integrated circuits sold by
DAVICOM Semiconductor are covered by the
warranty and patent indemnification provisions
stipulated in the terms of sale only. DAVICOM makes
no warranty, express, statutory, implied or by
description regarding the information in this
publication or regarding the information in this
publication or regarding the freedom of the described
chip(s) from patent infringement.
FURTHER,
DAVICOM
MAKES
NO
WARRANTY
OF
MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE. DAVICOM reserves the right to halt
production or alter the specifications and prices at
any time without notice. Accordingly, the reader is
cautioned to verify that the data sheets and other
information in this publication are current before
placing orders. Products described herein are
intended for use in normal commercial applications.
Applications involving unusual environmental or
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recommended without additional processing by
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application circuits illustrated in this document are for
reference purposes only.
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DAVICOM will not be bound by any terms
inconsistent with these unless DAVICOM agrees
otherwise in writing. Acceptance of the buyer’s orders
shall be based on these terms.
Company Overview
DAVICOM Semiconductor Inc. develops and
manufactures integrated circuits for integration into
data communication products. Our mission is to
design and produce IC products that are the
industry’s best value for Data, Audio, Video, and
Internet/Intranet applications. To achieve this goal,
we have built an organization that is able to develop
chipsets in response to the evolving technology
requirements of our customers while still delivering
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WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the
limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and function.
Final
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145