DATA SHEET - Davicom Semiconductor Inc.

DM9621A
USB2.0 to Fast Ethernet Controller
DAVICOM Semiconductor, Inc.
DM9621A
USB2.0 to 10/100M Fast Ethernet Controller
DATA SHEET
Final
Version: DM9621A-13-MCO-DS-F01
June 30, 2015
Final
Doc No: DM9621A-13-MCO-DS-F01
June 30, 2015
1
DM9621A
USB2.0 to Fast Ethernet Controller
Content
1
2
3
4
Features ............................................................................................................................................. 5
1.1
General Description ............................................................................................................ 6
Block Diagram and Block Description.............................................................................................. 7
Pin Configuration .............................................................................................................................. 8
3.1
48-Pin QFN with RMII Interface........................................................................................... 8
3.2
48-Pin QFN with RMII Interface........................................................................................... 9
3.2.1 RMII Interface ............................................................................................................ 9
3.2.2 EEPROM Interface ..................................................................................................... 9
3.2.3 USB Interface ............................................................................................................ 9
3.2.4 Clock Interface......................................................................................................... 10
3.2.5 LED Interface .......................................................................................................... 10
3.2.5 10/100 PHY ............................................................................................................. 10
3.2.6 Miscellaneous .......................................................................................................... 11
3.2.7 Power ..................................................................................................................... 11
3.3
Strap Pin Table .................................................................................................................. 11
Vender Control an Status Register Set ............................................................................................12
4.1
Network Control Register (00H) .........................................................................................14
4.2
Network Status Register (01H) ...........................................................................................15
4.3
TX Control Register (02H) ..................................................................................................16
4.4
RX Control Register (05H) .................................................................................................16
4.5
RX Status Register (06H) ...................................................................................................17
4.6
Receive Overflow Counter Register (07H) ..........................................................................17
4.7
Back Pressure Threshold Register (08H) ...........................................................................18
4.8
Flow Control Threshold Register (09H)...............................................................................18
4.9
RX/TX Flow Control Register (0AH) ...................................................................................19
4.10
EEPROM & PHY Control Register (0BH) ...........................................................................19
4.11
EEPROM & PHY Address Register (0CH) ..........................................................................20
4.12
EEPROM & PHY Data Register (EE_PHY_L:0DH EE_PHY_H:0EH).........................20
4.13
Wake Up Control Register (0FH) ........................................................................................20
4.14
Physical Address Register (10H~15H)................................................................................20
4.15
Multicast Address Register (16H~1DH) ..............................................................................21
4.16
General Purpose Control Register (1EH)............................................................................21
4.17
General Purpose Register (1FH) ........................................................................................21
4.18
Vendor ID Register (28H~29H)...........................................................................................21
4.19
Product ID Register (2AH~2BH) .........................................................................................21
4.20
Chip Revision Register (2CH) ............................................................................................21
4.21
TX Special Control Register (2DH) .....................................................................................22
4.22
External PHY Force Mode Control Register (2EH)..............................................................22
4.23
Transmit Check Sum Control Register (31H) ......................................................................22
4.24
Receive Check Sum Control Status Register (32H) ............................................................23
4.25
External PHY Ceiver Address Register (33H) .....................................................................23
4.26
General Purpose Control Register 2 (34H) .........................................................................23
4.27
General Purpose Register 2 (35H) .....................................................................................23
4.28
EEPROM and PHY Control Register (3AH) ........................................................................24
4.29
Pause Packet Control/Status Register (3DH) .....................................................................24
4.30
IEEE802.3az Enter Time Register (3EH) ............................................................................24
4.31
IEEE802.3az Leave Time Register (3FH) ...........................................................................24
4.32
Link Up/Down Wakeup Event Register (51H) .....................................................................24
4.33
IPv6 NA/ARP Register (52H)..............................................................................................25
4.34
Minimum RX SOF Control Register (58H) ..........................................................................25
4.35
Minimum RX Burst Counter Register (59H) ........................................................................25
4.36
Transmit Packet Counter (81H) ..........................................................................................25
4.37
USB Packet Error Counter (82H)........................................................................................25
Final
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June 30, 2015
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DM9621A
USB2.0 to Fast Ethernet Controller
5
6
7
4.38
Ethernet Receive Packet CRC Error Counter (83H)............................................................25
4.39
Ethernet Transmit Excessive Collision Counter (84H) .........................................................26
4.40
Ethernet Transmit Collision Counter (85H) .........................................................................26
4.41
Ethernet Transmit Late Collision Counter (86H)..................................................................26
4.42
RX Header Control/Status Register (91H) ..........................................................................26
4.43
USB Squelch Control (95H) ...............................................................................................26
4.44
USB Address (96H)............................................................................................................27
4.45
USB Device Address Register (F0H) ..................................................................................27
4.46
Receive Packet Counter Register (F1H).............................................................................27
4.47
USB Status Register (F2H) ................................................................................................27
4.48
USB Control Register (F4H) ...............................................................................................27
EEPROM Format ...............................................................................................................................28
PHY Register Description.................................................................................................................29
6.1
Basic Mode Control Register (BMCR) – 00H ......................................................................30
6.2
Basic Mode Status Register (BMSR) – 01H........................................................................31
6.3
PHY ID Identifier Register #1 (PHYID1) – 02H ...................................................................32
6.4
PHY Identifier Register #2 (PHYID2) – 03H ........................................................................32
6.5
Auto-Negotiation Advertisement Register(ANAR) – 04H .....................................................33
6.6
Auto-Negotiation Link Partner Ability Register (ANLPAR) – 05H .........................................34
6.7
Auto-Negotiation Expansion Register (ANER)- 06H............................................................35
6.8
DAVICOM Specified Configuration Register (DSCR) – 10H ................................................36
6.9
DAVICOM Specified Configuration and Status Register (DSCSR) – 11H ............................37
6.10
10BASE-T Configuration/Status (10BTCSR) – 12H ............................................................38
6.11
Power down Control Register (PWDOR) – 13H ..................................................................38
6.12
(Specified Config) Register – 14H ......................................................................................39
6.13
DSP Control (DSP_CTRL) – 1BH.......................................................................................40
6.14
Power Saving Control Register (PSCR) – 1DH...................................................................40
Functional Description .....................................................................................................................41
7.1
USB Functional Description ...............................................................................................41
7.1.1 USB Functional Description ....................................................................................... 41
7.1.2 Vender Commands................................................................................................... 42
7.1.3 Interface 0 Configuration ........................................................................................... 43
7.1.4 Descriptor Values ..................................................................................................... 45
7.1.5 Descriptors of String/1/2/3 Are Loaded From EEPROM................................................. 48
7.2
Ethernet Functional Description .........................................................................................49
7.2.1 Serial Management Interface ..................................................................................... 49
7.2.2 100Base-TX Operation ............................................................................................. 50
7.2.3 4B5B Encoder ......................................................................................................... 50
7.2.4 Scrambler ............................................................................................................... 50
7.2.5 Parallel to Serial Converter ........................................................................................ 50
7.2.6 NRZ to NRZI Encoder ............................................................................................... 50
7.2.7 MLT-3 Converter ...................................................................................................... 50
7.2.8 MLT-3 Driver ............................................................................................................ 51
7.2.9 4B5B Code Group .................................................................................................... 51
7.2.10 100Base-TX Receiver ............................................................................................. 52
7.2.11 Signal Detect ......................................................................................................... 52
7.2.12 Adaptive Equalization.............................................................................................. 52
7.2.13 MLT-3 to NRZI Decoder .......................................................................................... 52
7.2.14 Clock Recovery Module .......................................................................................... 52
7.2.15 NRZI to NRZ .......................................................................................................... 52
7.2.16 Serial to Parallel ..................................................................................................... 53
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
8
9
10
11
12
13
7.2.17 Descrambler 53
7.2.18 Code Group Alignment ............................................................................................ 53
7.2.19 4B5B Decoder ....................................................................................................... 53
7.2.20 10Base-T Operation ............................................................................................... 53
7.2.21 Collision Detection .................................................................................................. 53
7.2.22 Carrier Sense ........................................................................................................ 53
7.2.23 Auto-Negotiation..................................................................................................... 53
7.2.24 Auto-Negotiation (continued).................................................................................... 54
7.2.25 Energy-Efficient Ethernet (EEE) ............................................................................... 54
DC and AC Electrical Characteristics ..............................................................................................55
8.1
Absolute Maximum Ratings................................................................................................55
8.1.1 Operating Conditions ................................................................................................ 55
8.2
DC Electrical Characteristics (VDD = 3.3V) ........................................................................56
8.3
AC Electrical Characteristics & Timing Waveforms .............................................................57
8.3.1
TP Interface ..................................................................................................... 57
8.3.2
Oscillator/Crystal Timing (25°C) .......................................................................... 57
AC Timing Waveform........................................................................................................................58
9.1
Power On Reset Timing .....................................................................................................58
9.2
EEPROM Timing................................................................................................................59
9.3
MII Management Timing.....................................................................................................59
9.4
RMII TX Timing ..................................................................................................................60
9.5
RMII TX Timing ..................................................................................................................60
Magnetic and Crystal Selection Guide ............................................................................................61
10.1
Magnetic Selection Guide ..................................................................................................61
10.2
Crystal Selection Guide......................................................................................................61
Application Circuit............................................................................................................................62
Package Information ........................................................................................................................65
Ordering Information ........................................................................................................................66
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
1
Features
l
l
l
USB Interface
§
USB2.0 Device
§
Support 12Mbps full speed operation
§
Support 480Mbps high speed operation
§
Support suspend mode and remote wake-up resume
§
Support USB standard commands
§
Support vendor specific commands
§
Efficient TX/RX FIFO auto management.
§
Embedded SRAM for RX/TX packet buffering
§
Supports 4 endpoints (Control, Interrupt, Bulk_IN, Bulk_OUT)
§
Supported Classes:USB Common Class / USB Communications Class
Ethernet
§
Support IEEE802.3u 100BASE-TX and with IEEE802.3 10BASE-T standards
§
Support IEEE802.3x flow control function for 100BASE-TX and 10BASE-T.
§
Support IEEE 802.3az Energy Efficient Ethernet (EEE)
§
Built-in 10/100Mbps Fast-Ethernet PHY with Auto-MDIX
§
Supports RMII interface or 8 pins GPIO
§
Support Auto-Negotiation function
§
Back Pressure Mode for Half-Duplex mode flow Control
§
PAUSE frame for Full-Duplex flow control
§
Support Power management: Wake-on-LAN, ARP/NDP Offload
§
Supports GPIO, wakeup frame, link status change and Magic packet events for
remote wake-up
§
Support TCP / UDP / IPv4 checksum offload checking and generating
EEPROM Interface
§
Supports 128/256/512 bytes (93C46/93C56/93C66) of serial EEPROM(for storing
USB Descriptors)
§
93C46/93C56/93C66 auto-detection
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
l
l
l
l
LED Indications
§
Ethernet – Link / Act indication
§
Ethernet – Speed (10M / 100M) indication
§
USB speed indication (full / high speed + traffic modes)
Clock
§
Single 25MHz / 30 ppm crystal or oscillator
§
Optional 12MHz crystal for USB
Power Input
§
Low-Power, Single-Supply 3.3V, 0.18um CMOS Technology
§
Built in 3.3V to 1.8V regulator
Miscellaneous
§
Very low power consumption in suspend mode
§
Power Reduced Mode (cable detection), and Power Down Mode
§
Compatible with 5.0V tolerant I/O
1.1 General Description
The DM9621A USB to 10/100Mbps Fast Ethernet controller is a high performance and highly integrated ASIC
with embedded SSRAM for packet buffering. It enables low cost and affordable Fast Ethernet network
connection to desktop, notebook PC, and embedded system using popular USB ports.
It has an USB interface to communicate with USB host controller and is compliant with USB specification V1.0,
V1.1 and V2.0. It implements 10/100Mbps Ethernet LAN function based on IEEE802.3, and IEEE802.3u
standards.
DM9621A integrates an on-chip 10/100Mbps Ethernet PHY to simplify system design and provides an
optional Reduce media-independent interface (RMII).
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
2
Block Diagram and Block Description
EP1
Bulk IN
FIFO
RX FIFO
SRAM
USB PHY
UTMI
SIE
MAC
Bulk OUT
FIFO
MII
Ethernet
PHY
TX FIFO
EP2
Register
Control table data
EEPROM interface
EEPROM
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
3
Pin Configuration
X2_12M
X2_12M
RSTB
WOL
VBUS_IN
TEST2
TEST1
LNK_LED
SPD_LED
USB_LED
SMI_CK
SMI_D
36
35
34
33
32
31
30
29
28
27
26
25
3.1 48-Pin QFN with RMII Interface
VCC3A
37
24
GND
38
23
VCC3
CLK50M
RREF
39
22
EECS
DM
40
21
EECK
DP
41
20
EEDIO
VCC33_PLL
42
19
MDIO
GND_PLL
43
18
VCCOUT
44
17
MDC
RXDV
VCC3
45
16
GND
X2
46
15
RXD0
X1
47
14
RXD1
GND
48
13
TXD0
VSS
1
2
3
4
5
6
7
8
9
10
11
12
BGGND
BGRES
RXVDDOUT
RX+
RX-
RXGND
TXGND
TX+
TX-
TXVDDOUT
TXE
TXD1
DM9621ANP
Note: The DM9621ANP IC employs a QFN package, which means the absence of a pin dedicated to ground
(GND). In the QFN package, the GND is located at the bottom of the IC directly in the middle. Square is where
the GND is connected. Exposed pad (VSS) on bottom of package must be connected to ground.
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
3.2 48-Pin QFN with RMII Interface
I = Input
O/D = Open Drain
O = Output
P = Power
3.2.1 RMII Interface
Pin No.
Pin Name
11
TXE
I/O
O
12,13
TXD[1:0]
O
14,15
RXD[1:0]
I
17
RXDV
I
18
19
MDC
MDIO
O
I/O
23
CLK50M
I
I/O = Input / Output
Description
External RMII Transmit Enable
GPIO2_0 in GPIO mode
External RMII Transmit Data
TXD[1] as GPIO2_1 in GPIO mode
TXD[0] as GPIO2_2 in GPIO mode
External RMII Receive Data
RXD[1] as GPIO2_3 in GPIO mode
RXD[0] as GPIO2_4 in GPIO mode
External RMII Receive Data Valid
GPIO2_5 in GPIO mode
MII Serial Management Data Clock
MII Serial Management Data
GPIO2_6 in GPIO mode
RMII 50MHz Clock
GPIO2_7 in GPIO mode
3.2.2 EEPROM Interface
Pin No.
Pin Name
20
EEDIO
21
EECK
22
EECS
I/O
I/O
O
O
Data to/from EEPROM
Clock to EEPROM
Chip Select to EEPROM
3.2.3 USB Interface
Pin No.
Pin Name
37
VCC3A
38
GND
39
RREF
40
DM
41
DP
42
VCC33_PLL
43
GND_PLL
44
VCCOUT
I/O
P
P
I
I/O
I/O
P
P
O
Description
3.3V for USB
Ground for USB
Reference resistor to analog USB ground (12K 1% for USB)
USB Data Minus
USB Data Plus
3.3V for USB PLL
Ground for USB PLL
1.8V power out for USB
Description
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
3.2.4 Clock Interface
Pin No.
Pin Name
46
X2
47
X1
35
X1_12M
I/O
O
I
I
3.2.5 LED Interface
Pin No.
Pin Name
27
USB_LED
I/O
O
Description
Crystal 25MHz Out for Ethernet
Crystal 25MHz In for Ethernet
Crystal 12MHz In for USB (Option, used when strap pin 22 EECS
pull-high), Normal N.C. * Note1
36
X2_12M
O
Crystal 12MHz out for USB (Option, used when strap pin 22 EECS
pull-high), Normal N.C. * Note1
* Note1: When strap pin 22 EECS pull-low, 12MHz clock from internal PLL, detail see 3.3 strap pins table
(Page 11)
28
SPD_LED
O
29
LNK_LED
O
3.2.5 10/100 PHY
Pin No.
Pin Name
1
BGGND
2
BGRES
3
RXVDDOUT
4
RX+
5
RX6
RXGND
7
TXGND
8
TX+
9
TX10
TXVDDOUT
I/O
P
I/O
O
I
I
P
P
O
O
O
Description
USB LED
Active low for USB HS mode
Floating for USB FS mode
Flash if traffic on USB
SPEED LED
Active low for Ethernet 100M
Floating for Ethernet 10M
Link LED
Active low for Ethernet link
Floating for Ethernet non-link
Flash if traffic on Ethernet
Description
Band gap ground.
Band gap pin. Connect 6.98K 1% resister to GND
1.8V power out for RX
TP RX input
TP RX input
RX ground
TX ground
TP TX output
TP TX output
1.8V power out for TX power
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
3.2.6 Miscellaneous
Pin No.
Pin Name
25
SMI_D
I/O
I/O
26
SMI_CK
I/O
32
VBUS_IN
I
33
34
WOL
RSTB
O
I
31
30
TEST2
TEST1
I
I
3.2.7 Power
Pin No.
24,45
16,48
Pin Name
VCC3
GND
I/O
P
P
Description
Serial Management Interface Data.
Tie to ground in application.
Serial Management Interface Clock.
Tie to ground in application.
This pin can also as a GPIO wakeup event defined in register 0FH.
VBUS input
Tie to high in bus power mode
Issue a wake-up signal when wake-up event happens.
Hardware Reset
Active low signal to initiate the DM9621A
Test Mode 2, tie to ground in application.
Define Pin11-15, 17-19 mode
1 = GPIO controlled by registers 34H~35H
0 = RMII
Description
Digital Power 3.3V
Digital Ground
3.3 Strap Pin Table
1: pull-high 1K~10K, 0: default floating.
Pin No.
Pin Name
Description
12
TXD[1]
1 = EEPROM force to 93C46 type
0 = EEPROM type auto-detection
13
TXD[0]
RX packet header format
1 = 4-byte Ethernet RX header mode :
The 4 bytes in Ethernet RX packet header are RX _flag, RX_status,
byte_ctr_low, and byte_ctr_high respectively.
0 = 3-byte Ethernet RX packet header mode:
The 3 bytes in Ethernet RX packet header are RX_status, byte_ctr_low,
and byte_ctr_high respectively.
22
EECS
1 = 12MHz clock from external crystal
0 = 12MHz clock from internal PLL
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
4
Vender Control an Status Register Set
The DM9621A implements several control and status registers, which can be accessed by the USB vendor
register type commands. All CRs are set to their default values by hardware or software reset unless
otherwise specified.
Default value
Register
Description
Offset
after reset
NCR
Network Control Register
00H
00H
NSR
Network Status Register
01H
00H
TCR
TX Control Register
02H
00H
RCR
RX Control Register
05H
00H
RSR
RX Status Register
06H
00H
ROCR
Receive Overflow Counter Register
07H
00H
BPTR
Back Pressure Threshold Register
08H
37H
FCTR
Flow Control Threshold Register
09H
38H
FCR
RX Flow Control Register
0AH
00H
EPCR
EEPROM & PHY Control Register
0BH
00H
EPAR
EEPROM & PHY Address Register
0CH
40H
EPDRL
EEPROM & PHY Low Byte Data Register
0DH
Unknown
EPDRH
EEPROM & PHY High Byte Data Register
0EH
Unknown
WCR
Wake Up Control Register
0FH
00H
PAR
Physical Address Register
10H-15H
Determined by
EEPROM
MAR
Multicast Address Register
16H-1DH
000000000000
0080
GPCR
General Purpose Control Register
1EH
01H
GPR
General Purpose Register
1FH
Unknown
VID
Vendor ID
28H-29H
0A46H
PID
Product ID
2AH-2BH
9621H
CHIPR
CHIP revision
2CH
01H
TSCR
TX Special Control Register
2DH
00H
TCSCR
Transmit Check Sum Control Register
31H
00H
RCSCSR
Receive Check Sum Control Status Register
32H
00H
GPCR2
General Purpose Control Register 2
34H
00H
GPR2
General Purpose Register 2
35H
00H
EEP_CTRL
EEPROM and PHY Control Register
3AH
00H
PPCSR
Pause Packet Control Status Register
3DH
04H
TX_CTR
Transmit Packet Counter
81H
00H
UPERR
USB Packet Error Counter
82H
00H
CRC_CTR
Ethernet Receive Packet CRC Error Counter
83H
00H
EXCOL_CT
Ethernet Transmit Excessive Collision Counter
84H
00H
R
COL_CTR
Ethernet Transmit Collision Counter
85H
00H
LCOL_CTR
Ethernet Transmit Late Collision Counter
86H
00H
MODE_CTL Mode Control
91H
00H
SQUELCH
USB squelch Control
95H
04H
USB_ADR
USB Address
96H
00H
USBDA
USB device address register
F0H
00H
RXC
Received packet counter register
F1H
00H
TXC/USBS
Transmit packet counter/USB status register
F2H
10H
USBC
USB control register
F4H
00H
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
Key to Default
In the register description that follows, the default column takes the form:
<Reset Value>:
1 = Bit set to logic one
0 = Bit set to logic zero
X = No default value
P = power on reset default value
H = hardware reset command default value
S = software reset default value
E = default value from EEPROM
T = default value from strap pin
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1 = Read/Write and Cleared by write 1
WO = Write only
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
4.1 Network Control Register (00H)
Bit
7
Name
EXT_PHY
Default
PT0,RW
6
WAKEEN
PE0,RW
This bit can be forced by register 2EH bit 5.
Wakeup Event Enable
This but enables the wakeup function.
5
WCR_MODE
PHS,RW
Clearing this bit will also clear all wakeup event status.
Write To Clear Mode
The following register bits are cleared by write ‘1”.
Register 1 bit 2 and 3
Register 7
Register 0AH bit 2
Register 82H ~ 86H
Force Collision in Loopback Mode
Used for testing only.
Full-Duplex Mode
1 = Full-Duplex mode
0 = Half-Duplex mode
4
FCOL
PHS0,RW
3
FDX
PHS0,RW
2:1
LBK
PH00,RW
0
RST
PH0,RW
Description
External PHY Mode (valid when pin TEST1 tie to ground)
1 = Select external PHY
0 = Select Internal PHY
Read only in Internal PHY mode.
This bit can be written only in External PHY mode.
This bit can also be forced by register 2EH bit 5 and 1.
Loopback Mode
00 = Normal
01 = MAC internal loopback
10 = Internal PHY digital loopback
11 = Internal PHY analog loopback
Software Reset
When write “1” to this bit, DM9621A enters software reset mode and
will be automatically cleared after 10us.
Write “0” to this bit can end the software reset mode.
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
4.2 Network Status Register (01H)
Bit
7
6
Name
SPEED
LINKST
Default
PHS0,
RW
PHS0,
RO
5
WAKEST
P0,
W/C1
4
RESERVED
3
RESERVED
2
RESERVED
1
RXOV
PHS0,
RO
PHS0,
RW/C1
PHS0,
RW/C1
PHS0,
RO
0
RXRDY
PHS0,
RO
Description
Media Speed Status
1 = 10Mbps
0 = 100Mbps
This bit is no meaning when LINKST=0.
This bit read only in internal PHY mode and it can be written in external
PHY mode.
This bit can also be forced by register 2EH bit 5 and 2.
Link Status
1 = Link OK
0 = Link failed
This bit read only in internal PHY mode and it can be written in external
PHY mode.
This bit can also be forced by register 2EH bit 5 and 0.
Wakeup Event Status
This bit is set when wakeup event status asserted.
This bit is cleared by write “1” or when wakeup mode disabled.
Reserved
Reserved
Reserved
RX FIFO Overflow Status
This bit is set when RX FIFO free space is less than 544-byte
This bit be cleared when RX FIFO free space is more than 2K.
RX Packet Ready
This bit is set when there are one or more packets in RX FIFO.
Final
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4.3 TX Control Register (02H)
Bit
7
6
Name
RESERVED
TJDIS
Default
0,RO
PHS0,
RW
5
EXCECM
PHS0,
RW
4
RESERVED
3
RESERVED
2
PAD_DIS1
PHS0,
RW
PHS0,
RW
PHS0,
RW
1
CRC_DIS1
PHS0,
RW
0
RESERVED
PHS0,
RW
Description
Reserved
Transmit Jabber Disable
The transmit Jabber Timer(2048 bytes) is disabled. Otherwise the
transmit packet size can more than 2048-byte.
Excessive Collision Mode Control
1 = still try to transmit this packet
0 = abort this packet when excessive collision count more than 15
Reserved
Reserved
TX Packet PAD Append Control
1 = the transmit packet size is unchanged from original setting
0 = the transmit packet size is appended to at least 64-byte
TX Packet Index II CRC Appends Control
1 = the CRC field is not appended
0 = the CRC field is appended automatically
Reserved
4.4 RX Control Register (05H)
Bit
7
6
Name
HASHALL
WTDIS
Default
PHS0,RW
PHS0,RW
5
DIS_LONG
PHS0,RW
4
DIS_CRC
PHS0,RW
3
ALL
PHS0,RW
2
RUNT
PHS0,RW
1
PRMSC
PHS0,RW
0
RXEN
PHS0,RW
Description
Filter All Address in Hash Table
Watchdog Timer Disable
When set, the Watchdog Timer(2048 bytes) is disabled and the RX
packet may more than 2048-byte.
When cleared, the Watchdog Timer(2048 bytes) is enabled and he RX
packet is truncated after the data more than 2048-byte.
Discard Long Packet
The packets with length over 1522-byte are discarded from RX
memory.
Discard CRC Error Packet
The packets with CRC error are discarded from RX memory.
Pass All Multicast
The packets with multicast destination address are stored to RX
memory.
Pass Runt Packet
The packets with size less than 64-byte are stored to RX memory.
Promiscuous Mode
The destination address is do not be checked.
RX Enable
The received accepted packets can be stored to RX memory.
Final
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4.5 RX Status Register (06H)
Bit
7
Name
RF
Default
PHS0,RO
6
MF
PHS0,RO
5
LCS
PHS0,RO
4
RWTO
PHS0,RO
3
PLE
PHS0,RO
2
AE
PHS0,RO
1
CE
PHS0,RO
0
FOE
PHS0,RO
Description
Runt Frame
It is set to indicate the received frame has the size smaller than 64
bytes.
Multicast Frame
It is set to indicate the received frame has a multicast address.
Late Collision Seen
It is set to indicate a late collision found during the frame reception.
Receive Watchdog Time-Out
It is set to indicate receive more than 2048 bytes.
Physical Layer Error
It is set to indicate a physical layer error found during the frame
reception.
Alignment Error
It is set to indicate the received frame ends with a non-byte boundary.
CRC Error
It is set to indicate the received frame ends with a CRC error.
FIFO Overflow Error
It is set to indicate a FIFO Overflow error happens during the frame
reception.
4.6 Receive Overflow Counter Register (07H)
07H can be cleared by writing any data this byte. They also can be cleared by read this byte if register 0H bit 5
is “0”.
Bit
Name
Default
Description
Receive Overflow Counter Overflow
7
RXFU
PHS0,
RW/C
This bit is set when the ROC has an overflow condition.
Receive Overflow Counter
6:0
ROC
PHS0,
RW/C
This is a statistic counter to indicate the received packet count upon
FIFO overflow.
Final
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4.7 Back Pressure Threshold Register (08H)
Bit
7:4
3:0
Name
BPHW
JPT
Default
PHS3h,
RW
PHS7h,
RW
Description
Back Pressure High Water Overflow Threshold. MAC will generate the
jam pattern when RX SRAM free space is lower than this threshold
value.
Default is 3K-byte free space. Please don’t exceed SRAM size.
(1 unit=1K bytes)
Jam Pattern Time. Default is 100us.
Bit3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Time
2.5us
5us
7.5us
12.5us
25us
50us
75us
100us
125us
150us
175us
200us
2250us
250us
275us
300us
4.8 Flow Control Threshold Register (09H)
Bit
7:4
Name
HWOT
Default
PHS3h,
RW
3:0
LWOT
PHS8h,
RW
Description
RX FIFO High Water Overflow Threshold
Send a pause packet with pause_time=FFFFH when the RX RAM free
space is less than this value., If this value is zero, its meaning is no free
RX SARM space. Default is 3K-byte free space. Please don’t exceed
SRAM size.
(1 unit=1K bytes)
RX FIFO Low Water Overflow Threshold
Send a pause packet with pause_time=0000 when RX SARM free
space is larger than this value. This pause packet is enabled after high
water pause packet transmitted. Default SRAM free space is 8K-byte.
Please don’t exceed SRAM size.
(1 unit=1K bytes)
Final
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4.9 RX/TX Flow Control Register (0AH)
Bit
7
Name
TXP0
Default
PHS0,RW
6
TXPF
PHS0,RW
5
TXPEN
PHS0,RW
4
BKPA
PHS0,RW
3
BKPM
PHS0,RW
2
RXPS
PHS0,
RW/C
1
RXPCS
PHS0,RO
0
FLCE
PHS0,RW
Description
Force to TX Pause Packet with Time 0000H
This bit will be automatically cleared after pause packet transmission
completion.
Set to TX pause packet with time = 0000H.
Force to TX Pause Packet with Time FFFFH
This bit will be automatically cleared after pause packet transmission
completion.
Set to TX pause packet with time = FFFFH.
TX Pause Packet Enable
Enable the pause packet for high/low water threshold of register 09H in
Full-Duplex mode.
Back Pressure Packet Mode Enable
Generate a jam pattern when any packet coming and RX SRAM over
BPHW of register 8H in Half-Duplex mode.
Back Pressure DA Mode
Generate a jam pattern when a packet’s DA match and RX SRAM over
BPHW of register 8H in Half-Duplex mode.
RX Pause Packet Status
This bit latched the RX pause packet in Full-Duplex mode.
This bit can be cleared by write “1” to this bit or cleared automatically
after read if register 0H bit 5 is “0”.
RX Pause Packet Current Status
When set, it indicated that the pause timer is not down count to “0” yet.
Flow Control Enable
When set, it enable the flow control mode(i.e. can to disable TX
function).
4.10 EEPROM & PHY Control Register (0BH)
Bit
7
Name
NO_EEP
Default
P0,RO
6
EE_TYPE
P0,RO
5
REEP
PH0,RW
4
WEP
PH0,RW
3
EPOS
PH0,RW
2
ERPRR
PH0,RW
1
ERPRW
PH0,RW
0
ERRE
PH0,RO
Description
EEPROM Absent
When set, it indicates the EEPROM 93C46 or 93C56/66 is not
detected.
EEPROM Type
1 = 93C56/66
0 = 93C46
Reload EEPROM
The EEPROM is re-loaded.
Driver needs to clear it after operation complete.
Write EEPROM Enable
The written ability of EEPROM is enabled.
EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY.
EEPROM Read or PHY Register Read Command
Write “1” to start EEPROM or PHY read operation.
This bit will be cleared after the completion of read operation.
EEPROM Write or PHY Register Write Command
Write “1” to start EEPROM or PHY write operation.
This bit will be cleared after the completion of write operation.
EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress.
Final
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4.11 EEPROM & PHY Address Register (0CH)
Bit
7:6
Name
PHY_ADR
Default
PH01,RW
5:0
EROA
PH0,RW
Description
PHY Address bit [1:0] or EEPROM Word Address[7:6]
If it is in PHY mode operation , the PHY address bit [4:2] is force to 0.
Force to 01 if internal PHY is selected.
Or EEPROM Word Address[7:6] if EEPROM 93C56/66 is used
EEPROM Word Address[5:0] or PHY Register Number
4.12 EEPROM & PHY Data Register (EE_PHY_L:0DH
Bit
7:0
7:0
Name
EE_PHY_L
EE_PHY_H
Default
X,RW
X,RW
EE_PHY_H:0EH)
Description
EEPROM or PHY Low Byte Data
EEPROM or PHY High Byte Data
4.13 Wake Up Control Register (0FH)
Bit
7
Name
SMI_EN
Type
P0,RW
6
SMI_ST
P0,RO
5
LINKEN
PE0,RW
4
SAMPLEEN
PE0,RW
3
MAGICEN
PE0,RW
2
LINKST
P0,RO
1
SAMPLEST
P0,RO
0
MAGICST
P0,RO
Description
SMI_C Event Enable
When set, enable SMI_C as GPIO Wake-up Event.
This event occurred in 100ms low state and then 100ms high state in
SMI_C pin
SMI_C Even Status
When set, indicates SMI_C Event occurred.
Link Change Event Enable
When set, enable Link Status Change Wake-up Event.
Sample Frame Match Event Enable
When set, enable Sample Frame Wake-up Event.
Magic Packet Event Enable
When set, enable Magic Packet Wake-up Event.
Link change Event Status
When set, indicates link change and Link Status Change Event
occurred.
Sample Frame Mtach Event Status
When set, indicates the sample frame is received and Sample Frame
Event occurred. This bit will not be affected after a software reset.
Magic Packet Event Status
When set, indicates the Magic Packet is received and Magic packet
Event occurred. This bit will not be affected after a software reset.
4.14 Physical Address Register (10H~15H)
Bit
7:0
7:0
7:0
7:0
7:0
7:0
Name
PAB5
PAB4
PAB3
PAB2
PAB1
PAB0
Default
E,RW
E,RW
E,RW
E,RW
E,RW
E,RW
Physical Address Byte 5
Physical Address Byte 4
Physical Address Byte 3
Physical Address Byte 2
Physical Address Byte 1
Physical Address Byte 0
Description
(15H)
(14H)
(13H)
(12H)
(11H)
(10H)
Final
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4.15 Multicast Address Register (16H~1DH)
Bit
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Name
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
Default
P80,RW
P00,RW
P00,RW
P00,RW
P00,RW
P00,RW
P00,RW
P00,RW
Multicast Address Byte 7
Multicast Address Byte 6
Multicast Address Byte 5
Multicast Address Byte 4
Multicast Address Byte 3
Multicast Address Byte 2
Multicast Address Byte 1
Multicast Address Byte 0
Description
(1DH)
(1CH)
(1BH)
(1AH)
(19H)
(18H)
(17H)
(16H)
4.16 General Purpose Control Register (1EH)
Bit
7:4
3:0
Name
RESERVED
RESERVED
Default
P0,RO
P0111,
RW
Description
Reserved
Reserved
4.17 General Purpose Register (1FH)
Bit
7:4
3:1
0
Name
RESERVED
RESERVED
GEPIO0
Default
P0,RO
P0,RW
PE1,RW
Description
Reserved
Reserved
General Purpose
When the correspondent bit of General Purpose Control Register is 1,
the value of the bit is output to pin GEPIO0.
When the correspondent bit of General Purpose Control Register is 0,
the value of the bit be read is reflected from pin GEPIO0.
GEPIO0 default output 1 to POWER_DOWN internal PHY. Driver need
to clear this POWER_DOWN signal by write “0” when it wants PHY
active. If other device need, it also can refer this signal. This default
value can be programmed by EEPROM. Please refer EEPROM
description.
4.18 Vendor ID Register (28H~29H)
Bit
7:0
7:0
Name
VIDH
VIDL
Default
0AH,RO
46H,RO
Description
Vendor ID high byte (29H)
Vendor ID low byte (28H)
4.19 Product ID Register (2AH~2BH)
Bit
7:0
7:0
Name
PIDH
PIDL
Default
96H,R
20H,R
Description
Product ID high byte (2BH)
Product ID low byte (2AH)
4.20 Chip Revision Register (2CH)
Bit
7:0
Name
CHIPR
Default
01H,RO
Description
CHIP revision
Final
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4.21 TX Special Control Register (2DH)
Bit
7
6
5
3
3:0
Name
RESERVED
LCOL_TRY
RESERVED
RESERVED
TX_GAP
Default
PH0,RW
PH0,RW
PH0,RW
PH0,RW
PH0,RW
Description
Reserved
Late Collision Retry
Reserved
Reserved
TX Inter frame Gap
0XXX =
96-bit
1000 =
64-bit
1001 =
72-bit
1010 =
80-bit
1011 =
88-bit
1100 =
96-bit
1101 =
104-bit
1110 =
112-bit
1111 =
120-bit
4.22 External PHY Force Mode Control Register (2EH)
Bit
7:6
5
4
3
2
Name
RESERVED
EXTERNAL
RESERVED
RESERVED
SPEED
Default
0,RO
HP0,RW
0,RO
PH0,RW
HP0,RW
1
DUPLEX
HP0,RW
0
LINK
HP0,RW
Description
Reserved
Force to external PHY mode
Reserved
Reserved
Force external PHY Speed Mode in MAC register 1 bit 7
1 = Force to 10Mbps mode
0 = Force to 100Mbps mode
Force External PHY Duplex Mode in MAC register 0 bit 3
1 = Force to Half-Duplex
0 = Force to Full-Duplex
Force external PHY Link Mode in MAC register 1 bit 6
1 = Force to link OFF
0 = Force to link ON
4.23 Transmit Check Sum Control Register (31H)
Bit
7:3
2
1
0
Name
RESERVED
UDPCSE
TCPCSE
IPCSE
Default
0,RO
HPS0,RW
HPS0,RW
HPS0,RW
Description
Reserved
UDP Checksum Generation Enable
TCP Checksum Generation Enable
IP Checksum Generation Enable
Final
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4.24 Receive Check Sum Control Status Register (32H)
Bit
7
Name
UDPS
Default
HPS0,RO
6
TCPS
HPS0,RO
5
IPS
HPS0,RO
4
3
2
1
UDPP
TCPP
IPP
RCSEN
HPS0,RO
HPS0,RO
HPS0,RO
HPS0,RW
0
DCSE
HPS0,RW
Description
UDP Checksum Status
1 = UDP packet checksum error
0 = UDP packet checksum OK, or this is not UDP packet
TCP Checksum Status
1 = TCP packet checksum error
0 = TCP packet checksum OK, or this is not TCP packet
IP Checksum Status
1 = IP packet checksum error
0 = IP packet checksum OK, this is not IP packet
UDP Packet
TCP Packet
IP Packet
Receive Checksum Checking Enable
The checksum status will store in packet first byte of status header in
4-byte RX header register 91h.bit7 mode.
Discard Checksum Error Packet
When set, if IP/TCP/UDP checksum field is error, this packet will be
discarded.
4.25 External PHY Ceiver Address Register (33H)
Bit
7
Name
ADR_EN
Default
HPS0,RW
6:5
4:0
Reserved
EPHYADR
HPS0,RO
HPS01,
RW
Description
External PHY Address Enabled
When set in external MII mode, the external PHYceiver address is
defined at bit 4:0.
Reserved
External PHY Address Bit 4:0
The PHY address in external MII mode.
4.26 General Purpose Control Register 2 (34H)
Bit
7:0
Name
GPC2
Default
HP0,RW
Description
General Purpose Control 2
Define the input mode (“0”,) or output mode (“1”) of pins GP_GRP2.
Where the GP_GRP2 are pins GPIO2 listed in pin description
4.27 General Purpose Register 2 (35H)
Bit
7:0
Name
GPD2
Default
HP0,RW
Description
General Purpose Register 2 Data
When the correspondent bit of General Purpose Control Register 2 is
set, i.e. output mode, the value of the bit is reflected to pins GP_GPR2
When the correspondent bit of General Purpose Control Register 2 is
0, i.e. input mode, the value of the bit to be read is reflected from
correspondent pins GP_GPR2.
NOTE: DM9621/9621a no register 36H,37H
Final
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4.28 EEPROM and PHY Control Register (3AH)
Bit
7
6
5
4:3
Name
FORCE_46
DET_46
DET_56
EECK_SPD
Default
PT0,RW
P0,RO
P0,RO
P0,RW
2
1:0
NO_PRE
MDC_SPD
P0,RW
P0,RW
Description
Force EEPROM to 93C46 type
Auto-detect EEPROM as 93C46
Auto-detect EEPROM as 93C56/66
Re-define EEPROM EECK speed
00=0.2Mhz, 01=0.5MHz, 10=1MHz, 11=2MHz
Do no generate Ethernet PHY preamble in MDIO
Re-define Ethernet PHY MDC speed
00=1Mhz, 01=3.1MHz, 10=12.5MHz, 11=0.25MHz
4.29 Pause Packet Control/Status Register (3DH)
Bit
7:4
Name
PAUSE_CTR
Default
P0,RO
3:0
PAUSE_MAX
PHS4,
RW
Description
Pause Packet Counter
The Pause packet counter before RX SRAM flow control low threshold
reached.
Max. Pause Packet Count
The maximum pause packet with timer FFFFH is transmit, when the
RX SRAM is still in high threshold when pause timer timeout.
4.30 IEEE802.3az Enter Time Register (3EH)
Bit
7
6:0
Name
RESERVED
ENTER_TIME
Default
P,RO
PHS5,
RW
Description
Reserved
Timer to Enter EEE LPI Mode (unit 2us)
When the idle time of transmit is greater than this timer, the DM9621A
enter Low Power Idle mode.
4.31 IEEE802.3az Leave Time Register (3FH)
Bit
7
6:0
Name
EEE_EN
LEAVE_TIME
Default
P0,RO
PHSF,
RW
Description
EEE Enable
Timer to Leave EEE LPI Mode (unit 2us)
In Low Power Idle mode, when the TX SRAM have packets to be
transmit, the DM9621A enter normal operation mode after this timer
timeout.
4.32 Link Up/Down Wakeup Event Register (51H)
Bit
7:2
1
Name
RESERVED
LINK_DW_D
Default
P,RO
PHS0,
RW
0
LINK_UP_D
PHS1,
RW
Description
Reserved
Link Down WOL Control
1 = Enable link down wakeup event
0 = Disable link down wakeup event
Link UP WOL Control
1 = Enable link up wakeup event
0 = Disable link up wakeup event
Final
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4.33 IPv6 NA/ARP Register (52H)
Bit
7:4
3
Name
RESERVED
IPV6_ND_A
Default
P,RO
PHS0,
RW
2
IP_ARP_A
PHS0,
RW
1
IPV6_NA_E
PHS0,
RW
0
IP_ARP_E
PHS0,
RW
Description
Reserved
IPv6 Neighbor Solicitation Remote Address Control
1= Enable to check remote address field
0 = Disable to check remote address field
IP ARP Request Destination IP Address Control
1 = Enable to check DST IP address field
0 = Disable to check DST IP address field
IPv6 Neighbor Advertisement Control
1 = Enabled
0 = Disabled
IP ARP Offload Control
1 = Enabled
0 = Disabled
4.34 Minimum RX SOF Control Register (58H)
Bit
7:0
Name
SOF_count
Default
PS0,RO
Description
SOF Control Counter
The minimum SOF count to report packet ready in Multi-RX mode
4.35 Minimum RX Burst Counter Register (59H)
Bit
7:0
Name
RX_count
Default
PS0,RO
Description
Multi-RX Mode
Minimum RX byte count (Unit: 512-byte) to report packet ready in
Multi-RX mode.
4.36 Transmit Packet Counter (81H)
Bit
7:0
Name
TX_CTR
Default
PS0,RO
Description
TX Packet Count
The TX packet count in TX SRAM.
4.37 USB Packet Error Counter (82H)
Bit
7:0
Name
USB_ERR
Default
PHS0,
RW/C
Description
USB Data Error Count
This counter is increased when there has been data CRC error in USB
packet. This counter can be cleared by read if register 5 is “0” or by
write to this register with any data.
4.38 Ethernet Receive Packet CRC Error Counter (83H)
Bit
7:0
Name
RX_ERR
Default
PHS0,
RW/C
Description
Ethernet RX Packet CRC Error Count
This counter is increased when there has been CRC error in Ethernet
receive packet. This counter can be cleared by read if register 5 is “0”
or by write to this register with any data.
Final
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4.39 Ethernet Transmit Excessive Collision Counter (84H)
Bit
7:0
Name
ECOL_CTR
Default
PHS0,
RW/C
Description
Ethernet TX Packet Excessive Collision Count
This counter is increased when there has been excessive collision, i.e.
continued 16 collisions, in Ethernet transmit packet. This counter can
be cleared by read if register 5 is “0” or by write to this register with any
data.
4.40 Ethernet Transmit Collision Counter (85H)
Bit
7:0
Name
COL_CTR
Default
PHS0,
RW/C
Description
Ethernet TX Packet Collision Count
This counter is increased when there has been collision in Ethernet
transmit packet. This counter can be cleared by read if register 5 is “0”
or by write to this register with any data.
4.41 Ethernet Transmit Late Collision Counter (86H)
Bit
7:0
Name
LCOL_CTR
Default
PHS0,
RW/C
Description
Ethernet TX Packet Late Collision Count
This counter is increased when there has been late collision in Ethernet
transmit packet. This counter can be cleared by read if register 5 is “0”
or by write to this register with any data.
4.42 RX Header Control/Status Register (91H)
Bit
7
Name
RX Header
MODE
Default
PT,RW
6:4
3
RESERVED
Multi RX_USB
P,RO
PT,RW
2
Multi TX _ USB
PT,RW
1:0
RESERVED
P0,RW
Description
RX Header Mode
Reference to sec. 7.1.3.1
1 = 4-byte RX header
0 = 3-byte RX header. This is compatible with DM9601.
Reserved
USB Bulk IN Transfer for Ethernet RX Packet
1 = Multiple Ethernet RX packets in one USB Bulk IN transfer
0 = Only one Ethernet RX packet in one USB Bulk IN transfer
USB Bulk OUT Transfer for Ethernet TX Packet
1 = Allow multiple Ethernet TX packets in one USB Bulk OUT transfer
0 = Only one Ethernet TX packet in one USB Bulk OUT transfer
Reserved
4.43 USB Squelch Control (95H)
Bit
7:2
2:0
Name
RESERVED
SQUELCH
Default
P0,RO
P101,
RW
Description
Reserved
Reference Voltage for USB Squelch Circuit
000 for Reference voltage = 27.5mV
100 for Reference voltage = 137.5mV (default)
111 for Reference voltage = 220mV
Final
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DM9621A
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4.44 USB Address (96H)
Bit
7:0
Name
USB_ADR
Default
P0,RO
Description
USB Address
4.45 USB Device Address Register (F0H)
Bit
7
6:0
Name
RESERVED
USBFA
Default
0,RO
0,RO
Description
Reserved
USB device address
4.46 Receive Packet Counter Register (F1H)
Bit
7:0
Name
RXC
Default
0,RO
Description
RXC is the packet counter received in SRAM
4.47 USB Status Register (F2H)
Bit
7
6
5
4
3
2
1
0
Name
RXFAULT
SUSFLAG
EP1RDY
RESERVED
BOFAULT
TXC2
TXC1
TXC0
Default
0,RC
0,RC
0,RO
0,RO
0,RO
0,RO
0,RO
0,RO
Description
Indicate RX has unexpected condition
Indicate device has suspend condition
Indicate there are data ready for read from EP1 pipe
Reserved
Indicate Bulk Out has unexpected condition
Represent there is full in transmit buffer
Represent there is almost full in transmit buffer
Represent there have packets in transmit buffer.
4.48 USB Control Register (F4H)
Bit
7:6
5
Name
RESERVED
EP3ACK
Default
0,RW
0,RW
4
3:1
0
EP3NAK
RESERVED
MEMTST
0,RW
0,RW
0,RW
Description
Reserved
When set and EP3_NAK=0, EP3 will always return 8-byte data to host
per interrupt-interval
When set, EP3 will always return NAK.
Reserved
Before any memory-command, this bit must be set to 1. When in
MEM_TST, TX/RX FIFO controller will be flushed.
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
5
EEPROM Format
Name
MAC Address
Auto Load Control
Word
0
3
Vendor ID
Product ID
802.3az
Control
4
5
6
Wake-UP Mode
Control
7
String1 Address
String1 Length
String2 Address
String2 Length
String3 Address
String3 Length
USB Control
8
8
9
9
10
10
11
EP3
Interrupt Interval
12
Offset
Description
0~5 6 byte Ethernet Address
6~7 If Bit 1:0 = 01: Update vendor ID and product ID
If Bit 3:2 = 01: Reserved
If Bit 5:4 = 01: Accept setting of WORD7[10] and WORD6
If Bit 7:6 = 01: Accept setting of WORD7[11,3:0]
If Bit 9:8 = 01: Accept setting of WORD7[6:4]
If Bit 11:10 = 01: Accept setting of WORD7[7]
If Bit 13:12 = 01: Accept setting of WORD7[9:8]
If Bit 15:14 = 01: Accept setting of WORD7[15:12], WORD11
8~9 2 byte vendor ID (Default: 0A46h)
10~11 2 byte product ID (Default: 9621h)
12~13 Bit 6:0 = Load into register 3EH bit [6:0]
Bit 14:8 = Load into register 3FH bit [6:0]
Bit 15 = Load into register 3FH bit [7]
14~15 Bit 0:1 = WOL active low when set (default: active high)
Bit 1:1 = WOL is pulse mode (default: level mode)
Bit 2:1 = Wakeup event enabled, load into register 0 bit 6. (default: no)
Bit 3 = Reserved
Bit 4:1 = Magic wakeup event enabled if USB in suspend state
(default: no)
Bit 5:1 = link_change wakeup event enabled if USB in suspend state
(default: no)
Bit 6 = Reserved
Bit 7 = LED mode 1 (default: 0)
Bit 8:1 = Internal PHY is enabled after power-on (default: no)
Bit 9:1 = Ethernet PHY in fiber mode (default: no)
Bit 10 = Reserved
Bit 11:1 = WOL SMI event enable, to register 0FH bit 7 (default: no)
Bit 12:Reserved, set to “0” in application
Bit 13:Reserved, set to “0” in application
Bit 14:1 = Enable MDIX (default: yes)
Bit 15 = Reserved, set to “0” in application
16
Vendor describe string start address
17
Vendor describe string length
18
Product describe string start address
19
Product describe string length
20
Product describe string start address
21
Product describe string length
22~23 Bit 7:0 = USB maximum power. Unit is 2ma., default 5AH
Bit 15:8 = USB class code
24
Bit 3:0 EP3 interrupt interval, default 0BH
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
6
PHY Register Description
Key to Default
In the register description that follows, the default column takes the form:
<Reset Value>:
<Access Type>:
1
Bit set to logic one
RO = Read only
0
Bit set to logic zero
RW = Read/Write
X
No default value
(PIN#) Value latched in from pin # at reset
<Attribute(s)>:
SC = Self clearing
P=
Value permanently set
LL = Latching low
LH = Latching high
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DM9621A
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6.1 Basic Mode Control Register (BMCR) – 00H
Bit
15
14
13
Bit Name
Reset
Loopback
Speed Selection
Default
0,RW/SC Reset
1 = Software reset
0 = Normal operation
0,RW
1,RW
12
Auto-Negotiation
Enable
1,RW
11
Power Down
0,RW
10
Isolate
9
Restart
Auto-Negotiation
8
Duplex Dode
Description
This bit sets the status and controls the PHY registers to their default
states. This bit, which is self-clearing, will keep returning a value of
one until the reset process is completed.
Loopback
Loop-back control register
1 = Loop-back enabled
0 = Normal operation
When in 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 1300ms "dead
time" before any valid data appear at the MII receive outputs
Speed Select
1 = 100Mbps
0 = 10Mbps
Link speed may be selected either by this bit or by Auto-Negotiation.
When Auto-Negotiation is enabled and bit 12 is set, this bit will return
auto-negotiation selected media type.
Auto-Negotiation Enable
1 = Auto-Negotiation is enabled, bit 8 and 13 will be in
Auto-Negotiation status
Power Down
While in the power-down state, the PHY should respond to
management transactions. During the transition to power-down state
and while in the power-down state, the PHY should not generate
spurious signals on the MII.
1 = Power down
0 = Normal operation
Isolate
0,RW
1 = Isolates (Reserved)
0 = Normal operation
0,RW/SC Restart Auto-Negotiation
1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation
process. When Auto-Negotiation is disabled (bit 12 of this
register cleared), this bit has no function and it should be
cleared. This bit is self-clearing and it will keep returning a value
of 1 until Auto-Negotiation is initiated by the PHY. The operation
of the Auto-Negotiation process will not be affected by the
management entity that clears this bit
0 = Normal operation
Duplex mode
1,RW
1 = Full-Duplex operation. Duplex selection is allowed when
Auto-Negotiation is disabled (bit 12 of this register is cleared).
With Auto-Negotiation enabled, this bit reflects the duplex
capability selected by Auto-Negotiation
0 = Normal operation
Final
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DM9621A
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7
Collision Test
0,RW
6:0
RESERVED
0,RO
Collision Test
1 = Collision test enabled. When set, this bit will cause the COL
signal to be asserted in response to the assertion of TX_EN
0 = Normal operation
Reserved
Write as 0, ignore on read
6.2 Basic Mode Status Register (BMSR) – 01H
Bit
15
Bit Name
100BASE-T4
Default
0,RO/P
14
100BASE-TX
Full-Duplex
1,RO/P
13
100BASE-TX
Half-Duplex
1,RO/P
12
10BASE-T
Full-Duplex
1,RO/P
11
10BASE-T
Half-Duplex
1,RO/P
10:7
RESERVED
0,RO
6
MF Preamble
Suppression
0,RO
5
Auto-Negotiation
Complete
0,RO
4
Remote fault
0,RO/LH
3
Auto-Negotiation
Ability
1,RO/P
2
Link Status
0,RO/LL
Description
100BASE-T4 Capable
1 = Able to perform in 100BASE-T4 mode
0 = Not able to perform in 100BASE-T4 mode
100BASE-TX Full-Duplex Capable
1 = Able to perform 100BASE-TX in Full-Duplex mode
0 = Not able to perform 100BASE-TX in Full-Duplex mode
100BASE-TX Half- Duplex Capable
1 = Able to perform 100BASE-TX in Half-Duplex mode
0 = Not able to perform 100BASE-TX in Half-Duplex mode
10BASE-T Full-Duplex Capable
1 = Able to perform 10BASE-T in Full-Duplex mode
0 = Not able to perform 10BASE-TX in Full-Duplex mode
10BASE-T Half-Duplex Capable
1 = Able to perform 10BASE-T in Half-Duplex mode
0 = Not able to perform 10BASE-T in Half-Duplex mode
Reserved
Write as 0, ignore on read
MII Frame Preamble Suppression
1 = PHY will accept management frames with preamble suppressed
0 = PHY will not accept management frames with preamble
suppressed
Auto-Negotiation Complete
1 = Auto-Negotiation process completed
0 = Auto-Negotiation process not completed
Remote Fault
1 = Remote fault condition detected (cleared on read or by a chip
reset). Fault criteria and detection method is PHY
implementation specific. This bit will set after the RF bit in the
ANLPAR (bit 13, register address 05) is set
0 = No remote fault condition detected
Auto Configuration Ability
1 = Able to perform Auto-Negotiation
0 = Not able to perform Auto-Negotiation
Link Status
1 = Valid link is established (for either 10Mbps or 100Mbps
operation)
0 = Link is not established
The link status bit is implemented with a latching function, so that the
occurrence of a link failure condition causes the link status bit to be
cleared and remain cleared until it is read via the management
interface
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DM9621A
USB2.0 to Fast Ethernet Controller
1
0
Jabber Detect
Extended
Capability
0,RO/LH
1,RO/P
Jabber Detect
1 = Jabber condition detected
0 = No jabber
This bit is implemented with a latching function. Jabber conditions
will set this bit unless it is cleared by a read to this register through a
management interface or a PHY reset. This bit works only in 10Mbps
mode
Extended Capability
1 = Extended register capable
0 = Basic register capable only
6.3 PHY ID Identifier Register #1 (PHYID1) – 02H
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9621A. The Identifier
consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a
model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Bit
Bit Name
Default
Description
OUI Most Significant Bits
15:0
OUI_MSB
<0181h>
This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of
this register respectively. The most significant two bits of the OUI
are ignored (the IEEE standard refers to these as bit 1 and 2)
6.4 PHY Identifier Register #2 (PHYID2) – 03H
Bit
15:10
Bit Name
OUI_LSB
Default
<101110>,
RO/P
9:4
VNDR_MDL
<001010>,
RO/P
3:0
MDL_REV
<0000>,
RO/P
Description
OUI Least Significant Bits
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this
register respectively
Vendor Model Number
Six bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9)
Model Revision Number
Four bits of vendor model revision number mapped to bit 3 to 0
(most significant bit to bit 3)
Final
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DM9621A
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6.5 Auto-Negotiation Advertisement Register(ANAR) – 04H
This register contains the advertised abilities of this DM9621A device as they will be transmitted to its link
partner during Auto-Negotiation.
Bit
Bit Name
Default
Description
Next Page Indication
15
NP
0,RO/P
1 = Next page available
0 = No next page available
The PHY has no next page, so this bit is permanently set to 0
Acknowledge
14
ACK
0,RO
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
13
RF
0,RW
12:11
RESERVED
X,RW
10
FCS
0,RW
9
T4
0,RO/P
8
TX_FDX
7
TX_HDX
6
10_FDX
5
10_HDX
4:0
Selector
The PHY's Auto-Negotiation state machine will automatically
control this bit in the outgoing FLP bursts and set it at the
appropriate time during the Auto-Negotiation process. Software
should not attempt to write to this bit.
Remote Fault
1 = Local device senses a fault condition
0 = No fault detected
Reserved
Write as 0, ignore on read
Flow Control Support
1 = Controller chip supports flow control ability
0 = Controller chip doesn’t support flow control ability
100BASE-T4 Support
1 = 100BASE-T4 is supported by the local device
0 = 100BASE-T4 is not supported
The PHY does not support 100BASE-T4 so this bit is permanently
set to 0
100BASE-TX Full-Duplex Support
1,RW
1 = 100BASE-TX Full-Duplex is supported by the local device
0 = 100BASE-TX Full-Duplex is not supported
100BASE-TX Support
1,RW
1 = 100BASE-TX is supported by the local device
0 = 100BASE-TX is not supported
10BASE-T Full-Duplex Support
1,RW
1 = 10BASE-T Full-Duplex is supported by the local device
0 = 10BASE-T Full-Duplex is not supported
10BASE-T Support
1,RW
1 = 10BASE-T is supported by the local device
0 = 10BASE-T is not supported
<00001>,RW Protocol Selection Bits
These bits contain the binary encoded protocol selector supported
by this node.
<00001> indicates that this device supports IEEE 802.3 CSMA/CD.
Final
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DM9621A
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6.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) – 05H
Bit
15
Bit Name
NP
Default
0,RO
14
ACK
0,RO
13
RF
12:11
RESERVED
10
FCS
9
T4
8
TX_FDX
7
TX_HDX
6
10_FDX
5
10_HDX
4:0
Selector
Description
Next Page Indication
0 = Link partner, no next page available
1 = Link partner, next page available
Acknowledge
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The PHY's Auto-Negotiation state machine will automatically
control this bit from the incoming FLP bursts. Software should not
attempt to write to this bit.
Remote Fault
0,RO
1 = Remote fault indicated by link partner
0 = No remote fault indicated by link partner
Reserved
X,RO
Write as 0, ignore on read
Flow Control Support
0,RW
1 = Controller chip supports flow control ability by link partner
0 = Controller chip doesn’t support flow control ability by link
partner
100BASE-T4
Support
0,RO
1 = 100BASE-T4 is supported by the link partner
0 = 100BASE-T4 is not supported by the link partner
100BASE-TX Full-Duplex Support
0,RO
1 = 100BASE-TX Full-Duplex is supported by the link partner
0 = 100BASE-TX Full-Duplex is not supported by the link partner
100BASE-TX Support
0,RO
1 = 100BASE-TX Half-Duplex is supported by the link partner
0 = 100BASE-TX Half-Duplex is not supported by the link partner
10BASE-T Full-Duplex Support
0,RO
1 = 10BASE-T Full-Duplex is supported by the link partner
0 = 10BASE-T Full-Duplex is not supported by the link partner
10BASE-T Support
0,RO
1 = 10BASE-T Half-Duplex is supported by the link partner
0 = 10BASE-T Half-Duplex is not supported by the link partner
<00000>,RO Protocol Selection Bits
Link partner’s binary encoded protocol selector
Final
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DM9621A
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6.7 Auto-Negotiation Expansion Register (ANER)- 06H
Bit
15:5
Bit Name
RESERVED
Default
X,RO
4
PDF
0,RO/LH
3
LP_NP_ABLE
0,RO
2
NP_ABLE
0,RO/P
1
PAGE_RX
0,RO/LH
0
LP_AN_ABLE
0,RO
Description
Reserved
Write as 0, ignore on read
Local Device Parallel Detection Fault
1 = A fault detected via parallel detection function.
0 = No fault detected via parallel detection function
Link Partner Next Page Able
1 = Link partner, next page available
0 = Link partner, no next page
Local Device Next Page Able
1 = Next page available
0 = No next page
New Page Received
A new link code word page received. This bit will be automatically
cleared when the register (register 6) is read by management.
Link Partner Auto-Negotiation Able
A “1” in this bit indicates that the link partner supports
Auto-Negotiation.
Final
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6.8 DAVICOM Specified Configuration Register (DSCR) – 10H
Bit
15
Bit Name
BP_4B5B
Default
0,RW
14
BP_SCR
0,RW
13
BP_ALIGN
0,RW
12
BP_ADPOK
0,RW
11
RESERVED
0,RO
10
TX
1,RW
9
8
RESERVED
RESERVED
0,RO
0,RO
7
F_LINK_100
0,RW
6
RESERVED
0,RO
5
RESERVED
0,RO
4
RPDCTR-EN
1,RW
3
SMRST
0,RW
2
MFPSC
1,RW
1
SLEEP
0,RW
0
RESERVED
0,RW
Description
Bypass 4B5B Encoding and 5B4B Decoding
1 = 4B5B encoder and 5B4B decoder function bypassed
0 = Normal 4B5B and 5B4B operation
Bypass Scrambler/Descrambler Function
1 = Scrambler and descrambler function bypassed
0 = Normal scrambler and descrambler operation
Bypass Symbol Alignment Function
1 = Receive functions (descrambler, symbol alignment and
symbol decoding functions) bypassed. Transmit functions
(symbol encoder and scrambler) bypassed
0 = Normal operation
BYPASS ADPOK
Force signal detector (SD) active. This register is for debug only,
not release to customer.
1=Force SD is OK
0=Normal operation
Reserved
Write as 0, ignore on read.
100BASE-TX or FX Mode Control
1 = 100BASE-TX operation
0 = 100BASE-FX operation
Reserved
Reserved
Write as 0, ignore on read.
Force good link in 100Mbps
1 = Force 100Mbps good link status
0 = Normal 100Mbps operation
This bit is useful for diagnostic purposes.
Reserved:
Write as 0, ignore on read.
Reserved:
Write as 0, ignore on read.
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down.
1 = Enable automatic reduced power down
0 = Disable automatic reduced power down.
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed.
MF Preamble Suppression Control
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Sleep Mode
Writing a 1 to this bit will cause PHY entering the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset.
Reserved
Force to 0 in application.
Final
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DM9621A
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6.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H
Bit
15
Bit Name
100FDX
Default
1,RO
14
100HDX
1,RO
13
10FDX
1,RO
12
10HDX
1,RO
11:9
RESERVED
0,RO
8:4
PHYADR[4:0]
(PHYADR),
RW
3:0
ANMB[3:0]
0,RO
Description
100M Full-Duplex Operation Mode
After Auto-Negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 100M Full-Duplex
mode. The software can read bit[15:12] to see which mode is
selected after Auto-Negotiation. This bit is invalid when it is not in
the Auto-Negotiation mode.
100M Half-Duplex Operation Mode
After Auto-Negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 100M Half-Duplex
mode. The software can read bit[15:12] to see which mode is
selected after Auto-Negotiation. This bit is invalid when it is not in
the Auto-Negotiation mode.
10M Full-Duplex Operation Mode
After Auto-Negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 10M Full-Duplex
mode. The software can read bit[15:12] to see which mode is
selected after Auto-Negotiation. This bit is invalid when it is not in
the Auto-Negotiation mode.
10M Half-Duplex Operation Mode
After Auto-Negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 10M Half-Duplex
mode. The software can read bit[15:12] to see which mode is
selected after Auto-Negotiation. This bit is invalid when it is not in
the Auto-Negotiation mode.
Reserved
Write as 0, ignore on read.
PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of the
address (bit 4). A station management entity connected to multiple
PHY entities must know the appropriate address of each PHY.
Auto-Negotiation Monitor Bits:
These bits are for debug only. The Auto-Negotiation status will be
written to these bits.
B3 B2 B1 B0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
In IDLE state
Ability match
Acknowledge match
Acknowledge match fail
Consistency match
Consistency match fail
Parallel detects signal_link_ready
Parallel detects signal_link_ready fail
Auto-Negotiation completed successfully
Final
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DM9621A
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6.10 10BASE-T Configuration/Status (10BTCSR) – 12H
Bit
15
Bit Name
RESERVED
Default
0,RO
14
LP_EN
1,RW
13
HBE
1,RW
12
SQUELCH
1,RW
11
JABEN
1,RW
10:1
RESERVED
0,RO
0
POLR
0,RO
Description
Reserved
Write as 0, ignore on read.
Link Pulse Enable
1 = Transmission of link pulses enabled
0 = Link pulses disabled, good link condition forced
This bit is valid only in 10Mbps operation.
Heartbeat Enable
1 = Heartbeat function enabled
0 = Heartbeat function disabled
When the PHY is configured for Full-Duplex operation, this bit will
be ignored (the collision/heartbeat function is invalid in Full-Duplex
mode).
Squelch Enable
1 = Normal Squelch
0 = Low Squelch
Jabber Enable
Enables or disables the Jabber function when the PHY is in
10BASE-T Full-Duplex or 10BASE-T transceiver loopback mode
1 = Jabber function enabled
0 = Jabber function disabled
Reserved
Write as 0, ignore on read.
Polarity Reversed
When this bit is set to 1, it indicates that the 10Mbps cable polarity
is reversed. This bit is set and cleared by 10BASE-T module
automatically.
6.11 Power down Control Register (PWDOR) – 13H
Bit
15:9
Bit Name
RESERVED
Default
0, RO
Description
Reserved
Read as 0, ignore on write
8
PD10DRV
0, RW
Vendor power down control test
7
PD100DL
0, RW
Vendor power down control test
6
PDchip
0, RW
Vendor power down control test
5
PDcom
0, RW
Vendor power down control test
4
PDaeq
0, RW
Vendor power down control test
3
PDdrv
0, RW
Vendor power down control test
2
PDedi
0, RW
Vendor power down control test
1
PDedo
0, RW
Vendor power down control test
0
PD10
0, RW
Vendor power down control test
* When selected, the power down value is control by Register 14H
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
6.12 (Specified Config) Register – 14H
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
TSTSE1
TSTSE2
FORCE_TXSD
Default
0,RW
0,RW
0,RW
Description
Vendor test select control
Vendor test select control
Force Signal Detect
1 = Force SD signal OK in 100M
0 = Normal SD signal.
FORCE_FEF
0,RW
Vendor test select control
Preamble Saving Control
PREAMBLEX
1,RW
1 = Transmit preamble bit count is normal in 10BASE-T mode
0 = When bit 10 is set, the 10BASE-T transmit preamble count is
reduced. When bit 11 of register 1DH is set, 12-bit preamble is
reduced; otherwise 22-bit preamble is reduced.
10BASE-T Mode Transmit Power Saving Control
TX10M_PWR
1,RW
1 = Enable transmit power saving in 10BASE-T mode
0 = Disable transmit power saving in 10BASE-T mode
Auto-Negotiation Power Saving Control
NWAY_PWR
0,RW
1 = Disable power saving during Auto-Negotiation period
0 = Enable power saving during Auto-Negotiation period
RESERVED
0,RW
Reserved
MDIX_CNTL MDI/MDIX,RO The Polarity of MDI/MDIX Value
1 = MDIX mode
0 = MDI mode
Auto-Negotiation Loop-back
AutoNeg_lpbk
0,RW
1 = Test internal digital Auto-Negotiation Loop-back
0 = Normal
MDIX_CNTL Force Value
Mdix_fix Value
0, RW
When Mdix_down = 1, MDIX_CNTL value depend on the register
value.
MDIX Down
Mdix_do wn
0,RW
Manual force MDI/MDIX.
1 = Disable HP Auto-MDIX, MDIX_CNTL value depend on 14H bit
5
0 = Enable HP Auto-MDIX
MonSel1
0,RW
Vendor Monitor Select
MonSel0
0,RW
Vendor Monitor Select
Reserved
RESERVED
0,RW
Force to 0, in application.
Power Down Control Value
PD_value
0,RW
Decision the value of each field Register 13H
1 = Power down
0 = Normal
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
6.13 DSP Control (DSP_CTRL) – 1BH
Bit
15:0
Bit Name
DSP_CTRL
Default
0,RW
Description
DSP Control
For internal testing only
6.14 Power Saving Control Register (PSCR) – 1DH
Bit
15:13
12
11
Bit Name
RESERVED
LPI
PREAMBLEX
Default
0,RO
0,RO
0,RW
10
AMPLITUDE
0,RW
9
TX_PWR
0,RW
8:0
RESERVED
0,RO
Description
Reserved
Low Power Idle Mode
Preamble Saving Control
When both bit 10and 11 of register 14H are set, the 10BASE-T transmit
preamble count is reduced.
1 = 12-bit preamble is reduced.
0 = 22-bit preamble is reduced.
Transmit Amplitude Control Disabled
1 = When cable is unconnected with link partner, the TX amplitude is
reduced for power saving.
0 = Disable Transmit amplitude reduce function
Transmit Power Saving Control Disabled
1 = When cable is unconnected with link partner, the driving current of
transmit is reduced for power saving.
0 = Disable transmit driving power saving function
Reserved
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
7
Functional Description
7.1 USB Functional Description
7.1.1 USB Functional Description
1. Support Standard Command
BmReqType
00000000B
00000001B
00000010B
10000000B
GET_CONFIGURATION
10000000B
GET_DESCRIPTOR
10000001B
10000000B
10000001B
10000010B
00000000B
GET_INTERFACE
Zero
Descriptor
type/index
Zero
GET_STATUS
Zero
00000000B
00000000B
BRequest
Setup Stage
wValue
CLEAR_FEATURE
Feature
Selector
SET_ADDRESS
Device address
Configuration
SET_CONFIGURATION
value
Descriptor
SET_DESCRIPTOR
type/index
00000000B
00000001B
00000010B
SET_FEATURE
00000001B
SET_INTERFACE
10000010B
SYNCH_FRAME
Feature
Selector
Alternate
setting
Zero
wIndex
Zero
Interface
Endpoint
Zero
wLength
Data Stage
Data
Zero
None
One
Configuration value
Zero/LID
Length
Descriptor
Interface
Zero
Interface
Endpoint
Zero
One
Alternate Interface
Two
Status
Zero
None
Zero
Zero
None
Zero/LID
Length
Descriptor
Zero
Interface
Endpoint
Zero
None
Interface
Zero
None
Endpoint
Two
Frame Number
2. Not Supported Standard Commands
l
Clear_Feature (Interface)
l
Set_Feature (Interface)
l
Set_Descriptor ( )
l
Sync_Frame ( )
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
7.1.2 Vender Commands
There are two types of vendor’s command. We can access internal register maximum 64 bytes, and can
access internal memory.
7.1.2.1 Register Type
READ_REGISTER ( )
Setup Stage
BmReqType
BReq
WValue
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
C0H
00H
00H
00H
RegOffset[7:0]
00H
BC[7:0]
00H
WRITE_REGISTER ( )
Setup Stage
BmReqType
BReq
WIndex
WValue
WLength
WIndex
WLength
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
40H
01H
00H
00H
RegOffset[7:0]
00H
BC[7:0]
00H
WRITE1_REGISTER ( )
Setup Stage
BmReqType
BReq
WValue
WIndex
WLength
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
40H
03H
Data[7:0]
00H
RegOffset[7:0]
00H
0000H
40H
7.1.2.2 Memory Type
These kind of commands are valid when the bit “MEM_MODE “ is set, otherwise device will respond with
request error when receiving these commands.
READ_MEMORY ( )
Setup Stage
BmReqType
BReq
Byte 0
Byte 1
Byte 2
Byte 3
C0H
02H
00H
00H
WRITE_MEMORY ( )
Setup Stage
BmReqType BReq
WValue
Byte 1
Byte 2
Byte 3
C0H
02H
00H
00H
Byte 0
Byte 1
40H
07H
Byte 4
WIndex
Byte 4
Byte 5
MemOff[7:0] MemOff[15:8]
WValue
Byte 2 Byte 3
Data[7:0
00H
]
Byte 5
MemOff[7:0] MemOff[15:8]
WValue
Byte 0
WRITE1_MEMORY ( )
Setup Stage
BmReqType BReq
WIndex
WIndex
Byte 4
Byte 5
MemOff[7:0] MemOff[15:8]
WLength
Byte 6
Byte 7
BC[7:0]
00H
WLength
Byte 6
Byte 7
BC[7:0]
00H
WLength
Byte 6
Byte 7
0000H
40H
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
7.1.3 Interface 0 Configuration
Definition: len-byte is 64-byte in full speed mode and 256-byte in high speed mode.
7.1.3.1 Endpoint 1
Type: Bulk In
Packet Padload: len-byte
When host accessing EP1.
If IN-FIFO is full, device will send len-byte data.
If IN-FIFO isn’t full and Ethernet packet isn’t end, device will send a NAK.
If IN-FIFO isn’t full and Ethernet packet is end, device will send the surplus data in IN-FIFO.
Data Format
For 3-byte header mode (when Register 91H bit 7 is “0”)
Fist byte
Ethernet Receive Packet Status, the bit format is same as register 6 (RSR)
Second byte
Ethernet Receive Packet byte count low
Third byte
Ethernet Receive Packet byte count high
The others
Ethernet Receive Packet Data
For 4-byte header mode (when Register 91H bit 7 is “1” or pin GPIO2_2 is pull-high)
Fist byte
Ethernet Receive Packet Checksum Status, the bit[7:2] format is same as
register 32H (RCSCSR)
Second byte
Ethernet Receive Packet Status, the bit format is same as register 6 (RSR)
Third byte
Ethernet Receive Packet byte count low
Fourth byte
Ethernet Receive Packet byte count high
The others
Ethernet Receive Packet Data
7.1.3.2 Endpoint 2
Type: Bulk Out
Packet Padload: len-byte
When host accessing EP2.
If OUT-FIFO isn’t full, host sends data, device response ACK.
If OUT-FIFO is full, host sends data, device response NAK.
If host sends data less len-byte or zero byte, it means Ethernet packet end.
Data Format
Fist byte
Second byte
The others
Ethernet Transmit Packet byte count low
Ethernet Transmit Packet byte count high
Ethernet Transmit Packet data
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
7.1.3.3 Endpoint 3
Type: Interrupt In
Packet Load: 8-byte
When host accessing EP3.
If no interrupt condition, device response NAK.
If interrupt condition, device will send content back to host.
Data Format
Offset
Name
Byte 0
NSR
Byte 1
TSR1
Byte 2
TSR2
Byte 3
RSR
Byte 4
ROCR
Byte 5
RXC
Byte 6
TXC
Byte 7
GPR
Description
Network status register
Reserved
Reserved
RX status register
Received overflow counter register
Received packet counter
Transmit packet counter
Reserved
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
7.1.4 Descriptor Values
All descriptors are stored in its default values. Values which are “?” in the table below are under define.
Device Descriptor/18-Byte
Offset
Field
Size
Value
Description
0
bLength
1
12H
Size of descriptor in bytes
1
bDescriptorType
1
01H
DEVICE Descriptor Type
2
bcdUSB
2
0200H USB BCD version
4
bDeviceClass
1
00H
Class code, assign by USB
Zero: No device level class
01H~FEH : Valid device class
FFH : Vender-specific
5
bDeviceSubClass
1
00H
SubClass code, assign by USB
6
bDeviceProtocol
1
00H
Protocol code, assign by USB
7
bMaxPacketSize0
1
08H
Maximum PL for EP0(8,16,32,64)
8
idVender
2
0A46H Vendor ID(0A46) (fm EEP)
10
idProduce
2
9621H Product ID
9621H, RX header is 4-byte mode
12
bcdDevice
2
0101H Device release number
14
iManufacturer
1
01H
Index of string descriptor for manufacturer
15
iProduct
1
02H
Index of string descriptor for product
16
iSerialNumber
1
03H
Index of string descriptors for serial number
17
bNumConfigurations
1
01H
Number of configurations
Configuration0 Descriptor/9-Byte
Offset
Field
0
bLength
1
bDescriptorType
2
wTotalLength
4
bNumInterfaces
5
bConfigurationValue
6
iConfiguration
7
bmAttributes
8
MaxPower
Interface0 Descriptor/9-Byte
Offset
Field
0
bLength
1
bDescriptorType
2
bInterfaceNumber
3
bAlternateSetting
4
bNumEndpoints
5
bInterfaceClass
6
bInterfaceSubClass
7
bInterfaceProtocol
8
iInterface
Size
1
1
2
1
1
1
1
Value
09H
02H
0027H
01H
01H
00H
A(8)0H
1
3CH
Size
1
1
1
1
1
1
1
1
1
Value
09H
04H
00H
00H
03H
00H
00H
00H
00H
Description
Size of descriptors
CONFIGURATION Descriptor Type
Total descriptor length
Number of interfaces
Value of this configuration
Index of string descriptor for configuration
Configuration characteristics
D7:Reserved (set to 1)
D6: Self-powered
D5: Remote WakeUp
1 = if REG00H bit 6 is “1”
0 = if REG00H bit 6 is “0”
D4: Reserved ( reset to 0)
Maximum power, 2mA units (fm EEP)
Description
Size of this descriptor
INTERFACE Descriptor Type
Number of interface
Value used to select alternate setting
Number of ednpoints
Class code
SunClass code
Protocol code
Index of string for this interface
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
Endpoint1 Descriptor/6-Byte
Offset
Field
0
bLength
1
bDescriptorType
2
bEndpointAddress
Size
1
1
1
Value
07H
05H
81H
3
bmAttributes
1
02H
4
wMaxPacketSize
2
0040H
6
bInterval
1
00H
Size
1
1
1
Value
07H
05H
02H
02H
Endpoint 2 Descriptor/6-Byte
Offset
Field
0
bLength
1
bDescriptorType
2
bEndpointAddress
3
bmAttributes
1
4
wMaxPacketSize
2
6
bInterval
1
0040H
00H
Description
Size of this descriptor
ENDPOINT Descriptor Type
Address of the endpoint
Bit3~0: The endpoint number
Bit 6~4: Reserved(0)
Bit7 : Direction(Control EP exclude)
1 = IN endpoint
0 = OUT endpoint
EP's attributes
Bit1~0: Transfer Type
00 = Control
01 = Isochronous
10 = Bulk
11 = Interrupt
Maximum packet size of this EP
(0200H for high speed)
Interval for polling (periodical pipe) (fm EEP)
Interrupt Tpye = 1 ~ 255 (ms)
Isochronoous Type = 1 (ms)
Description
Size of this descriptor
ENDPOINT Descriptor Type
Address of the endpoint
Bit3~0: The endpoint number
Bit 6~4: Reserved(0)
Bit7: Direction(Control EP exclude)
1 = IN endpoint
0 = OUT endpoint
EP's attributes
Bit1~0: Transfer Type
00 = Control
01 = Isochronous
10 = Bulk
11 = Interrupt
Maximum packet size of this EP
(0200H for high speed)
Interval for polling (periodical pipe) (fm EEP)
Interrupt Tpye = 1 ~ 255 (ms)
Isochronoous Type = 1 (ms)
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
Endpoint3 Descriptor/6-Byte
Offset
Field
0
bLength
1
bDescriptorType
2
bEndpointAddress
Size
1
1
1
Value
07H
05H
83H
3
bmAttributes
1
03H
4
6
wMaxPacketSize
bInterval
2
1
0008H
01H
Size
1
1
2
Value
04H
03H
0409H
String0 Descriptor/Code array
Offset
Field
0
bLength
1
bDescriptorType
2
wLANGID[1]
Description
Size of this descriptor
ENDPOINT Descriptor Type
Address of the endpoint
Bit3~0: The endpoint number
Bit 6~4: Reserved(0)
Bit7: Direction(Control EP exclude)
1 = IN endpoint
0 = OUT endpoint
EP's attributes
Bit1~0: Transfer Type
00 = Control
01 = Isochronous
10 = Bulk
11 = Interrupt
Maximum packet size of this EP
Interval for polling (periodical pipe)
Interrupt Tpye = 1 ~ 255 (ms)
Isochronoous Type = 1 (ms)
Description
Size of this descriptor
STRING Descriptor Type
LANGID code(Eng.)
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
7.1.5 Descriptors of String/1/2/3 Are Loaded From EEPROM
String1 Descriptor/UNICODE String
Offset
Field
Size
0
bLength
1
1
bDescriptorType
1
2~
bString
n
Value
03H
String2 Descriptor/UNICODE String
Offset
Field
0
bLength
1
bDescriptorType
2~
bString
Size
1
1
n
Value
String3 Descriptor/UNICODE String
Offset
Field
0
bLength
1
bDescriptorType
2~
bString
Size
1
1
n
Value
03H
03H
Description
Descriptor length loading from EEPROM
STRING Descriptor Type
Manufacture
Description
Descriptor length loading from EEPROM
STRING Descriptor Type
Product
Description
Descriptor length loading from EEPROM
STRING Descriptor Type
Serial Number
7.1.6 Descriptors of String/1/2/3 If No EEPROM Exist
String1 Descriptor/UNICODE String
Offset
Field
0
bLength
1
bDescriptorType
2~
bString
Size
1
1
2
Value
04H
03H
0020H
Description
Descriptor length
STRING Descriptor Type
Manufacture
String2 Descriptor/UNICODE String
Offset
Field
0
bLength
1
bDescriptorType
2~
bString
Size
1
1
14
Value
10H
03H
Description
Descriptor length
STRING Descriptor Type
55 00 53 00 42 00 20 00 45 00 74 00 68 00
String3 Descriptor/UNICODE String
Offset
Field
0
bLength
1
bDescriptorType
2~
bString
Size
1
1
2
Value
04H
03H
0031H
Description
Descriptor length
STRING Descriptor Type
Serial Number
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
7.2 Ethernet Functional Description
7.2.1 Serial Management Interface
DM9621A
MII SMI
MDC
MDIO
MDC
MDIO
PHY
External PHY can be accessed via the MDC, MDIO
SMI - Read Frame Structure
SMI_C
SMI_D read
32 "1"s
Idle
0
Preamble
1
SFD
1
0
A1
A0
R7
Device Address
Op Code
R6
R5
0
Z
Register Address
//
//
R0
D15
D14
Turn Around
D1
D0
Idle
Data
Read
Write
SMI_R_8203
SMI - Write Frame Structure
SMI_C
SMI_D write
32 "1"s
Idle
Preamble
0
1
SFD
0
1
Op Code
A1
A0
Device Address
R7
R6
R5
R0
Register Address
Write
1
0
Turn Around
D15
D14
Data
D1
D0
Idle
SMI_W_8203
Final
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DM9621A
USB2.0 to Fast Ethernet Controller
7.2.2 100Base-TX Operation
The block diagram in figure 3 provides an overview of the functional blocks contained in the transmit section.
The transmitter section contains the following functional blocks:
- 4B5B Encoder
- Scrambler
- Parallel to Serial Converter
- NRZ to NRZI Converter
- NRZI to MLT-3
- MLT-3 Driver
7.2.3 4B5B Encoder
The 4B5B encoder converts 4-bit (4B) nibble data generated by the MAC Reconciliation Layer into a 5-bit (5B)
code group for transmission, reference Table 1. This conversion is required for control and packet data to be
combined in code groups. The 4B5B encoder substitutes the first 8 bits of the MAC preamble with a J/K
code-group pair (11000 10001) upon transmit. The 4B5B encoder continues to replace subsequent 4B
preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the
deassertion of the Transmit Enable signal from the MAC Reconciliation layer, the 4B5B encoder injects the
T/R code-group pair (01101 00111) indicating end of frame. After the T/R code-group pair, the 4B5B encoder
continuously injects IDLEs into the transmit data stream until Transmit Enable is asserted and the next
transmit packet is detected.
The DM9621A includes a Bypass 4B5B conversion option within the 100Base-TX Transmitter for support of
applications like 100 Mbps repeaters which do not require 4B5B conversion.
7.2.4 Scrambler
The scrambler is required to control the radiated emissions (EMI) by spreading the transmit energy across the
frequency spectrum at the media connector and on the twisted pair cable in 100Base-TX operation.
By scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency
range. Without the scrambler, energy levels on the cable could peak beyond FCC limitations at frequencies
related to repeated 5B sequences like continuous transmission of IDLE symbols. The scrambler output is
combined with the NRZ 5B data from the code-group encoder via an XOR logic function. The result is a
scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies.
7.2.5 Parallel to Serial Converter
The Parallel to Serial Converter receives parallel 5B scrambled data from the scrambler and serializes it
(converts it from a parallel to a serial data stream). The serialized data stream is then presented to the NRZ to
NRZI Encoder block.
7.2.6 NRZ to NRZI Encoder
After the transmit data stream has been scrambled and serialized, the data must be NRZI encoded for
compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted
pair cable.
7.2.7 MLT-3 Converter
The MLT-3 conversion is accomplished by converting the data stream output from the NRZI encoder into two
binary data streams with alternately phased logic one events.
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DM9621A
USB2.0 to Fast Ethernet Controller
7.2.8 MLT-3 Driver
The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver which
converts these streams to current sources and alternately drives either side of the transmit transformer
primary winding resulting in a minimal current MLT-3 signal. Refer to figure 4 for the block diagram of the
MLT-3 converter.
7.2.9 4B5B Code Group
Symbol
Meaning
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
4B code
3210
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
5B Code
43210
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
I
J
K
T
R
H
Idle
SFD (1)
SFD (2)
ESD (1)
ESD (2)
Error
undefined
0101
0101
undefined
undefined
undefined
11111
11000
10001
01101
00111
00100
V
V
V
V
V
V
V
V
V
V
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
undefined
undefined
undefined
undefined
Undefined
undefined
undefined
undefined
undefined
undefined
Table 1
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
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DM9621A
USB2.0 to Fast Ethernet Controller
7.2.10 100Base-TX Receiver
The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to
synchronous 4-bit nibble data that is then provided to the MII.
The receive section contains the following functional blocks:
- Signal Detect
- Digital Adaptive Equalization
- MLT-3 to Binary Decoder
- Clock Recovery Module
- NRZI to NRZ Decoder
- Serial to Parallel
- Descrambler
- Code Group Alignment
- 4B5B Decoder
7.2.11 Signal Detect
The signal detect function meets the specifications mandated by the ANSI XT12 TP-PMD 100Base-TX
Standards for both voltage thresholds and timing parameters.
7.2.12 Adaptive Equalization
When transmitting data at high speeds over copper twisted pair cable, attenuation based on frequency
becomes a concern. In high speed twisted pair signaling, the frequency content of the transmitted signal can
vary greatly during normal operation based on the randomness of the scrambled data stream. This variation
in signal attenuation caused by frequency variations must be compensated for to ensure the integrity of the
received data. In order to ensure quality transmission when employing MLT-3 encoding, the compensation
must be able to adapt to various cable lengths and cable types depending on the installed environment. The
selection of long cable lengths for a given implementation, requires significant compensation which will be
over-kill in a situation that includes shorter, less attenuating cable lengths. Conversely, the selection of short
or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer
length cables. Therefore, the compensation or equalization must be adaptive to ensure proper conditioning of
the received signal independent of the cable length.
7.2.13 MLT-3 to NRZI Decoder
The DM9621A decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data. The
relationship between NRZI and MLT-3 data is shown in figure 4.
7.2.14 Clock Recovery Module
The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery
Module locks onto the data stream and extracts the 125Mhz reference clock. The extracted and synchronized
clock and data are presented to the NRZI to NRZ Decoder.
7.2.15 NRZI to NRZ
The transmit data stream is required to be NRZI encoded in for compatibility with the TP-PMD standard for
100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must be
reversed on the receive end. The NRZI to NRZ decoder, receives the NRZI data stream from the Clock
Recovery Module and converts it to a NRZ data stream to be presented to the Serial to Parallel conversion
block.
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DM9621A
USB2.0 to Fast Ethernet Controller
7.2.16 Serial to Parallel
The Serial to Parallel Converter receives a serial data stream from the NRZI to NRZ converter, and converts
the data stream to parallel data to be presented to the descrambler.
7.2.17 Descrambler
Because of the scrambling process required to control the radiated emissions of transmit data streams, the
receiver must descramble the receive data streams. The descrambler receives scrambled parallel data
streams from the Serial to Parallel converter, descrambles the data streams, and presents the data streams to
the Code Group alignment block.
7.2.18 Code Group Alignment
The Code Group Alignment block receives un-aligned 5B data from the descrambler and converts it into 5B
code group data. Code Group Alignment occurs after the J/K is detected, and subsequent data is aligned on a
fixed boundary.
7.2.19 4B5B Decoder
The 4B5B Decoder functions as a look-up table that translates incoming 5B code groups into 4B (Nibble) data.
When receiving a frame, the first 2 5-bit code groups received are the start-of-frame delimiter (J/K symbols).
The J/K symbol pair is stripped and two nibbles of preamble pattern are substituted. The last two code groups
are the end-of-frame delimiter (T/R symbols).
The T/R symbol pair is also stripped from the nibble presented to the Reconciliation layer.
7.2.20 10Base-T Operation
The 10Base-T transceiver is IEEE 802.3u compliant. When the DM9621A is operating in 10Base-T mode, the
coding scheme is Manchester. Data processed for transmit is presented to the MII interface in nibble format,
converted to a serial bit stream, then Manchester encoded. When receiving, the Manchester encoded bit
stream is decoded and converted into nibble format for presentation to the MII interface.
7.2.21 Collision Detection
For Half-Duplex operation, a collision is detected when the transmit and receive channels are active
simultaneously. When a collision has been detected, it will be reported by the COL signal on the MII interface.
Collision detection is disabled in Full-Duplex operation.
7.2.22 Carrier Sense
Carrier Sense (CRS) is asserted in Half-Duplex operation during transmission or reception of data. During
Full-Duplex mode, CRS is asserted only during receive operations.
7.2.23 Auto-Negotiation
The objective of Auto-Negotiation is to provide a means to exchange information between segment linked
devices and to automatically configure both devices to take maximum advantage of their abilities. It is
important to note that Auto-Negotiation does not test the link segment characteristics. The Auto-Negotiation
function provides a means for a device to advertise supported modes of operation to a remote link partner,
acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes
of operation. This allows devices on both ends of a segment to establish a link at the best common mode of
operation. If more than one common mode exists between the two devices, a mechanism is provided to allow
the devices to resolve to a single mode of operation using a predetermined priority resolution function.
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7.2.24 Auto-Negotiation (continued)
Auto-Negotiation also provides a parallel detection function for devices that do not support the
Auto-Negotiation feature. During Parallel detection there is no exchange of configuration information, instead,
the receive signal is examined. If it is discovered that the signal matches a technology that the receiving
device supports, a connection will be automatically established using that technology. This allows devices
that do not support Auto-Negotiation but support a common mode of operation to establish a link.
7.2.25 Energy-Efficient Ethernet (EEE)
DM9621A support IEEE 802.3az Energy-Efficient Ethernet (EEE) for 100Base-TX transmission. When
DM9621A detects low link utilization, it requests the transmitter to enter the Low Power Idle (LPI) mode and
send appropriate symbols over the link. Upon receiving and decoding those symbols, the receiver can enter
the LPI mode. The transmitter and receiver can enter and exit low power states independently. Energy is
conserved by deactivating the corresponding functional blocks.
Auto-Negotiation function is used to determine whether both link partners support EEE. If both link partners
support EEE capability of 100Base-TX, DM9621A enables the EEE function to save power when no packets
are being transmitted. PHY register 1D bit 12 is high to indicate the status.
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8
DC and AC Electrical Characteristics
8.1 Absolute Maximum Ratings
Symbol
DVDD
VIN
VOUT
TSTG
TA
LT
Parameter
Supply Voltage
DC Input Voltage (VIN)
DC Output Voltage(VOUT)
Storage Temperature range
Ambient Temperature
Lead Temperature
(LT, soldering, 10 sec.).
Min.
-0.3
-0.5
-0.3
-65
0
-
Max.
3.6
5.5
3.6
+150
+70
+260
Unit
V
V
V
°C
°C
°C
Conditions
*1
*2
*2
-
*1: Power pin
*2: IO pin
8.1.1 Operating Conditions
Symbol
Parameter
DVDD
Supply Voltage
PD
100BASE-TX
(Power
100BASE-TX AZ Enable W/O Traffic
Dissipation) 100BASE-TX AZ Enable With Traffic
*1
10BASE-T
10BASE-T idle
USB suspend mode
*1: demo board testing result
Min.
3.135
-------------
Typ.
3.300
163
118
160
163
135
2.48
Max.
3.465
-------------
Unit
V
mA
mA
mA
mA
mA
mA
Conditions
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
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8.2 DC Electrical Characteristics (VDD = 3.3V)
Symbol
Inputs
VIL
VIH
IIL
IIH
Outputs
VOL
VOH
Receiver
VICM
Parameter
Min.
Typ.
Max.
Unit
Conditions
Input Low Voltage
Input High Voltage
Input Low Leakage Current
Input High Leakage Current
2.0
-1
-
-
0.8
1
V
V
uA
uA
VIN = 0.0V
VIN = 3.3V
Output Low Voltage
Output High Voltage
2.4
-
0.4
-
V
V
IOL = 4mA
IOH = -4mA
-
1.8
-
V
100 W Termination
Across
1.9
2.0
2.1
V
Peak to Peak
4.4
│19│
5
│20│
5.6
│21│
V
mA
Peak to Peak
Absolute Value
│44│
│50│
│56│
mA
Absolute Value
RX+/RX- Common Mode Input
Voltage
Transmitter
VTD100 100TX+/- Differential Output
Voltage
VTD10
10TX+/- Differential Output Voltage
ITD100 100TX+/- Differential Output
Current
ITD10
10TX+/- Differential Output Current
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8.3 AC Electrical Characteristics & Timing Waveforms
8.3.1 TP Interface
Symbol
Parameter
tTR/F
100TX+/- Differential Rise/Fall Time
tTM
100TX+/- Differential Rise/Fall Time
Mismatch
tTDC
100TX+/- Differential Output Duty Cycle
Distortion
Tt/T
100TX+/- Differential Output Peak-to-Peak
Jitter
XOST
100TX+/- Differential Voltage Overshoot
8.3.2 Oscillator/Crystal Timing (25°C)
Symbol
Parameter
TCKC
OSC Clock Cycle
TPWH
OSC Pulse Width High
TPWL
OSC Pulse Width Low
Min.
3.0
0
Typ.
-
Max.
5.0
0.5
Unit
ns
ns
0
-
0.5
ns
0
-
1.4
ns
0
-
5
%
Min.
39.9988
-
Typ
40
20
20
Max.
40.0012
-
Unit
ns
ns
ns
Conditions
Conditions
30ppm
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9
AC Timing Waveform
9.1 Power On Reset Timing
T1
Power on
T2
RSTB
T3
T6
Strap pins
T4
EECS
T5
Symbol
T1
T2
T3
T4
T5
T6
Parameter
Power on reset time
RSTB Low Period
Strap pin setup time with RSTB
Strap pin hold time with RSTB
RSTB high to EECS high
RSTB high to EECS burst end
Min.
15
5
40
40
-
Typ.
1
--
Max.
1.85
Unit
ms
ms
ns
ns
us
ms
Conditions
-
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9.2 EEPROM Timing
T1
EECS
T2
EECK
T4
EEDIO
T5
T3
Symbol
T1
T2
T3
T4
T5
Parameter
Min.
EECS Hold Time
EECK cycle time
EEDIO Hold Time in output state
EEDIO Setup Time in input state
EEDIO Hold Time in input state
Typ.
4.2
5.12
4.2
Max.
Unit
us
us
us
ns
ns
Max.
Unit
MHz
ns
ns
ns
8
1
9.3 MII Management Timing
T1
MDC
MDIO (Output)
T3
T2
MDIO (Input)
T4
Symbol
T1
T2
T3
T4
Parameter
MDC Frequency
MDIO Output Delay Time
MDIO by External MII Setup Time
MDIO by External MII Hold Time
Min.
368
1
Typ.
1.04
600
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9.4 RMII TX Timing
CLK50M
TXE
T1
TXD_1~0
Symbol
Parameter
T1
TXE,TXD_1~0 Delay Time
Min.
Typ.
6
Max.
Unit
ns
Max.
Unit
ns
ns
9.5 RMII TX Timing
CLK50M
RXDV
T1
T2
RXD_1~0
Symbol
Parameter
T1
RXDV,RXD_1~0 Setup Time
T2
RXDV,RXD_1~0 Hold Time
Min.
2
3
Typ.
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10 Magnetic and Crystal Selection Guide
10.1 Magnetic Selection Guide
Refer to Table 1 for transformer requirements. Transformers, meeting these requirements, are available from
a variety of magnetic manufacturers. Designers should test and qualify all magnetic before using them in an
application. The transformers listed in Table 1 are electrical equivalents, but may not be pin-to-pin equivalents.
Designers should test and qualify all magnetic specifications before using them in an application. RoHS
regulations, please contact with your magnetic vendor, this table only for you reference
Manufacturer
DELTA
MAGCOM
Halo
Bel Fuse
Part Number
LFE8505-DC, LFE8563-DC, LFE8583-DC
HS9016, HS9024
TG110-S050N2, TG110-LC50N2
S558-5999-W2
Table 1
10.2 Crystal Selection Guide
A crystal can be used to generate the 25MHz reference clock instead of an oscillator. The crystal must be a
fundamental type, and series-resonant. Connects to pins X1 and X2, and shunts each crystal lead to ground
with a 15pf capacitor (see figure 10-1).
PARAMETER
SPEC
Type
Frequency
Equivalent Series Resistance
Load Capacitance
Case Capacitance
Power Dissipation
Fundamental, series-resonant
25.000 MHz +/- 30ppm
25 ohms max
22 pF typ.
7 pF max.
1mW max.
X1
X2
46
47
25MHz
15pf
GND
15pf
GND
Figure 10-1
Crystal Circuit Diagram
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11 Application Circuit
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12 Package Information
QFN 48L Outline Dimension
unit: inch/mm
Symbol
A
A1
A2
A3
b
D/E
D1/E1
D2/E2
e
L
θ
R
K
aaa
bbb
ccc
ddd
eee
fff
Dimension in
MIN
NOM
0.80
0.85
0.00
0.02
0.60
0.65
0.02 REF
0.18
0.25
6.90
7.00
6.75 BSC
4.90
5.05
0.50 BSC
0.30
0.40
0o
--0.09
--0.20
--0.15
0.10
0.10
0.05
0.08
0.10
mm
MAX
0.90
0.05
0.70
0.30
7.10
5.20
0.50
14o
-----
Dimension in inch
MIN
NOM
MAX
0.031 0.033 0.035
0.000 0.001 0.002
0.024 0.026 0.028
0.008 REF
0.007 0.010 0.012
0.272 0.276 0.280
0.266 BSC
0.193 0.199 0.205
0.020 BSC
0.012 0.016 0.020
o
0
--14o
0.004
----0.008
----0.006
0.004
0.004
0.002
0.003
0.004
NOTE:
1. CONTROLLING DIMENSION: MILLIMETER
2. REFERENCE DOCUMENT: JEDEC MO-220
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13 Ordering Information
Part Number
DM9621ANP
Pin Count
48
Package
QFN (Pb-Free)
Disclaimer
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WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near
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Final
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