DM9051(I) - Davicom Semiconductor Inc.

DM9051(I)
SPI to Ethernet Controller
DAVICOM Semiconductor, Inc.
DM9051(I)
SPI to Ethernet Controller
DATA SHEET
Version: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
1
DM9051(I)
SPI to Ethernet Controller
Content
1
2
3
4
5
6
General Description........................................................................................................................... 5
Features ............................................................................................................................................. 6
Block Diagram ................................................................................................................................... 7
Pin Configuration .............................................................................................................................. 8
4.1 32-Pin QFN ................................................................................................................................... 8
Pin Description .................................................................................................................................. 9
5.1 SPI Processor Interface ................................................................................................................. 9
5.2 EEPROM Interface ........................................................................................................................ 9
5.3 Clock Interface............................................................................................................................... 9
5.4 LED Interface................................................................................................................................10
5.5 10/100 PHY/Fiber .........................................................................................................................10
5.6 Miscellaneous ............................................................................................................................... 11
5.8 Strap Pins..................................................................................................................................... 11
MAC Control and Status Register Set .............................................................................................12
6.1 Network Control Register (00H) ....................................................................................................14
6.2 Network Status Register (01H)......................................................................................................14
6.3 TX Control Register (02H).............................................................................................................15
6.4 TX Status Register I (03H) for Packet Index I ................................................................................16
6.5 TX Status Register II (04H) for packet index II ...............................................................................17
6.6 RX Control Register (05H) ............................................................................................................18
6.7 RX Status Register (06H)..............................................................................................................19
6.8 Receive Overflow Counter Register (07H).....................................................................................20
6.9 Back Pressure Threshold Register (08H) ......................................................................................20
6.10 Flow Control Threshold Register (09H) .......................................................................................21
6.11 RX/TX Flow Control Register (0AH) ............................................................................................21
6.12 EEPROM & PHY Control Register (0BH) ....................................................................................22
6.13 EEPROM & PHY Address Register (0CH) ...................................................................................22
6.14 EEPROM & PHY Data Register (EE_PHY_L:0DH EE_PHY_H:0EH) ......................................22
6.15 Wake Up Control Register (0FH) .................................................................................................23
6.16 Physical Address Register (10H~15H) ........................................................................................23
6.17 Multicast Address Hash Table Register (16H~1DH) .....................................................................23
6.18 General Purpose Control Register (1EH) ....................................................................................24
6.19 General Purpose Register (1FH) .................................................................................................24
6.20 TX Memory Read Pointer Address Register (22H~23H) ..............................................................24
6.21 RX Memory Write Pointer Address Register (24H~25H) ..............................................................25
6.22 Vendor ID Register (28H~29H) ...................................................................................................25
6.23 Product ID Register (2AH~2BH)..................................................................................................25
6.24 CHIP Revision (2CH) ..................................................................................................................25
6.25 Transmit Control Register 2 (2DH) ..............................................................................................25
6.26 Auto-Transmit Control Register (30H) .........................................................................................26
6.27 Transmit Check Sum Control Register (31H) ...............................................................................26
6.28 Receive Check Sum Status Register (32H) .................................................................................26
6.29 SPI Bus Control Register (38H)...................................................................................................27
6.30 INT Pin Control Register (39H)....................................................................................................27
6.31 Pause Packet Control/Status Register (3DH) ..............................................................................27
6.32 IEEE 802.3az Enter Counter Register (3EH) ...............................................................................27
6.33 IEEE 802.3az Leave Counter Register (3FH) ..............................................................................27
6.34 SPI Byte Align Error Counter Register (4AH) ...............................................................................28
6.35 RX Packet Length Control Register (52H) ...................................................................................28
6.36 RX Broadcast Control Register (53H)..........................................................................................28
6.37 INT Pin Clock Output Control Register (54H)...............................................................................28
6.38 Memory Pointer Control Register (55H).......................................................................................28
6.39 More LED Control Register (57H) ...............................................................................................29
6.40 Memory Control Register (59H)...................................................................................................29
6.41 Transmit Memory Size Register (5AH) ........................................................................................29
6.42 Memory BIST Status Register (5DH) ...........................................................................................30
6.43 Memory Data Pre-Fetch Read Command without Address Increment Register (70H) ..................30
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DM9051(I)
SPI to Ethernet Controller
7
8
9
6.44 Memory Read Command without Data Pre-Fetch and Address Increment Register (71H) ...........30
6.45 Memory Data Read Command with Address Increment Register (72H) .......................................31
6.46 SPI Data Read Delay Counter Register (73H) .............................................................................31
6.47 Memory Data Read Address Register (74H~75H) .......................................................................31
6.48 Memory Data Write Command without Address Increment Register (76H)...................................31
6.49 Memory Data Write Command with Address Increment Register (78H) .......................................31
6.50 Memory Data Write Address Register (7AH~7BH) .......................................................................31
6.51 TX Packet Length Register (7CH~7DH) ......................................................................................31
6.52 Interrupt Status Register (7EH) ...................................................................................................32
6.53 Interrupt Mask Register (7FH) .....................................................................................................32
EEPROM and SPI Command Format ...............................................................................................33
7.1 EEPROM Format ..........................................................................................................................33
7.2 SPI Command Format ..................................................................................................................34
PHY Register Description ................................................................................................................36
8.1 Basic Mode Control Register (BMCR) – 00H .................................................................................37
8.2 Basic Mode Status Register (BMSR) – 01H ..................................................................................38
8.3 PHY ID Identifier Register #1 (PHYID1) – 02H ..............................................................................39
8.4 PHY ID Identifier Register #2 (PHYID2) – 03H ..............................................................................39
8.5 Auto-Negotiation Advertisement Register (ANAR) – 04H ...............................................................40
8.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) – 05H ....................................................41
8.7 Auto-Negotiation Expansion Register (ANER) – 06H .....................................................................42
8.8 DAVICOM Specified Configuration Register (DSCR) – 10H ...........................................................42
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H .......................................43
8.10 10BASE-T Configuration/Status (10BTCSR) – 12H .....................................................................44
8.11 Power Down Control Register (PWDOR) – 13H................................................................................45
8.12 Specified Config Register – 14H .................................................................................................45
8.13 Power Saving Control Register (PSCR) – 1DH............................................................................46
Functional Description .....................................................................................................................47
9.1 SPI Processor Interface ................................................................................................................47
9.2 Direct Memory Access Control ......................................................................................................47
9.3 Packet Transmission .....................................................................................................................47
9.4 Packet Reception..........................................................................................................................47
9.5 100Base –TX Operation................................................................................................................48
9.5.1 4B5B Encoder ...................................................................................................................48
9.5.2 Scrambler..........................................................................................................................48
9.5.3 Parallel to Serial Converter ................................................................................................48
9.5.4 NRZ to NRZI Encoder........................................................................................................48
9.5.5 MLT-3 Converter................................................................................................................48
9.5.6 MLT-3 Driver......................................................................................................................48
9.5.7 4B5B Code Group .............................................................................................................49
9.6 100Base-TX Receiver ...................................................................................................................50
9.6.1 Signal Detect .....................................................................................................................50
9.6.2 Adaptive Equalization ........................................................................................................50
9.6.3 MLT-3 to NRZI Decoder .....................................................................................................50
9.6.4 Clock Recovery Module .....................................................................................................50
9.6.5 NRZI to NRZ .....................................................................................................................50
9.6.6 Serial to Parallel ................................................................................................................51
9.6.7 Descrambler ......................................................................................................................51
9.6.8 Code Group Alignment ......................................................................................................51
9.6.9 4B5B Decoder ...................................................................................................................51
9.7 10Base-T Operation......................................................................................................................51
9.8 Collision Detection ........................................................................................................................51
9.9 Carrier Sense ...............................................................................................................................51
9.10 Auto-Negotiation .........................................................................................................................52
9.11 Power Reduced Mode ................................................................................................................52
9.11.1 Power Down Mode...........................................................................................................52
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DM9051(I)
SPI to Ethernet Controller
10 DC Characteristics ............................................................................................................................53
10.1 Absolute Maximum Ratings (25°C) (DM9051I support -40°C~+85°C) ..........................................53
10.1.1 Operating Conditions .......................................................................................................53
10.2 DC Electrical Characteristics (VDD = 3.3V) .................................................................................53
11 AC Electrical Characteristics & Timing Waveforms.........................................................................54
11.1 SPI Timing ..................................................................................................................................54
11.2 TP Interface ................................................................................................................................55
11.3 Oscillator/Crystal Timing .............................................................................................................55
11.4 Power On Reset Timing ..............................................................................................................55
11.5 EEPROM Interface Timing ..........................................................................................................56
11.6 LED (traffic ON/OFF timing) any LED as Traffic ...........................................................................56
12 Package Information ........................................................................................................................57
13 Ordering Information ........................................................................................................................58
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DM9051(I)
SPI to Ethernet Controller
1 General Description
The DM9051(I) is a fully integrated and cost-effective low pin count single chip Fast Ethernet controller with a
Serial Peripheral Interface (SPI), a 10/100M PHY and MAC, and 16K-byte SRAM. It is designed with low
power and high performance process interface that support 3.3V with 5V IO tolerance.
The PHY of the DM9051(I) can interface to the UTP3, 4, 5 in 10Base-T and UTP5 in 100Base-TX with HP
Auto-MDIX.It is fully compliant with the IEEE 802.3u Spec. Its Auto-Negotiation function will automatically
configure the DM9051(I) to take the maximum advantage of its 10M or 100M abilities.
The DM9051(I) supports IEEE 802.3az in PHY and MAC to save power consumption when Ethernet is idle.
The IEEE 802.3x Full-Duplex flow control and Half-Duplex back-pressure function also supported to avoid
Ethernet packet loss with link partner.
The slave SPI interface is designed to support SPI clock mode 0 and 3 that compatible with the all master SPI
interface of CPU. The clock speed can up to 50Mhz to co-operation with most high throughput master SPI.
The SPI burst command format is code-effective to minimize the command overhead in access DM9051(I)
internal registers and packet data in memory.
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DM9051(I)
SPI to Ethernet Controller
2 Features
l
Slave SPI Interface with clock speeds up to 50MHz for high throughput applications
l
Support SPI clock mode 0 and 3
l
Support 10BASE-T and 100BASE-TX and 100M Fiber interface
l
Support HP Auto-MDIX crossover function in 10BASE-T and 100BASE-TX
l
Support IEEE 802.3az Energy Efficient Ethernet (EEE)
l
Support interface for EEPROM to configure chip settings
l
Support back pressure flow control for Half-Duplex mode
l
Support IEEE802.3x flow control for Full-Duplex mode
l
Supports wakeup frame, link status change and magic packet events to generate
remote wake on LAN (WOL) signal
l
Support IPv4/ TCP / UDP checksum generation and checking
l
Configurable of internal transmit/receive buffers within 16K-byte memory
l
Built-in integrated 3.3V to 1.8V low noise regulator for core and analog blocks
l
Support EMI (Class B) and HBM ESD Rating 8KV
l
Support Industrial Temperature Range: –40℃ to +85℃ (DM9051I)
l
3.3V I/O with 5V tolerant
l
DSP architecture PHY Transceiver
l
0.18um process
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DM9051(I)
SPI to Ethernet Controller
3 Block Diagram
EEPROM
Interface
LED
100 Base-TX
Transceiver
TX Machine
100 Base-TX
PCS
MII
TX+/AUTO-MDIX
10 Base-T
TX/RX
Control &
Status
Register
Memory
Management
RX Machine
Processor Interface
MAC
PHY ceiver
RX+/Internal
SRAM
Autonegotiation
Doc No: DM9051(I)-12-MCO-DS-P01
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MII Management
Control & MII Register
7
DM9051(I)
SPI to Ethernet Controller
4 Pin Configuration
SPI_MOSI
SPI_CK
SPI_CSN
19
18
17
EECK
30
11
EEDIO
X1
31
10
GP1
AGND
32
9
TEST3
6
7
8
TX+
TX-
AVDD
X2
SPI_MISO
12
5
29
20
EECS
AGND
VDD33
VDD33
13
DM9051 NP
DM9051INP
32-Pin QFN
4
28
21
WOL
RX-
GP3
TEST2
14
3
27
22
VDD33
RX+
RSTB
GP2
15
VSS
2
26
23
FDXLED
AVDD
SPDLED
INT
16
1
25
BGRES
LINKLED
24
4.1 32-Pin QFN
Note: The DM9051(I) IC employs a QFN package, which means the absence of a pin dedicated to ground
(GND). In the QFN package, the GND is located at the bottom of the IC directly in the middle. Exposed pad
(VSS) on bottom of package must be connected to ground.
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DM9051(I)
SPI to Ethernet Controller
5 Pin Description
Buffer Type
I = Input
O = Output
O/D = Open Drain
I/O = Input/Output
PD = Internal Pull-low about 60K
P = Power
PU = Internal Pull-high about 60K
5.1 SPI Processor Interface
Pin No.
17
Pin Name
SPI_CSN
Type
I,PU
18
SPI_CK
I,PD
19
SPI_MOSI
I
20
SPI_MISO
O,PD
24
INT
O,PD
Description
SPI Chip Select
The low active chip select pin from master SPI.
SPI Clock
The SPI clock mode 0 or 3 from master SPI.
SPI Data In
The data pin from master SPI.
SPI Data Out
The data pin to master SPI.
Interrupt Request
This pin is high active at default; its polarity can be modified by
EEPROM setting or by strap pin EECK or by MAC register 39H.
See the EEPROM content and MAC register 39H description for
detailed.
5.2 EEPROM Interface
Pin No.
11
Pin Name
EEDIO
Type
I/O,PD
12
EECK
O,PD
Description
EEPROM IO Data
The IO data pin to or from EEPROM.
EEPROM Clock
The clock pin to EEPROM.
This pin is also used as the strap pin of the polarity of the INT
pin.
13
EECS
O,PD
When this pin is pulled-high, the INT pin is low active; otherwise
the INT pin is high active.
EEPROM Chip Select
The high active chip select to EEPROM.
5.3 Clock Interface
Pin No.
30
31
Pin Name
X2
X1
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March 30, 2015
Type
O
I
Description
Crystal 25MHz Out
Crystal 25MHz In
9
DM9051(I)
SPI to Ethernet Controller
5.4 LED Interface
Pin No.
16
Pin Name
FDXLED
Type
O/D
Description
Full-Duplex LED
In LED mode 1, its low output indicates that the internal PHY is
operated in Full-Duplex mode, or it is floating for the Half-Duplex
mode of the internal PHY.
In LED mode 0, its low output indicates that the internal PHY is
operated in 10M mode, or it is floating for the 100M mode of the
internal PHY.
25
LINKLED
O/D
More LED modes are controlled by MAC register 57H
Link / Active LED
In LED mode 1, it is the combined LED of link and carrier sense
signal of the internal PHY.
In LED mode 0, it is the LED of the carrier sense signal of the
internal PHY only.
26
SPDLED
O/D
More LED modes are controlled by MAC register 57H.
Speed LED
Its low output indicates that the internal PHY is operated in
100M/S, or it is floating for the 10M mode of the internal PHY.
More LED modes are controlled by MAC register 57H.
Note: LED mode 0 or 1 is defined in MAC register 2DH or EEPROM setting.
5.5 10/100 PHY/Fiber
Pin No.
1
Pin Name
BGRES
Type
I/O
2,8
AVDD
P
3,4
RX+/ RX-
I/O
5,32
6,7
AGND
TX+/ TX-
P
I/O
Description
Band gap Pin, 6.8K Resistor
Connect a 6.8K 1% resistor to this pin and pin 5 AGND.
1.8V Power Output
The 1.8V regulator output pin.
Please do not use the pin as devices power source except the
central tap of transformer.
RX+/The RX input in 10BASE-T/100BASE-TX MDI mode or TX
output in 10BASE-T/100BASE-TX MDIX mode.
In 100M Fiber mode, these pins are for RX input only.
Analog Ground
TX+/The TX output in 10BASE-T/100BASE-TX MDI mode or RX
input in 10BASE-T/100BASE-TX MDIX mode.
In 100M Fiber mode, these pins are for TX output only.
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DM9051(I)
SPI to Ethernet Controller
5.6 Miscellaneous
Pin No.
9
Pin Name
TEST3
Type
I,PD
10
GP1
I/O
14
WOL
O,PD
22
TEST2
I,PD
23
GP2
I/O
27
RSTB
I
28
GP3
I/O,PD
Pin No.
15,21,29
Pin Name
VDD33
Type
P
33
VSS
P
Description
Operation Mode
Force to high in normal application
General Purpose Pin 1
This is a general purpose pin controlled by bit 1 of MAC register
1EH/1FH.
Wake On Lan
This is a control signal when wake up event occurred.
Its polarity and output type can be controlled by EEPROM
setting.
Operation Mode
Force to ground in normal application
General Purpose Pin 2
This is a general purpose pin controlled by bit 2 of MAC register
1EH/1FH.
Power on Reset
Active low signal to initiate the DM9051(I).
The DM9051(I) is ready after 5us when this pin disserted.
General Purpose Pin 3
This is a general purpose pin controlled by bit 3 of MAC register
1EH/1FH.
5.7 Power Pins
Description
VDD
3.3V power input
The QFN package ground
5.8 Strap Pins
Pin No.
12
Pin Name
EECK
Description
Polarity of INT
1 = INT pin low active
0 = INT pin high active
BIST Control
13
EECS
1 = Enable BIST
0 = Disable BIST
INT Output Type
14
WOL
1 = Open-Drain
0 = Push-pull mode
Note: If memory BIST function is enabled, the SPI interface should not active before RSTB go high 2ms.
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DM9051(I)
SPI to Ethernet Controller
6
MAC Control and Status Register Set
The DM9051(I) implements several control and status registers, which can be accessed by the host. These
CSRs are byte aligned. All CSRs are set to their default values by hardware or software reset unless they are
specified.
Default Value
Register
Description
Offset
after Reset
NCR
Network Control Register
00H
00H
NSR
Network Status Register
01H
00H
TCR
TX Control Register
02H
00H
TSR I
TX Status Register I
03H
00H
TSR II
TX Status Register II
04H
00H
RCR
RX Control Register
05H
00H
RSR
RX Status Register
06H
00H
ROCR
Receive Overflow Counter Register
07H
00H
BPTR
Back Pressure Threshold Register
08H
37H
FCTR
Flow Control Threshold Register
09H
38H
FCR
RX/TX Flow Control Register
0AH
00H
EPCR
EEPROM & PHY Control Register
0BH
00H
EPAR
EEPROM & PHY Address Register
0CH
40H
EPDRL
EEPROM & PHY Low Byte Data Register
0DH
XXH
EPDRH
EEPROM & PHY High Byte Data Register
0EH
XXH
WCR
Wake Up Control Register
0FH
00H
PAR
Physical Address Register
10H-15H
Determined by
EEPROM
MAR
Multicast Address Hash Table Register
16H-1DH
XXH
GPCR
General Purpose Control Register
1EH
71H
GPR
General Purpose Register
1FH
XXH
TRPAL
TX Memory Read Pointer Address Low Byte
22H
00H
TRPAH
TX Memory Read Pointer Address High Byte
23H
00H
RWPAL
RX Memory Write Pointer Address Low Byte
24H
00H
RWPAH
RX Memory Write Pointer Address High Byte
25H
0CH
VID
Vendor ID
28H-29H
0A46H
PID
Product ID
2AH-2BH
9051H
CHIPR
CHIP Revision
2CH
01H
TCR2
Transmit Control Register 2
2DH
00H
ATCR
Auto-Transmit Control Register
30H
00H
TCSCR
Transmit Check Sum Control Register
31H
00H
RCSCSR
Receive Check Sum Control Status Register
32H
00H
SBCR
SPI Bus Control Register
38H
44H
INTCR
INT Pin Control Register
39H
00H
PPCSR
Pause Packet Control Status Register
3DH
01H
EEE_IN
IEEE 802.3az Enter Counter Register
3EH
05H
EEE_OUT
IEEE 802.3az Leave Counter Register
3FH
0FH
ALNCR
SPI Byte Align Error Counter Register
4AH
00H
RLENCR
RX Packet Length Control Register
52H
00H
BCASTCR
RX Broadcast Control Register
53H
00H
INTCKCR
INT Pin Clock Output Control Register
54H
00H
MPTRCR
Memory Pointer Control Register
55H
00H
MLEDCR
More LED Control Register
57H
00H
MEMSCR
Memory Control Register
59H
00H
TMEMR
Transmit Memory Size Register
5AH
03H
MBSR
Memory BIST Status Register
5DH
40H
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DM9051(I)
SPI to Ethernet Controller
MRCMDX
MRCMDX1
MRCMD
SDR_DLY
MRRL
MRRH
MWCMDX
MWCMD
MWRL
MWRH
TXPLL
TXPLH
ISR
IMR
Memory Data Pre-Fetch Read Command Without Address
Increment Register
Memory Read Command Without Pre-Fetch and Without
Address Increment Register
Memory Data Read Command With Address Increment
Register
SPI Data Read Delay Counter Register
Memory Data Read Address Register Low Byte
Memory Data Read Address Register High Byte
Memory Data Write Command Without Address Increment
Register
Memory Data Write Command With Address Increment
Register
Memory Data Write Address Register Low Byte
Memory Data Write Address Register High Byte
TX Packet Length Low Byte Register
TX Packet Length High Byte Register
Interrupt Status Register
Interrupt Mask Register
70H
XXH
71H
XXH
72H
XXH
73H
74H
75H
76H
00H
00H
00H
XXH
78H
XXH
7AH
7BH
7CH
7DH
7EH
7FH
00H
00H
XXH
XXH
00H
00H
Key to Default
In the register description that follows, the default column takes the form:
<Reset Value>:
<Access Type>:
1
Bit set to logic one
RO = Read Only
0
Bit set to logic zero
RW = Read/Write
X
No default value
R/C = Read and Clear
P=
Power on reset default value
H=
Hardware reset default value
S=
Software reset default value
E=
Default value from EEPROM
T=
Default value from strap pin
h=
Hex, format
RW/C1=Read/Write and Cleared by write 1 WO = Write Only
Reserved bits are shaded and should be written with 0. Reserved bits are undefined on read access.
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DM9051(I)
SPI to Ethernet Controller
6.1 Network Control Register (00H)
Bit
7
Bit Name
RESERVED
Default
P0,RW
6
WAKEEN
P0,RW
5
RESERVED
0,RO
4
FCOL
PS0,RW
3
FDX
PS0,RO
2:1
LBK
PS00,RW
0
RST
P0,RW
Description
Reserved
Enables Wakeup Function
Clearing this bit will also clears all wakeup event status. This bit will
not be affected after a software reset.
1 = Enable
0 = Disable
Reserved
Force Collision Mode
1 = Force Collision Mode, used for testing
0 = Disable
Duplex Mode of the Internal PHY
1 = Full-Duplex
0 = Half-Duplex
Loopback Mode
Bit: 2 1
0
0
Normal
0 1
MAC Internal loopback
1 0
Internal PHY 100M mode digital loopback
1
1
(Reserved)
Software Reset and Auto-Clear after 10us
1 = Reset state
0 = Non-reset state
6.2 Network Status Register (01H)
Bit
7
Bit Name
SPEED
Default
X,RO
6
LINKST
X,RO
5
WAKEST
P0,
RW/C1
4
3
2
RESERVED
TX2END
TX1END
0,RO
PS1,
RW/C1
PS1,
RW/C1
Description
Speed of Internal PHY
This bit has no meaning when LINKST=0
1 = 10Mbps
0 = 100Mbps
Link Status of Internal PHY
1 = Link OK
0 = Link failed
Wakeup Event Status
Clears by read or write 1. This bit will not be affected after software
reset.
1 = Wakeup event
0 = No wakeup event
Reserved
TX Packet Index II Complete Status
Auto-Clear at begin transmitting of TX packet index II and Auto-Set
at the end of transmitting of TX packet index II.
1 = Transmit completion or idle of packet index II
0 = Packet index II transmit in progress
TX Packet Index I Complete Status
Auto-Clear at begin transmitting of TX packet index I and Auto-Set at
the end of transmitting of TX packet index I.
1 = Transmit completion or idle of packet index I
0 = Packet index I transmit in progress
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DM9051(I)
SPI to Ethernet Controller
1
RXOV
PS0,RO
0
RXRDY
PS0,RO
RX Memory Overflow Status
1 = RX memory Overflow
0 = Non-overflow
RX Packet Ready
1 = Have packet in RX memory
0 = No packet in RX memory
6.3 TX Control Register (02H)
Bit
7
6
Bit Name
RESERVED
TJDIS
Default
0,RO
PS0,RW
5
EXCECM
PS0,RW
4
PAD_DIS2
PS0,RW
3
CRC_DIS2
PS0,RW
2
PAD_DIS1
PS0,RW
1
CRC_DIS1
PS0,RW
0
TXREQ
PS0,RW
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Description
Reserved
Transmit Jabber Timer (2048 bytes) Control
1 = Disabled.
0 = Enable
Excessive Collision Mode Control
1 = Still tries to transmit this packet
0 = Aborts this packet when excessive collision counts more than 15
PAD Appends for Packet Index II
1 = Disable
0 = Enable
CRC Appends for Packet Index II
1 = Disable
0 = Enable
PAD Appends for Packet Index I
1 = Disable
0 = Enable
CRC Appends for Packet Index I
1 = Disable
0 = Enable
TX Request. Auto-Clear after Sending Completely
1 = Transmit in progress
0 = No transmit in progress
15
DM9051(I)
SPI to Ethernet Controller
6.4 TX Status Register I (03H) for Packet Index I
Bit
7
6
5
4
3
2
1:0
Bit Name
TJTO
LC
NC
LC
COL
EC
RESERVED
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Default
PS0,RO
Description
Transmit Jabber Time Out
It is set to indicate that the transmitted frame is truncated due to
more than 2048 bytes are transmitted.
PS0,RO
1 = Timeout
0 = Non-timeout
Loss of Carrier
It is set to indicate the loss of carrier during the frame transmission.
It is not valid in internal loopback mode.
PS0,RO
1 = Loss of carrier
0 = No carrier have been loss
No Carrier
It is set to indicate that there is no carrier signal during the frame
transmission. It is not valid in internal loopback mode.
PS0,RO
1 = No carrier during transmit
0 = Normal carrier status during transmit
Late Collision
It is set when a collision occurs after the collision window of 64
bytes.
PS0,RO
PS0,RO
0,RO
1 = Late collision
0 = No late collision
Collision Packet
It is set to indicate that the collision occurs during transmission.
1 = Have been collision
0 = No collision
Excessive Collision
It is set to indicate that the transmission is aborted due to 16
excessive collisions.
1 = 16 excessive collisions
0 = Less than 16 collisions
Reserved
16
DM9051(I)
SPI to Ethernet Controller
6.5 TX Status Register II (04H) for packet index II
Bit
7
6
5
4
3
2
1:0
Bit Name
TJTO
LC
NC
LC
COL
EC
RESERVED
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Default
PS0,RO
Description
Transmit Jabber Time Out
It is set to indicate that the transmitted frame is truncated due to
more than 2048 bytes are transmitted.
PS0,RO
1 = Timeout
0 = Non-timeout
Loss of Carrier
It is set to indicate the loss of carrier during the frame transmission.
It is not valid in internal loopback mode.
PS0,RO
1 = Loss of carrier
0 = No carrier have been loss
No Carrier
It is set to indicate that there is no carrier signal during the frame
transmission. It is not valid in internal loopback mode.
PS0,RO
1 = No carrier during transmit
0 = Normal carrier status during transmit
Late Collision
It is set when a collision occurs after the collision window of 64
bytes.
PS0,RO
PS0,RO
0,RO
1 = Late collision
0 = No late collision
Collision Packet
It is set to indicate that the collision occurs during transmission.
1 = Have been collision
0 = No collision
Excessive Collision
It is set to indicate that the transmission is aborted due to 16
excessive collisions.
1 = 16 excessive collisions
0 = Less than 16 collisions
Reserved
17
DM9051(I)
SPI to Ethernet Controller
6.6 RX Control Register (05H)
Bit
7
6
Bit Name
RESERVED
WTDIS
Default
PS0,RW
PS0,RW
5
DIS_LONG
PS0,RW
4
DIS_CRC
PS0,RW
3
ALL
PS0,RW
2
1
0
RUNT
PRMSC
RXEN
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
PS0,RW
PS0,RW
PS0,RW
Description
Reserved
Watchdog Timer Disable
1 = When set, the Watchdog Timer (2048 bytes) is disabled
0 = Otherwise it is enabled
Discard Long Packet
If Packet length is over 1522byte
1 = Enable
0 = Disable
Discard CRC Error Packet
1 = Enable
0 = Disable
Receive All Multicast
To receive packet with multicast destination address
1 = Enable
0 = Disable
Receive Runt Packet
To receive packet with size less than 64-bytes
1 = Enable
0 = Disable
Promiscuous Mode
To receive packet without destination address checking
1 = Enable
0 = Disable
RX Enable
1 = Enable
0 = Disable
18
DM9051(I)
SPI to Ethernet Controller
6.7 RX Status Register (06H)
Bit
7
6
5
4
3
2
1
0
Bit Name
RF
MF
LCS
RWTO
PLE
AE
CE
FOE
Default
PS0,RO
PS0,RO
PS0,RO
PS0,RO
Description
Runt Frame
It is set to indicate that the size of the received frame is smaller
than 64 bytes.
1 = Affirmative
0 = Negative
Multicast Frame
It is set to indicate that the received frame has a multicast address.
1 = Affirmative
0 = Negative
Late Collision Seen
It is set to indicate that a late collision is found during the frame
reception.
1 = Affirmative
0 = Negative
Receive Watchdog Time-Out
It is set to indicate that it receives more than 2048 bytes.
PS0,RO
1 = Affirmative
0 = Negative
Physical Layer Error
It is set to indicate that a physical layer error is found during the
frame reception.
PS0,RO
1 = Affirmative
0 = Negative
Alignment Error
It is set to indicate that the received frame ends with a non-byte
aligned.
PS0,RO
PS0,RO
1 = Affirmative
0 = Negative
CRC Error
It is set to indicate that the received frame ends with a CRC error.
1 = Affirmative
0 = Negative
RX Memory Overflow Error
It is set to indicate that a RX memory overflow error happens
during the frame reception.
1 = Affirmative
0 = Negative
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
19
DM9051(I)
SPI to Ethernet Controller
6.8 Receive Overflow Counter Register (07H)
Bit
7
6:0
Bit Name
RXFU
ROC
Default
PS0,R/C
PS0,R/C
Description
Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition.
1 = Affirmative
0 = Negative
Receive Overflow Counter
This is a statistic counter to indicate the received packet count
upon FIFO overflow.
6.9 Back Pressure Threshold Register (08H)
Bit
7:4
3:0
Bit Name
BPHW
JPT
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Default
PS3, RW
PS7, RW
Description
Back Pressure High Water Overflow Threshold
MAC will generate the jam pattern when RX SRAM free space is
lower than this threshold value.
The default is 3K-byte free space. Please do not exceed SRAM
size (1 unit=1K bytes).
Jam Pattern Time
Default is 200us
bit3 bit2 bit1 bit0
time
0
0
0
0
10.3us
0
0
0
1
20.5us
0
0
1
0
30.8us
0
0
1
1
51.4us
0
1
0
0
102us
0
1
0
1
195us
0
1
1
0
288us
0
1
1
1
380us
1
0
0
0
483us
1
0
0
1
576us
1
0
1
0
678us
1
0
1
1
771us
1
1
0
0
867us
1
1
0
1
966us
1
1
1
0
1.06ms
1
1
1
1
1.15ms
20
DM9051(I)
SPI to Ethernet Controller
6.10 Flow Control Threshold Register (09H)
Bit
7:4
Bit Name
HWOT
Default
PS3, RW
3:0
LWOT
PS8, RW
Description
RX Memory High Water Overflow Threshold
Send a pause packet with pause time=FFFFH when the RX memory
free space is less than this value. If this value is zero, its means no fRX
flow control. The default value is 3K-byte free space. Please do not
exceed RX memory size (1 unit=1K bytes).
RX Memory Low Water Overflow Threshold
Send a pause packet with pause time=0000H when RX memory free
space is larger than this value. This pause packet is enabled after the
high water pause packet is transmitted. The default memory free space
is 8K-byte. Please do not exceed RX memory size
(1 unit=1K bytes).
6.11 RX/TX Flow Control Register (0AH)
Bit
7
Bit Name
TXP0
Default
PS0,RW
6
TXPF
PS0,RW
5
TXPEN
PS0,RW
4
3
2
BKPA
BKPM
RXPS
PS0,RW
PS0,RW
PS0,R/C
1
RXPCS
PS0,RO
0
FLCE
PS0,RW
Description
Force TX Pause Packet with 0000H
Set to TX pause packet with pause time field is 0000H. Auto-Clears
after pause packet transmission completion.
Force TX Pause Packet with FFFFH
Set to TX pause packet with pause time field is FFFFH. Auto-Clears
after pause packet transmission completion.
TX Pause Packet Enable
Enables the pause packet for high/low water threshold control in
Full-Duplex mode.
1 = Enable
0 = Disable
Back Pressure Mode
This mode is for Half-Duplex mode only. It generates a jam pattern
when any packet comes and RX SRAM is over BPHW of MAC
register 8H.
1 = Enable
0 = Disable
Back Pressure Mode
This mode is for Half-Duplex mode only. It generates a jam pattern
when a packet’s DA matches and RX SRAM is over BPHW of MAC
register 8H.
1 = Enable
0 = Disable
RX Pause Packet Status, Latch and Read Clearly
When there has been packet received, this bit will be latched. This bit is
cleared after read.
1 = Has been receive pause packet
0 = No pause packet received
RX Pause Packet Current Status
1 = Received pause packet timer down-count in progress
0 = Pause packet timer value is zero
Flow Control Enable
Set to enable the flow control mode (i.e. can disable DM9051(I) TX
function temperately).
1 = Enable
0 = Disable
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
21
DM9051(I)
SPI to Ethernet Controller
6.12 EEPROM & PHY Control Register (0BH)
Bit
7:6
5
Bit Name
RESERVED
REEP
Default
0,RO
P0,RW
4
WEP
P0,RW
3
EPOS
P0,RW
2
ERPRR
P0,RW
1
ERPRW
P0,RW
0
ERRE
P0,RO
Description
Reserved
Reload EEPROM
Set one to reload EEPROM. Driver needs to clear it before to
enable this function.
Write EEPROM Enable
Set this bit to one before the operation of write EEPROM.
1 = Enable
0 = Disable
EEPROM or PHY Operation Select
0 = Select EEPROM
1 = Select PHY
EEPROM Read or PHY Register Read Command
Set one to read EEPROM or PHY register.
Auto-Cleared after the operation completes.
EEPROM Write or PHY Register Write Command
Set one to write EEPROM or PHY register.
Auto-Cleared after the operation completes.
EEPROM Access Status or PHY Access Status
1 = The EEPROM or PHY access is in progress
0 = Completion of the EEPROM or PHY access
6.13 EEPROM & PHY Address Register (0CH)
Bit
7:6
Bit Name
PHY_ADR
Default
P001,RW
5:0
EROA
P00,RW
Description
PHY Address bit 1 and 0, the PHY address bit [4:2] is force to 0.
Force to 01 in application.
EEPROM Word Address or PHY Register Number.
6.14 EEPROM & PHY Data Register (EE_PHY_L:0DH
Bit
7:0
Bit Name
EE_PHY_L
Default
P00,RW
7:0
EE_PHY_H
P00,RW
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
EE_PHY_H:0EH)
Description
EEPROM or PHY Low Byte Data
The low byte data read from or write to EEPROM or PHY.
EEPROM or PHY High Byte Data
The high byte data read from or write to EEPROM or PHY.
22
DM9051(I)
SPI to Ethernet Controller
6.15 Wake Up Control Register (0FH)
Bit
7:6
5
4
3
Bit Name
RESERVED
LINKEN
SAMPLEEN
MAGICEN
Default
0,RO
P0,RW
P0,RW
P0,RW
2
LINKST
P0,RO
1
SAMPLEST
P0,RO
0
MAGICST
P0,RO
Description
Reserved
Link Status Change Wake up Event
To control the link status change event in WOL pin function.
1 = Enable
0 = Disable
Sample Frame Wake up Event
To control the sample frame matched event in WOL pin function.
1 = Enable
0 = Disable
Magic Packet Wake up Event
To control the Magic packet event in WOL pin function.
1 = Enable
0 = Disable
Link Status Change Event Occurred
1 = Link change event occurred
0 = No link change event
Sample Frame Event Occurred
1 = Sample frame matched event occurred
0 = No sample frame matched
Magic Packet Event Occurred
1 = Magic packet received
0 = No magic packet received
6.16 Physical Address Register (10H~15H)
Bit
7:0
7:0
7:0
7:0
7:0
7:0
Bit Name
PAB5
PAB4
PAB3
PAB2
PAB1
PAB0
Default
E,RW
E,RW
E,RW
E,RW
E,RW
E,RW
Physical Address Byte 5
Physical Address Byte 4
Physical Address Byte 3
Physical Address Byte 2
Physical Address Byte 1
Physical Address Byte 0
Description
(15H)
(14H)
(13H)
(12H)
(11H)
(10H)
6.17 Multicast Address Hash Table Register (16H~1DH)
Bit
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Bit Name
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Default
X,RW
X,RW
X,RW
X,RW
X,RW
X,RW
X,RW
X,RW
Description
Multicast Address Hash Table Byte 7 (1DH)
Multicast Address Hash Table Byte 6 (1CH)
Multicast Address Hash Table Byte 5 (1BH)
Multicast Address Hash Table Byte 4 (1AH)
Multicast Address Hash Table Byte 3 (19H)
Multicast Address Hash Table Byte 2 (18H)
Multicast Address Hash Table Byte 1 (17H)
Multicast Address Hash Table Byte 0 (16H)
23
DM9051(I)
SPI to Ethernet Controller
6.18 General Purpose Control Register (1EH)
Bit
7:4
3
2
1
0
Bit Name
RESERVED
GPC3
GPC2
GPC1
RESERVED
Default
PH0,RO
P0,RW
Description
Reserved
General Purpose Control 3
Define the input/output direction of pin GP3.
1 = Pin GP3 in output mode
0 = Pin GP3 in input mode
General Purpose Control 2
Define the input/output direction of pin GP2.
P0,RW
1 = Pin GP2 in output mode
0 = Pin GP2 in input mode
General Purpose Control 1
Define the input/output direction of pins GP 1.
P0,RW
1 = Pin GP1 in output mode
0 = Pin GP1 in input mode
Reserved
P1,RO
6.19 General Purpose Register (1FH)
Bit
7:4
3
2
1
0
Bit Name
RESERVED
GPIO3
GPIO2
GPIO1
PHYPD
Default
0,RO
P0,RW
Description
Reserved
General Purpose Pin Data 3
When GPC3 of register 1EH is 1, the value of this bit is reflected to
pin GP3.
P0,RW
When GPC3 of register 1EH is 0, the value of this bit to be read is
reflected from correspondent pin of GP3.
General Purpose Pin Data 2
When GPC2 of register 1EH is 1, the value of this bit is reflected to
pin GP2.
P0,RW
When GPC2 of register 1EH is 0, the value of this bit to be read is
reflected from correspondent pin of GP2.
General Purpose Pin Data 1
When GPC1 of register 1EH is 1, the value of this bit is reflected to
pin GP1.
PE1,WO
When GPC1 of register 1EH is 0, the value of this bit to be read is
reflected from correspondent pin of GP1.
PHY Power Down Control
1 = Power down PHY
0 = Power up PHY
Note: If this bit is updated from ‘1’ to ‘0’, the whole MAC and PHY
Registers can not be accessed within 1ms.
6.20 TX Memory Read Pointer Address Register (22H~23H)
Bit
7:0
7:0
Bit Name
TRPAH
TRPAL
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Default
PS0,RO
PS0,RO
Description
TX Memory Read Pointer Address High Byte (23H)
TX Memory Read Pointer Address Low Byte (22H)
24
DM9051(I)
SPI to Ethernet Controller
6.21 RX Memory Write Pointer Address Register (24H~25H)
Bit
7:0
7:0
Bit Name
RWPAH
RWPAL
Default
PS,0CH,RO
PS,00H,RO
Description
RX Memory Write Pointer Address High Byte (25H)
RX Memory Write Pointer Address Low Byte (24H)
6.22 Vendor ID Register (28H~29H)
Bit
7:0
7:0
Bit Name
VIDH
VIDL
Default
PE,0AH,RO
PE,46H,RO
Description
Vendor ID High Byte (29H)
Vendor ID Low Byte (28H)
6.23 Product ID Register (2AH~2BH)
Bit
7:0
7:0
Bit Name
PIDH
PIDL
Default
PE,90H,RO
PE,51H,RO
Description
Product ID High Byte (2BH)
Product ID Low Byte (2AH)
6.24 CHIP Revision (2CH)
Bit
7:0
Bit Name
CHIPR
Default
P,01H,RO
Description
CHIP Revision
6.25 Transmit Control Register 2 (2DH)
Bit
7
6
Bit Name
LED
RLCP
Default
PE0,RW
P0,RW
5
4
RESERVED
ONEPM
P0,RW
P0,RW
3:0
IFGS
P00,RW
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Description
LED Mode
See the LED pin description for detailed.
1 = LED mode 1
0 = LED mode 0
Retry Late Collision Packet
Re-transmit the packet with late-collision.
1 = Enable
0 = Disable
Reserved
One Packet Mode
1 = Only one packet transmit command can be issued before
transmit completed
0 = At most two packet transmit command can be issued before
transmit completed
Inter-Frame Gap Setting
0XXX = 96-bit
1000 = 64-bit
1001 = 72-bit
1010 = 80-bit
1011 = 88-bit
1100 = 96-bit
1101 = 104-bit
1110 = 112-bit
1111 = 120-bit
25
DM9051(I)
SPI to Ethernet Controller
6.26 Auto-Transmit Control Register (30H)
Bit
7
Bit Name
AUTO_TX
Default
PS0,RW
6:2
1:0
RESERVED
RESERVED
P00,RO
PS0,RW
Description
Auto-Transmit Control
1 = Auto-Transmit enabled. Packet transmitted automatically when
end of write TX buffer
0 = Auto-Transmit disabled. When transmit packet, need to set
MAC register 2H bit 0 to “1”
Reserved
Reserved
6.27 Transmit Check Sum Control Register (31H)
Bit
7:3
2
Bit Name
RESERVED
UDPCSE
Default
0,RO
PS0,RW
1
TCPCSE
PS0,RW
0
IPCSE
PS0,RW
Description
Reserved
UDP CheckSum Generation
1 = Enable
0 = Disable
TCP CheckSum Generation
1 = Enable
0 = Disable
IPv4 CheckSum Generation
1 = Enable
0 = Disable
6.28 Receive Check Sum Status Register (32H)
Bit
7
Bit Name
UDPS
Default
PS0,RO
6
TCPS
PS0,RO
5
IPS
PS0,RO
4
UDPP
PS0,RO
3
TCPP
PS0,RO
2
IPP
PS0,RO
1
RCSEN
PS0,RW
0
DCSE
PS0,RW
Description
UDP CheckSum Status
1 = Checksum fail, if UDP packet
0 = No UDP checksum error
TCP CheckSum Status
1 = Checksum fail, if TCP packet
0 = No TCP checksum error
IPv4 CheckSum Status
1 = Checksum fail, if IP packet
0 = No IP checksum error
UDP Packet of Current Received Packet
1 = UDP packet
0 = Non UDP packet
TCP Packet of Current Received Packet
1 = TCP Packet
0 = Non TCP Packet
IPv4 Packet of Current Received Packet
1 = IP Packet
0 = Non IP Packet
Receive CheckSum Checking Enable
When set, the checksum status (bit 7~2) will be stored in bit 7:2 of
packet’s first byte of RX packets status header respectively.
1 = Enable
0 = Disable
Discard CheckSum Error Packet
When set, if IPv4/TCP/UDP checksum field is error, this packet will
be discarded.
1 = Enable
0 = Disable
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
26
DM9051(I)
SPI to Ethernet Controller
6.29 SPI Bus Control Register (38H)
Bit
7
Bit Name
RESERVED
Default
P0,RW
6:5
CURR
PE10,RW
4:3
RESERVED
P00,RW
2
CSB_SPIKE
PE1,RW
1:0
RESERVED
P00,RW
Description
Reserved
SPI_MISO Current Driving/Sinking Capability
00 = 2mA
01 = 4mA
10 = 6mA (default)
11 = 8mA
Reserved
Eliminate SPI_CSB Spike
1 = Eliminate about 2ns SPI_CSB spike
Reserved
6.30 INT Pin Control Register (39H)
Bit
7:2
Bit Name
RESERVED
Default
PS0,RO
1
INT_TYPE
PET0,RW
0
INT_POL
PET0,RW
Description
Reserved
INT Pin Output Type Control
1 = INT Open-Collector output
0 = INT push-pull output
INT Pin Polarity Control
1 = INT active low
0 = INT active high
6.31 Pause Packet Control/Status Register (3DH)
Bit
7:4
Bit Name
PAUSE_CTR
Default
P00,RO
3:0
PAUSE_MAX
PS1,RW
Description
Pause Packet Counter
The Pause packet counter before RX SRAM flow control low
threshold reached.
Max. Pause Packet Count
The maximum count of to generate pause packet with timer field
FFFFH, when the RX memory is reached to high threshold.
If the value of these bits are zero, the pause packet with timer field
FFFFH is generated whenever the RX memory is reached to the
high threshold.
6.32 IEEE 802.3az Enter Counter Register (3EH)
Bit
7
6:0
Bit Name
RESERVED
ENTER
Default
P0,RO
P5,RW
Description
Reserved
Timer to Enter EEE State (unit 2us)
The DM9051(I) will enter EEE state after TX idle timer timeout.
6.33 IEEE 802.3az Leave Counter Register (3FH)
Bit
7
6:0
Bit Name
EEE_EN
LEAVE
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Default
PE0,RW
P0Fh,RW
Description
EEE Enable
Timer to Leave EEE State (unit 2us)
The DM9051(I) will leave EEE state after TX leave timer timeout
when transmit command issued by set MAC register 2H bit 0 or
Auto-Transmit.
27
DM9051(I)
SPI to Ethernet Controller
6.34 SPI Byte Align Error Counter Register (4AH)
Bit
7:0
Bit Name
ALN_ERR
Default
P00,RO
Description
SPI Clock Byte Align Error Counter
The counter to count the byte align error of SPI_CK at end of
SPI_CSN. The maximum value is 255. Cleared by write this
register with any value.
6.35 RX Packet Length Control Register (52H)
Bit
7
Bit Name
RXLEN
Default
PS0,RW
6:5
4:0
RESERVED
MAXRXLEN
P00,RO
PS0,RW
Description
RX Packet Length Filter
1 = Enable check RX packet length
0 = Not to check RX packet length
Reserved
Maximum RX Packet Length Allowed (unit 64-byte)
The RX packet will be discarded if the data length is more than this
count.
Note: all bits 0 means no length limitation
6.36 RX Broadcast Control Register (53H)
Bit
7:6
Bit Name
BC_EN
Default
PS0,RW
5
4:0
RESERVED
MAXBCLEN
P0,RO
PS0,RW
Description
New RX Broadcast Packet Control Mode
0X = Broadcast packet control by bit 7 of MAC register 1DH
10 = Not to accept broadcast packet
11 = Enable packet length filter of broadcast packet
Reserved
Maximum RX Broadcast Packet Length Allowed (unit 64-byte)
The RX packet will be discarded if the data length is more than this
count.
Note: all bits 0 means no length limitation
6.37 INT Pin Clock Output Control Register (54H)
Bit
7
Bit Name
INT_CTL
Default
PS0,RW
6
CK_UNIT
PS0,RW
5
4:0
RESERVED
DUTY_LEN
P0,RO
PS0,RW
Description
INT Pin in Clock Output Control
1 = Enable INT pin in clock output
0 = INT pin output controlled by MAC register 39H
Clock Output Duty Cycle Width Unit
1 = 1.3ms
0 = 40.96us
Reserved
Clock Output Duty Cycle Width
Note: all bits 0 means INT pin is controlled by register 39H
6.38 Memory Pointer Control Register (55H)
Bit
7:2
1
Bit Name
RESERVED
RST_TX
Default
P00,RO
PS0,RW
0
RST_RX
PS0,RW
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Description
Reserved
Reset TX Memory Pointer
1 = Reset TX write/read memory address, Auto-Cleared after 1us
Reset RX Memory Pointer
1 = Reset RX write/read memory address, Auto-Cleared after 1us
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DM9051(I)
SPI to Ethernet Controller
6.39 More LED Control Register (57H)
Bit
7
Bit Name
LED_MOD3
Default
P0,RW
6:3
2
RESERVED
LED_POL
P00,RO
P0,RW
1:0
LED_TYPE
P00,RW
LED_Type
00
01
10
11
Description
New LED Mode
1 = LED types in bit 2:0
0 = The old LED mode 0 or 1 function
Reserved
The Reverse Polarity of LED Type
1 = LED in high active
0 = LED in low active
LED Type
Note: see following table
LNKLED (pin 25)
Link
Link & Traffic
Traffic
Link
SPDLED (pin 26)
Traffic
Speed100M
Speed100M
Traffic100M
FDXLED (pin 16)
Full-Duplex
Full-Duplex
Speed10M
Traffic10M
6.40 Memory Control Register (59H)
Bit
7:1
0
Bit Name
RESERVED
MSIZE_EN
Default
P00,RO
P0,RW
Description
Reserved
TX/RX Memory Size Configurable
1 = Enable to configure TX/RX memory size by MAC register 5AH
0 = 3K-byte for TX and 13K-byte for RX
6.41 Transmit Memory Size Register (5AH)
Bit
7:5
4:0
Bit Name
RESERVED
TRAM_SIZE
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Default
P00,RO
P3,RW
Description
Reserved
TX Memory Size (unit K-byte)
The RX memory size is 16 – TRAM_SIZE.
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DM9051(I)
SPI to Ethernet Controller
6.42 Memory BIST Status Register (5DH)
Bit
7
Bit Name
BIST_END
Default
P0,RO
6
BIST_DIS
P0,RO
5
4
RESERVED
PAT_00
P0,RO
P0,RO
3
PAT_DEC
P0,RO
2
PAT_INC
P0,RO
1
PAT_AA
P0,RO
0
PAT_55
P0,RO
Description
Memory BIST Completion
1 = Completed
0 = In progress
Memory BIST Control
This bit is the inverse of strap pin EECS.
1 = BIST disabled
0 = BIST enabled
Reserved
BIST 00H Pattern Status
1 = OK
0 = Fail
BIST Decrement Pattern Status
1 = OK
0 = Fail
BIST Increment Pattern Status
1 = OK
0 = Fail
BIST AAH Pattern Status
1 = OK
0 = Fail
BIST 55H Pattern Status
1 = OK
0 = Fail
6.43 Memory Data Pre-Fetch Read Command without Address Increment Register (70H)
Bit
7:0
Bit Name
MRCMDX
Default
X,RO
Description
Memory Read Command
Read data from RX SRAM. After the read of this command, the
read pointer of internal SRAM is unchanged. And the DM9051(I)
starts to pre-fetch the SRAM data to internal data buffers.
6.44 Memory Read Command without Data Pre-Fetch and Address Increment Register (71H)
Bit
7:0
Bit Name
MRCMDX1
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Default
X,RO
Description
Memory Read Command
Read data from RX Memory. After the read of this command, the
read pointer of RX memory is unchanged. And the DM9051(I) do
not pre-fetch the memory data.
30
DM9051(I)
SPI to Ethernet Controller
6.45 Memory Data Read Command with Address Increment Register (72H)
Bit
7:0
Bit Name
MRCMD
Default
X,RO
Description
Memory Read Command
Read data from RX SRAM. After the read of this command, the
read pointer is increased by 1.
6.46 SPI Data Read Delay Counter Register (73H)
Bit
7:0
Bit Name
RD_DLY
Default
0,WO
Description
Read Data Delay Counter
The byte delay counter that first data is valid after command byte.
6.47 Memory Data Read Address Register (74H~75H)
Bit
7:0
Bit Name
MDRAH
Default
PS0,RW
7:0
MDRAL
PS0,RW
Description
Memory Data Read Addresses High Byte
It will be set to 0CH, when IMR bit7 =1 (75H)
Memory Data Read Address Low Byte (74H)
6.48 Memory Data Write Command without Address Increment Register (76H)
Bit
7:0
Bit Name
MWCMDX
Default
X,WO
Description
Write Data to TX Memory
After the write of this command, the write pointer is unchanged
6.49 Memory Data Write Command with Address Increment Register (78H)
Bit
7:0
Bit Name
MWCMD
Default
X,WO
Description
Write Data to TX SRAM
After the write of this command, the write pointer is increased by 1.
6.50 Memory Data Write Address Register (7AH~7BH)
Bit
7:0
7:0
Bit Name
MDWAH
MDWAL
Default
PS0,RW
PS0,RW
Description
Memory Data Write Address High Byte (7BH)
Memory Data Write Address Low Byte (7AH)
6.51 TX Packet Length Register (7CH~7DH)
Bit
7:0
7:0
Bit Name
TXPLH
TXPLL
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Default
X,R/W
X,R/W
Description
TX Packet Length High Byte (7DH)
TX Packet Length Low Byte (7CH)
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DM9051(I)
SPI to Ethernet Controller
6.52 Interrupt Status Register (7EH)
Bit
7
6
5
Bit Name
RESERVED
RESERVED
LNKCHG
4
3
RESERVED
ROO
2
ROS
1
PT
0
PR
Default
Description
P1,RO
Reserved
RO
Reserved
PS0,RW/C1 Link Status Change
1 = Affirmative
0 = Negative
RO
Reserved
PS0,RW/C1 Receive Overflow Counter Overflow
1 = Affirmative
0 = Negative
PS0,RW/C1 Receive Overflow
1 = Affirmative
0 = Negative
PS0,RW/C1 Packet Transmitted
1 = Affirmative
0 = Negative
PS0,RW/C1 Packet Received
1 = Affirmative
0 = Negative
6.53 Interrupt Mask Register (7FH)
Bit
7
Bit Name
PAR
Default
PS0,RW
6
5
RESERVED
LNKCHGI
RO
PS0,RW
4
3
RESERVED
ROOI
RO
PS0,RW
2
ROI
PS0,RW
1
PTI
PS0,RW
0
PRI
PS0,RW
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Description
Pointer Auto-Return Mode
Enable the TX/RX memory read/write pointer to automatically
return to the start address when pointers are over the TX/RX
memory size. When this bit is set, the MAC register 75H will be set
to 0CH automatically if RX memory size is 13K-byte.
1 = Enable
0 = Disable
Reserved
Enable Link Status Change Interrupt
1 = Enable
0 = Disable
Reserved
Enable Receive Overflow Counter Overflow Interrupt
1 = Enable
0 = Disable
Enable Receive Overflow Interrupt
1 = Enable
0 = Disable
Enable Packet Transmitted Interrupt
1 = Enable
0 = Disable
Enable Packet Received Interrupt
1 = Enable
0 = Disable
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DM9051(I)
SPI to Ethernet Controller
7
EEPROM and SPI Command Format
7.1 EEPROM Format
Name
MAC Address
Auto Load Control
Word
0
3
Vendor ID
Product ID
Pin Control /
Control 1
4
5
6
Wake-up Mode
Control / Control 2
7
Control 3
8
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Offset
Description
0~5 6 Byte Ethernet Address
6~7 Bit 1:0 = 01: Update vendor ID and product ID from WORD4 and 5.
Bit 3:2 = 01: Accept setting of WORD6 [15,4:3]
Bit 5:4 = 01: Reserved, set to 00 in application
Bit 7:6 = 01: Accept setting of WORD7 [3:0]
Bit 9:8 = 01: Accept setting of WORD8[3:0]
Bit 11:10 = 01: Accept setting of WORD7 [7]
Bit 13:12 = 01: Accept setting of WORD7 [9:8]
Bit 15:14 = 01: Accept setting of WORD7 [15:12]
8~9 2 byte vendor ID (Default: 0A46H)
10~11 2 byte product ID (Default: 9051H)
12~13 When word 3 bit [3:2]=01, these bits can control the INT pins polarity.
Bit 2:0: Reserved; set to 0 in application
Bit 3: INT pin is active low when set (default: active high)
Bit 4: INT pin is open-collected (default: push-pull output)
Bit 14:5: Reserved; set to 0 in application
Bit 15: Enable 802.3az, to MAC register 3FH bit [7]
14~15 Bit 0: The WOL pin is active low when set (default: active high)
Bit 1: The WOL pin is in pulse mode when set (default: push-pull mode)
Bit 2: Magic wakeup event is enabled when set. (default: disable)
Bit 3: Link change wakeup event is enabled when set (default disable)
Bit 6:4: Reserved; set to 0 in application
Bit 7:0 = LED mode 0, 1=LED mode 1 (default: mode 0)
Bit 8:1 = Internal PHY is enabled after power-on (default: disable)
Bit 9: Fiber Mode Control; 1= Fiber mode, 0 = TP mode
Bit 13:10: Reserved; set to 0 in application
Bit 14: Reserved; set to 1 in application
Bit 15: Reserved; set to 0 in application
Bit 0: Reserved; set to 1 in application.
Bit 1: Eliminate SPI_CSB high spike control
16~17 This bit will be load into MAC register 38H bit 2
Bit 3:2: SPI_MISO driving capability
This bit will be load into MAC register 38H bit [6:5]
33
DM9051(I)
SPI to Ethernet Controller
7.2 SPI Command Format
Command Phase (MOSI pin)
Data Phase (MOSI pin)
Byte 0 [7:0]
Byte 1
SPI
Opcode
Register Address
Register Data
1
A6~A0
D7~D0
Register Write
Command Phase (MOSI pin)
Data Phase (MISO pin)
Byte 0 [7:0]
Byte 1
SPI
Opcode
Register Address
Register Data
0
A6~A0
D7~D0
0
1110000
D7~D0
Register Read
Memory
Dummy Read
Command Phase (MOSI pin)
Data Phase (MISO pin)
Byte 0 [7:0]
Byte 1~N
SPI
Opcode
Register Address
Memory Data
0
1110001
(D7~D0)*N
Memory Dummy Read
Without Pre-fetch
Note 1: N can be 1~4
Command Phase (MOSI pin)
Data Phase (MOSI pin)
Byte 0 [7:0]
Byte 1~N
SPI
Opcode
Register Address
Memory Data
1
1111000
(D7~D0)*N
Memory Write
Command Phase (MOSI pin)
Data Phase (MISO pin)
Byte 0 [7:0]
Byte 1~N
SPI
Opcode
Register Address
Memory Data
0
1110010
(D7~D0)*N
Memory Read
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
34
DM9051(I)
SPI to Ethernet Controller
Command Phase (MOSI pin)
Data Phase (MOSI pin)
Byte 0
Byte 1~N
Transmit Length and
Packet Data
SPI
Opcode
Register Address
1
1111100
Auto-Transmit
(D7~D0)*N (see Note1)
Note 2:
Byte 1: Transmit Length bit 7~0 of n-byte
Byte 2: FDH
Byte 3: Transmit Length bit 15~8 of n-byte
Byte 4: F8H
Byte 5~n+4: 5~n+4: n-byte transmit data
Note 3: This command burst is used only when register 30H bit 7 is set
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
35
DM9051(I)
SPI to Ethernet Controller
8
PHY Register Description
Key to Default
In the register description that follows, the default column takes the form:
<Reset Value>:
<Access Type>:
1
Bit set to logic one
RO = Read Only
0
Bit set to logic zero
RW = Read/Write
X
No default value
(PIN#) Value latched in from pin # at reset
<Attribute(s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
36
DM9051(I)
SPI to Ethernet Controller
8.1 Basic Mode Control Register (BMCR) – 00H
Bit
15
14
13
Bit Name
Reset
Default
0, RW/SC Reset
1=Software reset
0=Normal operation
Loopback
Speed Selection
0, RW
1, RW
12
Auto-Negotiation
Enable
1, RW
11
Power Down
0, RW
10
Isolate
0,RW
9
Restart
Auto-Negotiation
0,RW/SC
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Description
This bit sets the status and controls the PHY registers to their default
states. This bit, which is self-clearing, will keep returning a value of
one until the reset process is completed.
Loopback
Loopback control register
1 = Loopback enabled
0 = Normal operation
When in 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 1300ms "dead
time" before any valid data appear at the MII receive outputs.
Speed select
1 = 100Mbps
0 = 10Mbps
Link speed may be selected either by this bit or by Auto-Negotiation.
When Auto-Negotiation is enabled and bit 12 is set, this bit will return
Auto-Negotiation selected media type.
Auto-Negotiation enable
1 = Auto-Negotiation is enabled, bit 8 and 13 will be in
Auto-Negotiation status
Power Down
While in the power down state, the PHY should respond to
management transactions. During the transition to power down state
and while in the power down state, the PHY should not generate
spurious signals on the MII.
1 = Power down
0 = Normal operation
Isolate
1 = Isolates the PHY from the MII with the exception of the serial
management. (When this bit is asserted, the PHY does not
respond to the TXD[0:3], TX_EN, and TX_ER inputs, and it shall
present a high impedance on its TX_CLK, RX_CLK, RX_DV,
RX_ER, RX[0:3], COL and CRS outputs. When PHY is isolated
from the MII it shall respond to the management transactions)
0 = Normal operation
Restart Auto-Negotiation
1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation
process. When Auto-Negotiation is disabled (bit 12 of this
register cleared), this bit has no function and it should be
cleared. This bit is self-clearing and it will keep returning a value
of 1 until Auto-Negotiation is initiated by the PHY. The operation
of the Auto-Negotiation process will not be affected by the
management entity that clears this bit
0 = Normal operation
37
DM9051(I)
SPI to Ethernet Controller
8
Duplex Mode
1,RW
7
Collision Test
0,RW
6:0
RESERVED
0,RO
Duplex Mode
1 = Full-Duplex operation. Duplex selection is allowed when
Auto-Negotiation is disabled (bit 12 of this register is cleared).
With Auto-Negotiation enabled, this bit reflects the duplex
capability selected by Auto-Negotiation
0 = Normal operation
Collision Test
1 = Collision test enabled. When set, this bit will cause the COL
signal to be asserted in response to the assertion of TX_EN
0 = Normal operation
Reserved
Write as 0, ignore on read
8.2 Basic Mode Status Register (BMSR) – 01H
Bit
15
Bit Name
100BASE-T4
Default
0,RO/P
14
100BASE-TX
Full-Duplex
1,RO/P
13
100BASE-TX
Half-Duplex
1,RO/P
12
10BASE-T
Full-Duplex
1,RO/P
11
10BASE-T
Half-Duplex
1,RO/P
10:7
RESERVED
0,RO
6
MF Preamble
Suppression
0,RO
5
Auto-Negotiation
Complete
0,RO
4
Remote Fault
0,RO/LH
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Description
100BASE-T4 Capable
1 = Able to perform in 100BASE-T4 mode
0 = Not able to perform in 100BASE-T4 mode
100BASE-TX Full-Duplex Capable
1 = Able to perform 100BASE-TX in Full-Duplex mode
0 = Not able to perform 100BASE-TX in Full-Duplex mode
100BASE-TX Half-Duplex Capable
1 = Able to perform 100BASE-TX in Half-Duplex mode
0 = Not able to perform 100BASE-TX in Half-Duplex mode
10BASE-T Full-Duplex Capable
1 = Able to perform 10BASE-T in Full-Duplex mode
0 = Not able to perform 10BASE-TX in Full-Duplex mode
10BASE-T Half-Duplex Capable
1 = Able to perform 10BASE-T in Half-Duplex mode
0 = Not able to perform 10BASE-T in Half-Duplex mode
Reserved
Write as 0, ignore on read
MII Frame Preamble Suppression
1 = PHY will accept management frames with preamble suppressed
0 = PHY will not accept management frames with preamble
suppressed
Auto-Negotiation Complete
1 = Auto-Negotiation process completed
0 = Auto-Negotiation process not completed
Remote Fault
1 = Remote fault condition detected (cleared on read or by a chip
reset). Fault criteria and detection method is PHY
implementation specific. This bit will set after the RF bit in the
ANLPAR (bit 13, register address 05H) is set
0 = No remote fault condition detected
38
DM9051(I)
SPI to Ethernet Controller
3
Auto-Negotiation
Ability
1,RO/P
2
Link Status
0,RO/LL
1
0
Jabber Detect
Extended
Capability
0,RO/LH
1,RO/P
Auto Configuration Ability
1 = Able to perform Auto-Negotiation
0 = Not able to perform Auto-Negotiation
Link Status
1 = Valid link is established (for either 10Mbps or 100Mbps
operation)
0 = Link is not established
The link status bit is implemented with a latching function, so that the
occurrence of a link failure condition causes the link status bit to be
cleared and remain cleared until it is read via the management
interface.
Jabber Detect
1 = Jabber condition detected
0 = No jabber
This bit is implemented with a latching function. Jabber conditions
will set this bit unless it is cleared by a read to this register through a
management interface or a PHY reset. This bit works only in 10Mbps
mode.
Extended Capability:
1 = Extended register capable
0 = Basic register capable only
8.3 PHY ID Identifier Register #1 (PHYID1) – 02H
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9051(I). The Identifier
consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a
model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Bit
Bit Name
Default
Description
OUI Most Significant Bits
15.0
OUI_MSB
0181h
This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of
this register respectively. The most significant two bits of the OUI
are ignored (the IEEE standard refers to these as bit 1 and 2).
8.4 PHY ID Identifier Register #2 (PHYID2) – 03H
Bit
15:10
Bit Name
OUI_LSB
Default
101110,
RO/P
9:4
VNDR_MDL
001010,
RO/P
3:0
MDL_REV
0000,
RO/P
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Description
OUI Least Significant Bits:
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this
register respectively.
Vendor Model Number
Six bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9).
Model Revision Number
Four bits of vendor model revision number mapped to bit 3 to 0
(most significant bit to bit 3).
39
DM9051(I)
SPI to Ethernet Controller
8.5 Auto-Negotiation Advertisement Register (ANAR) – 04H
This register contains the advertised abilities of this DM905(I) device as they will be transmitted to its link
partner during Auto-Negotiation.
Bit
Bit Name
Default
Description
Next Page Indication
15
NP
0,RO/P
1 = Next page available
0 = No next page available
14
ACK
0,RO
13
RF
0,RW
12:11
RESERVED
X,RW
10
FCS
0,RW
9
T4
0,RO/P
8
TX_FDX
1,RW
7
TX_HDX
1,RW
6
10_FDX
1,RW
5
10_HDX
1,RW
4:0
Selector
00001,RW
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
The PHY has no next page, so this bit is permanently set to 0.
Acknowledge
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The PHY's Auto-Negotiation state machine will automatically control
this bit in the outgoing FLP bursts and set it at the appropriate time
during the Auto-Negotiation process. Software should not attempt to
write to this bit.
Remote Fault
1 = Local device senses a fault condition
0 = No fault detected
Reserved
Write as 0, ignore on read
Flow Control Support
1 = Controller chip supports flow control ability
0 = Controller chip doesn’t support flow control ability
100BASE-T4 Support
1 = 100BASE-T4 is supported by the local device
0 = 100BASE-T4 is not supported
The PHY does not support 100BASE-T4 so this bit is permanently
set to 0
100BASE-TX Full-Duplex Support
1 = 100BASE-TX Full-Duplex is supported by the local device
0 = 100BASE-TX Full-Duplex is not supported
100BASE-TX Support
1 = 100BASE-TX is supported by the local device
0 = 100BASE-TX is not supported
10BASE-T Full-Duplex support
1 = 10BASE-T Full-Duplex is supported by the local device
0 = 10BASE-T Full-Duplex is not supported
10BASE-T Support
1 = 10BASE-T is supported by the local device
0 = 10BASE-T is not supported
Protocol Selection Bits
These bits contain the binary encoded protocol selector supported
by this node.
<00001> indicates that this device supports IEEE 802.3 CSMA/CD.
40
DM9051(I)
SPI to Ethernet Controller
8.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) – 05H
This register contains the advertised abilities of the link partner when received during Auto-Negotiation.
Bit
Bit Name
Default
Description
Next Page Indication
15
NP
0,RO
1 = Link partner, next page available
0 = Link partner, no next page available
Acknowledge
14
ACK
0,RO
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
13
RF
0,RO
12:11
RESERVED
X,RO
10
FCS
0,RW
9
T4
0,RO
8
TX_FDX
0,RO
7
TX_HDX
0,RO
6
10_FDX
0,RO
5
10_HDX
0,RO
4:0
Selector
00000,RO
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
The PHY's Auto-Negotiation state machine will automatically control
this bit from the incoming FLP bursts. Software should not attempt
to write to this bit.
Remote Fault
1 = Remote fault indicated by link partner
0 = No remote fault indicated by link partner
Reserved
Write as 0, ignore on read
Flow Control Support
1 = Controller chip supports flow control ability by link partner
0 = Controller chip doesn’t support flow control ability by link partner
100BASE-T4 Support
1 = 100BASE-T4 is supported by the link partner
0 = 100BASE-T4 is not supported by the link partner
100BASE-TX Full-Duplex Support
1 = 100BASE-TX Full-Duplex is supported by the link partner
0 = 100BASE-TX Full-Duplex is not supported by the link partner
100BASE-TX Support
1 = 100BASE-TX Half-Duplex is supported by the link partner
0 = 100BASE-TX Half-Duplex is not supported by the link partner
10BASE-T Full-Duplex Support
1 = 10BASE-T Full-Duplex is supported by the link partner
0 = 10BASE-T Full-Duplex is not supported by the link partner
10BASE-T Support
1 = 10BASE-T Half-Duplex is supported by the link partner
0 = 10BASE-T Half-Duplex is not supported by the link partner
Protocol Selection Bits
Link partner’s binary encoded protocol selector.
41
DM9051(I)
SPI to Ethernet Controller
8.7 Auto-Negotiation Expansion Register (ANER) – 06H
Bit
15:5
Bit Name
RESERVED
Default
X,RO
4
PDF
0,RO/LH
3
LP_NP_ABLE
0,RO
2
NP_ABLE
0,RO/P
1
PAGE_RX
0,RO/LH
0
LP_AN_ABLE
0,RO
Description
Reserved
Write as 0, ignore on read
Local Device Parallel Detection Fault
1 = A fault detected via parallel detection function
0 = No fault detected via parallel detection function
Link Partner Next Page Able
1 = Link partner, next page available
0 = Link partner, no next page
Local Device Next Page Able
1 = Next page available
0 = No next page
New Page Received
A new link code word page received. This bit will be automatically
cleared when the register (register 6H) is read by management.
Link Partner Auto-Negotiation Able
A “1” in this bit indicates that the link partner supports
Auto-Negotiation.
8.8 DAVICOM Specified Configuration Register (DSCR) – 10H
Bit
15
Bit Name
BP_4B5B
Default
0,RW
14
BP_SCR
0,RW
13
BP_ALIGN
0,RW
12
BP_ADPOK
0,RW
11
RESERVED
0,RO
10
TX
1,RW
9
8
RESERVED
RESERVED
0,RO
0,RO
7
F_LINK_100
0,RW
6
RESERVED
0,RO
5
RESERVED
0,RO
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Description
Bypass 4B5B Encoding and 5B4B Decoding
1 = 4B5B encoder and 5B4B decoder function bypassed
0 = Normal 4B5B and 5B4B operation
Bypass Scrambler/Descrambler Function
1 = Scrambler and descrambler function bypassed
0 = Normal scrambler and descrambler operation
Bypass Symbol Alignment Function
1 = Receive functions (descrambler, symbol alignment and
symbol decoding functions) bypassed. Transmit functions
(symbol encoder and scrambler) bypassed
0 = Normal operation
BYPASS ADPOK
Force signal detector (SD) active. This register is for debug only,
not release to customer.
1 = Force SD is OK
0 = Normal operation
Reserved
Write as 0, ignore on read.
100BASE-TX or FX Mode Control
1 = 100BASE-TX operation
0 = 100BASE-FX operation
Reserved
Reserved
Write as 0, ignore on read.
Force Good Link in 100Mbps
1 = Force 100Mbps good link status
0 = Normal 100Mbps operation
This bit is useful for diagnostic purposes.
Reserved
Write as 0, ignore on read.
Reserved
Write as 0, ignore on read.
42
DM9051(I)
SPI to Ethernet Controller
4
RPDCTR-EN
1,RW
3
SMRST
0,RW
2
MFPSC
1,RW
1
SLEEP
0,RW
0
RESERVED
0,RW
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down.
1 = Enable automatic reduced power down
0 = Disable automatic reduced power down
Reset state machine
When writes 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed.
MF Preamble Suppression Control
MII frame preamble suppression control bit.
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Sleep Mode
Writing a 1 to this bit will cause PHY entering the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset.
Reserved
Force to 0 in application.
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H
Bit
15
Bit Name
100FDX
Default
1,RO
14
100HDX
1,RO
13
10FDX
1,RO
12
10HDX
1,RO
11:9
RESERVED
0,RO
8:4
PHYADR[4:0]
00001,RW
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Description
100M Full-Duplex Operation Mode
After Auto-Negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 100M
Full-Duplex mode. The software can read bit[15:12] to see which
mode is selected after Auto-Negotiation. This bit is invalid when it
is not in the Auto-Negotiation mode.
100M Half-Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 100M
Half-Duplex mode. The software can read bit[15:12] to see which
mode is selected after Auto-Negotiation. This bit is invalid when it
is not in the Auto-Negotiation mode.
10M Full-Duplex Operation Mode
After Auto-Negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 10M
Full-Duplex mode. The software can read bit[15:12] to see which
mode is selected after Auto-Negotiation. This bit is invalid when it
is not in the Auto-Negotiation mode.
10M Half-Duplex Operation Mode
After Auto-Negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 10M
Half-Duplex mode. The software can read bit[15:12] to see which
mode is selected after Auto-Negotiation. This bit is invalid when it
is not in the Auto-Negotiation mode.
Reserved
Write as 0, ignore on read.
PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of the
address (bit 4). A station management entity connected to multiple
PHY entities must know the appropriate address of each PHY.
43
DM9051(I)
SPI to Ethernet Controller
3:0
ANMB[3:0]
0,RO
Auto-Negotiation Monitor Bits
These bits are for debug only. The Auto-Negotiation status will be
written to these bits.
b3
0
0
0
0
0
0
0
0
b2
0
0
0
0
1
1
1
1
b1
0
0
1
1
0
0
1
1
b0
0
1
0
1
0
1
0
1
1
0
0
0
In IDLE state
Ability match
Acknowledge match
Acknowledge match fail
Consistency match
Consistency match fail
Parallel detects signal_link_ready
Parallel detects signal_link_ready fail
Auto-Negotiation completed
successfully
8.10 10BASE-T Configuration/Status (10BTCSR) – 12H
Bit
15
Bit Name
RESERVED
Default
0,RO
14
LP_EN
1,RW
13
HBE
1,RW
12
SQUELCH
1,RW
11
JABEN
1,RW
10:1
RESERVED
0,RO
0
POLR
0,RO
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March 30, 2015
Description
Reserved
Write as 0, ignore on read.
Link Pulse Enable
1 = Transmission of link pulses enabled
0 = Link pulses disabled, good link condition forced
This bit is valid only in 10Mbps operation.
Heartbeat Enable
1 = Heartbeat function enabled
0 = Heartbeat function disabled
When the PHY is configured for Full-Duplex operation, this bit will
be ignored (the collision/heartbeat function is invalid in
Full-Duplex mode).
Squelch Enable
1 = Normal squelch
0 = Low squelch
Jabber Enable
Enables or disables the Jabber function when the PHY is in
10BASE-T Full-Duplex or 10BASE-T transceiver loopback mode.
1 = Jabber function enabled
0 = Jabber function disabled
Reserved
Write as 0, ignore on read.
Polarity Reversed
When this bit is set to 1, it indicates that the 10Mbps cable polarity
is reversed. This bit is set and cleared by 10BASE-T module
automatically.
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DM9051(I)
SPI to Ethernet Controller
8.11 Power Down Control Register (PWDOR) – 13H
Bit
15:9
Bit Name
RESERVED
Default
0,RO
Description
Reserved
Read as 0, ignore on write
8
PD10DRV
0,RW
Vendor power down control test
7
PD100DL
0,RW
Vendor power down control test
6
PDCHIP
0,RW
Vendor power down control test
5
PDCOM
0,RW
Vendor power down control test
4
PDAEQ
0,RW
Vendor power down control test
3
PDDRV
0,RW
Vendor power down control test
2
PDEDI
0,RW
Vendor power down control test
1
PDEDO
0,RW
Vendor power down control test
0
PD10
0,RW
Vendor power down control test
Note: When selected, the power down value is control by register 14H bit0.
8.12 Specified Config Register – 14H
Bit
15
14
13
12
11
10
9
8
7
6
5
Bit Name
TSTSE1
TSTSE2
FORCE_TXSD
Description
Vendor test select control
Vendor test select control
Force Signal Detect
1 = Force SD signal OK in 100M
0 = Normal SD signal
FORCE_FEF
0,RW
Vendor test select control
Preamble Saving Control
PREAMBLEX
1,RW
1 = Transmit preamble bit count is normal in 10BASE-T mode
0 = When bit 10 is set, the 10BASE-T transmit preamble count is
reduced. When bit 11 of register 1DH is set, 12-bit preamble is
reduced; otherwise 22-bit preamble is reduced
10BASE-T Mode Transmit Power Saving Control
TX10M_PWR
1,RW
1 = Enable transmit power saving in 10BASE-T mode
0 = Disable transmit power saving in 10BASE-T mode
Auto-Negotiation Power Saving Control
NWAY_PWR
0,RW
1 = Disable power saving during Auto-Negotiation period
0 = Enable power saving during Auto-Negotiation period
RESERVED
0,RW
Reserved
MDIX_CNTL MDI/MDIX,RO The Polarity of MDI/MDIX Value
1 = MDIX mode
0 = MDI mode
Auto-Negotiation Loopback
AutoNeg_LPBK
0,RW
1 = Test internal digital Auto-Negotiation Loopback
0 = Normal
MDIX_CNTL Force Value
MDIX_FIX Value
0,RW
When Mdix_down = 1, MDIX_CNTL value depend on the register
value.
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Default
0,RW
0,RW
0,RW
45
DM9051(I)
SPI to Ethernet Controller
4
MDIX_Down
0,RW
3
2
1
MonSel1
MonSel0
RESERVED
0,RW
0,RW
0,RW
0
PD_Value
0,RW
HP Auto-MDIX Down
Manual force MDI/MDIX.
1 = Disable HP Auto-MDIX , MDIX_CNTL value depend on Bit5
0 = Enable HP Auto-MDIX
Vendor monitor select
Vendor monitor select
Reserved
Force to 0, in application.
Power Down Control Value
Decision the value of each field register 19H.
1 = Power down
0 = Normal
8.13 Power Saving Control Register (PSCR) – 1DH
Bit
15:13
12
Bit Name
RESERVED
LPI
Default
0,RO
0,RO
11
PREAMBLEX
0,RW
10
AMPLITUDE
0,RW
9
TX_PWR
0,RW
8:0
RESERVED
0,RO
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Description
Reserved
Low Power Idle Status
1 = In Low power idle mode
0 = In normal mode
Preamble Saving Control
When both bit 10and 11 of PHY register 14H are set, the
10BASE-T transmit preamble count is reduced.
1 = 12-bit preamble is reduced
0 = 22-bit preamble is reduced
Transmit Amplitude Control Disabled
1 = When cable is unconnected with link partner, the TX amplitude
is reduced for power saving
0 = Disable Transmit amplitude reduce function
Transmit Power Saving Control Disabled
1 = When cable is unconnected with link partner, the driving
current of transmit is reduced for power saving
0 = Disable transmit driving power saving function
Reserved
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DM9051(I)
SPI to Ethernet Controller
9
Functional Description
9.1 SPI Processor Interface
The DM9051(I) supports a slave mode SPI interface. In this mode, an external SPI master device (from
micro-controller or CPU) supplies the operating serial clock (SPI_CK), chip select (SPI_CSN), and serial input
data (SPI_MOSI). A Serial output data (SPI_MISO) is driven from DM9051(I). SPI_MOSI is the output on
SPI_CK falling edge of SPI master device, sampled by DM9051(I) on SPI_CK rising edge. SPI_MISO is
driven from DM9051(I) on SPI_CK falling edge and sampled on SPI_CK rising edge by SPI master device.
The falling edge of SPI_CSN starts the SPI burst operation and the rising edge of SPI_CSN stops the SPI
burst operation. The SPI_CK stays in low state at SPI mode 0 or stays in high state at SPI mode 3 when SPI
burst operation is idle (the SPI_CSN in high state).
9.2 Direct Memory Access Control
The DM9051(I) provides DMA capability to simplify the access of the internal memory. After the programming
of the starting address of the internal memory and then issuing a dummy read/write command to load the
current data to internal data buffer, the desired location of the internal memory can be accessed by the
read/write command registers. The memory’s address will be increased with one byte and the data of the next
location will be loaded into internal data buffer automatically. It is noted that the data of the first access (the
dummy read/write command) in a sequential burst should be ignored because that the data was the contents
of the last read/write command.
The internal memory size is 16K bytes. The first location of 3K bytes is used for the data buffer of the packet
transmission. The other 13K bytes are used for the buffer of the receiving packets. So in the write memory
operation, when the bit 7 of IMR is set, the memory address increment will wrap to location 0 if the end of
address (i.e. 3K) is reached. In a similar way, in the read memory operation, when the bit 7 of IMR is set, the
memory address increment will wrap to location 0C00H if the end of address (i.e. 16K) is reached.
9.3 Packet Transmission
There are two packets, sequentially named as index I and index II, can be stored in the TX SRAM at the same
time. The index MAC register 02H controls the insertion of CRC and pads. Their statuses are recorded at
index MAC registers 03H and 04H respectively.
The start address of transmission is 00h and the current packet is index I after software or power-on reset.
Firstly write data to the TX memory using the DMA port MAC register 78H and then write the byte count to TX
packet length register at MAC register 7CH and 7DH. Set the bit 1 of transmit control register MAC 02H or by
Auto-Transmit command burst, the DM9051(I) starts to transmit the index I packet. Before the transmission of
the index I packet ends, the data of the next (index II) packet can be write into TX memory and transmit it.
After the index I/II packet ends the transmission, the status MAC register 01H bit 3 and 4 will be set to indicate
the next index I or II packet can be transmitted.
9.4 Packet Reception
The RX memory is a ring data structure. The start address of RX memory is default 0C00H after software or
power-on reset or by set MAC register 55H bit 0. Each packet content format is a 4-byte status header
followed with the data of the reception packet which CRC field is included. The format of the 4-byte status
header is flag byte, RX status, low byte of RX size, and high byte of RX size respectively. The flag byte is 01h
or is RX checksum status if register 32H bit 1 is set.
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DM9051(I)
SPI to Ethernet Controller
9.5 100Base –TX Operation
The transmitter section contains the following functional blocks:
- 4B5B Encoder
- Scrambler
- Parallel to Serial Converter
- NRZ to NRZI Encoder
- NRZI to MLT-3
- MLT-3 Driver
9.5.1 4B5B Encoder
The 4B5B encoder converts 4-bit (4B) nibble data generated by the MAC reconciliation layer into a 5-bit (5B)
code group for transmission, see reference Table 1. This conversion is required for control and packet data to
be combined in code groups. The 4B5B encoder substitutes the first 8 bits of the MAC preamble with a J/K
code group pair (11000 10001) upon transmit. The 4B5B encoder continues to replace subsequent 4B
preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the
deassertion of the Transmit Enable signal from the MAC reconciliation layer, the 4B5B encoder injects the T/R
code group pair (01101 00111) indicating end-of-frame. After the T/R code group pair, the 4B5B encoder
continuously injects IDLEs into the transmit data stream until Transmit Enable is asserted and the next
transmit packet is detected.
The DM9051(I) includes a Bypass 4B5B conversion option within the 100Base-TX Transmitter for support of
applications like 100 Mbps repeaters, which do not require 4B5B conversion.
9.5.2 Scrambler
The scrambler is required to control the radiated emissions (EMI) by spreading the transmit energy across the
frequency spectrum at the media connector and on the twisted pair cable in 100Base-TX operation.
By scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency
range. Without the scrambler, energy levels on the cable could peak beyond FCC limitations at frequencies
related to repeated 5B sequences like continuous transmission of IDLE symbols. The scrambler output is
combined with the NRZ 5B data from the code group encoder via an XOR logic function. The result is a
scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies.
9.5.3 Parallel to Serial Converter
The parallel to serial converter receives parallel 5B scrambled data from the scrambler and serializes it
(converts it from a parallel to a serial data stream). The serialized data stream is then presented to the NRZ to
NRZI encoder block.
9.5.4 NRZ to NRZI Encoder
Since the transmit data stream has been scrambled and serialized, the data must be NRZI encoded for
compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted
pair cable.
9.5.5 MLT-3 Converter
The MLT-3 conversion is accomplished by converting the data stream output from the NRZI encoder into two
binary data streams with alternately phased logic one event.
9.5.6 MLT-3 Driver
The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver, which
converts these streams to current sources and alternately drives either side of the transmit transformer’s
primary winding, resulting in a minimal current MLT-3 signal.
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DM9051(I)
SPI to Ethernet Controller
9.5.7 4B5B Code Group
Symbol
Meaning
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
Table 1
4B Code
3210
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
I
J
K
T
R
H
Idle
SFD (1)
SFD (2)
ESD (1)
ESD (2)
Error
Undefined
0101
0101
Undefined
Undefined
Undefined
11111
11000
10001
01101
00111
00100
V
V
V
V
V
V
V
V
V
V
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
5B Code
43210
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
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DM9051(I)
SPI to Ethernet Controller
9.6 100Base-TX Receiver
The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to
synchronous 4-bit nibble data.
The receive section contains the following functional blocks:
- Signal Detect
- Digital Adaptive Equalization
- MLT-3 to Binary Decoder
- Clock Recovery Module
- NRZI to NRZ Decoder
- Serial to Parallel
- Descrambler
- Code Group Alignment
- 4B5B Decoder
9.6.1 Signal Detect
The signal detects function meets the specifications mandated by the ANSI XT12 TP-PMD 100Base-TX
standards for both voltage thresholds and timing parameters.
9.6.2 Adaptive Equalization
When transmitting data over copper twisted pair cable at high speed, attenuation based on frequency
becomes a concern. In high speed twisted pair signaling, the frequency content of the transmitted signal can
vary greatly during normal operation based on the randomness of the scrambled data stream. This variation
in signal attenuation, caused by frequency variations, must be compensated for to ensure the integrity of the
received data. In order to ensure quality transmission when employing MLT-3 encoding, the compensation
must be able to adapt to various cable lengths and cable types depending on the installed environment. The
selection of long cable lengths for a given implementation requires significant compensation, which will be
over-killed in a situation that includes shorter, less attenuating cable lengths. Conversely, the selection of
short or intermediate cable lengths requiring less compensation will cause serious under-compensation for
longer length cables. Therefore, the compensation or equalization must be adaptive to ensure proper
conditioning of the received signal independent of the cable length.
9.6.3 MLT-3 to NRZI Decoder
The DM9051(I) decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data.
9.6.4 Clock Recovery Module
The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery
Module locks onto the data stream and extracts the 125 MHz reference clock. The extracted and
synchronized clock and data are presented to the
NRZI to NRZ decoder.
9.6.5 NRZI to NRZ
The transmit data stream is required to be NRZI encoded for compatibility with the TP-PMD standard for
100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must be
reversed on the receive end. The NRZI to NRZ decoder, receives the NRZI data stream from the Clock
Recovery Module and converts it to a NRZ data stream to be presented to the Serial to parallel conversion
block.
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DM9051(I)
SPI to Ethernet Controller
9.6.6 Serial to Parallel
The serial to parallel converter receives a serial data stream from the NRZI to NRZ converter. It converts the
data stream to parallel data to be presented to the descrambler.
9.6.7 Descrambler
Because of the scrambling process requires to control the radiated emissions of transmit data streams, the
receiver must descramble the receive data streams. The descrambler receives scrambled parallel data
streams from the serial to parallel converter, and it descrambles the data streams, and presents the data
streams to the code GGoup alignment block.
9.6.8 Code Group Alignment
The code group alignment block receives un-aligned 5B data from the descrambler and converts it into 5B
code group data. Code group alignment occurs after the J/K is detected, and subsequent data is aligned on a
fixed boundary.
9.6.9 4B5B Decoder
The 4B5B Decoder functions as a look-up table that translates incoming 5B code groups into 4B (Nibble) data.
When receiving a frame, the first 2 5-bit code groups receive the start-of-frame delimiter (J/K symbols). The
J/K symbol pair is stripped and two nibbles of preamble pattern are substituted. The last two code groups are
the end-of-frame delimiter (T/R Symbols).
The T/R symbol pair is also stripped from the nibble, presented to the reconciliation layer.
9.7 10Base-T Operation
The 10Base-T transceiver is IEEE 802.3u compliant. When the DM9051(I) is operating in 10Base-T mode, the
coding scheme is Manchester. Data processed for transmit is presented in nibble format, converted to a serial
bit stream, then the Manchester encoded. When receiving, the bit stream, encoded by the Manchester, is
decoded and converted into nibble format.
9.8 Collision Detection
For Half-Duplex operation, a collision is detected when the transmit and receive channels are active
simultaneously. Collision detection is disabled in Full-Duplex operation.
9.9 Carrier Sense
Carrier Sense (CRS) in internal MII is asserted in Half-Duplex operation during transmission or reception of
data. During Full-Duplex mode, CRS is asserted only during receive operations.
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DM9051(I)
SPI to Ethernet Controller
9.10 Auto-Negotiation
The objective of Auto-Negotiation is to provide a means to exchange information between linked devices and
to automatically configure both devices to take maximum advantage of their abilities. It is important to note
that Auto-Negotiation does not test the characteristics of the linked segment. The Auto-Negotiation function
provides a means for a device to advertise supported modes of operation to a remote link partner,
acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes
of operation. This allows devices on both ends of a segment to establish a link at the best common mode of
operation. If more than one common mode exists between the two devices, a mechanism is provided to allow
the devices to resolve to a single mode of operation using a predetermined priority resolution function.
Auto-Negotiation also provides a parallel detection function for devices that do not support the
Auto-Negotiation feature. During parallel detection there is no exchange of information of configuration.
Instead, the receive signal is examined. If it is discovered that the signal matches a technology, which the
receiving device supports, a connection will be automatically established using that technology. This allows
devices not to support Auto-Negotiation but support a common mode of operation to establish a link.
9.11 Power Reduced Mode
The signal detect circuit is always turned to monitor whether there is any signal on the media (cable
disconnected).
The DM9051(I) automatically turns off the power and enters the Power Reduced mode, whether its operation
mode is N-way or force mode. When enters the Power Reduced mode, the transmit circuit still sends out
fast link pulse with minimum power consumption. If a valid signal is detected from the media, which might be
N-ways fast link pulse, 10Base-T normal link pulse, or 100Base-TX MLT3 signals, the device will wake up and
resume a normal operation mode.
That can be writing zero to PHY register 16 bit 4 to disable Power Reduced mode.
9.11.1 Power Down Mode
The PHY register 0 bit 11 can be set high to enter the power down mode, which disables all transmit and
receive functions, except the access of PHY registers
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DM9051(I)
SPI to Ethernet Controller
10 DC Characteristics
10.1 Absolute Maximum Ratings (25°C) (DM9051I support -40°C~+85°C)
Symbol
DVDD
VIN
VOUT
Tstg
TA
TA
LT
Parameter
Supply Voltage
DC Input Voltage (VIN)
DC Output Voltage(VOUT)
Storage Temperature Range
Ambient Temperature
Ambient Temperature
Lead Temperature
(TL,soldering,10 sec.).
Min.
-0.3
-0.5
-0.3
-65
0
-40
-
10.1.1 Operating Conditions
Symbol
Parameter
DVDD
Supply Voltage
100BASE-TX
PD
100BASE-TX (802.3az)
(Power Dissipation)
10BASE-T TX
Auto-Negotiation
Power Down Mode
Min.
3.135
-----------
Max.
3.6
5.5
3.6
+150
+70
+85
+260
Typ.
3.300
142
95
106
49
11
Unit
V
V
V
℃
℃
℃
℃
Max.
3.465
-----------
Conditions
DM9051INP
Unit
V
mA
mA
mA
mA
mA
Conditions
3.3V
3.3V
3.3V
3.3V
3.3V
10.2 DC Electrical Characteristics (VDD = 3.3V)
Symbol
Inputs
VIL
VIH
IIL
IIH
Outputs
VOL
VOH
Receiver
VICM
Parameter
Min.
Typ.
Max.
Unit
Conditions
Input Low Voltage
Input High Voltage
Input Low Leakage Current
Input High Leakage Current
2.0
-1
-
-
0.8
1
V
V
uA
uA
Input Voltage = 0.0V
Input Voltage = 3.3V
Output Low Voltage
Output High Voltage
2.4
-
0.4
-
V
V
IOL = 4mA
IOH = -4mA
-
1.8
-
V
100 W Termination
Across
1.9
2.0
2.1
V
Peak to Peak
4.4
│19│
5
│20│
5.6
│21│
V
mA
Peak to Peak
Absolute Value
│44│
│50│
│56│
mA
Absolute Value
RX+/RX- Common Mode Input
Voltage
Transmitter
VTD100 100TX+/- Differential Output
Voltage
VTD10
10TX+/- Differential Output Voltage
ITD100
100TX+/- Differential Output
Current
ITD10
10TX+/- Differential Output Current
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DM9051(I)
SPI to Ethernet Controller
11
AC Electrical Characteristics & Timing Waveforms
11.1 SPI Timing
M0 Mode
T2
T3
SPI_CSN
T1
SPI_CK
T4
SPI_MOSI
T5
Data
T6
Data
SPI_MISO
Symbol
T1
T2
T3
T4
T5
T6
Parameter
SPI_CK Frequency
SPI_CSN go low to SPI_CK go high
SPI_CK go low to SPI_CSN go high
SPI_MOSI setup time from SPI_CK go high
SPI_MOSI hold time after SPI_CK go high
SPI_MISO Output Delay after SPI_CK go low
Min.
10
10
3
3
5
Typ.
40
6
Max.
50
7
Unit
MHz
ns
ns
ns
ns
ns
M3 Mode
T2
T3
SPI_CSN
T1
SPI_CK
T4
SPI_MOSI
T5
Data
T6
Data
SPI_MISO
Symbol
T1
T2
T3
T4
T5
T6
Parameter
SPI_CK Frequency
SPI_CSN go low to SPI_CK go low
SPI_CK go high to SPI_CSN go high
SPI_MOSI setup time from SPI_CK go high
SPI_MOSI hold time after SPI_CK go high
SPI_MISO output delay after SPI_CK go low
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Min.
0
0
3
3
5
Typ.
40
6
Max.
50
7
Unit
MHz
ns
ns
ns
ns
ns
54
DM9051(I)
SPI to Ethernet Controller
11.2 TP Interface
Symbol
tTR/F
tTM
tTDC
Tt/T
XOST
Parameter
100TX+/- Differential Rise/Fall Time
100TX+/- Differential Rise/Fall Time
Mismatch
100TX+/- Differential Output Duty Cycle
Distortion
100TX+/- Differential Output Peak-to-Peak
Jitter
100TX+/- Differential Voltage Overshoot
Min.
3.0
0
Typ.
-
Max.
5.0
0.5
Unit
ns
ns
Conditions
-
0
-
0.5
ns
-
0
-
1.4
ns
-
0
-
5
%
-
Min.
39.9988
16
16
Typ.
40
20
20
Max.
40.0012
24
24
Unit
ns
ns
ns
Conditions
30ppm
-
Max.
-
Unit
ms
ns
us
Conditions
-
11.3 Oscillator/Crystal Timing
Symbol
TCKC
TPWH
TPWL
Parameter
OSC Clock Cycle
OSC Pulse Width High
OSC Pulse Width Low
11.4 Power On Reset Timing
T1
RSTB
Strap Pins
T2
EECS
T3
Symbol
T1
T2
T3
Parameter
RSTB Low Period
Strap Pins hold time with RSTB
RSTB high to EECS high
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Min.
1
40
-
Typ.
9.5
-
55
DM9051(I)
SPI to Ethernet Controller
11.5 EEPROM Interface Timing
T3
T2
EECS
T1
EECK
T4
T6
EEDIO
T5
T7
Symbol
T1
T2
T3
T4
T5
T6
T7
Parameter
EECK Frequency
EECS setup time
EECS hold time
EEDIO setup time when output
EEDIO hold time when output
EEDIO setup time when input
EEDIO hold time when input
Min.
15
8
Typ.
0.1953
960
1600
920
4200
-
Max.
-
Unit
MHz
ns
ns
ns
ns
ns
ns
Min.
64
Typ.
16
-
Max.
-
Unit
ms
ms
11.6 LED (traffic ON/OFF timing) any LED as Traffic
Symbol
T1
T2
Parameter
LED Traffic ON Time
LED Traffic OFF Time
Doc No: DM9051(I)-12-MCO-DS-P01
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DM9051(I)
SPI to Ethernet Controller
12 Package Information
32 Pins QFN Package Outline Information:
Symbol
A
A1
A3
b
D/E
D2/E2
e
L
K
R
aaa
bbb
ccc
ddd
eee
fff
Dimension in mm
MIN
NOM MAX
0.80
0.85
0.90
0.00
0.02
0.05
0.02 REF
0.18
0.25
0.30
5.00 BSC
3.35
3.50
3.65
0.50 BSC
0.35
0.40
0.45
0.20
----0.09
----0.15
0.10
0.10
0.05
0.08
0.10
Dimension in inch
MIN
NOM MAX
0.031 0.033 0.035
0.000 0.001 0.002
0.008 REF
0.007 0.010 0.012
0.197 BSC
0.132 0.138 0.144
0.020 BSC
0.014 0.016 0.018
0.008
----0.004
----0.006
0.004
0.004
0.002
0.003
0.004
NOTE:
1. CONTROLLING DIMENSION: MILLIMETER
2. REFERENCE DOCUMENT: JEDEC MO-220
Doc No: DM9051(I)-12-MCO-DS-P01
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57
DM9051(I)
SPI to Ethernet Controller
13 Ordering Information
Part Number
DM9051NP
DM9051INP
Pin Count
32
32
Package
QFN(Pb-Free)
QFN(Pb-Free)
Disclaimer
The information appearing in this publication is
believed to be accurate. Integrated circuits sold by
DAVICOM Semiconductor are covered by the
warranty and patent indemnification provisions
stipulated in the terms of sale only. DAVICOM makes
no warranty, express, statutory, implied or by
description regarding the information in this publication
or regarding the information in this publication or
regarding the freedom of the described chip(s) from
patent infringement. FURTHER, DAVICOM MAKES
NO WARRANTY OF MERCHANTABILITY OR
FITNESS FOR ANY PURPOSE. DAVICOM reserves
the right to halt production or alter the specifications
and prices at any time without notice. Accordingly, the
reader is cautioned to verify that the data sheets and
other information in this publication are current before
placing orders. Products described herein are
intended for use in normal commercial applications.
Applications involving unusual environmental or
reliability requirements, e.g. military equipment or
medical life support equipment, are specifically not
recommended without additional processing by
DAVICOM for such applications.
Please note that application circuits illustrated in
this document are for reference purposes only.
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order acknowledgment govern all sales by
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terms inconsistent with these unless DAVICOM
agrees otherwise in writing. Acceptance of the
buyer’s orders shall be based on these terms.
Company Overview
DAVICOM Semiconductor Inc. develops and
manufactures integrated circuits for integration
into data communication products. Our mission
is to design and produce IC products that are the
industry’s best value for Data, Audio, Video, and
Internet/Intranet applications. To achieve this
goal, we have built an organization that is able to
develop chipsets in response to the evolving
technology requirements of our customers while
still delivering products that meet their cost
requirements.
Products
We offer only products that satisfy high
performance requirements and which are
compatible with major hardware and software
standards. Our currently available and soon to
be released products are based on our
proprietary designs and deliver high quality, high
performance chipsets that comply with modem
communication
standards
and
Ethernet
networking standards.
Contact Windows
For additional information about DAVICOM products, contact the Sales department at:
Headquarters
Hsin-chu Office:
No.6, Li-Hsin 6th Rd.,
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MAIL: sales@davicom.com.tw
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WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near
the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and function.
Doc No: DM9051(I)-12-MCO-DS-P01
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