4i2i Communications Ltd., Doig Scott Building, Craibstone, Aberdeen AB21 9YA, UK. Tel. +44 1224 712844, Fax +44 1224 714413, email: [email protected], web: http://www.4i2i.com Convolutional Encoder and Viterbi Decoder Core Datasheet For Actel FPGAs Overview popular form of which follows the Viterbi algorithm. By determining the most 4i2i’s Viterbi FEC core consists of a likely original sequence, the decoder can convolutional encoder and a Viterbi de- thus correct errors in the bitstream. coder. It supports error correction for both burst mode and continuous data 4i2i’s core uses a convolutional code with input. Convolutional encoding works by a constraint length K of 7 and supports mapping k input bits to n output bits, to various selectable code rates, including give a rate nk coded bitstream. At the re- 12 , 13 , 23 , 34 , 65 and 78 . Industry standard ceiver, this bitstream is passed through puncturing algorithms are used, whereby a maximum-likelihood decoder, the most certain patterns of bits are deleted to ob- 1 tain a lower bit rate at the encoder out- A comprehensive testbench is supplied put. which simulates the encoding and subsequent decoding of a stream of data of The Viterbi core can be configured to arbitrary length. Errors can be added to work using 1-bit hard-decision decoding the channel with a specified probability. or n-bits of soft-decision decoding. Both The testbench provides a good illustrathe convolutional encoder output width tion of writing code to interface to the and the Viterbi decoder input width can core. Optionally the complete encoder, be selectable depending on the needs of decoder and testbench can be additionthe application. ally provided in ANSI C. The compact Viterbi decoder architecture offers a maximum throughput at the output of fCLK bits per second. Encoder overview 4 The following sections describe the main features of the core, the core functions The convolutional encoder has a constraint length of 7 and therefore takes and its interface: the form of a shift register with 6 elements. One bit can be input every clock Features cycle. The output bits are defined as The following features are selected via a combination of the shift register elements, according to the chosen generuser-configurable parameters: ator polynomial, and are concatenated • Selectable code rates 31 , 12 , 23 , 34 , 56 to form the encoded output sequence. or 78 . There is the option of a serial and a byte• 1-bit hard decision or n-bits soft wide parallel data interface at the input. The output width is programmable dedecision. pending on the code rate of the applica• Constraint length K = 7, genera- tion in order to avoid unnecessary glue tor polynomials g0 = 171o , g1 = logic between the blocks. 165o (rate 13 only) and g2 = 133o . The polynomials used are g0 = 171o , g1 = 133o (rate 12 or rate 31 ) and g2 = • Optional pseudo-BER calculation. 165o (rate 1 only). 3 • Optional in-phase detection. • Selectable interface widths. Deliverables Decoder overview The core can be supplied either as synthesizable Verilog or VHDL source code. The synthesizable source code is supplied for internal use along with a license to allow redistribution of the synthesized design within one specified product or product line without payment of per unit royalties. The decoder block consists of a depuncturer and Viterbi decoder which can decode data using either hard or soft decision decoding. It is based on 21 and 13 rate codes but supports punctured code rates 23 , 34 , 56 and 78 . The minimum traceback depth is 64. 2 Figure 1: Encoder block Figure 2: Decoder block Depuncturer is dependent on the depuncturer input data rat and must be increased if the input data for the Viterbi decoder occurs in high speed data bursts. The Viterbi algorithm performs the traceback operation in parallel with the path calculations. The width of the metric registers must be enlarged when using high rate punctured codes, when the number of bits used in soft decision is large and when the Bit Error Rate at the input of the Viterbi decoder is high. The trace back depth can be set with the programmable parameter trb, and should be sufficiently long to avoid loss of accuracy. The depuncturer block replaces the deleted symbols in the puncturing process to recover the original data rate. Viterbi decoder The Viterbi decoder divides the input data stream into blocks, estimating the most likely data sequence and outputting each decoded data sequence in a burst. The input and the calculations are continuous, and for the standard decoder require 4 clock cycles for every 2 bits of data input (3 bits when working with 13 code). The size of the input fifo 3 Term K Codif Rate Widout Name Constraint length Convolutional code rate Puncture rate Output data width Definition Number of input bits over which the convolutional code is computed. Ratio of input to output bits for the convolutional encoder. Ratio of input to output bits for the convolutional encoder using the puncturing process. The puncturing code rates are derived from the 1/2 mother rate. The output data width is configurable to avoid using unnecessary glue logic between blocks, depending on the application. Range 7 1 1 , 2 3 1 1 2 , , , 3 2 3 3 5 , 4 6 or 7 8 Configurable depending on rates Table 1: Encoder parameters Term Codif Rate Name Convolutional code rate Puncture rate Bitin Input bits Widin Viterbi input width Hard or soft decision. Traceback depth Hosd Trb Definition Ratio of input to output bits for the convolutional encoder. Ratio of output to input bits for the convolutional encoder using the puncturing process. Number of processing bits for the decoder, dependent on Hosd. Width of input data to the Viterbi decoder. Indicates if the decoder is working in hard or soft decision mode. Length of the path used by the decoder. Range 1 1 , 2 3 1 1 2 , , , 3 2 3 3 5 , or 87 4 6 Configurable Like widout, multiple of Bitin 0,1 Configurable Table 2: Decoder parameters Implementation (It should be noted that implementing the decoder in the SX/SX-A and RTSXExample implementations of the convoS devices would require the use of exlutional encoder core and of the Viterbi ternal RAM, and that additional RAM decoder core in Actel devices are given would be required for the use of a puncin Table 4 and Table 5. The decoder is a tured code or the pseudo-BER calculastandard 12 rate implementation: further tor.) examples can be generated on request. 4 Term Memsize Name Storage of path metrics Lfif Size of input FIFO Widoutb Viterbi output width Definition Size of memory storing path information. Size of the FIFO required for the depuncturing mode. Width of output data from decoder. Range Configurable Configurable Configurable Table 3: Decoder parameters (continued) Family Device (-speed grade) Seq. (R-cells) ProASICPlus APA075-STD Axcelerator AX125-3 31 RTSX-S RT54SX32S-1 SX/SX-A 54SX08A-1 Comb. (C-Cells) Total util. RAM (blocks) Performance Throughput 26% 0 63 MHz 63 Mbps 29 3% 0 106 MHz 106 Mbps 31 29 3% n/a 79 MHz 79 Mbps 31 29 8% n/a 85 MHz 85 Mbps Table 4: Example implementations of Convolutional Encoder in Actel FPGAs Family Device (-speed grade) Seq. (R-cells) ProASICPlus APA450-STD Axcelerator AX500-3 1016 RTSX-S RT54SX72S-1 SX/SX-A 54SX72A-1 Comb. (C-Cells) Total util. RAM (blocks) Performance Throughput 42% 9 24.3 MHz 6.1 Mbps 1246 29% 3 55.1 MHz 13.8 Mbps 1012 1823 47% n/a 21.6 MHz 5.4 Mbps 1012 1823 47% n/a 25.1 Mhz 6.3 Mbps Table 5: Example implementations of Viterbi Decoder in Actel FPGAs 5 Family Device (-speed grade) Seq. (R-cells) ProASICPlus APA450-STD Axcelerator AX500-3 1050 RTSX-S RT54SX72S-1 SX/SX-A 54SX72A-1 Comb. (C-Cells) Total util. RAM (blocks) Performance Throughput 43% 9 24.3 MHz 6.1 Mbps 1273 29% 3 58.4 MHz 14.6 Mbps 1041 1851 48% n/a 25.4 MHz 6.4 Mbps 1041 1851 48% n/a 29.4 Mhz 7.4 Mbps Table 6: Example implementations of Convolutional Encoder and Viterbi Decoder core in Actel FPGAs 6

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