CorePWM v4.3 Handbook

CorePWM v4.3
Handbook
Microsemi Corporation, Mountain View, CA 94043
© 2015 Microsemi Corporation. All rights reserved.
Printed in the United States of America
Part Number: 50200113-7
Release: January 2015 Revision 7
No part of this document may be copied or reproduced in any form or by any means without prior written
consent of Microsemi.
Microsemi makes no warranties with respect to this documentation and disclaims any implied warranties
of merchantability or fitness for a particular purpose. Information in this document is subject to change
without notice. Microsemi assumes no responsibility for any errors that may appear in this document.
This document contains confidential proprietary information that is not to be disclosed to any
unauthorized person without prior written consent of Microsemi Corporation.
Trademarks
Microsemi, IGLOO, Microsemi Fusion, ProASIC, SmartFusion, SmartFusion2, IGLOO2, RTG4,
Libero, Pigeon Point and the associated logos are trademarks or registered trademarks of Microsemi
Corporation. All other trademarks and service marks are the property of their respective owners.
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Core Overview . . . . . . .
Core Version . . . . . . . .
Supported Interfaces . . . .
Utilization and Performance
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.4
.5
.5
.5
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
11
12
16
21
24
Tool Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SmartDesign . . . . . . . . . .
Importing into Libero IDE . . .
Simulation Flows . . . . . . . .
Synthesis in the Libero IDE . .
Place-and-Route in Libero IDE
3
.
.
.
.
Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Blocks . . .
I/O Signals . . . . . .
Register Map . . . . .
Configuration Example
APB Interface Timing
2
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
25
27
27
28
28
Example Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
General Purpose PWM Application – Temperature Monitor . . . . . . . . . . . . . . . . . . . 29
DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4
Software Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
A List of Document Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
B Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Customer Service . . . . . . . . . . . . . . . . . .
Customer Technical Support Center . . . . . . . .
Technical Support . . . . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Customer Technical Support Center
ITAR Technical Support . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
34
34
34
34
34
35
C Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Revision 7
3
Introduction
Core Overview
Intended Use
CorePWM is a general purpose, multi-channel pulse width modulator (PWM) module for motor control, tone
generation, battery charging, heating elements, and more.
In General Purpose PWM mode, duty cycle updates can be performed asynchronously or synchronously, based on
parameter selection. In synchronous mode, all channels are updated at the beginning of the PWM period, which is
useful for motor control and can be used to keep a constant dead band space between channel waveforms. Asynchronous
mode is relevant to applications such as LED control, where synchronous updates are not required. Asynchronous mode
lowers the area size, reducing shadow register requirements.
In addition to the general purpose PWM modes, there is a "Low Ripple DAC" mode that creates a minimum period
pulse train whose High/Low average is that of the chosen duty cycle. When used with a low-pass filter (such as a simple
RC circuit), a DAC can be created with far better bandwidth and ripple performance than a standard PWM algorithm
can achieve. This type of DAC is ideally suited for fine tuning of power supply output levels.
CorePWM also provides support for tachometer monitoring of 3- and 4-wire fans. Incoming tachometer data is read by
the firmware through the APB interface to calculate fan speed.
Key Features
• Configuration updates for all channels can be synchronized to the beginning of the PWM period, allowing precise
updates and maintaining phase alignments between channels
• Configurable resolution based on the APB bus width
• Low-cost PWM solution with up to 16 separate PWM digital outputs, configurable via a register interface
• For DAC applications: Optional, per-channel Low Ripple DAC mode, allowing for greater resolution output of a given
filter
• Low-cost TACHOMETER solution with up to 16 separate TACH digital inputs, configurable via a register interface
• All PWM outputs are double-edge-controlled
• Per-channel fixed register option for lower tile count
• Edge control based on a configurable PWM period with prescaler value and 0% to 100% duty cycle capability
• Set High, set Low, and Toggle Edge-Control modes
• Can be programmed on-the-fly from a microcontroller, such as Core8051s, CoreABC, or the Fusion backbone
• Can be used to perform open or closed-loop margining of power supplies
Revision 7
4
CorePWM v4.3
Core Version
Supported Families
• IGLOO®/e
• ProASIC®3/E/L
• Fusion
• ProASICPLUS®
• Axcelerator®
• RTAX-S
• RTAX-DSP
• SmartFusion®
• SmartFusion®2
• IGLOO®2
• RTG4™
Core Version
This handbook supports CorePWM version 4.3.
Supported Interfaces
CorePWM is available with an APB interface, which is described in the “APB Interface Timing” section on page 24.
Utilization and Performance
CorePWM has been implemented in several of Microsemi’s device families. A summary of various implementation data
is listed in the following tables (using standard speed grades).
As shown in Table 1 through Table 8 on page 10, it is recommended to fix all registers that are not used, via parameters,
to ensure optimal synthesis tile reduction.
Table 1 · CorePWM Device Utilization and Performance (one 8-bit DAC channel configuration)
Tiles
Utilization
Family
Performance
(MHz)
Sequential
Combinatorial
Total
Device
Total
IGLOO/e
20
96
116
AGLE600
1.0%
72
ProASIC3/E
20
76
96
A3P250
2.0%
96
Fusion
20
76
96
AFS600
1.0%
101
ProASICPLUS
20
102
122
APA300
1.0%
101
Axcelerator
20
31
51
AX250
1.0%
252
RTAX-S
20
31
51
RTAX250S
1.0%
223
SmartFusion
20
78
98
A2F500M3G
0.85%
180
Note:
Data in this table were achieved using typical synthesis and layout settings. Top-level parameters/generics were set as
follows: PWM_NUM = 1, APB_DWIDTH = 8; DAC_MODE1 = 1 (DAC mode), FIXED_PRESCALE_EN = 1,
FIXED_PRESCALE = 0, FIXED_PERIOD_EN = 1, FIXED_PERIOD = 1, SHADOW_REG_EN1 = 0.
Revision 7
5
Introduction
CorePWM v4.3
Table 1 · CorePWM Device Utilization and Performance (one 8-bit DAC channel configuration) (continued)
SmartFusion2
20
30
50
M2S150T
0.03%
450
IGLOO2
20
30
50
M2GL150T
0.03%
450
RTG4
20
40
60
RT4G150
0.04%
300
Note:
Data in this table were achieved using typical synthesis and layout settings. Top-level parameters/generics were set as
follows: PWM_NUM = 1, APB_DWIDTH = 8; DAC_MODE1 = 1 (DAC mode), FIXED_PRESCALE_EN = 1,
FIXED_PRESCALE = 0, FIXED_PERIOD_EN = 1, FIXED_PERIOD = 1, SHADOW_REG_EN1 = 0.
Table 2 · CorePWM Device Utilization and Performance
(one 16-bit DAC channel configuration)
Tiles
Utilization
Family
Performance
(MHz)
Sequential
Combinatorial
Total
Device
Total
IGLOO/e
54
147
201
AGLE600V2
2.0%
59
ProASIC3/E
54
111
165
A3P250
3.0%
85
Fusion
54
111
165
AFS600
1.0%
94
55
209
264
APA200
3.0%
74
Axcelerator
57
53
110
AX250
2.0%
210
RTAX-S
57
53
110
RTAX250S
1.0%
176
SmartFusion
86
140
226
A2F500M3G
2.0%
132
SmartFusion2
53
68
121
M2S150T
0.09%
245
IGLOO2
53
68
121
M2GL150T
0.09%
245
RTG4
69
75
144
RT4G150
0.1%
227
ProASIC
Note:
PLUS
Data in this table were achieved using typical synthesis and layout settings. Top-level parameters/generics were set as
follows: PWM_NUM = 1, APB_DWIDTH = 16; DAC_MODE1 = 1 (DAC mode), FIXED_PRESCALE_EN = 1,
FIXED_PRESCALE = 0, FIXED_PERIOD_EN = 1, FIXED_PERIOD = 1, SHADOW_REG_EN1 = 1.
Table 3 · CorePWM Device Utilization and Performance
(one 8-bit general purpose PWM channel configuration)
Tiles
Utilization
Family
Sequential
Combinatorial
Total
Device
Total
IGLOO/e
15
55
70
AGLE600V2
1.0%
82
ProASIC3/E
15
55
70
A3P250
1.0%
130
Note:
6
Performance
(MHz)
Data in this table were achieved using typical synthesis and layout settings. Top-level parameters/generics were set as follows:
PWM_NUM = 1, APB_DWIDTH = 8; DAC_MODE1 = 0 (general purpose PWM mode), FIXED_PRESCALE_EN = 1,
FIXED_PRESCALE = 0, FIXED_PERIOD_EN = 1, FIXED_PERIOD = 8, FIXED_PWM_POS_EN1 = 1,
FIXED_PWM_POSEDGE1 = 0, FIXED_PWM_NEG_EN1 = 0, FIXED_PWM_NEGEDGE1 = 0,
SHADOW_REG_EN1 = 0
Revision 7
CorePWM v4.3
Utilization and Performance
Table 3 · CorePWM Device Utilization and Performance
(one 8-bit general purpose PWM channel configuration) (continued)
Fusion
15
55
70
AFS600
1.0%
144
ProASIC
15
58
73
APA300
1.0%
141
Axcelerator
16
40
56
AX250
1.0%
181
RTAX-S
16
40
56
RTAX250S
1.0%
187
SmartFusion
15
60
75
A2F500M3G
0.65%
211
SmartFusion2
23
45
68
M2S150T
0.05%
319
IGLOO2
23
45
68
M2GL150T
0.05%
319
RTG4
21
58
79
RT4G150
0.05%
238
PLUS
Note:
Data in this table were achieved using typical synthesis and layout settings. Top-level parameters/generics were set as follows:
PWM_NUM = 1, APB_DWIDTH = 8; DAC_MODE1 = 0 (general purpose PWM mode), FIXED_PRESCALE_EN = 1,
FIXED_PRESCALE = 0, FIXED_PERIOD_EN = 1, FIXED_PERIOD = 8, FIXED_PWM_POS_EN1 = 1,
FIXED_PWM_POSEDGE1 = 0, FIXED_PWM_NEG_EN1 = 0, FIXED_PWM_NEGEDGE1 = 0,
SHADOW_REG_EN1 = 0
Table 4 · CorePWM Device Utilization and Performance
(one 16-bit general purpose PWM channel configuration)
Tiles
Utilization
Family
Performance
(MHz)
Sequential
Combinatorial
Total
Device
Total
IGLOO/e
91
272
363
AGLE600V2
3.0%
46
ProASIC3/E
91
275
366
A3P250
6.0%
72
Fusion
91
275
366
AFS600
3.0%
79
ProASICPLUS
127
482
609
APA300
6.0%
59
Axcelerator
93
145
238
AX250
6.0%
110
RTAX-S
93
145
238
RTAX250S
6.0%
88
SmartFusion
90
324
414
A2F500M3G
3.6%
110
SmartFusion2
100
150
350
M2S150T
0.17%
170
IGLOO2
100
150
350
M2GL150T
0.17%
170
RTG4
134
166
300
RT4G150
0.2%
182
Note:
Data in this table were achieved using typical synthesis and layout settings. Top-level parameters/generics were set as follows:
PWM_NUM = 1, APB_DWIDTH = 16; DAC_MODE1 = 0 (General Purpose PWM mode); SHADOW_REG_EN1 = 1,
FIXED_PRESCALE_EN = 1, FIXED_PRESCALE = 64.
Revision 7
7
Introduction
CorePWM v4.3
Table 5 · CorePWM Device Utilization and Performance (8-bit multiple-output configuration example: 3 DAC mode
outputs without shadow update register)
Family
Tiles
Utilization
Sequential
Combinatorial
Total
Device
Total
Performance
(MHz)
IGLOO/e
58
208
266
AGLE600V2
2.0%
76
ProASIC3/E
58
150
208
A3P250
3.0%
101
Fusion
58
150
208
AFS600
2.0%
109
ProASICPLUS
58
280
338
APA300
4.0%
101
Axcelerator
58
66
124
AX250
2.0%
250
RTAX-S
58
66
124
RTAX250S
2.0%
217
SmartFusion
66
159
225
A2F500M3G
2.0%
157
SmartFusion2
66
72
138
M2S150T
0.1%
467
IGLOO2
66
72
138
M2GL150T
0.1%
467
RTG4
66
77
143
RT4G150
0.09%
300
Note:
Data in this table were achieved using typical synthesis and layout settings. Top-level parameters/generics were set as
follows: PWM_NUM = 3, APB_DWIDTH = 8; DAC_MODE1, DAC_MODE2, and DAC_MODE3 = 1 (DAC
Mode) FIXED_PERIOD_EN = 1, FIXED_PERIOD = 1, FIXED_PRESCALE_EN = 1,
FIXED_PRESCALE = 0, SHADOW_REG_EN1 = 0, SHADOW_REG_EN2 = 0, SHADOW_REG_EN3 = 0.
Table 6 · CorePWM Device Utilization and Performance (12-bit multiple-output configuration example: 3 DAC mode
outputs, 3 general purpose PWM mode outputs)
Tiles
Utilization
Family
Sequential
Combinatorial
Total
Device
Total
IGLOO/e
212
723
935
AGLE600V2
7.0%
45
ProASIC3/E
212
694
906
A3P250
15.0%
74
Fusion
212
694
906
AFS600
7.0%
82
ProASIC
229
1054
1,283
APA300
16.0%
67
Axcelerator
216
307
523
AX250
12.0%
103
RTAX-S
216
307
523
RTAX250S
12.0%
87
SmartFusion
148
396
552
A2F500M3G
4.8%
132
PLUS
Note:
8
Performance
(MHz)
Data in this table were achieved using typical synthesis and layout settings. Top-level parameters/generics were set as
follows: PWM_NUM = 6, APB_DWIDTH = 16; DAC_MODE1, DAC_MODE2, and DAC_MODE3 = 1 (DAC
mode), DAC_MODE4, DAC_MODE5, and DAC_MODE6 = 0 (general purpose PWM mode),
FIXED_PRESCALE_EN = 1, FIXED_PRESCALE = 8, SHADOW_REG_EN1 = 0,
SHADOW_REG_EN2 = 0, SHADOW_REG_EN3 = 0, SHADOW_REG_EN3 = 0, SHADOW_REG_EN4 = 0,
SHADOW_REG_EN5 = 0, SHADOW_REG_EN6 = 0,.
Revision 7
CorePWM v4.3
Utilization and Performance
Table 6 · CorePWM Device Utilization and Performance (12-bit multiple-output configuration example: 3 DAC mode
outputs, 3 general purpose PWM mode outputs) (continued)
Tiles
Utilization
Family
Performance
(MHz)
Sequential
Combinatorial
Total
Device
Total
SmartFusion2
176
274
450
M2S150T
0.31%
215
IGLOO2
176
274
450
M2GL150T
0.31%
215
RTG4
254
339
593
RT4G150
0.39%
114
Note:
Data in this table were achieved using typical synthesis and layout settings. Top-level parameters/generics were set as
follows: PWM_NUM = 6, APB_DWIDTH = 16; DAC_MODE1, DAC_MODE2, and DAC_MODE3 = 1 (DAC
mode), DAC_MODE4, DAC_MODE5, and DAC_MODE6 = 0 (general purpose PWM mode),
FIXED_PRESCALE_EN = 1, FIXED_PRESCALE = 8, SHADOW_REG_EN1 = 0,
SHADOW_REG_EN2 = 0, SHADOW_REG_EN3 = 0, SHADOW_REG_EN3 = 0, SHADOW_REG_EN4 = 0,
SHADOW_REG_EN5 = 0, SHADOW_REG_EN6 = 0,.
Table 7 · CorePWM Device Utilization and Performance (one 16-bit general purpose PWM channel and one TACH input
configuration)
Tiles
Utilization
Family
Performance
(MHz)
Sequential
Combinatorial
Total
Device
Total
IGLOO/e
314
768
082
AGLE600V2
8.0%
47
ProASIC3/E
314
768
082
A3P250
18.0%
75
Fusion
314
768
1,082
AF600
8.0%
83
ProASIC
328
1,043
1,371
APA300
17.0%
70
Axcelerator
319
483
802
AX250
19.0%
103
RTAX-S
319
483
802
RTAX250S
19.0%
87
SmartFusion
197
613
810
A2F500M3G
7.1%
115
SmartFusion2
252
416
668
M2S150T
0.45%
137
IGLOO2
252
416
668
M2GL150T
0.45%
137
RTG4
329
436
765
RT4G150
0.51%
164
PLUS
Note:
Data in this table were achieved using typical synthesis and layout settings. Top-level parameters/generics were set as
follows: CONFIG_MODE = 1, PWM_NUM=3, TACH_NUM=3,APB_DWIDTH=16; DAC_MODE1=0
(General Purpose PWM mode), FIXED_PRESCALE_EN=1, FIXED_PRESCALE=8,
FIXED_PERIOD_EN=0, FIXED_PWM_POS_EN1=1, FIXED_PWM_POSEDGE1=0,
FIXED_PWM_NEG_EN1=0, FIXED_PWM_NEGEDGE1=0, SHADOW_REG_EN1=0,
FIXED_PWM_POS_EN2=1, FIXED_PWM_POSEDGE2=0, FIXED_PWM_NEG_EN2=0,
FIXED_PWM_NEGEDGE2=0, SHADOW_REG_EN2=0, FIXED_PWM_POS_EN3=1,
FIXED_PWM_POSEDGE3=0, FIXED_PWM_NEG_EN3=0, FIXED_PWM_NEGEDGE3=0,
SHADOW_REG_EN3=0
Revision 7
9
Introduction
CorePWM v4.3
Table 8 · CorePWM Device Utilization and Performance (one TACH input configuration with 16-bit APB data width)
Tiles
Utilization
Family
Sequential
Combinatorial
Total
Device
Total
IGLOO/e
207
389
596
AGLE600V2
4.0%
52
ProASIC3/E
207
383
590
A3P250
10.0%
89
Fusion
207
383
590
AF600
4.0%
98
ProASIC
207
506
713
APA300
9.0%
92
Axcelerator
209
269
478
AX250
5%
114
RTAX-S
209
269
478
RTAX250S
11%
101
SmartFusion
204
469
673
A2F500M3G
5.8%
132
SmartFusion2
156
248
404
M2S150T
0.28
210
IGLOO2
156
248
404
M2GL150T
0.28
210
RTG4
204
243
447
RT4G150
0.29%
172
PLUS
Note:
10
Performance
(MHz)
Data in this table were achieved using typical synthesis and layout settings. Top-level parameters/generics were set as
follows: CONFIG_MODE = 2, TACH_NUM=3, APB_DWIDTH=16.
Revision 7
1
Design Description
Functional Blocks
The CorePWM (pulse width modulation) macro generates up to 16 general purpose PWM signals, as shown in
Figure 1-1. CorePWM includes a Register Interface block, Timebase Generation block, TACK INF block, and PWM
Generation block.
CorePWM
PWM[PWM_NUM:1]
Timebase
Generation
APB I/F
TACHIN[TACH_NUM-1:0]
PWM
Waveform
Generation
Register Interface
TACH INF
TACHINT
Figure 1-1 · CorePWM Block Diagram
The Register Interface block connects to an APB bus for PWM register configuration and updating. Descriptions for all
registers are given in Table 1-3 on page 16. A Shadow Register may be used so that PWM waveform updates occur only
at the beginning of a PWM period. A shadow register holds all values and writes them when the SYNC_UPDATE
register is set to 1. In other words, for all channel synchronous updates, write a "1" to the SYNC_UPDATE register
after writing to all the channel registers.
The Timebase Generation block accepts PRESCALE and PERIOD register values and produces a PERIOD count.
The number of system clocks between PERIOD counts is equal to the PRESCALE value.
The PWM Waveform Generation block has two modes:
General Purpose PWM mode takes input Period_cnt counter values and compares them with the register values for
all the PWM positive and negative edge locations. When a comparison is met, each respective output waveform is set
to the correct high/low/toggle value. An example General Purpose PWM waveform configuration is demonstrated in
Figure 1-3 on page 21. The example explains the relationship between the Prescale and Period register values, and how
to configure the PWM waveforms with a given Prescale/Period timebase.
Low Ripple DAC mode is intended to drive a low-pass filter, typically a single-pole RC filter. Narrow pulses of
constant width are spread evenly over time such that the average voltage is equal to the duty cycle. The output of the
filter is then a DC voltage directly proportional to the duty cycle. This type of pulse train allows for much lower ripple
at the output of the filter, and benefits from either higher bandwidth and/or smaller R and C values.
In the Tach interface module, the width of the decrementing counter is configured to 16 bits. The Tach interface module
is used to measure the period of the TACHIN[x] signal by measuring between two successive positive or negative edges
of TACHIN[x]. The measured value will be stored in the corresponding input’s TACHPULSEDUR register. The
measured value will be read by the firmware through the APB interface. The access to the control and status registers of
the Tach interface module is through the APB interface. The stored value in TACHPULSEDUR will correspond to the
count for half of a revolution of a four pole fan. When determining the speed for other than four pole fans, the algorithm
Revision 7
11
CorePWM v4.3
that converts the counter value to RPMs must be adjusted by the firmware. TACH INF supports 16- and 32-bit APB
interface, but it does not support 8-bit interfaces.
To accurately measure the speed of 3-wire fans, you must turn on the fan periodically and long enough to get a complete
tach measurement, often referred to as PWM pulse stretching. The PWM_STRETCH register allows you to set the
desired PWMx signals to the level specified by PWM_STRETCH_VALUE. The following algorithm can be used to
measure the speed of 3-wire fans. This algorithm assumes that the TACHMODEy bit is set to ‘1’ (one-shot mode):
• Software enables pulse stretching by writing a ‘1’ to PWM_STRETCHx, which forces PWMx to
PWM_STRETCH_VALUEx. This requirement is not enforced by the hardware.
• Software can add a delay to ensure the fan tachometer circuitry is operational before enabling fan speed measurement.
• Software clears the TACHSTATUSy bit, enabling a one-time Tach measurement on the input signal TACHINy
corresponding to one of the fans controlled by PWMx
• Software receives an interrupt and verifies that the Tach measurement for TACHINy has been completed (via
TACHSTATUSy bit)
• Software disables pulse stretching by writing a ‘0’ to PWM_STRETCHx.
I/O Signals
The port signals for the CorePWM macro are defined in Table 1-1 on page 13 and illustrated in Figure 1-2. All signals
are either Input (input only) or Output (output only).
CorePWM
PRESETN
PCLK
PSEL
PWM[PWM_NUM:1]
PENABLE
PWRITE
PADDR[7:0]
PWDATA[APB_DWIDTH-1:0]
PREADY
PSLEVRR
PRDATA[APB_DWIDTH-1:0]
TACHIN[TACH_NUM-1:0]
PWM_CLK
Figure 1-2 · CorePWM I/O Signal Diagram
12
Revision 7
TACHINT
CorePWM v4.3
I/O Signals
Table 1-1 · CorePWM I/O Signal Descriptions
Name
Type
Description
System Signals
PRESETN
Input
Active low asynchronous reset
PCLK
Input
System clock – all operations and status shall be synchronous to
the rising edge of this clock signal
PSEL
Input
Select line for CorePWM
PENABLE
Input
Read output enable
PWRITE
Input
Write enable
PADDR[7:0]
Input
Register address
PWDATA[APB_DWIDTH-1:0]
Input
Write address/data input
PREADY
Output
Ready signal, tied High
PSLVERR
Output
Transfer error signal, tied Low
PRDATA[APB_DWIDTH-1:0]
Output
Read data output
Output
Pulse width modulation output
Microcontroller Signals
PWM Signals
PWM[PWM_NUM:1]
TACH Signals
TACHIN[TACH_NUM -1:0]
Input
TACHINT
Output
PWM_CLK
Input
Note:
TACH input
Interrupt output for the tachometer. This signal indicates a
TACHSTATUS register bit has been set to one.
The polarity of this signal is controlled by the
TACHINT_ACT_LEVEL configurable option.
PWM clock - This clock used if the required frequency for PWM
generation is greater/less than PCLK. This signal is only enabled
when SEPERATE_PWM_CLK = 1
All signals active-High (logic 1) unless otherwise noted.
Revision 7
13
CorePWM v4.3
Verilog/VHDL Parameters
CorePWM has parameters (Verilog) and generics (VHDL) for configuring the RTL code, described in Table 1-2. All
parameters and generics are integer types.
Table 1-2 · CorePWM Parameters/Generics Descriptions
Name
Description
Selects the Target family. Must be set to match the supported FPGA family:
11 - Axcelerator
12 - RTAX-S
14 - ProASICPLUS
15 - ProASIC3
16 - ProASIC3E
FAMILY
17 - Fusion
18 - SmartFusion
19 - SmartFusion2
20 - IGLOO
21 - IGLOOe
22 - ProASIC3L
24 - IGLOO2
25 - RTG4
When 0, supports PWM only (legacy with dead banding support)
CONFIG_MODE
When 1, supports both PWM and TACH
When 2, supports TACH only
PWM_NUM
Number of PWM outputs from 1 to 16. This parameter is used only when CONFIG_MODE is set to
0 or 1.
APB_DWIDTH
PWM resolution and APB bus width from 8 to 32. This parameter must be set to either 16 or 32 when
CONFIG_MODE is either 1 or 2.
FIXED_PRESCALE_EN
Fixed Prescale Enable. FIXED_PRESCALE_EN hardwires the register, disallowing APB write-access,
and reducing tile count. This parameter is used only when CONFIG_MODE set to 0 or 1.
FIXED_PRESCALE
Hardwired PRESCALE[APB_DWIDTH -1:0] register value. This parameter is used only when
CONFIG_MODE set to 0 or 1.
FIXED_PERIOD_EN
Fixed Period Enable. FIXED_PERIOD_EN hardwires the register, disallowing APB write-access, and
reducing tile count. This parameter is used only when CONFIG_MODE set to 0 or 1.
FIXED_PERIOD
Hardwired PERIOD[APB_DWIDTH -1:0] register value. This parameter is used only when
CONFIG_MODE set to 0 or 1.
SHADOW_REG_ENx
Shadow Register Enable. Synchronizes all register modification changes to the beginning of the PWM
cycle; that is, when PERIOD Count = 0. This parameter is used only when CONFIG_MODE set to 0
or 1.
DAC mode. 1 = Low ripple DAC mode; 0 = General purpose PWM mode.
DAC_MODEx
Note:
x refers to each channel, from 1 to 16.
This parameter is used only when CONFIG_MODE set to 0 or 1.
14
Revision 7
CorePWM v4.3
I/O Signals
Table 1-2 · CorePWM Parameters/Generics Descriptions (continued)
Fixed per channel Positive Edge Enable.
Note:
FIXED_PWM_POS_ENx
x refers to each channel, from 1 to 16. FIXED_PWM_POS_ENx hardwires the register, disallowing
APB write-access, and reducing tile count.
In a typical PWM application, either the FIXED_PWM_POS_ENx or the
FIXED_PWM_NEG_ENx could be set if one of those edges do not need to be software controlled
with APB write-accesses. Fixing both edges would result in static output.
This parameter is used only when CONFIG_MODE set to 0 or 1.
Hardwired POSEDGE[APB_DWIDTH -1:0] register value.
FIXED_PWM_POSEDGEx
Note:
x refers to each channel, from 1 to 16.
This parameter is used only when CONFIG_MODE set to 0 or 1.
Fixed per channel Negative Edge Enable.
Note:
FIXED_PWM_NEG_ENx
FIXED_DAC_OUT_ENx
x refers to each channel, from 1 to 16. FIXED_PWM_NEG_ENx hardwires the register, disallowing
APB write-access, and reducing tile count.
In a typical PWM application, either the FIXED_PWM_NEG_ENx or the
FIXED_PWM_POS_ENx could be set if one of those edges do not need to be software-controlled
with APB write-accesses. Fixing both edges would result in static output.
For DAC applications, the FIXED_PWM_POS_ENx value is unconnected while the
FIXED_DAC_OUT_ENx value would typically be disabled, as using it would result in static output.
This parameter is used only when CONFIG_MODE set to 0 or 1.
FIXED_PWM_NEGEDGEx
FIXED_DAC_LEVELOUTx
Hardwired NEGEDGE[APB_DWIDTH -1:0] register value. When in DAC Mode, this parameter
also fixes DACx_LEVELOUT, which is typically not fixed in DAC applications, as it would only create
a static duty cycle output. Note: x refers to each channel, from 1 to 16.
This parameter is used only when CONFIG_MODE set to 0 or 1.
Defines PWMx level when PWM_STRETCHx is set to 1.
PWM_STRETCH_VALUEx
When 0, PWMx is set to 0 if PWM_STRETCHx is set to 1.
When 1, PWMx is set to 1 if PWM_STRETCHx is set to 1 (default).
This parameter is used only when CONFIG_MODE set to 1.
TACH_NUM
Number of Tachometer inputs from 1 to 16. This parameter is used only when CONFIG_MODE set
to 1 or 2.
TACH_EDGEy
Fixed per Tachometer input edge select. Selects the edge used to capture the counter value for the
TACH[x] input signals. 0, capture counter value on falling edge of TACH[x] (default); 1, capture
counter value on rising edge of TACH[x]. This parameter is used only when CONFIG_MODE set to
1 or 2.
TACHINT_ACT_LEVEL
Selects active Low or active High TACHINT interrupt: 0, active Low interrupt (default); 1, active High
interrupt. This parameter is used only when CONFIG_MODE set to 1 or 2.
SEPERATE_PWM_CLK
Separate PWM Clock - If the clock frequency required for PWM generation is greater/less than PCLK
this signal should be enabled. When enabled (1) input PWM_CLK can be used for PWM_CLK
generation. If PCLK is at the desired clock frequency this parameter/generic should be disabled (0).
Note:
APB_DWIDTH must always be greater than or equal to PWM_NUM for all APB read and write operations to be successful.
Revision 7
15
CorePWM v4.3
Register Map
All registers are based on APB width parameter selection; default is 8 bits.
Table 1-3 · CorePWM Register Definitions
Register Name
Paddr[7:0]
PRESCALE
0x00
PERIOD
0x04
PWM_ENABLE_0_7
PWM_ENABLE_8_15
0x08
0x0C
SYNC_UPDATE
0xE4
PWM1_POSEDGE
0x10
PWM1_NEGEDGE
DAC1_LEVELOUT
0x14
PWM2_POSEDGE
0x18
PWM2_NEGEDGE
DAC2_LEVELOUT
0x1C
PWM3_POSEDGE
0x20
PWM3_NEGEDGE
DAC3_LEVELOUT
0x24
PWM4_POSEDGE
0x28
PWM4_NEGEDGE
DAC4_LEVELOUT
0x2C
PWM5_POSEDGE
0x30
PWM5_NEGEDGE
DAC5_LEVELOUT
0x34
16
Description
PWM MODE: The system clock cycle is multiplied with the PRESCALE
value resulting in the minimum PERIOD count timebase.
DAC MODE: The Prescale and Period Registers could be used in
conjunction with the shadow register to synchronize DAC LEVELOUT.
PWM MODE: The PRESCALE value is multiplied with the PERIOD
value yielding the PWM waveform cycle.
Bitwise channel enables for PWM/DAC channels 1 through 8.
Bitwise channel enables for PWM/DAC channels 9 through 16.
SYNC_UPDATE: When this bit is set to "1" and SHADOW_REG_EN
is selected, all POSEDGE and NEGEDGE registers are updated
synchronously. Synchronous updates to the PWM waveform occur only
when SHADOW_REG_EN is asserted and SYNC_UPDATE is set to
“1”.
When this bit is set to "0", all the POSEDGE and NEGEDGE registers
are updated asynchronously.
PWM MODE: Sets the positive edge of the output with respect to the
PERIOD resolution. When APB writes to this register, all the channels are
updated.
PWM MODE: Sets the negative edge of the output with respect to the
PERIOD resolution.
DAC MODE: Sets the desired output level, from 0-100%.
PWM MODE: Sets the positive edge of the output with respect to the
PERIOD resolution.
PWM MODE: Sets the negative edge of the output with respect to the
PERIOD resolution.
DAC MODE: Sets the desired output level, from 0-100%.
PWM MODE: Sets the positive edge of the output with respect to the
PERIOD resolution.
PWM MODE: Sets the negative edge of the output with respect to the
PERIOD resolution.
DAC MODE: Sets the desired output level, from 0-100%.
PWM MODE: Sets the positive edge of the output with respect to the
PERIOD resolution.
PWM MODE: Sets the negative edge of the output with respect to the
PERIOD resolution.
DAC MODE: Sets the desired output level, from 0-100%.
PWM MODE: Sets the positive edge of the output with respect to the
PERIOD resolution.
PWM MODE: Sets the negative edge of the output with respect to the
PERIOD resolution.
DAC MODE: Sets the desired output level, from 0-100%.
Revision 7
Type
Default
R/W
0x08
R/W
0x08
R/W
R/W
0x00
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
CorePWM v4.3
Register Map
Table 1-3 · CorePWM Register Definitions (continued)
Register Name
Paddr[7:0]
PWM6_POSEDGE
0x38
PWM6_NEGEDGE
DAC6_LEVELOUT
0x3C
PWM7_POSEDGE
0x40
PWM7_NEGEDGE
DAC7_LEVELOUT
0x44
PWM8_POSEDGE
0x48
PWM8_NEGEDGE
DAC8_LEVELOUT
0x4C
PWM9_POSEDGE
0x50
PWM9_NEGEDGE
DAC9_LEVELOUT
0x54
PWM10_POSEDGE
0x58
PWM10_NEGEDGE
DAC10_LEVELOUT
0x5C
PWM11_POSEDGE
0x60
PWM11_NEGEDGE
DAC11_LEVELOUT
0x64
PWM12_POSEDGE
0x68
PWM12_NEGEDGE
DAC12_LEVELOUT
0x6C
PWM13_POSEDGE
0x70
PWM13_NEGEDGE
DAC13_LEVELOUT
0x74
PWM14_POSEDGE
0x78
Description
PWM MODE: Sets the positive edge of the output with respect to the
PERIOD resolution.
PWM MODE: Sets the negative edge of the output with respect to the
PERIOD resolution.
DAC MODE: Sets the desired output level, from 0-100%.
PWM MODE: Sets the positive edge of the output with respect to the
PERIOD resolution.
PWM MODE: Sets the negative edge of the output with respect to the
PERIOD resolution.
DAC MODE: Sets the desired output level, from 0-100%.
PWM MODE: Sets the positive edge of the output with respect to the
PERIOD resolution.
PWM MODE: Sets the negative edge of the output with respect to the
PERIOD resolution.
DAC MODE: Sets the desired output level, from 0-100%.
PWM MODE: Sets the positive edge of the output with respect to the
PERIOD resolution.
PWM MODE: Sets the negative edge of the output with respect to the
PERIOD resolution.
DAC MODE: Sets the desired output level, from 0-100%.
PWM MODE: Sets the positive edge of the output with respect to the
PERIOD resolution.
PWM MODE: Sets the negative edge of the output with respect to the
PERIOD resolution.
DAC MODE: Sets the desired output level, from 0-100%.
PWM MODE: Sets the positive edge of the output with respect to the
PERIOD resolution.
PWM MODE: Sets the negative edge of the output with respect to the
PERIOD resolution.
DAC MODE: Sets the desired output level, from 0-100%.
PWM MODE: Sets the positive edge of the output with respect to the
PERIOD resolution.
PWM MODE: Sets the negative edge of the output with respect to the
PERIOD resolution.
DAC MODE: Sets the desired output level, from 0-100%.
PWM MODE: Sets the positive edge of the output with respect to the
PERIOD resolution.
PWM MODE: Sets the negative edge of the output with respect to the
PERIOD resolution.
DAC MODE: Sets the desired output level, from 0-100%.
PWM MODE: Sets the positive edge of the output with respect to the
PERIOD resolution.
Revision 7
Type
Default
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
17
CorePWM v4.3
Table 1-3 · CorePWM Register Definitions (continued)
Register Name
Paddr[7:0]
PWM14_NEGEDGE
DAC14_LEVELOUT
0x7C
PWM15_POSEDGE
0x80
PWM15_NEGEDGE
DAC15_LEVELOUT
0x84
PWM16_POSEDGE
0x88
PWM16_NEGEDGE
DAC16_LEVELOUT
PWM_STRETCH
Description
PWM MODE: Sets the negative edge of the output with respect to the
PERIOD resolution.
DAC MODE: Sets the desired output level, from 0-100%.
PWM MODE: Sets the positive edge of the output with respect to the
PERIOD resolution.
PWM MODE: Sets the negative edge of the output with respect to the
PERIOD resolution.
Type
Default
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
0x8C
DAC MODE: Sets the desired output level, from 0-100%.
PWM MODE: Sets the positive edge of the output with respect to the
PERIOD resolution.
PWM MODE: Sets the negative edge of the output with respect to the
PERIOD resolution.
R/W
0x00
0x90
DAC MODE: Sets the desired output level, from 0-100%.
When 0, the state of PWMx is determined by PWMx_POSEDGE/
NEGEDGE register settings.
R/W
0x0000
R/W
0x0
R/
W1C
0x0000
R/W
0x0000
R/W
0x0000
When 1, PWMx is set to PWM_STRETCH_VALUEx.
Clock prescale setting. Determines effective clock rate for the counter
based on PCLK:
0000 = divide by 1 (default)
0001 = divide by 2
0010 = divide by 4
0011 = divide by 8
0100 = divide by 16
TACHPRESCALE
0x94
0101 = divide by 32
0110 = divide by 64
0111 = divide by 128
1000 = divide by 256
1001 = divide by 512
1010 = divide by 1,024
1011 = divide by 2,048
TACHSTATUS
0x98
TACHIRQMASK
0x9C
TACHMODE
0xA0
Others = divide by 2,048
TACH status register which contains one bit per TACH input, indicating
whether the respective TACHPULSEDUR register has been updated at
least once since the bit was cleared. The bits in this register gets cleared by
writing “1”, “0” does not have any effect.
TACH interrupt mask register with one bit per tachometer signal,
indicating whether CorePWM needs to assert an interrupt if the respective
bit in TACHSTATUS register is asserted.
TACH Mode. Sets the measurement mode used for each TACH input.
When 0: TACH input is continuously measured and stored in the
respective TACHPULSEDUR register.
When 1: A one-time measurement is performed only if the respective bit
in TACHSTATUS register is cleared.
18
Revision 7
CorePWM v4.3
Register Map
Table 1-3 · CorePWM Register Definitions (continued)
Register Name
Paddr[7:0]
TACHPULSEDUR_0
0xA4
TACHPULSEDUR_1
0xA8
TACHPULSEDUR_2
0xAC
TACHPULSEDUR_3
0xB0
TACHPULSEDUR_4
0xB4
TACHPULSEDUR_5
0xB8
TACHPULSEDUR_6
0xBC
TACHPULSEDUR_7
0xC0
TACHPULSEDUR_8
0xC4
TACHPULSEDUR_9
0xC8
TACHPULSEDUR_10
0xCC
TACHPULSEDUR_11
0xD0
Description
Stores the number of timer ticks between two successive positive (or
negative) edges from the TACHIN[0]. The edge to be used is configurable.
If the number of timer ticks exceeds the maximum register value, the value
of 0 shall be stored instead.
Stores the number of timer ticks between two successive positive (or
negative) edges from the TACHIN[1]. The edge to be used is configurable.
If the number of timer ticks exceeds the maximum register value, the value
of 0 shall be stored instead.
Stores the number of timer ticks between two successive positive (or
negative) edges from the TACHIN[2]. The edge to be used is configurable.
If the number of timer ticks exceeds the maximum register value, the value
of 0 shall be stored instead.
Stores the number of timer ticks between two successive positive (or
negative) edges from the TACHIN[3]. The edge to be used is configurable.
If the number of timer ticks exceeds the maximum register value, the value
of 0 shall be stored instead.
Stores the number of timer ticks between two successive positive (or
negative) edges from the TACHIN[4]. The edge to be used is configurable.
If the number of timer ticks exceeds the maximum register value, the value
of 0 shall be stored instead.
Stores the number of timer ticks between two successive positive (or
negative) edges from the TACHIN[5]. The edge to be used is
configurable.If the number of timer ticks exceeds the maximum register
value, the value of 0 shall be stored instead.
Stores the number of timer ticks between two successive positive (or
negative) edges from the TACHIN[6]. The edge to be used is configurable.
If the number of timer ticks exceeds the maximum register value, the value
of 0 shall be stored instead.
Stores the number of timer ticks between two successive positive (or
negative) edges from the TACHIN[7]. The edge to be used is configurable.
If the number of timer ticks exceeds the maximum register value, the value
of 0 shall be stored instead.
Stores the number of timer ticks between two successive positive (or
negative) edges from the TACHIN[8]. The edge to be used is configurable.
If the number of timer ticks exceeds the maximum register value, the value
of 0 shall be stored instead.
Stores the number of timer ticks between two successive positive (or
negative) edges from the TACHIN[9]. The edge to be used is configurable.
If the number of timer ticks exceeds the maximum register value, the value
of 0 shall be stored instead.
Stores the number of timer ticks between two successive positive (or
negative) edges from the TACHIN[10]. The edge to be used is
configurable. If the number of timer ticks exceeds the maximum register
value, the value of 0 shall be stored instead.
Stores the number of timer ticks between two successive positive (or
negative) edges from the TACHIN[11]. The edge to be used is
configurable. If the number of timer ticks exceeds the maximum register
value, the value of 0 shall be stored instead.
Revision 7
Type
Default
R
0x0000
R
0x0000
R
0x0000
R
0x0000
R
0x0000
R
0x0000
R
0x0000
R
0x0000
R
0x0000
R
0x0000
R
0x0000
R
0x0000
19
CorePWM v4.3
Table 1-3 · CorePWM Register Definitions (continued)
Register Name
Paddr[7:0]
TACHPULSEDUR_12
0xD4
TACHPULSEDUR_13
0xD8
TACHPULSEDUR_14
0xDC
TACHPULSEDUR_15
0xE0
Description
Stores the number of timer ticks between two successive positive (or
negative) edges from the TACHIN[12]. The edge to be used is
configurable. If the number of timer ticks exceeds the maximum register
value, the value of 0 shall be stored instead.
Stores the number of timer ticks between two successive positive (or
negative) edges from the TACHIN[13]. The edge to be used is
configurable. If the number of timer ticks exceeds the maximum register
value, the value of 0 shall be stored instead.
Stores the number of timer ticks between two successive positive (or
negative) edges from the TACHIN[14]. The edge to be used is
configurable. If the number of timer ticks exceeds the maximum register
value, the value of 0 shall be stored instead.
Stores the number of timer ticks between two successive positive (or
negative) edges from the TACHIN[15]. The edge to be used is
configurable. If the number of timer ticks exceeds the maximum register
value, the value of 0 shall be stored instead.
Type
Default
R
0x0000
R
0x0000
R
0x0000
R
0x0000
Notes:
1. 0d = decimal; 0x = hexidecimal; 0b = binary.
2. If DAC mode for all active channels is configured as "Low ripple DAC mode" (DAC_MODEx = 1) and shadow register are disabled
(SHADOW_REG_ENx = 0) for all active channels register PRESCALE and PERIOD become read only because they are not used in Low ripple
DAC mode.
20
Revision 7
CorePWM v4.3
Configuration Example
Configuration Example
Figure 1-3 demonstrates how several register configurations affect General Purpose and Low Ripple DAC PWM
output waveform generation.
Configuring the following registers using an 8-bit APB resolution will yield the example
PWM waveforms below, based on a 25 MHz system clock = 40 ns system clock period:
Note: 0x = hexadecimal
PWM period granularity = PWM_PG =
clock period × (PRESCALE + 1) =
40 ns × 2 = 80 ns
PWM period = PWM_PG × (PERIOD +1) =
80 ns × 14 = 1.12 µs
Enable PWM signals 1, 2, 3, 4, and 5.
PRESCALE = 0x1
PERIOD = 0x0D
PWM_ENABLE = 0x1F
PWM1_POSEDGE = 0x02
PWM1_NEGEDGE = 0x08
PWM2_POSEDGE = 0x08
PWM2_NEGEDGE = 0x02
PWM3_POSEDGE = 0x00
PWM3_NEGEDGE = 0x01
PWM4_POSEDGE = 0x01
PWM4_NEGEDGE = 0x01
PWM1 and PWM2 duty cycle = 6/14 => 42.8%
PWM3 duty cycle => 7.1%
Toggle PWM4 output
(always 50% duty cycle)
DAC5_LEVELOUT = 0x3F
25% duty cycle DAC mode output,
based on averaging by phase
accumulator circuit
0 1
Prescale value of 1 =
2 system clock periods
PCLK
PWM1
PWM2
PWM3
PWM4
13
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
1
2
3
Period value of 13 with prescale value of 1 =
14 × 2 system clock periods per PWM period
PWM5
Low Ripple DAC mode uses phase accumulator to create an average density duty cycle. if the
shadow register has been configured for this channel, then updates will occur at the beginning
of the period. In either mode, using the shadow register with prescale/period allows for
synchronized updates.
Figure 1-3 · CorePWM Waveform Generation Example
Note: If SEPERATE_PWM_CLK is enabled (1) then replace PCLK with PWM_CLK in above timing diagram.
Revision 7
21
CorePWM v4.3
Figure 1-4 to Figure 1-7 on page 24 demonstrate how to avoid overlapping of the dead banding issue using the register
configurations of channel 1 and channel 2 as a pair. Both channel 1(PWM1) and channel 2(PWM2) are updated after
writing a “1” to the SYNC_UPDATE configuration register to avoid overlapping of dead band space.
APB Write
PWM2_POSEDGE = 0x03
APB Write
PWM1_POSEDGE = 0x01
APB Write
PWM1_POSEDGE = 0x02
APB Write
PWM2_POSEDGE = 0x02
PCLK
PWM1
PWM2
Dead Band Space
Dead Band Space
13
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
1
2
3
Period Value of 13 with Prescale Value of 1
= 14 × 2 system clock periods per PWM period
Figure 1-4 · Dead Band Space Example
Note: If SEPERATE_PWM_CLK is enabled (1) then replace PCLK with PWM_CLK in above timing diagram.
22
Revision 7
CorePWM v4.3
Configuration Example
APB Write
PWM1_NEGEDGE = 0x11
APB Write
PWM1_POSEDGE = 0x03
PCLK
PWM1
13
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
1
2
3
Period value of 13 with prescale value of 1
= 14 × 2 system clock periods per PWM period
Figure 1-5 · Center-Aligned PWM Waveform Example
Note: If SEPERATE_PWM_CLK is enabled (1) then replace PCLK with PWM_CLK in above timing diagram.
APB Write
PWM1_NEGEDGE = 0x06
APB Write
PWM1_POSEDGE = 0x00
PCLK
PWM1
13
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
1
2
3
Period value of 13 with prescale value of 1
= 14 × 2 system clock periods per PWM period
Figure 1-6 · Left-Aligned PWM Waveform Example
Note: If SEPERATE_PWM_CLK is enabled (1) then replace PCLK with PWM_CLK in above timing diagram.
Revision 7
23
CorePWM v4.3
PWM_STRETCH_VALUE = 0
PWM_STRETCH_VALUE = 1
Change the value
on PWM[0] based on
PWM_STRETCH[0]
Start TACH
Measurement
Change the value
on PWM[0] based on
PWM_STRETCH[0]
Read Tach
Count Value
PWM[0]
Period Count
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
PWM_STRETCH[0]
TACHIN[0]
Tach Measurement
TACHSTATUS[0]
Tach Count
1 2 3 4 5 6 7 8 9 10 11
0
12
TACHINT
Figure 1-7 · Tach Measurement
APB Interface Timing
Figure 1-8 and Figure 1-9 depict typical write cycle and read cycle timing relationships relative to the system clock.
PCLK
PSEL
PWRITE
PENABLE
PADDR
PWDATA
Register Address
Register Write Data
Figure 1-8 · Data Write Cycle
PCLK
PSEL
PWRITE
PENABLE
PADDR
PRDATA
Register Address
Register Read Data
Figure 1-9 · Data Read Cycle
24
Revision 7
2
Tool Flows
CorePWM is license free.
RTL
Complete RTL source code is provided for the core and testbenches.
SmartDesign
The core can be configured using the configuration GUI within SmartDesign. An example of configuring one channel
for PWM mode operation is shown in Figure 2-1 on page 26. Note the following in this example:
• Number of PWM Channels is 1.
• APB bit width and corresponding PWM resolution is 8 bits.
• The Prescale value (the number of clock ticks between Period ticks) is selected to be Fixed at 64, reducing the tile count,
as no registers are used.
• The Period value is not Fixed and hence software-controlled.
• The Shadow Update Register is enabled, allowing for synchronized PWM updates at the beginning of the Period
count.
• The Positive edge of the PWM is not Fixed and hence software-controlled.
• The Negative edge of the PWM waveform is Fixed at Period count 0.
• The User Testbench is selected to be generated.
Revision 7
25
CorePWM v4.3
Figure 2-1 · CorePWM Configuration within SmartDesign – PWM Mode
An example of configuring one Channel for low ripple DAC operation is shown in Figure 2-2 on page 27. Note the
following in this example:
• Number of PWM Channels is 1.
• APB bit width and corresponding PWM/DAC resolution is 8 bits.
• The Prescale and Period Values can be used in conjunction with the Shadow Update Register to update
DAC1_LEVELOUT values at a given period. For example, 3 DACs could be updated simultaneously based on the
Prescale and Period values if the Shadow Update Register is enabled. In this example, the DAC1_LEVELOUT value
is updated whenever the APB bus updates the DAC1_LEVELOUT register.
• The DAC LevelOut value is not Fixed and hence software-controlled. Note the DAC1_LEVELOUT value is
synonymous with a Duty Cycle value; i.e., an 8-bit DAC1_LEVELOUT hex value of 7F is equal to an average duty
cycle of 50% and will yield half of the full analog value after RC filtering.
• Note the “Fixed PWM PosEdge” value does not apply to DAC mode channel.
• The User Testbench is selected to be generated.
26
Revision 7
CorePWM v4.3
Importing into Libero IDE
Figure 2-2 · CorePWM Configuration within SmartDesign – DAC Mode
Importing into Libero IDE
CorePWM is available for download to the SmartDesign IP Catalog, via the Libero IDE web repository. For
information on using SmartDesign to instantiate, configure, connect, and generate cores, refer to the Libero IDE online
help.
Simulation Flows
To run simulations, select the user testbench within the SmartDesign CorePWM configuration GUI, right-click, and
select Generate Design. When SmartDesign generates the design files, it will install the appropriate testbench files. Set
the design root to the CorePWM instantiation in the Libero IDE design hierarchy pane, and click the Simulation icon
in the Libero IDE Design Flow window. This will invoke ModelSim® and automatically run simulation.
Revision 7
27
CorePWM v4.3
A simplified block diagram of the User Testbench is shown in Figure 2-3. The user testbench instantiates the
CorePWM macro and provides a Register Write Stimulus process, Register Read process, and a PWM output duty
cycle check process.
User Testbench
Register Write
Stimulus
CorePWM
PWM Output
Checker
Register Read
Checker
Figure 2-3 · CorePWM Verification Testbench
Synthesis in the Libero IDE
Having set the design route appropriately, click the Synthesis icon in Libero IDE. The Synthesis window appears,
displaying the Synplicity® project. Set Synplicity to use the Verilog 2001 standard if Verilog is being used. To run
Synthesis, select the Run icon.
Place-and-Route in Libero IDE
Having set the design route appropriately and run Synthesis, click on the Layout icon in Libero IDE to invoke
Designer. CorePWM requires no special place-and-route settings.
28
Revision 7
3
Example Applications
For General Purpose PWM applications, a duty cycle calculator is available online to assist in calculating the PWM
POSEDGE and NEGEDGE register values, given a requested duty cycle. This is provided on the Microsemi website as
a downloadable Excel spreadsheet:
http://www.microsemi.com/documents/duty_cycle_calc.zip
For DAC applications, a low ripple DAC calculator is also available online:
http://www.microsemi.com/documents/low_ripple_dac_calc.zip
General Purpose PWM Application – Temperature Monitor
A typical temperature monitor application using CorePWM is shown in Figure 3-1. In this example, fan speed is
controlled by fluctuations in the NTC thermistor’s resistive value. As shown, changes in the input voltage to the voltage
monitor port will be converted to a digital value via the ADC and forwarded to an on-chip microcontroller (such as
Core8051s). The microcontroller algorithm will periodically configure/reconfigure CorePWM registers based on the
thermistor value and/or the fan’s tachometer value.
+12 V
Fusion Device
12 V,
4-Wire Fan
Output
Pad
CorePWM
PWM
Tach
CoreAI
Analog Block (AB)
OSC
ADC
Analog
MUX
Quad
Analog Block
(voltage
monitor port)
+5 V
NTC
Thermistor
10K @ 25°C
10K ± 1%
Microcontroller
(Core8051s)
Figure 3-1 · Temperature/Voltage Monitor Application Using CorePWM in a Fusion Device
DAC
A typical DAC application using CorePWM is shown in Figure 3-2 on page 30. In this example, PWM output is
averaged to a varying DC voltage. At reset, the PWM duty cycle, or level out value, is 100% and the voltage increases to
the rail of 12 volts. The PWM duty cycle / level out value changes to 75% and then 50%, and the output of the RC filter
follows this by dropping to 8 volts and then 6 volts. The generated ripple voltage is a function of the RC circuit values,
the APB system clock period, and the PWM duty cycle.
Revision 7
29
CorePWM v4.3
As shown, a field-effect transistor (FET) is used to increase and decouple the output voltage/current from the Fusion
device. The load is monitored and changes to the PWM output are processed via a microcontroller (Core8051s,
CoreABC, etc.).
Fusion Device
CoreAI
+12 V
Analog Block (AB)
Quad Analog Block
(power MOSFET
gate driver port)
CorePWM
OSC
R
Microcontroller
(Core8051)
ADC
Analog
MUX
Quad
Analog Block
(voltage
monitor port)
Load
C
12 V
8V
6V
3.3 V
PWM Duty
Cycle: 100%
75%
50%
PWM Output
to FET
Load
Output
6V
3.3 V
In General-Purpose PWM mode, ripple voltage is a
function of PWM duty cycle, PWM period, and the RC
time constant.
In Low-Ripple DAC mode, pulse width is effectively reduced
to 1 clock cycle period, significantly reducing the ripple at the
output of a low pass filter.
Figure 3-2 · DAC Application Using CorePWM in Fusion Device
30
Revision 7
Time
CorePWM v4.3
DAC
The FET, in this case, is used to illustrate the ability to extend the DAC’s output to 12 V. For most applications, 3.3 V is
sufficient. Higher clock speeds (and therefore lower ripple) can be achieved by driving the RC filter with a general
purpose TTL output.
Using Low Ripple DAC mode has the added benefit of requiring a smaller time constant for the filter, which allows for
smaller R and C components to be used. A Low Ripple DAC calculator is available to assist in determining the ideal
values for R and C.
Revision 7
31
4
Software Driver
Drivers for CorePWM are available via the Firmware Catalog tool provided with Libero IDE. For more information on
the Firmware Catalog, refer to www.microsemi.com/products/software/firmwarecat/default.aspx.
Revision 7
32
A
List of Document Changes
The following table lists critical changes that were made in the current version of the document.
Previous
Version
5020113-7
5020113-6
5020113-5
Changes in Current Version (5020113-7)
Page
Updated Table 1-2 (SAR 63930).
14
Updated “Tool Flows” section (SAR 64045).
25
Added RTG4 information in “Supported Families”and “Utilization and Performance” Tables.
5-10
Updated core version to 4.3 in “Core Version”.
5
Added SmartFusion, SmartFusion2, and IGLOO2 families in “Supported Families” section (SAR 57616).
5
Changed core version from 4.1 to 4.2 in “Core Version” section (SAR 57616).
5
5020113-4
Updated Figure 1-2 and Table 1-2 (SAR 57175).
5020113-3
Updated core version to v4.2.
N/A
5020113-1
Updated core version to v4.1.
N/A
Updated “Utilization and Performance” tables.
5–10
Added low-cost TACHOMETER solution with up to 16 digital inputs.
N/A
5020113-0
12, 14
Added center-aligned PWM support.
22
Updated tool flow to support Libero IDE v8.5 and SmartDesign.
25
Updated Figure 1-3, Figure 1-5, and Figure 1-6 in the “Configuration Example” section.
21, 23,
23
Updated Figure 3-2.
30
Updated the “Software Driver” section.
32
Revision 7
33
B
Product Support
Microsemi SoC Products Group backs its products with various support services, including Customer Service,
Customer Technical Support Center, a website, electronic mail, and worldwide sales offices. This appendix
contains information about contacting Microsemi SoC Products Group and using these support services.
Customer Service
Contact Customer Service for non-technical product support, such as product pricing, product upgrades,
update information, order status, and authorization.
From North America, call 800.262.1060
From the rest of the world, call 650.318.4460
Fax, from anywhere in the world, 650.318.8044
Customer Technical Support Center
Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers
who can help answer your hardware, software, and design questions about Microsemi SoC Products. The
Customer Technical Support Center spends a great deal of time creating application notes, answers to
common design cycle questions, documentation of known issues, and various FAQs. So, before you contact
us, please visit our online resources. It is very likely we have already answered your questions.
Technical Support
Visit the Customer Support website (www.microsemi.com/soc/support/search/default.aspx) for more
information and support. Many answers available on the searchable web resource include diagrams,
illustrations, and links to other resources on the website.
Website
You can browse a variety of technical and non-technical information on the SoC home page, at
www.microsemi.com/soc.
Contacting the Customer Technical Support Center
Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be contacted
by email or through the Microsemi SoC Products Group website.
Email
You can communicate your technical questions to our email address and receive answers back by email, fax,
or phone. Also, if you have design problems, you can email your design files to receive assistance. We
constantly monitor the email account throughout the day. When sending your request to us, please be sure to
include your full name, company name, and your contact information for efficient processing of your request.
The technical support email address is [email protected]
My Cases
Microsemi SoC Products Group customers may submit and track technical cases online by going to My
Cases.
Revision 7
34
CorePWM v4.3
ITAR Technical Support
Outside the U.S.
Customers needing assistance outside the US time zones can either contact technical support via email
([email protected]) or contact a local sales office. Sales office listings can be found at
www.microsemi.com/soc/company/contact/default.aspx.
ITAR Technical Support
For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations
(ITAR), contact us via [email protected] Alternatively, within My Cases, select Yes in the ITAR
drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page.
Revision 7
35
Index
A
P
APB interface timing 24
applications 29
parameters, Verilog and VHDL 14
place-and-route 28
port signals 12
product support 34–??
customer service 34
email 34
My Cases 35
outside the U.S. 35
technical support 34
website 34
C
configuration examples 21
contacting Microsemi SoC Products Group
customer service 34
email 34
web-based technical support 34
CorePWM
key features 4
version 5
customer service 34
R
register map 16
D
S
DAC 29
simulation 27
simulation flows 27
SmartDesign 25
software driver 32
supported interfaces 5
synthesis 28
E
example
1 channel for low ripple DAC 26
DAC application 30
temperature monitor 29
F
functional blocks 11
I
importing into Libero IDE 27
M
Microsemi SoC Products Group
email 34
web-based technical support 34
website 34
modes
General Purpose PWM 11
Low Ripple DAC 11
T
tech support
ITAR 35
My Cases 35
outside the U.S. 35
technical support 34
tool flows 25
importing into Libero IDE 27
simulation 27
SmartDesign 25
U
utilization and performance 5
W
web-based technical support 34
O
overview 4
Revision 7
36
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor
and system solutions for communications, defense & security, aerospace and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and
synchronization devices and precise time solutions, setting the world’s standard for time; voice
processing devices; RF solutions; discrete components; security technologies and scalable
anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design
capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has
approximately 3,400 employees globally. Learn more at www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
E-mail: [email protected]
© 2015 Microsemi Corporation. All
rights reserved. Microsemi and the
Microsemi logo are trademarks of
Microsemi Corporation. All other
trademarks and service marks are the
property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any
liability whatsoever arising out of the application or use of any product or circuit. The products sold
hereunder and any other products sold by Microsemi have been subject to limited testing and should not
be used in conjunction with mission-critical equipment or applications. Any performance specifications are
believed to be reliable but are not verified, and Buyer must conduct and complete all performance and
other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely
on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's
responsibility to independently determine suitability of any products and to test and verify the same. The
information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire
risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or
implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such
information itself or anything described by such information. Information provided in this document is
proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
50200113-7/01.15